1/* 2 * Frame buffer driver for Trident Blade and Image series 3 * 4 * Copyright 2001,2002 - Jani Monoses <jani@iv.ro> 5 * 6 * 7 * CREDITS:(in order of appearance) 8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video 9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it> 10 * much inspired by the XFree86 4.x Trident driver sources by Alan Hourihane 11 * the FreeVGA project 12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,code,suggestions 13 * TODO: 14 * timing value tweaking so it looks good on every monitor in every mode 15 * TGUI acceleration 16 */ 17 18#include <linux/module.h> 19#include <linux/fb.h> 20#include <linux/init.h> 21#include <linux/pci.h> 22 23#include <linux/delay.h> 24#include <video/trident.h> 25 26#define VERSION "0.7.8-NEWAPI" 27 28struct tridentfb_par { 29 int vclk; //in MHz 30 void __iomem * io_virt; //iospace virtual memory address 31}; 32 33static unsigned char eng_oper; //engine operation... 34static struct fb_ops tridentfb_ops; 35 36static struct tridentfb_par default_par; 37 38static struct fb_info fb_info; 39static u32 pseudo_pal[16]; 40 41 42static struct fb_var_screeninfo default_var; 43 44static struct fb_fix_screeninfo tridentfb_fix = { 45 .id = "Trident", 46 .type = FB_TYPE_PACKED_PIXELS, 47 .ypanstep = 1, 48 .visual = FB_VISUAL_PSEUDOCOLOR, 49 .accel = FB_ACCEL_NONE, 50}; 51 52static int chip_id; 53 54static int defaultaccel; 55static int displaytype; 56 57 58/* defaults which are normally overriden by user values */ 59 60/* video mode */ 61static char * mode = "640x480"; 62static int bpp = 8; 63 64static int noaccel; 65 66static int center; 67static int stretch; 68 69static int fp; 70static int crt; 71 72static int memsize; 73static int memdiff; 74static int nativex; 75 76 77module_param(mode, charp, 0); 78module_param(bpp, int, 0); 79module_param(center, int, 0); 80module_param(stretch, int, 0); 81module_param(noaccel, int, 0); 82module_param(memsize, int, 0); 83module_param(memdiff, int, 0); 84module_param(nativex, int, 0); 85module_param(fp, int, 0); 86module_param(crt, int, 0); 87 88 89static int chip3D; 90static int chipcyber; 91 92static int is3Dchip(int id) 93{ 94 return ((id == BLADE3D) || (id == CYBERBLADEE4) || 95 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) || 96 (id == CYBER9397) || (id == CYBER9397DVD) || 97 (id == CYBER9520) || (id == CYBER9525DVD) || 98 (id == IMAGE975) || (id == IMAGE985) || 99 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) || 100 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) || 101 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) || 102 (id == CYBERBLADEXPAi1)); 103} 104 105static int iscyber(int id) 106{ 107 switch (id) { 108 case CYBER9388: 109 case CYBER9382: 110 case CYBER9385: 111 case CYBER9397: 112 case CYBER9397DVD: 113 case CYBER9520: 114 case CYBER9525DVD: 115 case CYBERBLADEE4: 116 case CYBERBLADEi7D: 117 case CYBERBLADEi1: 118 case CYBERBLADEi1D: 119 case CYBERBLADEAi1: 120 case CYBERBLADEAi1D: 121 case CYBERBLADEXPAi1: 122 return 1; 123 124 case CYBER9320: 125 case TGUI9660: 126 case IMAGE975: 127 case IMAGE985: 128 case BLADE3D: 129 case CYBERBLADEi7: /* VIA MPV4 integrated version */ 130 131 default: 132 /* case CYBERBLDAEXPm8: Strange */ 133 /* case CYBERBLDAEXPm16: Strange */ 134 return 0; 135 } 136} 137 138#define CRT 0x3D0 //CRTC registers offset for color display 139 140#ifndef TRIDENT_MMIO 141 #define TRIDENT_MMIO 1 142#endif 143 144#if TRIDENT_MMIO 145 #define t_outb(val,reg) writeb(val,((struct tridentfb_par *)(fb_info.par))->io_virt + reg) 146 #define t_inb(reg) readb(((struct tridentfb_par*)(fb_info.par))->io_virt + reg) 147#else 148 #define t_outb(val,reg) outb(val,reg) 149 #define t_inb(reg) inb(reg) 150#endif 151 152 153static struct accel_switch { 154 void (*init_accel)(int,int); 155 void (*wait_engine)(void); 156 void (*fill_rect)(__u32,__u32,__u32,__u32,__u32,__u32); 157 void (*copy_rect)(__u32,__u32,__u32,__u32,__u32,__u32); 158} *acc; 159 160#define writemmr(r,v) writel(v, ((struct tridentfb_par *)fb_info.par)->io_virt + r) 161#define readmmr(r) readl(((struct tridentfb_par *)fb_info.par)->io_virt + r) 162 163 164 165/* 166 * Blade specific acceleration. 167 */ 168 169#define point(x,y) ((y)<<16|(x)) 170#define STA 0x2120 171#define CMD 0x2144 172#define ROP 0x2148 173#define CLR 0x2160 174#define SR1 0x2100 175#define SR2 0x2104 176#define DR1 0x2108 177#define DR2 0x210C 178 179#define ROP_S 0xCC 180 181static void blade_init_accel(int pitch,int bpp) 182{ 183 int v1 = (pitch>>3)<<20; 184 int tmp = 0,v2; 185 switch (bpp) { 186 case 8:tmp = 0;break; 187 case 15:tmp = 5;break; 188 case 16:tmp = 1;break; 189 case 24: 190 case 32:tmp = 2;break; 191 } 192 v2 = v1 | (tmp<<29); 193 writemmr(0x21C0,v2); 194 writemmr(0x21C4,v2); 195 writemmr(0x21B8,v2); 196 writemmr(0x21BC,v2); 197 writemmr(0x21D0,v1); 198 writemmr(0x21D4,v1); 199 writemmr(0x21C8,v1); 200 writemmr(0x21CC,v1); 201 writemmr(0x216C,0); 202} 203 204static void blade_wait_engine(void) 205{ 206 while(readmmr(STA) & 0xFA800000); 207} 208 209static void blade_fill_rect(__u32 x,__u32 y,__u32 w,__u32 h,__u32 c,__u32 rop) 210{ 211 writemmr(CLR,c); 212 writemmr(ROP,rop ? 0x66:ROP_S); 213 writemmr(CMD,0x20000000|1<<19|1<<4|2<<2); 214 215 writemmr(DR1,point(x,y)); 216 writemmr(DR2,point(x+w-1,y+h-1)); 217} 218 219static void blade_copy_rect(__u32 x1,__u32 y1,__u32 x2,__u32 y2,__u32 w,__u32 h) 220{ 221 __u32 s1,s2,d1,d2; 222 int direction = 2; 223 s1 = point(x1,y1); 224 s2 = point(x1+w-1,y1+h-1); 225 d1 = point(x2,y2); 226 d2 = point(x2+w-1,y2+h-1); 227 228 if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) 229 direction = 0; 230 231 232 writemmr(ROP,ROP_S); 233 writemmr(CMD,0xE0000000|1<<19|1<<4|1<<2|direction); 234 235 writemmr(SR1,direction?s2:s1); 236 writemmr(SR2,direction?s1:s2); 237 writemmr(DR1,direction?d2:d1); 238 writemmr(DR2,direction?d1:d2); 239} 240 241static struct accel_switch accel_blade = { 242 blade_init_accel, 243 blade_wait_engine, 244 blade_fill_rect, 245 blade_copy_rect, 246}; 247 248 249/* 250 * BladeXP specific acceleration functions 251 */ 252 253#define ROP_P 0xF0 254#define masked_point(x,y) ((y & 0xffff)<<16|(x & 0xffff)) 255 256static void xp_init_accel(int pitch,int bpp) 257{ 258 int tmp = 0,v1; 259 unsigned char x = 0; 260 261 switch (bpp) { 262 case 8: x = 0; break; 263 case 16: x = 1; break; 264 case 24: x = 3; break; 265 case 32: x = 2; break; 266 } 267 268 switch (pitch << (bpp >> 3)) { 269 case 8192: 270 case 512: x |= 0x00; break; 271 case 1024: x |= 0x04; break; 272 case 2048: x |= 0x08; break; 273 case 4096: x |= 0x0C; break; 274 } 275 276 t_outb(x,0x2125); 277 278 eng_oper = x | 0x40; 279 280 switch (bpp) { 281 case 8: tmp = 18; break; 282 case 15: 283 case 16: tmp = 19; break; 284 case 24: 285 case 32: tmp = 20; break; 286 } 287 288 v1 = pitch << tmp; 289 290 writemmr(0x2154,v1); 291 writemmr(0x2150,v1); 292 t_outb(3,0x2126); 293} 294 295static void xp_wait_engine(void) 296{ 297 int busy; 298 int count, timeout; 299 300 count = 0; 301 timeout = 0; 302 for (;;) { 303 busy = t_inb(STA) & 0x80; 304 if (busy != 0x80) 305 return; 306 count++; 307 if (count == 10000000) { 308 /* Timeout */ 309 count = 9990000; 310 timeout++; 311 if (timeout == 8) { 312 /* Reset engine */ 313 t_outb(0x00, 0x2120); 314 return; 315 } 316 } 317 } 318} 319 320static void xp_fill_rect(__u32 x,__u32 y,__u32 w,__u32 h,__u32 c,__u32 rop) 321{ 322 writemmr(0x2127,ROP_P); 323 writemmr(0x2158,c); 324 writemmr(0x2128,0x4000); 325 writemmr(0x2140,masked_point(h,w)); 326 writemmr(0x2138,masked_point(y,x)); 327 t_outb(0x01,0x2124); 328 t_outb(eng_oper,0x2125); 329} 330 331static void xp_copy_rect(__u32 x1,__u32 y1,__u32 x2,__u32 y2,__u32 w,__u32 h) 332{ 333 int direction; 334 __u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; 335 336 direction = 0x0004; 337 338 if ((x1 < x2) && (y1 == y2)) { 339 direction |= 0x0200; 340 x1_tmp = x1 + w - 1; 341 x2_tmp = x2 + w - 1; 342 } else { 343 x1_tmp = x1; 344 x2_tmp = x2; 345 } 346 347 if (y1 < y2) { 348 direction |= 0x0100; 349 y1_tmp = y1 + h - 1; 350 y2_tmp = y2 + h - 1; 351 } else { 352 y1_tmp = y1; 353 y2_tmp = y2; 354 } 355 356 writemmr(0x2128,direction); 357 t_outb(ROP_S,0x2127); 358 writemmr(0x213C,masked_point(y1_tmp,x1_tmp)); 359 writemmr(0x2138,masked_point(y2_tmp,x2_tmp)); 360 writemmr(0x2140,masked_point(h,w)); 361 t_outb(0x01,0x2124); 362} 363 364static struct accel_switch accel_xp = { 365 xp_init_accel, 366 xp_wait_engine, 367 xp_fill_rect, 368 xp_copy_rect, 369}; 370 371 372/* 373 * Image specific acceleration functions 374 */ 375static void image_init_accel(int pitch,int bpp) 376{ 377 int tmp = 0; 378 switch (bpp) { 379 case 8:tmp = 0;break; 380 case 15:tmp = 5;break; 381 case 16:tmp = 1;break; 382 case 24: 383 case 32:tmp = 2;break; 384 } 385 writemmr(0x2120, 0xF0000000); 386 writemmr(0x2120, 0x40000000|tmp); 387 writemmr(0x2120, 0x80000000); 388 writemmr(0x2144, 0x00000000); 389 writemmr(0x2148, 0x00000000); 390 writemmr(0x2150, 0x00000000); 391 writemmr(0x2154, 0x00000000); 392 writemmr(0x2120, 0x60000000|(pitch<<16) |pitch); 393 writemmr(0x216C, 0x00000000); 394 writemmr(0x2170, 0x00000000); 395 writemmr(0x217C, 0x00000000); 396 writemmr(0x2120, 0x10000000); 397 writemmr(0x2130, (2047 << 16) | 2047); 398} 399 400static void image_wait_engine(void) 401{ 402 while(readmmr(0x2164) & 0xF0000000); 403} 404 405static void image_fill_rect(__u32 x, __u32 y, __u32 w, __u32 h, __u32 c, __u32 rop) 406{ 407 writemmr(0x2120,0x80000000); 408 writemmr(0x2120,0x90000000|ROP_S); 409 410 writemmr(0x2144,c); 411 412 writemmr(DR1,point(x,y)); 413 writemmr(DR2,point(x+w-1,y+h-1)); 414 415 writemmr(0x2124,0x80000000|3<<22|1<<10|1<<9); 416} 417 418static void image_copy_rect(__u32 x1,__u32 y1,__u32 x2,__u32 y2,__u32 w,__u32 h) 419{ 420 __u32 s1,s2,d1,d2; 421 int direction = 2; 422 s1 = point(x1,y1); 423 s2 = point(x1+w-1,y1+h-1); 424 d1 = point(x2,y2); 425 d2 = point(x2+w-1,y2+h-1); 426 427 if ((y1 > y2) || ((y1 == y2) && (x1 >x2))) 428 direction = 0; 429 430 writemmr(0x2120,0x80000000); 431 writemmr(0x2120,0x90000000|ROP_S); 432 433 writemmr(SR1,direction?s2:s1); 434 writemmr(SR2,direction?s1:s2); 435 writemmr(DR1,direction?d2:d1); 436 writemmr(DR2,direction?d1:d2); 437 writemmr(0x2124,0x80000000|1<<22|1<<10|1<<7|direction); 438} 439 440 441static struct accel_switch accel_image = { 442 image_init_accel, 443 image_wait_engine, 444 image_fill_rect, 445 image_copy_rect, 446}; 447 448/* 449 * Accel functions called by the upper layers 450 */ 451#ifdef CONFIG_FB_TRIDENT_ACCEL 452static void tridentfb_fillrect(struct fb_info * info, const struct fb_fillrect *fr) 453{ 454 int bpp = info->var.bits_per_pixel; 455 int col = 0; 456 457 switch (bpp) { 458 default: 459 case 8: col |= fr->color; 460 col |= col << 8; 461 col |= col << 16; 462 break; 463 case 16: col = ((u32 *)(info->pseudo_palette))[fr->color]; 464 465 break; 466 case 32: col = ((u32 *)(info->pseudo_palette))[fr->color]; 467 break; 468 } 469 470 acc->fill_rect(fr->dx, fr->dy, fr->width, fr->height, col, fr->rop); 471 acc->wait_engine(); 472} 473static void tridentfb_copyarea(struct fb_info *info, const struct fb_copyarea *ca) 474{ 475 acc->copy_rect(ca->sx,ca->sy,ca->dx,ca->dy,ca->width,ca->height); 476 acc->wait_engine(); 477} 478#else /* !CONFIG_FB_TRIDENT_ACCEL */ 479#define tridentfb_fillrect cfb_fillrect 480#define tridentfb_copyarea cfb_copyarea 481#endif /* CONFIG_FB_TRIDENT_ACCEL */ 482 483 484/* 485 * Hardware access functions 486 */ 487 488static inline unsigned char read3X4(int reg) 489{ 490 struct tridentfb_par * par = (struct tridentfb_par *)fb_info.par; 491 writeb(reg, par->io_virt + CRT + 4); 492 return readb( par->io_virt + CRT + 5); 493} 494 495static inline void write3X4(int reg, unsigned char val) 496{ 497 struct tridentfb_par * par = (struct tridentfb_par *)fb_info.par; 498 writeb(reg, par->io_virt + CRT + 4); 499 writeb(val, par->io_virt + CRT + 5); 500} 501 502static inline unsigned char read3C4(int reg) 503{ 504 t_outb(reg, 0x3C4); 505 return t_inb(0x3C5); 506} 507 508static inline void write3C4(int reg, unsigned char val) 509{ 510 t_outb(reg, 0x3C4); 511 t_outb(val, 0x3C5); 512} 513 514static inline unsigned char read3CE(int reg) 515{ 516 t_outb(reg, 0x3CE); 517 return t_inb(0x3CF); 518} 519 520static inline void writeAttr(int reg, unsigned char val) 521{ 522 readb(((struct tridentfb_par *)fb_info.par)->io_virt + CRT + 0x0A); //flip-flop to index 523 t_outb(reg, 0x3C0); 524 t_outb(val, 0x3C0); 525} 526 527static inline void write3CE(int reg, unsigned char val) 528{ 529 t_outb(reg, 0x3CE); 530 t_outb(val, 0x3CF); 531} 532 533static inline void enable_mmio(void) 534{ 535 /* Goto New Mode */ 536 outb(0x0B, 0x3C4); 537 inb(0x3C5); 538 539 /* Unprotect registers */ 540 outb(NewMode1, 0x3C4); 541 outb(0x80, 0x3C5); 542 543 /* Enable MMIO */ 544 outb(PCIReg, 0x3D4); 545 outb(inb(0x3D5) | 0x01, 0x3D5); 546} 547 548 549#define crtc_unlock() write3X4(CRTVSyncEnd, read3X4(CRTVSyncEnd) & 0x7F) 550 551/* Return flat panel's maximum x resolution */ 552static int __devinit get_nativex(void) 553{ 554 int x,y,tmp; 555 556 if (nativex) 557 return nativex; 558 559 tmp = (read3CE(VertStretch) >> 4) & 3; 560 561 switch (tmp) { 562 case 0: x = 1280; y = 1024; break; 563 case 2: x = 1024; y = 768; break; 564 case 3: x = 800; y = 600; break; 565 case 4: x = 1400; y = 1050; break; 566 case 1: 567 default:x = 640; y = 480; break; 568 } 569 570 output("%dx%d flat panel found\n", x, y); 571 return x; 572} 573 574/* Set pitch */ 575static void set_lwidth(int width) 576{ 577 write3X4(Offset, width & 0xFF); 578 write3X4(AddColReg, (read3X4(AddColReg) & 0xCF) | ((width & 0x300) >>4)); 579} 580 581/* For resolutions smaller than FP resolution stretch */ 582static void screen_stretch(void) 583{ 584 if (chip_id != CYBERBLADEXPAi1) 585 write3CE(BiosReg,0); 586 else 587 write3CE(BiosReg,8); 588 write3CE(VertStretch,(read3CE(VertStretch) & 0x7C) | 1); 589 write3CE(HorStretch,(read3CE(HorStretch) & 0x7C) | 1); 590} 591 592/* For resolutions smaller than FP resolution center */ 593static void screen_center(void) 594{ 595 write3CE(VertStretch,(read3CE(VertStretch) & 0x7C) | 0x80); 596 write3CE(HorStretch,(read3CE(HorStretch) & 0x7C) | 0x80); 597} 598 599/* Address of first shown pixel in display memory */ 600static void set_screen_start(int base) 601{ 602 write3X4(StartAddrLow, base & 0xFF); 603 write3X4(StartAddrHigh, (base & 0xFF00) >> 8); 604 write3X4(CRTCModuleTest, (read3X4(CRTCModuleTest) & 0xDF) | ((base & 0x10000) >> 11)); 605 write3X4(CRTHiOrd, (read3X4(CRTHiOrd) & 0xF8) | ((base & 0xE0000) >> 17)); 606} 607 608/* Use 20.12 fixed-point for NTSC value and frequency calculation */ 609#define calc_freq(n,m,k) ( ((unsigned long)0xE517 * (n+8) / ((m+2)*(1<<k))) >> 12 ) 610 611/* Set dotclock frequency */ 612static void set_vclk(int freq) 613{ 614 int m,n,k; 615 int f,fi,d,di; 616 unsigned char lo=0,hi=0; 617 618 d = 20; 619 for(k = 2;k>=0;k--) 620 for(m = 0;m<63;m++) 621 for(n = 0;n<128;n++) { 622 fi = calc_freq(n,m,k); 623 if ((di = abs(fi - freq)) < d) { 624 d = di; 625 f = fi; 626 lo = n; 627 hi = (k<<6) | m; 628 } 629 } 630 if (chip3D) { 631 write3C4(ClockHigh,hi); 632 write3C4(ClockLow,lo); 633 } else { 634 outb(lo,0x43C8); 635 outb(hi,0x43C9); 636 } 637 debug("VCLK = %X %X\n",hi,lo); 638} 639 640/* Set number of lines for flat panels*/ 641static void set_number_of_lines(int lines) 642{ 643 int tmp = read3CE(CyberEnhance) & 0x8F; 644 if (lines > 1024) 645 tmp |= 0x50; 646 else if (lines > 768) 647 tmp |= 0x30; 648 else if (lines > 600) 649 tmp |= 0x20; 650 else if (lines > 480) 651 tmp |= 0x10; 652 write3CE(CyberEnhance, tmp); 653} 654 655/* 656 * If we see that FP is active we assume we have one. 657 * Otherwise we have a CRT display.User can override. 658 */ 659static unsigned int __devinit get_displaytype(void) 660{ 661 if (fp) 662 return DISPLAY_FP; 663 if (crt || !chipcyber) 664 return DISPLAY_CRT; 665 return (read3CE(FPConfig) & 0x10)?DISPLAY_FP:DISPLAY_CRT; 666} 667 668/* Try detecting the video memory size */ 669static unsigned int __devinit get_memsize(void) 670{ 671 unsigned char tmp, tmp2; 672 unsigned int k; 673 674 /* If memory size provided by user */ 675 if (memsize) 676 k = memsize * Kb; 677 else 678 switch (chip_id) { 679 case CYBER9525DVD: k = 2560 * Kb; break; 680 default: 681 tmp = read3X4(SPR) & 0x0F; 682 switch (tmp) { 683 684 case 0x01: k = 512; break; 685 case 0x02: k = 6 * Mb; break; /* XP */ 686 case 0x03: k = 1 * Mb; break; 687 case 0x04: k = 8 * Mb; break; 688 case 0x06: k = 10 * Mb; break; /* XP */ 689 case 0x07: k = 2 * Mb; break; 690 case 0x08: k = 12 * Mb; break; /* XP */ 691 case 0x0A: k = 14 * Mb; break; /* XP */ 692 case 0x0C: k = 16 * Mb; break; /* XP */ 693 case 0x0E: /* XP */ 694 695 tmp2 = read3C4(0xC1); 696 switch (tmp2) { 697 case 0x00: k = 20 * Mb; break; 698 case 0x01: k = 24 * Mb; break; 699 case 0x10: k = 28 * Mb; break; 700 case 0x11: k = 32 * Mb; break; 701 default: k = 1 * Mb; break; 702 } 703 break; 704 705 case 0x0F: k = 4 * Mb; break; 706 default: k = 1 * Mb; 707 } 708 } 709 710 k -= memdiff * Kb; 711 output("framebuffer size = %d Kb\n", k/Kb); 712 return k; 713} 714 715/* See if we can handle the video mode described in var */ 716static int tridentfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 717{ 718 int bpp = var->bits_per_pixel; 719 debug("enter\n"); 720 721 /* check color depth */ 722 if (bpp == 24 ) 723 bpp = var->bits_per_pixel = 32; 724 /* check whether resolution fits on panel and in memory*/ 725 if (flatpanel && nativex && var->xres > nativex) 726 return -EINVAL; 727 if (var->xres * var->yres_virtual * bpp/8 > info->fix.smem_len) 728 return -EINVAL; 729 730 switch (bpp) { 731 case 8: 732 var->red.offset = 0; 733 var->green.offset = 0; 734 var->blue.offset = 0; 735 var->red.length = 6; 736 var->green.length = 6; 737 var->blue.length = 6; 738 break; 739 case 16: 740 var->red.offset = 11; 741 var->green.offset = 5; 742 var->blue.offset = 0; 743 var->red.length = 5; 744 var->green.length = 6; 745 var->blue.length = 5; 746 break; 747 case 32: 748 var->red.offset = 16; 749 var->green.offset = 8; 750 var->blue.offset = 0; 751 var->red.length = 8; 752 var->green.length = 8; 753 var->blue.length = 8; 754 break; 755 default: 756 return -EINVAL; 757 } 758 debug("exit\n"); 759 760 return 0; 761 762} 763/* Pan the display */ 764static int tridentfb_pan_display(struct fb_var_screeninfo *var, 765 struct fb_info *info) 766{ 767 unsigned int offset; 768 769 debug("enter\n"); 770 offset = (var->xoffset + (var->yoffset * var->xres)) 771 * var->bits_per_pixel/32; 772 info->var.xoffset = var->xoffset; 773 info->var.yoffset = var->yoffset; 774 set_screen_start(offset); 775 debug("exit\n"); 776 return 0; 777} 778 779#define shadowmode_on() write3CE(CyberControl,read3CE(CyberControl) | 0x81) 780#define shadowmode_off() write3CE(CyberControl,read3CE(CyberControl) & 0x7E) 781 782/* Set the hardware to the requested video mode */ 783static int tridentfb_set_par(struct fb_info *info) 784{ 785 struct tridentfb_par * par = (struct tridentfb_par *)(info->par); 786 u32 htotal,hdispend,hsyncstart,hsyncend,hblankstart,hblankend, 787 vtotal,vdispend,vsyncstart,vsyncend,vblankstart,vblankend; 788 struct fb_var_screeninfo *var = &info->var; 789 int bpp = var->bits_per_pixel; 790 unsigned char tmp; 791 debug("enter\n"); 792 htotal = (var->xres + var->left_margin + var->right_margin + var->hsync_len)/8 - 10; 793 hdispend = var->xres/8 - 1; 794 hsyncstart = (var->xres + var->right_margin)/8; 795 hsyncend = var->hsync_len/8; 796 hblankstart = hdispend + 1; 797 hblankend = htotal + 5; 798 799 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len - 2; 800 vdispend = var->yres - 1; 801 vsyncstart = var->yres + var->lower_margin; 802 vsyncend = var->vsync_len; 803 vblankstart = var->yres; 804 vblankend = vtotal + 2; 805 806 enable_mmio(); 807 crtc_unlock(); 808 write3CE(CyberControl,8); 809 810 if (flatpanel && var->xres < nativex) { 811 /* 812 * on flat panels with native size larger 813 * than requested resolution decide whether 814 * we stretch or center 815 */ 816 t_outb(0xEB,0x3C2); 817 818 shadowmode_on(); 819 820 if (center) 821 screen_center(); 822 else if (stretch) 823 screen_stretch(); 824 825 } else { 826 t_outb(0x2B,0x3C2); 827 write3CE(CyberControl,8); 828 } 829 830 /* vertical timing values */ 831 write3X4(CRTVTotal, vtotal & 0xFF); 832 write3X4(CRTVDispEnd, vdispend & 0xFF); 833 write3X4(CRTVSyncStart, vsyncstart & 0xFF); 834 write3X4(CRTVSyncEnd, (vsyncend & 0x0F)); 835 write3X4(CRTVBlankStart, vblankstart & 0xFF); 836 write3X4(CRTVBlankEnd, 0/*p->vblankend & 0xFF*/); 837 838 /* horizontal timing values */ 839 write3X4(CRTHTotal, htotal & 0xFF); 840 write3X4(CRTHDispEnd, hdispend & 0xFF); 841 write3X4(CRTHSyncStart, hsyncstart & 0xFF); 842 write3X4(CRTHSyncEnd, (hsyncend & 0x1F) | ((hblankend & 0x20)<<2)); 843 write3X4(CRTHBlankStart, hblankstart & 0xFF); 844 write3X4(CRTHBlankEnd, 0/*(p->hblankend & 0x1F)*/); 845 846 /* higher bits of vertical timing values */ 847 tmp = 0x10; 848 if (vtotal & 0x100) tmp |= 0x01; 849 if (vdispend & 0x100) tmp |= 0x02; 850 if (vsyncstart & 0x100) tmp |= 0x04; 851 if (vblankstart & 0x100) tmp |= 0x08; 852 853 if (vtotal & 0x200) tmp |= 0x20; 854 if (vdispend & 0x200) tmp |= 0x40; 855 if (vsyncstart & 0x200) tmp |= 0x80; 856 write3X4(CRTOverflow, tmp); 857 858 tmp = read3X4(CRTHiOrd) | 0x08; //line compare bit 10 859 if (vtotal & 0x400) tmp |= 0x80; 860 if (vblankstart & 0x400) tmp |= 0x40; 861 if (vsyncstart & 0x400) tmp |= 0x20; 862 if (vdispend & 0x400) tmp |= 0x10; 863 write3X4(CRTHiOrd, tmp); 864 865 tmp = 0; 866 if (htotal & 0x800) tmp |= 0x800 >> 11; 867 if (hblankstart & 0x800) tmp |= 0x800 >> 7; 868 write3X4(HorizOverflow, tmp); 869 870 tmp = 0x40; 871 if (vblankstart & 0x200) tmp |= 0x20; 872 write3X4(CRTMaxScanLine, tmp); 873 874 write3X4(CRTLineCompare,0xFF); 875 write3X4(CRTPRowScan,0); 876 write3X4(CRTModeControl,0xC3); 877 878 write3X4(LinearAddReg,0x20); //enable linear addressing 879 880 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84:0x80; 881 write3X4(CRTCModuleTest,tmp); //enable access extended memory 882 883 write3X4(GraphEngReg, 0x80); //enable GE for text acceleration 884 885#ifdef CONFIG_FB_TRIDENT_ACCEL 886 acc->init_accel(info->var.xres,bpp); 887#endif 888 889 switch (bpp) { 890 case 8: tmp = 0x00; break; 891 case 16: tmp = 0x05; break; 892 case 24: tmp = 0x29; break; 893 case 32: tmp = 0x09; 894 } 895 896 write3X4(PixelBusReg, tmp); 897 898 tmp = 0x10; 899 if (chipcyber) 900 tmp |= 0x20; 901 write3X4(DRAMControl, tmp); //both IO,linear enable 902 903 write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40); 904 write3X4(Performance,0x92); 905 write3X4(PCIReg,0x07); //MMIO & PCI read and write burst enable 906 907 /* convert from picoseconds to MHz */ 908 par->vclk = 1000000/info->var.pixclock; 909 if (bpp == 32) 910 par->vclk *=2; 911 set_vclk(par->vclk); 912 913 write3C4(0,3); 914 write3C4(1,1); //set char clock 8 dots wide 915 write3C4(2,0x0F); //enable 4 maps because needed in chain4 mode 916 write3C4(3,0); 917 write3C4(4,0x0E); //memory mode enable bitmaps ?? 918 919 write3CE(MiscExtFunc,(bpp==32)?0x1A:0x12); //divide clock by 2 if 32bpp 920 //chain4 mode display and CPU path 921 write3CE(0x5,0x40); //no CGA compat,allow 256 col 922 write3CE(0x6,0x05); //graphics mode 923 write3CE(0x7,0x0F); //planes? 924 925 if (chip_id == CYBERBLADEXPAi1) { 926 /* This fixes snow-effect in 32 bpp */ 927 write3X4(CRTHSyncStart,0x84); 928 } 929 930 writeAttr(0x10,0x41); //graphics mode and support 256 color modes 931 writeAttr(0x12,0x0F); //planes 932 writeAttr(0x13,0); //horizontal pel panning 933 934 //colors 935 for(tmp = 0;tmp < 0x10;tmp++) 936 writeAttr(tmp,tmp); 937 readb(par->io_virt + CRT + 0x0A); //flip-flop to index 938 t_outb(0x20, 0x3C0); //enable attr 939 940 switch (bpp) { 941 case 8: tmp = 0;break; //256 colors 942 case 15: tmp = 0x10;break; 943 case 16: tmp = 0x30;break; //hicolor 944 case 24: //truecolor 945 case 32: tmp = 0xD0;break; 946 } 947 948 t_inb(0x3C8); 949 t_inb(0x3C6); 950 t_inb(0x3C6); 951 t_inb(0x3C6); 952 t_inb(0x3C6); 953 t_outb(tmp,0x3C6); 954 t_inb(0x3C8); 955 956 if (flatpanel) 957 set_number_of_lines(info->var.yres); 958 set_lwidth(info->var.xres * bpp/(4*16)); 959 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 960 info->fix.line_length = info->var.xres * (bpp >> 3); 961 info->cmap.len = (bpp == 8) ? 256: 16; 962 debug("exit\n"); 963 return 0; 964} 965 966/* Set one color register */ 967static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, 968 unsigned blue, unsigned transp, 969 struct fb_info *info) 970{ 971 int bpp = info->var.bits_per_pixel; 972 973 if (regno >= info->cmap.len) 974 return 1; 975 976 977 if (bpp==8) { 978 t_outb(0xFF,0x3C6); 979 t_outb(regno,0x3C8); 980 981 t_outb(red>>10,0x3C9); 982 t_outb(green>>10,0x3C9); 983 t_outb(blue>>10,0x3C9); 984 985 } else if (bpp == 16) { /* RGB 565 */ 986 u32 col; 987 988 col = (red & 0xF800) | ((green & 0xFC00) >> 5) | 989 ((blue & 0xF800) >> 11); 990 col |= col << 16; 991 ((u32 *)(info->pseudo_palette))[regno] = col; 992 } else if (bpp == 32) /* ARGB 8888 */ 993 ((u32*)info->pseudo_palette)[regno] = 994 ((transp & 0xFF00) <<16) | 995 ((red & 0xFF00) << 8) | 996 ((green & 0xFF00)) | 997 ((blue & 0xFF00)>>8); 998 999// debug("exit\n"); 1000 return 0; 1001} 1002 1003/* Try blanking the screen.For flat panels it does nothing */ 1004static int tridentfb_blank(int blank_mode, struct fb_info *info) 1005{ 1006 unsigned char PMCont,DPMSCont; 1007 1008 debug("enter\n"); 1009 if (flatpanel) 1010 return 0; 1011 t_outb(0x04,0x83C8); /* Read DPMS Control */ 1012 PMCont = t_inb(0x83C6) & 0xFC; 1013 DPMSCont = read3CE(PowerStatus) & 0xFC; 1014 switch (blank_mode) 1015 { 1016 case FB_BLANK_UNBLANK: 1017 /* Screen: On, HSync: On, VSync: On */ 1018 case FB_BLANK_NORMAL: 1019 /* Screen: Off, HSync: On, VSync: On */ 1020 PMCont |= 0x03; 1021 DPMSCont |= 0x00; 1022 break; 1023 case FB_BLANK_HSYNC_SUSPEND: 1024 /* Screen: Off, HSync: Off, VSync: On */ 1025 PMCont |= 0x02; 1026 DPMSCont |= 0x01; 1027 break; 1028 case FB_BLANK_VSYNC_SUSPEND: 1029 /* Screen: Off, HSync: On, VSync: Off */ 1030 PMCont |= 0x02; 1031 DPMSCont |= 0x02; 1032 break; 1033 case FB_BLANK_POWERDOWN: 1034 /* Screen: Off, HSync: Off, VSync: Off */ 1035 PMCont |= 0x00; 1036 DPMSCont |= 0x03; 1037 break; 1038 } 1039 1040 write3CE(PowerStatus,DPMSCont); 1041 t_outb(4,0x83C8); 1042 t_outb(PMCont,0x83C6); 1043 1044 debug("exit\n"); 1045 1046 /* let fbcon do a softblank for us */ 1047 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; 1048} 1049 1050static int __devinit trident_pci_probe(struct pci_dev * dev, const struct pci_device_id * id) 1051{ 1052 int err; 1053 unsigned char revision; 1054 1055 err = pci_enable_device(dev); 1056 if (err) 1057 return err; 1058 1059 chip_id = id->device; 1060 1061 if(chip_id == CYBERBLADEi1) 1062 output("*** Please do use cyblafb, Cyberblade/i1 support " 1063 "will soon be removed from tridentfb!\n"); 1064 1065 1066 /* If PCI id is 0x9660 then further detect chip type */ 1067 1068 if (chip_id == TGUI9660) { 1069 outb(RevisionID,0x3C4); 1070 revision = inb(0x3C5); 1071 1072 switch (revision) { 1073 case 0x22: 1074 case 0x23: chip_id = CYBER9397;break; 1075 case 0x2A: chip_id = CYBER9397DVD;break; 1076 case 0x30: 1077 case 0x33: 1078 case 0x34: 1079 case 0x35: 1080 case 0x38: 1081 case 0x3A: 1082 case 0xB3: chip_id = CYBER9385;break; 1083 case 0x40 ... 0x43: chip_id = CYBER9382;break; 1084 case 0x4A: chip_id = CYBER9388;break; 1085 default:break; 1086 } 1087 } 1088 1089 chip3D = is3Dchip(chip_id); 1090 chipcyber = iscyber(chip_id); 1091 1092 if (is_xp(chip_id)) { 1093 acc = &accel_xp; 1094 } else 1095 if (is_blade(chip_id)) { 1096 acc = &accel_blade; 1097 } else { 1098 acc = &accel_image; 1099 } 1100 1101 /* acceleration is on by default for 3D chips */ 1102 defaultaccel = chip3D && !noaccel; 1103 1104 fb_info.par = &default_par; 1105 1106 /* setup MMIO region */ 1107 tridentfb_fix.mmio_start = pci_resource_start(dev,1); 1108 tridentfb_fix.mmio_len = chip3D ? 0x20000:0x10000; 1109 1110 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) { 1111 debug("request_region failed!\n"); 1112 return -1; 1113 } 1114 1115 default_par.io_virt = ioremap_nocache(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); 1116 1117 if (!default_par.io_virt) { 1118 release_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); 1119 debug("ioremap failed\n"); 1120 return -1; 1121 } 1122 1123 enable_mmio(); 1124 1125 /* setup framebuffer memory */ 1126 tridentfb_fix.smem_start = pci_resource_start(dev,0); 1127 tridentfb_fix.smem_len = get_memsize(); 1128 1129 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) { 1130 debug("request_mem_region failed!\n"); 1131 err = -1; 1132 goto out_unmap; 1133 } 1134 1135 fb_info.screen_base = ioremap_nocache(tridentfb_fix.smem_start, 1136 tridentfb_fix.smem_len); 1137 1138 if (!fb_info.screen_base) { 1139 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); 1140 debug("ioremap failed\n"); 1141 err = -1; 1142 goto out_unmap; 1143 } 1144 1145 output("%s board found\n", pci_name(dev)); 1146 displaytype = get_displaytype(); 1147 1148 if(flatpanel) 1149 nativex = get_nativex(); 1150 1151 fb_info.fix = tridentfb_fix; 1152 fb_info.fbops = &tridentfb_ops; 1153 1154 1155 fb_info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 1156#ifdef CONFIG_FB_TRIDENT_ACCEL 1157 fb_info.flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT; 1158#endif 1159 fb_info.pseudo_palette = pseudo_pal; 1160 1161 if (!fb_find_mode(&default_var,&fb_info,mode,NULL,0,NULL,bpp)) { 1162 err = -EINVAL; 1163 goto out_unmap; 1164 } 1165 fb_alloc_cmap(&fb_info.cmap,256,0); 1166 if (defaultaccel && acc) 1167 default_var.accel_flags |= FB_ACCELF_TEXT; 1168 else 1169 default_var.accel_flags &= ~FB_ACCELF_TEXT; 1170 default_var.activate |= FB_ACTIVATE_NOW; 1171 fb_info.var = default_var; 1172 fb_info.device = &dev->dev; 1173 if (register_framebuffer(&fb_info) < 0) { 1174 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n"); 1175 err = -EINVAL; 1176 goto out_unmap; 1177 } 1178 output("fb%d: %s frame buffer device %dx%d-%dbpp\n", 1179 fb_info.node, fb_info.fix.id,default_var.xres, 1180 default_var.yres,default_var.bits_per_pixel); 1181 return 0; 1182 1183out_unmap: 1184 if (default_par.io_virt) 1185 iounmap(default_par.io_virt); 1186 if (fb_info.screen_base) 1187 iounmap(fb_info.screen_base); 1188 return err; 1189} 1190 1191static void __devexit trident_pci_remove(struct pci_dev * dev) 1192{ 1193 struct tridentfb_par *par = (struct tridentfb_par*)fb_info.par; 1194 unregister_framebuffer(&fb_info); 1195 iounmap(par->io_virt); 1196 iounmap(fb_info.screen_base); 1197 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); 1198 release_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); 1199} 1200 1201/* List of boards that we are trying to support */ 1202static struct pci_device_id trident_devices[] = { 1203 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1204 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1205 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1206 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1207 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1208 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1209 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1210 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1211 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1212 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1213 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1214 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1215 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1216 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1217 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1218 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1219 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1220 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1221 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1222 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 1223 {0,} 1224}; 1225 1226MODULE_DEVICE_TABLE(pci,trident_devices); 1227 1228static struct pci_driver tridentfb_pci_driver = { 1229 .name = "tridentfb", 1230 .id_table = trident_devices, 1231 .probe = trident_pci_probe, 1232 .remove = __devexit_p(trident_pci_remove) 1233}; 1234 1235/* 1236 * Parse user specified options (`video=trident:') 1237 * example: 1238 * video=trident:800x600,bpp=16,noaccel 1239 */ 1240#ifndef MODULE 1241static int tridentfb_setup(char *options) 1242{ 1243 char * opt; 1244 if (!options || !*options) 1245 return 0; 1246 while((opt = strsep(&options,",")) != NULL ) { 1247 if (!*opt) continue; 1248 if (!strncmp(opt,"noaccel",7)) 1249 noaccel = 1; 1250 else if (!strncmp(opt,"fp",2)) 1251 displaytype = DISPLAY_FP; 1252 else if (!strncmp(opt,"crt",3)) 1253 displaytype = DISPLAY_CRT; 1254 else if (!strncmp(opt,"bpp=",4)) 1255 bpp = simple_strtoul(opt+4,NULL,0); 1256 else if (!strncmp(opt,"center",6)) 1257 center = 1; 1258 else if (!strncmp(opt,"stretch",7)) 1259 stretch = 1; 1260 else if (!strncmp(opt,"memsize=",8)) 1261 memsize = simple_strtoul(opt+8,NULL,0); 1262 else if (!strncmp(opt,"memdiff=",8)) 1263 memdiff = simple_strtoul(opt+8,NULL,0); 1264 else if (!strncmp(opt,"nativex=",8)) 1265 nativex = simple_strtoul(opt+8,NULL,0); 1266 else 1267 mode = opt; 1268 } 1269 return 0; 1270} 1271#endif 1272 1273static int __init tridentfb_init(void) 1274{ 1275#ifndef MODULE 1276 char *option = NULL; 1277 1278 if (fb_get_options("tridentfb", &option)) 1279 return -ENODEV; 1280 tridentfb_setup(option); 1281#endif 1282 output("Trident framebuffer %s initializing\n", VERSION); 1283 return pci_register_driver(&tridentfb_pci_driver); 1284} 1285 1286static void __exit tridentfb_exit(void) 1287{ 1288 pci_unregister_driver(&tridentfb_pci_driver); 1289} 1290 1291static struct fb_ops tridentfb_ops = { 1292 .owner = THIS_MODULE, 1293 .fb_setcolreg = tridentfb_setcolreg, 1294 .fb_pan_display = tridentfb_pan_display, 1295 .fb_blank = tridentfb_blank, 1296 .fb_check_var = tridentfb_check_var, 1297 .fb_set_par = tridentfb_set_par, 1298 .fb_fillrect = tridentfb_fillrect, 1299 .fb_copyarea= tridentfb_copyarea, 1300 .fb_imageblit = cfb_imageblit, 1301}; 1302 1303module_init(tridentfb_init); 1304module_exit(tridentfb_exit); 1305 1306MODULE_AUTHOR("Jani Monoses <jani@iv.ro>"); 1307MODULE_DESCRIPTION("Framebuffer driver for Trident cards"); 1308MODULE_LICENSE("GPL"); 1309