1/* 2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device 3 * 4 * Copyright (C) 1995 Jay Estabrook 5 * Copyright (C) 1997 Geert Uytterhoeven 6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha 7 * Copyright (C) 2002 Richard Henderson 8 * Copyright (C) 2006 Maciej W. Rozycki 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive for 12 * more details. 13 */ 14 15#include <linux/bitrev.h> 16#include <linux/delay.h> 17#include <linux/device.h> 18#include <linux/errno.h> 19#include <linux/fb.h> 20#include <linux/init.h> 21#include <linux/ioport.h> 22#include <linux/kernel.h> 23#include <linux/mm.h> 24#include <linux/module.h> 25#include <linux/pci.h> 26#include <linux/selection.h> 27#include <linux/slab.h> 28#include <linux/string.h> 29#include <linux/tc.h> 30 31#include <asm/io.h> 32 33#include <video/tgafb.h> 34 35#ifdef CONFIG_PCI 36#define TGA_BUS_PCI(dev) (dev->bus == &pci_bus_type) 37#else 38#define TGA_BUS_PCI(dev) 0 39#endif 40 41#ifdef CONFIG_TC 42#define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type) 43#else 44#define TGA_BUS_TC(dev) 0 45#endif 46 47/* 48 * Local functions. 49 */ 50 51static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *); 52static int tgafb_set_par(struct fb_info *); 53static void tgafb_set_pll(struct tga_par *, int); 54static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned, 55 unsigned, struct fb_info *); 56static int tgafb_blank(int, struct fb_info *); 57static void tgafb_init_fix(struct fb_info *); 58 59static void tgafb_imageblit(struct fb_info *, const struct fb_image *); 60static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *); 61static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *); 62static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); 63 64static int __devinit tgafb_register(struct device *dev); 65static void __devexit tgafb_unregister(struct device *dev); 66 67static const char *mode_option; 68static const char *mode_option_pci = "640x480@60"; 69static const char *mode_option_tc = "1280x1024@72"; 70 71 72static struct pci_driver tgafb_pci_driver; 73static struct tc_driver tgafb_tc_driver; 74 75/* 76 * Frame buffer operations 77 */ 78 79static struct fb_ops tgafb_ops = { 80 .owner = THIS_MODULE, 81 .fb_check_var = tgafb_check_var, 82 .fb_set_par = tgafb_set_par, 83 .fb_setcolreg = tgafb_setcolreg, 84 .fb_blank = tgafb_blank, 85 .fb_pan_display = tgafb_pan_display, 86 .fb_fillrect = tgafb_fillrect, 87 .fb_copyarea = tgafb_copyarea, 88 .fb_imageblit = tgafb_imageblit, 89}; 90 91 92#ifdef CONFIG_PCI 93/* 94 * PCI registration operations 95 */ 96static int __devinit tgafb_pci_register(struct pci_dev *, 97 const struct pci_device_id *); 98static void __devexit tgafb_pci_unregister(struct pci_dev *); 99 100static struct pci_device_id const tgafb_pci_table[] = { 101 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) }, 102 { } 103}; 104MODULE_DEVICE_TABLE(pci, tgafb_pci_table); 105 106static struct pci_driver tgafb_pci_driver = { 107 .name = "tgafb", 108 .id_table = tgafb_pci_table, 109 .probe = tgafb_pci_register, 110 .remove = __devexit_p(tgafb_pci_unregister), 111}; 112 113static int __devinit 114tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) 115{ 116 return tgafb_register(&pdev->dev); 117} 118 119static void __devexit 120tgafb_pci_unregister(struct pci_dev *pdev) 121{ 122 tgafb_unregister(&pdev->dev); 123} 124#endif /* CONFIG_PCI */ 125 126#ifdef CONFIG_TC 127/* 128 * TC registration operations 129 */ 130static int __devinit tgafb_tc_register(struct device *); 131static int __devexit tgafb_tc_unregister(struct device *); 132 133static struct tc_device_id const tgafb_tc_table[] = { 134 { "DEC ", "PMAGD-AA" }, 135 { "DEC ", "PMAGD " }, 136 { } 137}; 138MODULE_DEVICE_TABLE(tc, tgafb_tc_table); 139 140static struct tc_driver tgafb_tc_driver = { 141 .id_table = tgafb_tc_table, 142 .driver = { 143 .name = "tgafb", 144 .bus = &tc_bus_type, 145 .probe = tgafb_tc_register, 146 .remove = __devexit_p(tgafb_tc_unregister), 147 }, 148}; 149 150static int __devinit 151tgafb_tc_register(struct device *dev) 152{ 153 int status = tgafb_register(dev); 154 if (!status) 155 get_device(dev); 156 return status; 157} 158 159static int __devexit 160tgafb_tc_unregister(struct device *dev) 161{ 162 put_device(dev); 163 tgafb_unregister(dev); 164 return 0; 165} 166#endif /* CONFIG_TC */ 167 168 169/** 170 * tgafb_check_var - Optional function. Validates a var passed in. 171 * @var: frame buffer variable screen structure 172 * @info: frame buffer structure that represents a single frame buffer 173 */ 174static int 175tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 176{ 177 struct tga_par *par = (struct tga_par *)info->par; 178 179 if (par->tga_type == TGA_TYPE_8PLANE) { 180 if (var->bits_per_pixel != 8) 181 return -EINVAL; 182 } else { 183 if (var->bits_per_pixel != 32) 184 return -EINVAL; 185 } 186 var->red.length = var->green.length = var->blue.length = 8; 187 if (var->bits_per_pixel == 32) { 188 var->red.offset = 16; 189 var->green.offset = 8; 190 var->blue.offset = 0; 191 } 192 193 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres) 194 return -EINVAL; 195 if (var->nonstd) 196 return -EINVAL; 197 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ) 198 return -EINVAL; 199 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 200 return -EINVAL; 201 202 /* Some of the acceleration routines assume the line width is 203 a multiple of 64 bytes. */ 204 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64) 205 return -EINVAL; 206 207 return 0; 208} 209 210/** 211 * tgafb_set_par - Optional function. Alters the hardware state. 212 * @info: frame buffer structure that represents a single frame buffer 213 */ 214static int 215tgafb_set_par(struct fb_info *info) 216{ 217 static unsigned int const deep_presets[4] = { 218 0x00004000, 219 0x0000440d, 220 0xffffffff, 221 0x0000441d 222 }; 223 static unsigned int const rasterop_presets[4] = { 224 0x00000003, 225 0x00000303, 226 0xffffffff, 227 0x00000303 228 }; 229 static unsigned int const mode_presets[4] = { 230 0x00000000, 231 0x00000300, 232 0xffffffff, 233 0x00000300 234 }; 235 static unsigned int const base_addr_presets[4] = { 236 0x00000000, 237 0x00000001, 238 0xffffffff, 239 0x00000001 240 }; 241 242 struct tga_par *par = (struct tga_par *) info->par; 243 int tga_bus_pci = TGA_BUS_PCI(par->dev); 244 int tga_bus_tc = TGA_BUS_TC(par->dev); 245 u32 htimings, vtimings, pll_freq; 246 u8 tga_type; 247 int i; 248 249 /* Encode video timings. */ 250 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB) 251 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB)); 252 vtimings = (info->var.yres & TGA_VERT_ACTIVE); 253 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP; 254 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP; 255 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC; 256 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC; 257 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP; 258 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP; 259 260 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 261 htimings |= TGA_HORIZ_POLARITY; 262 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 263 vtimings |= TGA_VERT_POLARITY; 264 265 par->htimings = htimings; 266 par->vtimings = vtimings; 267 268 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN); 269 270 /* Store other useful values in par. */ 271 par->xres = info->var.xres; 272 par->yres = info->var.yres; 273 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock; 274 par->bits_per_pixel = info->var.bits_per_pixel; 275 276 tga_type = par->tga_type; 277 278 /* First, disable video. */ 279 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG); 280 281 /* Write the DEEP register. */ 282 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */ 283 continue; 284 mb(); 285 TGA_WRITE_REG(par, deep_presets[tga_type] | 286 (par->sync_on_green ? 0x0 : 0x00010000), 287 TGA_DEEP_REG); 288 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */ 289 continue; 290 mb(); 291 292 /* Write some more registers. */ 293 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG); 294 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG); 295 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG); 296 297 /* Calculate & write the PLL. */ 298 tgafb_set_pll(par, pll_freq); 299 300 /* Write some more registers. */ 301 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG); 302 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG); 303 304 /* Init video timing regs. */ 305 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG); 306 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG); 307 308 /* Initalise RAMDAC. */ 309 if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) { 310 311 /* Init BT485 RAMDAC registers. */ 312 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0), 313 BT485_CMD_0); 314 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE); 315 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */ 316 BT485_WRITE(par, 0x40, BT485_CMD_1); 317 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */ 318 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK); 319 320 /* Fill palette registers. */ 321 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE); 322 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); 323 324 for (i = 0; i < 256 * 3; i += 4) { 325 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8), 326 TGA_RAMDAC_REG); 327 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8), 328 TGA_RAMDAC_REG); 329 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8), 330 TGA_RAMDAC_REG); 331 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8), 332 TGA_RAMDAC_REG); 333 } 334 335 } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) { 336 337 /* Init BT459 RAMDAC registers. */ 338 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40); 339 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00); 340 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2, 341 (par->sync_on_green ? 0xc0 : 0x40)); 342 343 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00); 344 345 /* Fill the palette. */ 346 BT459_LOAD_ADDR(par, 0x0000); 347 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG); 348 349 for (i = 0; i < 256 * 3; i += 4) { 350 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG); 351 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 352 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 353 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 354 } 355 356 } else { /* 24-plane or 24plusZ */ 357 358 /* Init BT463 RAMDAC registers. */ 359 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40); 360 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08); 361 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2, 362 (par->sync_on_green ? 0xc0 : 0x40)); 363 364 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff); 365 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff); 366 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff); 367 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f); 368 369 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00); 370 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00); 371 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00); 372 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00); 373 374 /* Fill the palette. */ 375 BT463_LOAD_ADDR(par, 0x0000); 376 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG); 377 378#ifdef CONFIG_HW_CONSOLE 379 for (i = 0; i < 16; i++) { 380 int j = color_table[i]; 381 382 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG); 383 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG); 384 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG); 385 } 386 for (i = 0; i < 512 * 3; i += 4) { 387#else 388 for (i = 0; i < 528 * 3; i += 4) { 389#endif 390 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG); 391 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 392 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 393 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 394 } 395 396 /* Fill window type table after start of vertical retrace. */ 397 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01)) 398 continue; 399 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG); 400 mb(); 401 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01)) 402 continue; 403 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG); 404 405 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE); 406 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG); 407 408 for (i = 0; i < 16; i++) { 409 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 410 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG); 411 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 412 } 413 414 } 415 416 /* Finally, enable video scan (and pray for the monitor... :-) */ 417 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG); 418 419 return 0; 420} 421 422#define DIFFCHECK(X) \ 423do { \ 424 if (m <= 0x3f) { \ 425 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \ 426 if (delta < 0) \ 427 delta = -delta; \ 428 if (delta < min_diff) \ 429 min_diff = delta, vm = m, va = a, vr = r; \ 430 } \ 431} while (0) 432 433static void 434tgafb_set_pll(struct tga_par *par, int f) 435{ 436 int n, shift, base, min_diff, target; 437 int r,a,m,vm = 34, va = 1, vr = 30; 438 439 for (r = 0 ; r < 12 ; r++) 440 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG); 441 442 if (f > TGA_PLL_MAX_FREQ) 443 f = TGA_PLL_MAX_FREQ; 444 445 if (f >= TGA_PLL_MAX_FREQ / 2) 446 shift = 0; 447 else if (f >= TGA_PLL_MAX_FREQ / 4) 448 shift = 1; 449 else 450 shift = 2; 451 452 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG); 453 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG); 454 455 for (r = 0 ; r < 10 ; r++) 456 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 457 458 if (f <= 120000) { 459 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 461 } 462 else if (f <= 200000) { 463 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 464 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 465 } 466 else { 467 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 468 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 469 } 470 471 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 472 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 473 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 474 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 475 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 476 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 477 478 target = (f << shift) / TGA_PLL_BASE_FREQ; 479 min_diff = TGA_PLL_MAX_FREQ; 480 481 r = 7 / target; 482 if (!r) r = 1; 483 484 base = target * r; 485 while (base < 449) { 486 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) { 487 m = ((n + 3) / 7) - 1; 488 a = 0; 489 DIFFCHECK((m + 1) * 7); 490 m++; 491 DIFFCHECK((m + 1) * 7); 492 m = (n / 6) - 1; 493 if ((a = n % 6)) 494 DIFFCHECK(n); 495 } 496 r++; 497 base += target; 498 } 499 500 vr--; 501 502 for (r = 0; r < 8; r++) 503 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG); 504 for (r = 0; r < 8 ; r++) 505 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG); 506 for (r = 0; r < 7 ; r++) 507 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG); 508 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG); 509} 510 511 512/** 513 * tgafb_setcolreg - Optional function. Sets a color register. 514 * @regno: boolean, 0 copy local, 1 get_user() function 515 * @red: frame buffer colormap structure 516 * @green: The green value which can be up to 16 bits wide 517 * @blue: The blue value which can be up to 16 bits wide. 518 * @transp: If supported the alpha value which can be up to 16 bits wide. 519 * @info: frame buffer info structure 520 */ 521static int 522tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, 523 unsigned transp, struct fb_info *info) 524{ 525 struct tga_par *par = (struct tga_par *) info->par; 526 int tga_bus_pci = TGA_BUS_PCI(par->dev); 527 int tga_bus_tc = TGA_BUS_TC(par->dev); 528 529 if (regno > 255) 530 return 1; 531 red >>= 8; 532 green >>= 8; 533 blue >>= 8; 534 535 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) { 536 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE); 537 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); 538 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 539 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 540 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 541 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) { 542 BT459_LOAD_ADDR(par, regno); 543 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG); 544 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG); 545 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG); 546 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG); 547 } else { 548 if (regno < 16) { 549 u32 value = (regno << 16) | (regno << 8) | regno; 550 ((u32 *)info->pseudo_palette)[regno] = value; 551 } 552 BT463_LOAD_ADDR(par, regno); 553 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG); 554 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG); 555 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG); 556 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG); 557 } 558 559 return 0; 560} 561 562 563/** 564 * tgafb_blank - Optional function. Blanks the display. 565 * @blank_mode: the blank mode we want. 566 * @info: frame buffer structure that represents a single frame buffer 567 */ 568static int 569tgafb_blank(int blank, struct fb_info *info) 570{ 571 struct tga_par *par = (struct tga_par *) info->par; 572 u32 vhcr, vvcr, vvvr; 573 unsigned long flags; 574 575 local_irq_save(flags); 576 577 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG); 578 vvcr = TGA_READ_REG(par, TGA_VERT_REG); 579 vvvr = TGA_READ_REG(par, TGA_VALID_REG); 580 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK); 581 582 switch (blank) { 583 case FB_BLANK_UNBLANK: /* Unblanking */ 584 if (par->vesa_blanked) { 585 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG); 586 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG); 587 par->vesa_blanked = 0; 588 } 589 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG); 590 break; 591 592 case FB_BLANK_NORMAL: /* Normal blanking */ 593 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK, 594 TGA_VALID_REG); 595 break; 596 597 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ 598 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG); 599 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 600 par->vesa_blanked = 1; 601 break; 602 603 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ 604 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG); 605 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 606 par->vesa_blanked = 1; 607 break; 608 609 case FB_BLANK_POWERDOWN: /* Poweroff */ 610 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG); 611 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG); 612 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 613 par->vesa_blanked = 1; 614 break; 615 } 616 617 local_irq_restore(flags); 618 return 0; 619} 620 621 622/* 623 * Acceleration. 624 */ 625 626static void 627tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image) 628{ 629 struct tga_par *par = (struct tga_par *) info->par; 630 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask; 631 unsigned long rincr, line_length, shift, pos, is8bpp; 632 unsigned long i, j; 633 const unsigned char *data; 634 void __iomem *regs_base; 635 void __iomem *fb_base; 636 637 is8bpp = info->var.bits_per_pixel == 8; 638 639 /* For copies that aren't pixel expansion, there's little we 640 can do better than the generic code. */ 641 /* ??? There is a DMA write mode; I wonder if that could be 642 made to pull the data from the image buffer... */ 643 if (image->depth > 1) { 644 cfb_imageblit(info, image); 645 return; 646 } 647 648 dx = image->dx; 649 dy = image->dy; 650 width = image->width; 651 height = image->height; 652 vxres = info->var.xres_virtual; 653 vyres = info->var.yres_virtual; 654 line_length = info->fix.line_length; 655 rincr = (width + 7) / 8; 656 657 /* Crop the image to the screen. */ 658 if (dx > vxres || dy > vyres) 659 return; 660 if (dx + width > vxres) 661 width = vxres - dx; 662 if (dy + height > vyres) 663 height = vyres - dy; 664 665 regs_base = par->tga_regs_base; 666 fb_base = par->tga_fb_base; 667 668 /* Expand the color values to fill 32-bits. */ 669 /* ??? Would be nice to notice colour changes elsewhere, so 670 that we can do this only when necessary. */ 671 fgcolor = image->fg_color; 672 bgcolor = image->bg_color; 673 if (is8bpp) { 674 fgcolor |= fgcolor << 8; 675 fgcolor |= fgcolor << 16; 676 bgcolor |= bgcolor << 8; 677 bgcolor |= bgcolor << 16; 678 } else { 679 if (fgcolor < 16) 680 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor]; 681 if (bgcolor < 16) 682 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor]; 683 } 684 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG); 685 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG); 686 687 /* Acquire proper alignment; set up the PIXELMASK register 688 so that we only write the proper character cell. */ 689 pos = dy * line_length; 690 if (is8bpp) { 691 pos += dx; 692 shift = pos & 3; 693 pos &= -4; 694 } else { 695 pos += dx * 4; 696 shift = (pos & 7) >> 2; 697 pos &= -8; 698 } 699 700 data = (const unsigned char *) image->data; 701 702 /* Enable opaque stipple mode. */ 703 __raw_writel((is8bpp 704 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE 705 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE), 706 regs_base + TGA_MODE_REG); 707 708 if (width + shift <= 32) { 709 unsigned long bwidth; 710 711 /* Handle common case of imaging a single character, in 712 a font less than 32 pixels wide. */ 713 714 pixelmask = (1 << width) - 1; 715 pixelmask <<= shift; 716 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 717 wmb(); 718 719 bwidth = (width + 7) / 8; 720 721 for (i = 0; i < height; ++i) { 722 u32 mask = 0; 723 724 /* The image data is bit big endian; we need 725 little endian. */ 726 for (j = 0; j < bwidth; ++j) 727 mask |= bitrev8(data[j]) << (j * 8); 728 729 __raw_writel(mask << shift, fb_base + pos); 730 731 pos += line_length; 732 data += rincr; 733 } 734 wmb(); 735 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); 736 } else if (shift == 0) { 737 unsigned long pos0 = pos; 738 const unsigned char *data0 = data; 739 unsigned long bincr = (is8bpp ? 8 : 8*4); 740 unsigned long bwidth; 741 742 /* Handle another common case in which accel_putcs 743 generates a large bitmap, which happens to be aligned. 744 Allow the tail to be misaligned. This case is 745 interesting because we've not got to hold partial 746 bytes across the words being written. */ 747 748 wmb(); 749 750 bwidth = (width / 8) & -4; 751 for (i = 0; i < height; ++i) { 752 for (j = 0; j < bwidth; j += 4) { 753 u32 mask = 0; 754 mask |= bitrev8(data[j+0]) << (0 * 8); 755 mask |= bitrev8(data[j+1]) << (1 * 8); 756 mask |= bitrev8(data[j+2]) << (2 * 8); 757 mask |= bitrev8(data[j+3]) << (3 * 8); 758 __raw_writel(mask, fb_base + pos + j*bincr); 759 } 760 pos += line_length; 761 data += rincr; 762 } 763 wmb(); 764 765 pixelmask = (1ul << (width & 31)) - 1; 766 if (pixelmask) { 767 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 768 wmb(); 769 770 pos = pos0 + bwidth*bincr; 771 data = data0 + bwidth; 772 bwidth = ((width & 31) + 7) / 8; 773 774 for (i = 0; i < height; ++i) { 775 u32 mask = 0; 776 for (j = 0; j < bwidth; ++j) 777 mask |= bitrev8(data[j]) << (j * 8); 778 __raw_writel(mask, fb_base + pos); 779 pos += line_length; 780 data += rincr; 781 } 782 wmb(); 783 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); 784 } 785 } else { 786 unsigned long pos0 = pos; 787 const unsigned char *data0 = data; 788 unsigned long bincr = (is8bpp ? 8 : 8*4); 789 unsigned long bwidth; 790 791 /* Finally, handle the generic case of misaligned start. 792 Here we split the write into 16-bit spans. This allows 793 us to use only one pixel mask, instead of four as would 794 be required by writing 24-bit spans. */ 795 796 pixelmask = 0xffff << shift; 797 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 798 wmb(); 799 800 bwidth = (width / 8) & -2; 801 for (i = 0; i < height; ++i) { 802 for (j = 0; j < bwidth; j += 2) { 803 u32 mask = 0; 804 mask |= bitrev8(data[j+0]) << (0 * 8); 805 mask |= bitrev8(data[j+1]) << (1 * 8); 806 mask <<= shift; 807 __raw_writel(mask, fb_base + pos + j*bincr); 808 } 809 pos += line_length; 810 data += rincr; 811 } 812 wmb(); 813 814 pixelmask = ((1ul << (width & 15)) - 1) << shift; 815 if (pixelmask) { 816 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 817 wmb(); 818 819 pos = pos0 + bwidth*bincr; 820 data = data0 + bwidth; 821 bwidth = (width & 15) > 8; 822 823 for (i = 0; i < height; ++i) { 824 u32 mask = bitrev8(data[0]); 825 if (bwidth) 826 mask |= bitrev8(data[1]) << 8; 827 mask <<= shift; 828 __raw_writel(mask, fb_base + pos); 829 pos += line_length; 830 data += rincr; 831 } 832 wmb(); 833 } 834 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); 835 } 836 837 /* Disable opaque stipple mode. */ 838 __raw_writel((is8bpp 839 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE 840 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE), 841 regs_base + TGA_MODE_REG); 842} 843 844static void 845tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image) 846{ 847 struct tga_par *par = (struct tga_par *) info->par; 848 u32 color, dx, dy, width, height, vxres, vyres; 849 u32 *palette = ((u32 *)info->pseudo_palette); 850 unsigned long pos, line_length, i, j; 851 const unsigned char *data; 852 void *regs_base, *fb_base; 853 854 dx = image->dx; 855 dy = image->dy; 856 width = image->width; 857 height = image->height; 858 vxres = info->var.xres_virtual; 859 vyres = info->var.yres_virtual; 860 line_length = info->fix.line_length; 861 862 /* Crop the image to the screen. */ 863 if (dx > vxres || dy > vyres) 864 return; 865 if (dx + width > vxres) 866 width = vxres - dx; 867 if (dy + height > vyres) 868 height = vyres - dy; 869 870 regs_base = par->tga_regs_base; 871 fb_base = par->tga_fb_base; 872 873 pos = dy * line_length + (dx * 4); 874 data = image->data; 875 876 /* Now copy the image, color_expanding via the palette. */ 877 for (i = 0; i < height; i++) { 878 for (j = 0; j < width; j++) { 879 color = palette[*data++]; 880 __raw_writel(color, fb_base + pos + j*4); 881 } 882 pos += line_length; 883 } 884} 885 886/** 887 * tgafb_imageblit - REQUIRED function. Can use generic routines if 888 * non acclerated hardware and packed pixel based. 889 * Copies a image from system memory to the screen. 890 * 891 * @info: frame buffer structure that represents a single frame buffer 892 * @image: structure defining the image. 893 */ 894static void 895tgafb_imageblit(struct fb_info *info, const struct fb_image *image) 896{ 897 unsigned int is8bpp = info->var.bits_per_pixel == 8; 898 899 /* If a mono image, regardless of FB depth, go do it. */ 900 if (image->depth == 1) { 901 tgafb_mono_imageblit(info, image); 902 return; 903 } 904 905 /* For copies that aren't pixel expansion, there's little we 906 can do better than the generic code. */ 907 /* ??? There is a DMA write mode; I wonder if that could be 908 made to pull the data from the image buffer... */ 909 if (image->depth == info->var.bits_per_pixel) { 910 cfb_imageblit(info, image); 911 return; 912 } 913 914 /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */ 915 if (!is8bpp && image->depth == 8) { 916 tgafb_clut_imageblit(info, image); 917 return; 918 } 919 920 /* Silently return... */ 921} 922 923/** 924 * tgafb_fillrect - REQUIRED function. Can use generic routines if 925 * non acclerated hardware and packed pixel based. 926 * Draws a rectangle on the screen. 927 * 928 * @info: frame buffer structure that represents a single frame buffer 929 * @rect: structure defining the rectagle and operation. 930 */ 931static void 932tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 933{ 934 struct tga_par *par = (struct tga_par *) info->par; 935 int is8bpp = info->var.bits_per_pixel == 8; 936 u32 dx, dy, width, height, vxres, vyres, color; 937 unsigned long pos, align, line_length, i, j; 938 void __iomem *regs_base; 939 void __iomem *fb_base; 940 941 dx = rect->dx; 942 dy = rect->dy; 943 width = rect->width; 944 height = rect->height; 945 vxres = info->var.xres_virtual; 946 vyres = info->var.yres_virtual; 947 line_length = info->fix.line_length; 948 regs_base = par->tga_regs_base; 949 fb_base = par->tga_fb_base; 950 951 /* Crop the rectangle to the screen. */ 952 if (dx > vxres || dy > vyres || !width || !height) 953 return; 954 if (dx + width > vxres) 955 width = vxres - dx; 956 if (dy + height > vyres) 957 height = vyres - dy; 958 959 pos = dy * line_length + dx * (is8bpp ? 1 : 4); 960 961 /* ??? We could implement ROP_XOR with opaque fill mode 962 and a RasterOp setting of GXxor, but as far as I can 963 tell, this mode is not actually used in the kernel. 964 Thus I am ignoring it for now. */ 965 if (rect->rop != ROP_COPY) { 966 cfb_fillrect(info, rect); 967 return; 968 } 969 970 /* Expand the color value to fill 8 pixels. */ 971 color = rect->color; 972 if (is8bpp) { 973 color |= color << 8; 974 color |= color << 16; 975 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG); 976 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG); 977 } else { 978 if (color < 16) 979 color = ((u32 *)info->pseudo_palette)[color]; 980 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG); 981 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG); 982 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG); 983 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG); 984 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG); 985 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG); 986 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG); 987 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG); 988 } 989 990 /* The DATA register holds the fill mask for block fill mode. 991 Since we're not stippling, this is all ones. */ 992 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG); 993 994 /* Enable block fill mode. */ 995 __raw_writel((is8bpp 996 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL 997 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL), 998 regs_base + TGA_MODE_REG); 999 wmb(); 1000 1001 /* We can fill 2k pixels per operation. Notice blocks that fit 1002 the width of the screen so that we can take advantage of this 1003 and fill more than one line per write. */ 1004 if (width == line_length) 1005 width *= height, height = 1; 1006 1007 /* The write into the frame buffer must be aligned to 4 bytes, 1008 but we are allowed to encode the offset within the word in 1009 the data word written. */ 1010 align = (pos & 3) << 16; 1011 pos &= -4; 1012 1013 if (width <= 2048) { 1014 u32 data; 1015 1016 data = (width - 1) | align; 1017 1018 for (i = 0; i < height; ++i) { 1019 __raw_writel(data, fb_base + pos); 1020 pos += line_length; 1021 } 1022 } else { 1023 unsigned long Bpp = (is8bpp ? 1 : 4); 1024 unsigned long nwidth = width & -2048; 1025 u32 fdata, ldata; 1026 1027 fdata = (2048 - 1) | align; 1028 ldata = ((width & 2047) - 1) | align; 1029 1030 for (i = 0; i < height; ++i) { 1031 for (j = 0; j < nwidth; j += 2048) 1032 __raw_writel(fdata, fb_base + pos + j*Bpp); 1033 if (j < width) 1034 __raw_writel(ldata, fb_base + pos + j*Bpp); 1035 pos += line_length; 1036 } 1037 } 1038 wmb(); 1039 1040 /* Disable block fill mode. */ 1041 __raw_writel((is8bpp 1042 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE 1043 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE), 1044 regs_base + TGA_MODE_REG); 1045} 1046 1047/** 1048 * tgafb_copyarea - REQUIRED function. Can use generic routines if 1049 * non acclerated hardware and packed pixel based. 1050 * Copies on area of the screen to another area. 1051 * 1052 * @info: frame buffer structure that represents a single frame buffer 1053 * @area: structure defining the source and destination. 1054 */ 1055 1056/* Handle the special case of copying entire lines, e.g. during scrolling. 1057 We can avoid a lot of needless computation in this case. In the 8bpp 1058 case we need to use the COPY64 registers instead of mask writes into 1059 the frame buffer to achieve maximum performance. */ 1060 1061static inline void 1062copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy, 1063 u32 height, u32 width) 1064{ 1065 struct tga_par *par = (struct tga_par *) info->par; 1066 void __iomem *tga_regs = par->tga_regs_base; 1067 unsigned long dpos, spos, i, n64; 1068 1069 /* Set up the MODE and PIXELSHIFT registers. */ 1070 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG); 1071 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); 1072 wmb(); 1073 1074 n64 = (height * width) / 64; 1075 1076 if (sy < dy) { 1077 spos = (sy + height) * width; 1078 dpos = (dy + height) * width; 1079 1080 for (i = 0; i < n64; ++i) { 1081 spos -= 64; 1082 dpos -= 64; 1083 __raw_writel(spos, tga_regs+TGA_COPY64_SRC); 1084 wmb(); 1085 __raw_writel(dpos, tga_regs+TGA_COPY64_DST); 1086 wmb(); 1087 } 1088 } else { 1089 spos = sy * width; 1090 dpos = dy * width; 1091 1092 for (i = 0; i < n64; ++i) { 1093 __raw_writel(spos, tga_regs+TGA_COPY64_SRC); 1094 wmb(); 1095 __raw_writel(dpos, tga_regs+TGA_COPY64_DST); 1096 wmb(); 1097 spos += 64; 1098 dpos += 64; 1099 } 1100 } 1101 1102 /* Reset the MODE register to normal. */ 1103 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); 1104} 1105 1106static inline void 1107copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy, 1108 u32 height, u32 width) 1109{ 1110 struct tga_par *par = (struct tga_par *) info->par; 1111 void __iomem *tga_regs = par->tga_regs_base; 1112 void __iomem *tga_fb = par->tga_fb_base; 1113 void __iomem *src; 1114 void __iomem *dst; 1115 unsigned long i, n16; 1116 1117 /* Set up the MODE and PIXELSHIFT registers. */ 1118 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG); 1119 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); 1120 wmb(); 1121 1122 n16 = (height * width) / 16; 1123 1124 if (sy < dy) { 1125 src = tga_fb + (sy + height) * width * 4; 1126 dst = tga_fb + (dy + height) * width * 4; 1127 1128 for (i = 0; i < n16; ++i) { 1129 src -= 64; 1130 dst -= 64; 1131 __raw_writel(0xffff, src); 1132 wmb(); 1133 __raw_writel(0xffff, dst); 1134 wmb(); 1135 } 1136 } else { 1137 src = tga_fb + sy * width * 4; 1138 dst = tga_fb + dy * width * 4; 1139 1140 for (i = 0; i < n16; ++i) { 1141 __raw_writel(0xffff, src); 1142 wmb(); 1143 __raw_writel(0xffff, dst); 1144 wmb(); 1145 src += 64; 1146 dst += 64; 1147 } 1148 } 1149 1150 /* Reset the MODE register to normal. */ 1151 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); 1152} 1153 1154/* The general case of forward copy in 8bpp mode. */ 1155static inline void 1156copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy, 1157 u32 height, u32 width, u32 line_length) 1158{ 1159 struct tga_par *par = (struct tga_par *) info->par; 1160 unsigned long i, copied, left; 1161 unsigned long dpos, spos, dalign, salign, yincr; 1162 u32 smask_first, dmask_first, dmask_last; 1163 int pixel_shift, need_prime, need_second; 1164 unsigned long n64, n32, xincr_first; 1165 void __iomem *tga_regs; 1166 void __iomem *tga_fb; 1167 1168 yincr = line_length; 1169 if (dy > sy) { 1170 dy += height - 1; 1171 sy += height - 1; 1172 yincr = -yincr; 1173 } 1174 1175 /* Compute the offsets and alignments in the frame buffer. 1176 More than anything else, these control how we do copies. */ 1177 dpos = dy * line_length + dx; 1178 spos = sy * line_length + sx; 1179 dalign = dpos & 7; 1180 salign = spos & 7; 1181 dpos &= -8; 1182 spos &= -8; 1183 1184 /* Compute the value for the PIXELSHIFT register. This controls 1185 both non-co-aligned source and destination and copy direction. */ 1186 if (dalign >= salign) 1187 pixel_shift = dalign - salign; 1188 else 1189 pixel_shift = 8 - (salign - dalign); 1190 1191 /* Figure out if we need an additional priming step for the 1192 residue register. */ 1193 need_prime = (salign > dalign); 1194 if (need_prime) 1195 dpos -= 8; 1196 1197 /* Begin by copying the leading unaligned destination. Copy enough 1198 to make the next destination address 32-byte aligned. */ 1199 copied = 32 - (dalign + (dpos & 31)); 1200 if (copied == 32) 1201 copied = 0; 1202 xincr_first = (copied + 7) & -8; 1203 smask_first = dmask_first = (1ul << copied) - 1; 1204 smask_first <<= salign; 1205 dmask_first <<= dalign + need_prime*8; 1206 if (need_prime && copied > 24) 1207 copied -= 8; 1208 left = width - copied; 1209 1210 /* Care for small copies. */ 1211 if (copied > width) { 1212 u32 t; 1213 t = (1ul << width) - 1; 1214 t <<= dalign + need_prime*8; 1215 dmask_first &= t; 1216 left = 0; 1217 } 1218 1219 /* Attempt to use 64-byte copies. This is only possible if the 1220 source and destination are co-aligned at 64 bytes. */ 1221 n64 = need_second = 0; 1222 if ((dpos & 63) == (spos & 63) 1223 && (height == 1 || line_length % 64 == 0)) { 1224 /* We may need a 32-byte copy to ensure 64 byte alignment. */ 1225 need_second = (dpos + xincr_first) & 63; 1226 if ((need_second & 32) != need_second) 1227 printk(KERN_ERR "tgafb: need_second wrong\n"); 1228 if (left >= need_second + 64) { 1229 left -= need_second; 1230 n64 = left / 64; 1231 left %= 64; 1232 } else 1233 need_second = 0; 1234 } 1235 1236 /* Copy trailing full 32-byte sections. This will be the main 1237 loop if the 64 byte loop can't be used. */ 1238 n32 = left / 32; 1239 left %= 32; 1240 1241 /* Copy the trailing unaligned destination. */ 1242 dmask_last = (1ul << left) - 1; 1243 1244 tga_regs = par->tga_regs_base; 1245 tga_fb = par->tga_fb_base; 1246 1247 /* Set up the MODE and PIXELSHIFT registers. */ 1248 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG); 1249 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG); 1250 wmb(); 1251 1252 for (i = 0; i < height; ++i) { 1253 unsigned long j; 1254 void __iomem *sfb; 1255 void __iomem *dfb; 1256 1257 sfb = tga_fb + spos; 1258 dfb = tga_fb + dpos; 1259 if (dmask_first) { 1260 __raw_writel(smask_first, sfb); 1261 wmb(); 1262 __raw_writel(dmask_first, dfb); 1263 wmb(); 1264 sfb += xincr_first; 1265 dfb += xincr_first; 1266 } 1267 1268 if (need_second) { 1269 __raw_writel(0xffffffff, sfb); 1270 wmb(); 1271 __raw_writel(0xffffffff, dfb); 1272 wmb(); 1273 sfb += 32; 1274 dfb += 32; 1275 } 1276 1277 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63)) 1278 printk(KERN_ERR 1279 "tgafb: misaligned copy64 (s:%p, d:%p)\n", 1280 sfb, dfb); 1281 1282 for (j = 0; j < n64; ++j) { 1283 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC); 1284 wmb(); 1285 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST); 1286 wmb(); 1287 sfb += 64; 1288 dfb += 64; 1289 } 1290 1291 for (j = 0; j < n32; ++j) { 1292 __raw_writel(0xffffffff, sfb); 1293 wmb(); 1294 __raw_writel(0xffffffff, dfb); 1295 wmb(); 1296 sfb += 32; 1297 dfb += 32; 1298 } 1299 1300 if (dmask_last) { 1301 __raw_writel(0xffffffff, sfb); 1302 wmb(); 1303 __raw_writel(dmask_last, dfb); 1304 wmb(); 1305 } 1306 1307 spos += yincr; 1308 dpos += yincr; 1309 } 1310 1311 /* Reset the MODE register to normal. */ 1312 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); 1313} 1314 1315/* The (almost) general case of backward copy in 8bpp mode. */ 1316static inline void 1317copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy, 1318 u32 height, u32 width, u32 line_length, 1319 const struct fb_copyarea *area) 1320{ 1321 struct tga_par *par = (struct tga_par *) info->par; 1322 unsigned long i, left, yincr; 1323 unsigned long depos, sepos, dealign, sealign; 1324 u32 mask_first, mask_last; 1325 unsigned long n32; 1326 void __iomem *tga_regs; 1327 void __iomem *tga_fb; 1328 1329 yincr = line_length; 1330 if (dy > sy) { 1331 dy += height - 1; 1332 sy += height - 1; 1333 yincr = -yincr; 1334 } 1335 1336 /* Compute the offsets and alignments in the frame buffer. 1337 More than anything else, these control how we do copies. */ 1338 depos = dy * line_length + dx + width; 1339 sepos = sy * line_length + sx + width; 1340 dealign = depos & 7; 1341 sealign = sepos & 7; 1342 1343 /* ??? The documentation appears to be incorrect (or very 1344 misleading) wrt how pixel shifting works in backward copy 1345 mode, i.e. when PIXELSHIFT is negative. I give up for now. 1346 Do handle the common case of co-aligned backward copies, 1347 but frob everything else back on generic code. */ 1348 if (dealign != sealign) { 1349 cfb_copyarea(info, area); 1350 return; 1351 } 1352 1353 /* We begin the copy with the trailing pixels of the 1354 unaligned destination. */ 1355 mask_first = (1ul << dealign) - 1; 1356 left = width - dealign; 1357 1358 /* Care for small copies. */ 1359 if (dealign > width) { 1360 mask_first ^= (1ul << (dealign - width)) - 1; 1361 left = 0; 1362 } 1363 1364 /* Next copy full words at a time. */ 1365 n32 = left / 32; 1366 left %= 32; 1367 1368 /* Finally copy the unaligned head of the span. */ 1369 mask_last = -1 << (32 - left); 1370 1371 tga_regs = par->tga_regs_base; 1372 tga_fb = par->tga_fb_base; 1373 1374 /* Set up the MODE and PIXELSHIFT registers. */ 1375 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG); 1376 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); 1377 wmb(); 1378 1379 for (i = 0; i < height; ++i) { 1380 unsigned long j; 1381 void __iomem *sfb; 1382 void __iomem *dfb; 1383 1384 sfb = tga_fb + sepos; 1385 dfb = tga_fb + depos; 1386 if (mask_first) { 1387 __raw_writel(mask_first, sfb); 1388 wmb(); 1389 __raw_writel(mask_first, dfb); 1390 wmb(); 1391 } 1392 1393 for (j = 0; j < n32; ++j) { 1394 sfb -= 32; 1395 dfb -= 32; 1396 __raw_writel(0xffffffff, sfb); 1397 wmb(); 1398 __raw_writel(0xffffffff, dfb); 1399 wmb(); 1400 } 1401 1402 if (mask_last) { 1403 sfb -= 32; 1404 dfb -= 32; 1405 __raw_writel(mask_last, sfb); 1406 wmb(); 1407 __raw_writel(mask_last, dfb); 1408 wmb(); 1409 } 1410 1411 sepos += yincr; 1412 depos += yincr; 1413 } 1414 1415 /* Reset the MODE register to normal. */ 1416 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); 1417} 1418 1419static void 1420tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 1421{ 1422 unsigned long dx, dy, width, height, sx, sy, vxres, vyres; 1423 unsigned long line_length, bpp; 1424 1425 dx = area->dx; 1426 dy = area->dy; 1427 width = area->width; 1428 height = area->height; 1429 sx = area->sx; 1430 sy = area->sy; 1431 vxres = info->var.xres_virtual; 1432 vyres = info->var.yres_virtual; 1433 line_length = info->fix.line_length; 1434 1435 /* The top left corners must be in the virtual screen. */ 1436 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres) 1437 return; 1438 1439 /* Clip the destination. */ 1440 if (dx + width > vxres) 1441 width = vxres - dx; 1442 if (dy + height > vyres) 1443 height = vyres - dy; 1444 1445 /* The source must be completely inside the virtual screen. */ 1446 if (sx + width > vxres || sy + height > vyres) 1447 return; 1448 1449 bpp = info->var.bits_per_pixel; 1450 1451 /* Detect copies of the entire line. */ 1452 if (width * (bpp >> 3) == line_length) { 1453 if (bpp == 8) 1454 copyarea_line_8bpp(info, dy, sy, height, width); 1455 else 1456 copyarea_line_32bpp(info, dy, sy, height, width); 1457 } 1458 1459 /* ??? The documentation is unclear to me exactly how the pixelshift 1460 register works in 32bpp mode. Since I don't have hardware to test, 1461 give up for now and fall back on the generic routines. */ 1462 else if (bpp == 32) 1463 cfb_copyarea(info, area); 1464 1465 /* Detect overlapping source and destination that requires 1466 a backward copy. */ 1467 else if (dy == sy && dx > sx && dx < sx + width) 1468 copyarea_backward_8bpp(info, dx, dy, sx, sy, height, 1469 width, line_length, area); 1470 else 1471 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height, 1472 width, line_length); 1473} 1474 1475 1476/* 1477 * Initialisation 1478 */ 1479 1480static void 1481tgafb_init_fix(struct fb_info *info) 1482{ 1483 struct tga_par *par = (struct tga_par *)info->par; 1484 int tga_bus_pci = TGA_BUS_PCI(par->dev); 1485 int tga_bus_tc = TGA_BUS_TC(par->dev); 1486 u8 tga_type = par->tga_type; 1487 const char *tga_type_name = NULL; 1488 1489 switch (tga_type) { 1490 case TGA_TYPE_8PLANE: 1491 if (tga_bus_pci) 1492 tga_type_name = "Digital ZLXp-E1"; 1493 if (tga_bus_tc) 1494 tga_type_name = "Digital ZLX-E1"; 1495 break; 1496 case TGA_TYPE_24PLANE: 1497 if (tga_bus_pci) 1498 tga_type_name = "Digital ZLXp-E2"; 1499 if (tga_bus_tc) 1500 tga_type_name = "Digital ZLX-E2"; 1501 break; 1502 case TGA_TYPE_24PLUSZ: 1503 if (tga_bus_pci) 1504 tga_type_name = "Digital ZLXp-E3"; 1505 if (tga_bus_tc) 1506 tga_type_name = "Digital ZLX-E3"; 1507 break; 1508 default: 1509 tga_type_name = "Unknown"; 1510 break; 1511 } 1512 1513 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id)); 1514 1515 info->fix.type = FB_TYPE_PACKED_PIXELS; 1516 info->fix.type_aux = 0; 1517 info->fix.visual = (tga_type == TGA_TYPE_8PLANE 1518 ? FB_VISUAL_PSEUDOCOLOR 1519 : FB_VISUAL_DIRECTCOLOR); 1520 1521 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3); 1522 info->fix.smem_start = (size_t) par->tga_fb_base; 1523 info->fix.smem_len = info->fix.line_length * par->yres; 1524 info->fix.mmio_start = (size_t) par->tga_regs_base; 1525 info->fix.mmio_len = 512; 1526 1527 info->fix.xpanstep = 0; 1528 info->fix.ypanstep = 0; 1529 info->fix.ywrapstep = 0; 1530 1531 info->fix.accel = FB_ACCEL_DEC_TGA; 1532 1533 /* 1534 * These are needed by fb_set_logo_truepalette(), so we 1535 * set them here for 24-plane cards. 1536 */ 1537 if (tga_type != TGA_TYPE_8PLANE) { 1538 info->var.red.length = 8; 1539 info->var.green.length = 8; 1540 info->var.blue.length = 8; 1541 info->var.red.offset = 16; 1542 info->var.green.offset = 8; 1543 info->var.blue.offset = 0; 1544 } 1545} 1546 1547static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 1548{ 1549 /* We just use this to catch switches out of graphics mode. */ 1550 tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */ 1551 return 0; 1552} 1553 1554static int __devinit 1555tgafb_register(struct device *dev) 1556{ 1557 static const struct fb_videomode modedb_tc = { 1558 /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */ 1559 "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3, 1560 FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED 1561 }; 1562 1563 static unsigned int const fb_offset_presets[4] = { 1564 TGA_8PLANE_FB_OFFSET, 1565 TGA_24PLANE_FB_OFFSET, 1566 0xffffffff, 1567 TGA_24PLUSZ_FB_OFFSET 1568 }; 1569 1570 const struct fb_videomode *modedb_tga = NULL; 1571 resource_size_t bar0_start = 0, bar0_len = 0; 1572 const char *mode_option_tga = NULL; 1573 int tga_bus_pci = TGA_BUS_PCI(dev); 1574 int tga_bus_tc = TGA_BUS_TC(dev); 1575 unsigned int modedbsize_tga = 0; 1576 void __iomem *mem_base; 1577 struct fb_info *info; 1578 struct tga_par *par; 1579 u8 tga_type; 1580 int ret = 0; 1581 1582 /* Enable device in PCI config. */ 1583 if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) { 1584 printk(KERN_ERR "tgafb: Cannot enable PCI device\n"); 1585 return -ENODEV; 1586 } 1587 1588 /* Allocate the fb and par structures. */ 1589 info = framebuffer_alloc(sizeof(struct tga_par), dev); 1590 if (!info) { 1591 printk(KERN_ERR "tgafb: Cannot allocate memory\n"); 1592 return -ENOMEM; 1593 } 1594 1595 par = info->par; 1596 dev_set_drvdata(dev, info); 1597 1598 /* Request the mem regions. */ 1599 ret = -ENODEV; 1600 if (tga_bus_pci) { 1601 bar0_start = pci_resource_start(to_pci_dev(dev), 0); 1602 bar0_len = pci_resource_len(to_pci_dev(dev), 0); 1603 } 1604 if (tga_bus_tc) { 1605 bar0_start = to_tc_dev(dev)->resource.start; 1606 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1; 1607 } 1608 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) { 1609 printk(KERN_ERR "tgafb: cannot reserve FB region\n"); 1610 goto err0; 1611 } 1612 1613 /* Map the framebuffer. */ 1614 mem_base = ioremap_nocache(bar0_start, bar0_len); 1615 if (!mem_base) { 1616 printk(KERN_ERR "tgafb: Cannot map MMIO\n"); 1617 goto err1; 1618 } 1619 1620 /* Grab info about the card. */ 1621 tga_type = (readl(mem_base) >> 12) & 0x0f; 1622 par->dev = dev; 1623 par->tga_mem_base = mem_base; 1624 par->tga_fb_base = mem_base + fb_offset_presets[tga_type]; 1625 par->tga_regs_base = mem_base + TGA_REGS_OFFSET; 1626 par->tga_type = tga_type; 1627 if (tga_bus_pci) 1628 pci_read_config_byte(to_pci_dev(dev), PCI_REVISION_ID, 1629 &par->tga_chip_rev); 1630 if (tga_bus_tc) 1631 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff; 1632 1633 /* Setup framebuffer. */ 1634 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | 1635 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT; 1636 info->fbops = &tgafb_ops; 1637 info->screen_base = par->tga_fb_base; 1638 info->pseudo_palette = (void *)(par + 1); 1639 1640 /* This should give a reasonable default video mode. */ 1641 if (tga_bus_pci) { 1642 mode_option_tga = mode_option_pci; 1643 } 1644 if (tga_bus_tc) { 1645 mode_option_tga = mode_option_tc; 1646 modedb_tga = &modedb_tc; 1647 modedbsize_tga = 1; 1648 } 1649 ret = fb_find_mode(&info->var, info, 1650 mode_option ? mode_option : mode_option_tga, 1651 modedb_tga, modedbsize_tga, NULL, 1652 tga_type == TGA_TYPE_8PLANE ? 8 : 32); 1653 if (ret == 0 || ret == 4) { 1654 printk(KERN_ERR "tgafb: Could not find valid video mode\n"); 1655 ret = -EINVAL; 1656 goto err1; 1657 } 1658 1659 if (fb_alloc_cmap(&info->cmap, 256, 0)) { 1660 printk(KERN_ERR "tgafb: Could not allocate color map\n"); 1661 ret = -ENOMEM; 1662 goto err1; 1663 } 1664 1665 tgafb_set_par(info); 1666 tgafb_init_fix(info); 1667 1668 if (register_framebuffer(info) < 0) { 1669 printk(KERN_ERR "tgafb: Could not register framebuffer\n"); 1670 ret = -EINVAL; 1671 goto err1; 1672 } 1673 1674 if (tga_bus_pci) { 1675 pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n", 1676 par->tga_chip_rev); 1677 pr_info("tgafb: at PCI bus %d, device %d, function %d\n", 1678 to_pci_dev(dev)->bus->number, 1679 PCI_SLOT(to_pci_dev(dev)->devfn), 1680 PCI_FUNC(to_pci_dev(dev)->devfn)); 1681 } 1682 if (tga_bus_tc) 1683 pr_info("tgafb: SFB+ detected, rev=0x%02x\n", 1684 par->tga_chip_rev); 1685 pr_info("fb%d: %s frame buffer device at 0x%lx\n", 1686 info->node, info->fix.id, (long)bar0_start); 1687 1688 return 0; 1689 1690 err1: 1691 if (mem_base) 1692 iounmap(mem_base); 1693 release_mem_region(bar0_start, bar0_len); 1694 err0: 1695 framebuffer_release(info); 1696 return ret; 1697} 1698 1699static void __devexit 1700tgafb_unregister(struct device *dev) 1701{ 1702 resource_size_t bar0_start = 0, bar0_len = 0; 1703 int tga_bus_pci = TGA_BUS_PCI(dev); 1704 int tga_bus_tc = TGA_BUS_TC(dev); 1705 struct fb_info *info = NULL; 1706 struct tga_par *par; 1707 1708 info = dev_get_drvdata(dev); 1709 if (!info) 1710 return; 1711 1712 par = info->par; 1713 unregister_framebuffer(info); 1714 fb_dealloc_cmap(&info->cmap); 1715 iounmap(par->tga_mem_base); 1716 if (tga_bus_pci) { 1717 bar0_start = pci_resource_start(to_pci_dev(dev), 0); 1718 bar0_len = pci_resource_len(to_pci_dev(dev), 0); 1719 } 1720 if (tga_bus_tc) { 1721 bar0_start = to_tc_dev(dev)->resource.start; 1722 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1; 1723 } 1724 release_mem_region(bar0_start, bar0_len); 1725 framebuffer_release(info); 1726} 1727 1728static void __devexit 1729tgafb_exit(void) 1730{ 1731 tc_unregister_driver(&tgafb_tc_driver); 1732 pci_unregister_driver(&tgafb_pci_driver); 1733} 1734 1735#ifndef MODULE 1736static int __devinit 1737tgafb_setup(char *arg) 1738{ 1739 char *this_opt; 1740 1741 if (arg && *arg) { 1742 while ((this_opt = strsep(&arg, ","))) { 1743 if (!*this_opt) 1744 continue; 1745 if (!strncmp(this_opt, "mode:", 5)) 1746 mode_option = this_opt+5; 1747 else 1748 printk(KERN_ERR 1749 "tgafb: unknown parameter %s\n", 1750 this_opt); 1751 } 1752 } 1753 1754 return 0; 1755} 1756#endif /* !MODULE */ 1757 1758static int __devinit 1759tgafb_init(void) 1760{ 1761 int status; 1762#ifndef MODULE 1763 char *option = NULL; 1764 1765 if (fb_get_options("tgafb", &option)) 1766 return -ENODEV; 1767 tgafb_setup(option); 1768#endif 1769 status = pci_register_driver(&tgafb_pci_driver); 1770 if (!status) 1771 status = tc_register_driver(&tgafb_tc_driver); 1772 return status; 1773} 1774 1775/* 1776 * Modularisation 1777 */ 1778 1779module_init(tgafb_init); 1780module_exit(tgafb_exit); 1781 1782MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset"); 1783MODULE_LICENSE("GPL"); 1784