1/* 2 * Geode GX display controller. 3 * 4 * Copyright (C) 2005 Arcom Control Systems Ltd. 5 * 6 * Portions from AMD's original 2.4 driver: 7 * Copyright (C) 2004 Advanced Micro Devices, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by * the 11 * Free Software Foundation; either version 2 of the License, or * (at your 12 * option) any later version. 13 */ 14#include <linux/spinlock.h> 15#include <linux/fb.h> 16#include <linux/delay.h> 17#include <asm/io.h> 18#include <asm/div64.h> 19#include <asm/delay.h> 20 21#include "geodefb.h" 22#include "display_gx.h" 23 24#ifdef CONFIG_FB_GEODE_GX_SET_FBSIZE 25unsigned int gx_frame_buffer_size(void) 26{ 27 return CONFIG_FB_GEODE_GX_FBSIZE; 28} 29#else 30unsigned int gx_frame_buffer_size(void) 31{ 32 unsigned int val; 33 34 /* FB size is reported by a virtual register */ 35 /* Virtual register class = 0x02 */ 36 /* VG_MEM_SIZE(512Kb units) = 0x00 */ 37 38 outw(0xFC53, 0xAC1C); 39 outw(0x0200, 0xAC1C); 40 41 val = (unsigned int)(inw(0xAC1E)) & 0xFFl; 42 return (val << 19); 43} 44#endif 45 46int gx_line_delta(int xres, int bpp) 47{ 48 /* Must be a multiple of 8 bytes. */ 49 return (xres * (bpp >> 3) + 7) & ~0x7; 50} 51 52static void gx_set_mode(struct fb_info *info) 53{ 54 struct geodefb_par *par = info->par; 55 u32 gcfg, dcfg; 56 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; 57 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; 58 59 /* Unlock the display controller registers. */ 60 readl(par->dc_regs + DC_UNLOCK); 61 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); 62 63 gcfg = readl(par->dc_regs + DC_GENERAL_CFG); 64 dcfg = readl(par->dc_regs + DC_DISPLAY_CFG); 65 66 /* Disable the timing generator. */ 67 dcfg &= ~(DC_DCFG_TGEN); 68 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); 69 70 /* Wait for pending memory requests before disabling the FIFO load. */ 71 udelay(100); 72 73 /* Disable FIFO load and compression. */ 74 gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); 75 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 76 77 /* Setup DCLK and its divisor. */ 78 par->vid_ops->set_dclk(info); 79 80 /* 81 * Setup new mode. 82 */ 83 84 /* Clear all unused feature bits. */ 85 gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE; 86 dcfg = 0; 87 88 /* Set FIFO priority (default 6/5) and enable. */ 89 gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; 90 91 /* Framebuffer start offset. */ 92 writel(0, par->dc_regs + DC_FB_ST_OFFSET); 93 94 /* Line delta and line buffer length. */ 95 writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); 96 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, 97 par->dc_regs + DC_LINE_SIZE); 98 99 100 /* Enable graphics and video data and unmask address lines. */ 101 dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M; 102 103 /* Set pixel format. */ 104 switch (info->var.bits_per_pixel) { 105 case 8: 106 dcfg |= DC_DCFG_DISP_MODE_8BPP; 107 break; 108 case 16: 109 dcfg |= DC_DCFG_DISP_MODE_16BPP; 110 dcfg |= DC_DCFG_16BPP_MODE_565; 111 break; 112 case 32: 113 dcfg |= DC_DCFG_DISP_MODE_24BPP; 114 dcfg |= DC_DCFG_PALB; 115 break; 116 } 117 118 /* Enable timing generator. */ 119 dcfg |= DC_DCFG_TGEN; 120 121 /* Horizontal and vertical timings. */ 122 hactive = info->var.xres; 123 hblankstart = hactive; 124 hsyncstart = hblankstart + info->var.right_margin; 125 hsyncend = hsyncstart + info->var.hsync_len; 126 hblankend = hsyncend + info->var.left_margin; 127 htotal = hblankend; 128 129 vactive = info->var.yres; 130 vblankstart = vactive; 131 vsyncstart = vblankstart + info->var.lower_margin; 132 vsyncend = vsyncstart + info->var.vsync_len; 133 vblankend = vsyncend + info->var.upper_margin; 134 vtotal = vblankend; 135 136 writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); 137 writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); 138 writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); 139 140 writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); 141 writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); 142 writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); 143 144 /* Write final register values. */ 145 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); 146 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 147 148 par->vid_ops->configure_display(info); 149 150 /* Relock display controller registers */ 151 writel(0, par->dc_regs + DC_UNLOCK); 152} 153 154static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno, 155 unsigned red, unsigned green, unsigned blue) 156{ 157 struct geodefb_par *par = info->par; 158 int val; 159 160 /* Hardware palette is in RGB 8-8-8 format. */ 161 val = (red << 8) & 0xff0000; 162 val |= (green) & 0x00ff00; 163 val |= (blue >> 8) & 0x0000ff; 164 165 writel(regno, par->dc_regs + DC_PAL_ADDRESS); 166 writel(val, par->dc_regs + DC_PAL_DATA); 167} 168 169struct geode_dc_ops gx_dc_ops = { 170 .set_mode = gx_set_mode, 171 .set_palette_reg = gx_set_hw_palette_reg, 172}; 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