1/* 2 * ATI Frame Buffer Device Driver Core Definitions 3 */ 4 5#include <linux/spinlock.h> 6#include <linux/wait.h> 7 /* 8 * Elements of the hardware specific atyfb_par structure 9 */ 10 11struct crtc { 12 u32 vxres; 13 u32 vyres; 14 u32 xoffset; 15 u32 yoffset; 16 u32 bpp; 17 u32 h_tot_disp; 18 u32 h_sync_strt_wid; 19 u32 v_tot_disp; 20 u32 v_sync_strt_wid; 21 u32 vline_crnt_vline; 22 u32 off_pitch; 23 u32 gen_cntl; 24 u32 dp_pix_width; /* acceleration */ 25 u32 dp_chain_mask; /* acceleration */ 26#ifdef CONFIG_FB_ATY_GENERIC_LCD 27 u32 horz_stretching; 28 u32 vert_stretching; 29 u32 ext_vert_stretch; 30 u32 shadow_h_tot_disp; 31 u32 shadow_h_sync_strt_wid; 32 u32 shadow_v_tot_disp; 33 u32 shadow_v_sync_strt_wid; 34 u32 lcd_gen_cntl; 35 u32 lcd_config_panel; 36 u32 lcd_index; 37#endif 38}; 39 40struct aty_interrupt { 41 wait_queue_head_t wait; 42 unsigned int count; 43 int pan_display; 44}; 45 46struct pll_info { 47 int pll_max; 48 int pll_min; 49 int sclk, mclk, mclk_pm, xclk; 50 int ref_div; 51 int ref_clk; 52 int ecp_max; 53}; 54 55typedef struct { 56 u16 unknown1; 57 u16 PCLK_min_freq; 58 u16 PCLK_max_freq; 59 u16 unknown2; 60 u16 ref_freq; 61 u16 ref_divider; 62 u16 unknown3; 63 u16 MCLK_pwd; 64 u16 MCLK_max_freq; 65 u16 XCLK_max_freq; 66 u16 SCLK_freq; 67} __attribute__ ((packed)) PLL_BLOCK_MACH64; 68 69struct pll_514 { 70 u8 m; 71 u8 n; 72}; 73 74struct pll_18818 { 75 u32 program_bits; 76 u32 locationAddr; 77 u32 period_in_ps; 78 u32 post_divider; 79}; 80 81struct pll_ct { 82 u8 pll_ref_div; 83 u8 pll_gen_cntl; 84 u8 mclk_fb_div; 85 u8 mclk_fb_mult; /* 2 ro 4 */ 86 u8 sclk_fb_div; 87 u8 pll_vclk_cntl; 88 u8 vclk_post_div; 89 u8 vclk_fb_div; 90 u8 pll_ext_cntl; 91 u8 ext_vpll_cntl; 92 u8 spll_cntl2; 93 u32 dsp_config; /* Mach64 GTB DSP */ 94 u32 dsp_on_off; /* Mach64 GTB DSP */ 95 u32 dsp_loop_latency; 96 u32 fifo_size; 97 u32 xclkpagefaultdelay; 98 u32 xclkmaxrasdelay; 99 u8 xclk_ref_div; 100 u8 xclk_post_div; 101 u8 mclk_post_div_real; 102 u8 xclk_post_div_real; 103 u8 vclk_post_div_real; 104 u8 features; 105#ifdef CONFIG_FB_ATY_GENERIC_LCD 106 u32 xres; /* use for LCD stretching/scaling */ 107#endif 108}; 109 110/* 111 for pll_ct.features 112*/ 113#define DONT_USE_SPLL 0x1 114#define DONT_USE_XDLL 0x2 115#define USE_CPUCLK 0x4 116#define POWERDOWN_PLL 0x8 117 118union aty_pll { 119 struct pll_ct ct; 120 struct pll_514 ibm514; 121 struct pll_18818 ics2595; 122}; 123 124 /* 125 * The hardware parameters for each card 126 */ 127 128struct atyfb_par { 129 struct { u8 red, green, blue; } palette[256]; 130 const struct aty_dac_ops *dac_ops; 131 const struct aty_pll_ops *pll_ops; 132 void __iomem *ati_regbase; 133 unsigned long clk_wr_offset; /* meaning overloaded, clock id by CT */ 134 struct crtc crtc; 135 union aty_pll pll; 136 struct pll_info pll_limits; 137 u32 features; 138 u32 ref_clk_per; 139 u32 pll_per; 140 u32 mclk_per; 141 u32 xclk_per; 142 u8 bus_type; 143 u8 ram_type; 144 u8 mem_refresh_rate; 145 u16 pci_id; 146 u32 accel_flags; 147 int blitter_may_be_busy; 148 int asleep; 149 int lock_blank; 150 unsigned long res_start; 151 unsigned long res_size; 152 struct pci_dev *pdev; 153#ifdef __sparc__ 154 struct pci_mmap_map *mmap_map; 155 u8 mmaped; 156#endif 157 int open; 158#ifdef CONFIG_FB_ATY_GENERIC_LCD 159 unsigned long bios_base_phys; 160 unsigned long bios_base; 161 unsigned long lcd_table; 162 u16 lcd_width; 163 u16 lcd_height; 164 u32 lcd_pixclock; 165 u16 lcd_refreshrate; 166 u16 lcd_htotal; 167 u16 lcd_hdisp; 168 u16 lcd_hsync_dly; 169 u16 lcd_hsync_len; 170 u16 lcd_vtotal; 171 u16 lcd_vdisp; 172 u16 lcd_vsync_len; 173 u16 lcd_right_margin; 174 u16 lcd_lower_margin; 175 u16 lcd_hblank_len; 176 u16 lcd_vblank_len; 177#endif 178 unsigned long aux_start; /* auxiliary aperture */ 179 unsigned long aux_size; 180 struct aty_interrupt vblank; 181 unsigned long irq_flags; 182 unsigned int irq; 183 spinlock_t int_lock; 184#ifdef CONFIG_MTRR 185 int mtrr_aper; 186 int mtrr_reg; 187#endif 188 u32 mem_cntl; 189}; 190 191 /* 192 * ATI Mach64 features 193 */ 194 195#define M64_HAS(feature) ((par)->features & (M64F_##feature)) 196 197#define M64F_RESET_3D 0x00000001 198#define M64F_MAGIC_FIFO 0x00000002 199#define M64F_GTB_DSP 0x00000004 200#define M64F_FIFO_32 0x00000008 201#define M64F_SDRAM_MAGIC_PLL 0x00000010 202#define M64F_MAGIC_POSTDIV 0x00000020 203#define M64F_INTEGRATED 0x00000040 204#define M64F_CT_BUS 0x00000080 205#define M64F_VT_BUS 0x00000100 206#define M64F_MOBIL_BUS 0x00000200 207#define M64F_GX 0x00000400 208#define M64F_CT 0x00000800 209#define M64F_VT 0x00001000 210#define M64F_GT 0x00002000 211#define M64F_MAGIC_VRAM_SIZE 0x00004000 212#define M64F_G3_PB_1_1 0x00008000 213#define M64F_G3_PB_1024x768 0x00010000 214#define M64F_EXTRA_BRIGHT 0x00020000 215#define M64F_LT_LCD_REGS 0x00040000 216#define M64F_XL_DLL 0x00080000 217#define M64F_MFB_FORCE_4 0x00100000 218#define M64F_HW_TRIPLE 0x00200000 219 /* 220 * Register access 221 */ 222 223static inline u32 aty_ld_le32(int regindex, const struct atyfb_par *par) 224{ 225 /* Hack for bloc 1, should be cleanly optimized by compiler */ 226 if (regindex >= 0x400) 227 regindex -= 0x800; 228 229#ifdef CONFIG_ATARI 230 return in_le32(par->ati_regbase + regindex); 231#else 232 return readl(par->ati_regbase + regindex); 233#endif 234} 235 236static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par) 237{ 238 /* Hack for bloc 1, should be cleanly optimized by compiler */ 239 if (regindex >= 0x400) 240 regindex -= 0x800; 241 242#ifdef CONFIG_ATARI 243 out_le32(par->ati_regbase + regindex, val); 244#else 245 writel(val, par->ati_regbase + regindex); 246#endif 247} 248 249static inline void aty_st_le16(int regindex, u16 val, 250 const struct atyfb_par *par) 251{ 252 /* Hack for bloc 1, should be cleanly optimized by compiler */ 253 if (regindex >= 0x400) 254 regindex -= 0x800; 255#ifdef CONFIG_ATARI 256 out_le16(par->ati_regbase + regindex, val); 257#else 258 writel(val, par->ati_regbase + regindex); 259#endif 260} 261 262static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par) 263{ 264 /* Hack for bloc 1, should be cleanly optimized by compiler */ 265 if (regindex >= 0x400) 266 regindex -= 0x800; 267#ifdef CONFIG_ATARI 268 return in_8(par->ati_regbase + regindex); 269#else 270 return readb(par->ati_regbase + regindex); 271#endif 272} 273 274static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par) 275{ 276 /* Hack for bloc 1, should be cleanly optimized by compiler */ 277 if (regindex >= 0x400) 278 regindex -= 0x800; 279 280#ifdef CONFIG_ATARI 281 out_8(par->ati_regbase + regindex, val); 282#else 283 writeb(val, par->ati_regbase + regindex); 284#endif 285} 286 287#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \ 288 defined(CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT) 289extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par); 290extern u32 aty_ld_lcd(int index, const struct atyfb_par *par); 291#endif 292 293 /* 294 * DAC operations 295 */ 296 297struct aty_dac_ops { 298 int (*set_dac) (const struct fb_info * info, 299 const union aty_pll * pll, u32 bpp, u32 accel); 300}; 301 302extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */ 303extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */ 304extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */ 305extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */ 306extern const struct aty_dac_ops aty_dac_ct; /* Integrated */ 307 308 309 /* 310 * Clock operations 311 */ 312 313struct aty_pll_ops { 314 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll); 315 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll); 316 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll); 317 void (*get_pll) (const struct fb_info *info, union aty_pll * pll); 318 int (*init_pll) (const struct fb_info * info, union aty_pll * pll); 319 void (*resume_pll)(const struct fb_info *info, union aty_pll *pll); 320}; 321 322extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */ 323extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */ 324extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */ 325extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */ 326extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */ 327extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */ 328extern const struct aty_pll_ops aty_pll_ct; /* Integrated */ 329 330 331extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll); 332extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par); 333 334 335 /* 336 * Hardware cursor support 337 */ 338 339extern int aty_init_cursor(struct fb_info *info); 340 341 /* 342 * Hardware acceleration 343 */ 344 345static inline void wait_for_fifo(u16 entries, const struct atyfb_par *par) 346{ 347 while ((aty_ld_le32(FIFO_STAT, par) & 0xffff) > 348 ((u32) (0x8000 >> entries))); 349} 350 351static inline void wait_for_idle(struct atyfb_par *par) 352{ 353 wait_for_fifo(16, par); 354 while ((aty_ld_le32(GUI_STAT, par) & 1) != 0); 355 par->blitter_may_be_busy = 0; 356} 357 358extern void aty_reset_engine(const struct atyfb_par *par); 359extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info); 360extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par); 361 362void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area); 363void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect); 364void atyfb_imageblit(struct fb_info *info, const struct fb_image *image); 365