1/* 2 * linux/drivers/video/amba-clcd.c 3 * 4 * Copyright (C) 2001 ARM Limited, by David A Rusling 5 * Updated to 2.5, Deep Blue Solutions Ltd. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive 9 * for more details. 10 * 11 * ARM PrimeCell PL110 Color LCD Controller 12 */ 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/errno.h> 16#include <linux/string.h> 17#include <linux/slab.h> 18#include <linux/delay.h> 19#include <linux/mm.h> 20#include <linux/fb.h> 21#include <linux/init.h> 22#include <linux/ioport.h> 23#include <linux/list.h> 24#include <linux/amba/bus.h> 25#include <linux/amba/clcd.h> 26#include <linux/clk.h> 27 28#include <asm/sizes.h> 29 30#define to_clcd(info) container_of(info, struct clcd_fb, fb) 31 32/* This is limited to 16 characters when displayed by X startup */ 33static const char *clcd_name = "CLCD FB"; 34 35/* 36 * Unfortunately, the enable/disable functions may be called either from 37 * process or IRQ context, and we _need_ to delay. This is _not_ good. 38 */ 39static inline void clcdfb_sleep(unsigned int ms) 40{ 41 if (in_atomic()) { 42 mdelay(ms); 43 } else { 44 msleep(ms); 45 } 46} 47 48static inline void clcdfb_set_start(struct clcd_fb *fb) 49{ 50 unsigned long ustart = fb->fb.fix.smem_start; 51 unsigned long lstart; 52 53 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length; 54 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2; 55 56 writel(ustart, fb->regs + CLCD_UBAS); 57 writel(lstart, fb->regs + CLCD_LBAS); 58} 59 60static void clcdfb_disable(struct clcd_fb *fb) 61{ 62 u32 val; 63 64 if (fb->board->disable) 65 fb->board->disable(fb); 66 67 val = readl(fb->regs + CLCD_CNTL); 68 if (val & CNTL_LCDPWR) { 69 val &= ~CNTL_LCDPWR; 70 writel(val, fb->regs + CLCD_CNTL); 71 72 clcdfb_sleep(20); 73 } 74 if (val & CNTL_LCDEN) { 75 val &= ~CNTL_LCDEN; 76 writel(val, fb->regs + CLCD_CNTL); 77 } 78 79 /* 80 * Disable CLCD clock source. 81 */ 82 clk_disable(fb->clk); 83} 84 85static void clcdfb_enable(struct clcd_fb *fb, u32 cntl) 86{ 87 /* 88 * Enable the CLCD clock source. 89 */ 90 clk_enable(fb->clk); 91 92 /* 93 * Bring up by first enabling.. 94 */ 95 cntl |= CNTL_LCDEN; 96 writel(cntl, fb->regs + CLCD_CNTL); 97 98 clcdfb_sleep(20); 99 100 /* 101 * and now apply power. 102 */ 103 cntl |= CNTL_LCDPWR; 104 writel(cntl, fb->regs + CLCD_CNTL); 105 106 /* 107 * finally, enable the interface. 108 */ 109 if (fb->board->enable) 110 fb->board->enable(fb); 111} 112 113static int 114clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var) 115{ 116 int ret = 0; 117 118 memset(&var->transp, 0, sizeof(var->transp)); 119 120 var->red.msb_right = 0; 121 var->green.msb_right = 0; 122 var->blue.msb_right = 0; 123 124 switch (var->bits_per_pixel) { 125 case 1: 126 case 2: 127 case 4: 128 case 8: 129 var->red.length = var->bits_per_pixel; 130 var->red.offset = 0; 131 var->green.length = var->bits_per_pixel; 132 var->green.offset = 0; 133 var->blue.length = var->bits_per_pixel; 134 var->blue.offset = 0; 135 break; 136 case 16: 137 var->red.length = 5; 138 var->blue.length = 5; 139 /* 140 * Green length can be 5 or 6 depending whether 141 * we're operating in RGB555 or RGB565 mode. 142 */ 143 if (var->green.length != 5 && var->green.length != 6) 144 var->green.length = 6; 145 break; 146 case 32: 147 if (fb->panel->cntl & CNTL_LCDTFT) { 148 var->red.length = 8; 149 var->green.length = 8; 150 var->blue.length = 8; 151 break; 152 } 153 default: 154 ret = -EINVAL; 155 break; 156 } 157 158 /* 159 * >= 16bpp displays have separate colour component bitfields 160 * encoded in the pixel data. Calculate their position from 161 * the bitfield length defined above. 162 */ 163 if (ret == 0 && var->bits_per_pixel >= 16) { 164 if (fb->panel->cntl & CNTL_BGR) { 165 var->blue.offset = 0; 166 var->green.offset = var->blue.offset + var->blue.length; 167 var->red.offset = var->green.offset + var->green.length; 168 } else { 169 var->red.offset = 0; 170 var->green.offset = var->red.offset + var->red.length; 171 var->blue.offset = var->green.offset + var->green.length; 172 } 173 } 174 175 return ret; 176} 177 178static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 179{ 180 struct clcd_fb *fb = to_clcd(info); 181 int ret = -EINVAL; 182 183 if (fb->board->check) 184 ret = fb->board->check(fb, var); 185 186 if (ret == 0 && 187 var->xres_virtual * var->bits_per_pixel / 8 * 188 var->yres_virtual > fb->fb.fix.smem_len) 189 ret = -EINVAL; 190 191 if (ret == 0) 192 ret = clcdfb_set_bitfields(fb, var); 193 194 return ret; 195} 196 197static int clcdfb_set_par(struct fb_info *info) 198{ 199 struct clcd_fb *fb = to_clcd(info); 200 struct clcd_regs regs; 201 202 fb->fb.fix.line_length = fb->fb.var.xres_virtual * 203 fb->fb.var.bits_per_pixel / 8; 204 205 if (fb->fb.var.bits_per_pixel <= 8) 206 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 207 else 208 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; 209 210 fb->board->decode(fb, ®s); 211 212 clcdfb_disable(fb); 213 214 writel(regs.tim0, fb->regs + CLCD_TIM0); 215 writel(regs.tim1, fb->regs + CLCD_TIM1); 216 writel(regs.tim2, fb->regs + CLCD_TIM2); 217 writel(regs.tim3, fb->regs + CLCD_TIM3); 218 219 clcdfb_set_start(fb); 220 221 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000); 222 223 fb->clcd_cntl = regs.cntl; 224 225 clcdfb_enable(fb, regs.cntl); 226 227#ifdef DEBUG 228 printk(KERN_INFO "CLCD: Registers set to\n" 229 KERN_INFO " %08x %08x %08x %08x\n" 230 KERN_INFO " %08x %08x %08x %08x\n", 231 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1), 232 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3), 233 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS), 234 readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL)); 235#endif 236 237 return 0; 238} 239 240static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) 241{ 242 unsigned int mask = (1 << bf->length) - 1; 243 244 return (val >> (16 - bf->length) & mask) << bf->offset; 245} 246 247/* 248 * Set a single color register. The values supplied have a 16 bit 249 * magnitude. Return != 0 for invalid regno. 250 */ 251static int 252clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, 253 unsigned int blue, unsigned int transp, struct fb_info *info) 254{ 255 struct clcd_fb *fb = to_clcd(info); 256 257 if (regno < 16) 258 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | 259 convert_bitfield(blue, &fb->fb.var.blue) | 260 convert_bitfield(green, &fb->fb.var.green) | 261 convert_bitfield(red, &fb->fb.var.red); 262 263 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) { 264 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3); 265 u32 val, mask, newval; 266 267 newval = (red >> 11) & 0x001f; 268 newval |= (green >> 6) & 0x03e0; 269 newval |= (blue >> 1) & 0x7c00; 270 271 /* 272 * 3.2.11: if we're configured for big endian 273 * byte order, the palette entries are swapped. 274 */ 275 if (fb->clcd_cntl & CNTL_BEBO) 276 regno ^= 1; 277 278 if (regno & 1) { 279 newval <<= 16; 280 mask = 0x0000ffff; 281 } else { 282 mask = 0xffff0000; 283 } 284 285 val = readl(fb->regs + hw_reg) & mask; 286 writel(val | newval, fb->regs + hw_reg); 287 } 288 289 return regno > 255; 290} 291 292/* 293 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL 294 * then the caller blanks by setting the CLUT (Color Look Up Table) to all 295 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due 296 * to e.g. a video mode which doesn't support it. Implements VESA suspend 297 * and powerdown modes on hardware that supports disabling hsync/vsync: 298 * blank_mode == 2: suspend vsync 299 * blank_mode == 3: suspend hsync 300 * blank_mode == 4: powerdown 301 */ 302static int clcdfb_blank(int blank_mode, struct fb_info *info) 303{ 304 struct clcd_fb *fb = to_clcd(info); 305 306 if (blank_mode != 0) { 307 clcdfb_disable(fb); 308 } else { 309 clcdfb_enable(fb, fb->clcd_cntl); 310 } 311 return 0; 312} 313 314static int clcdfb_mmap(struct fb_info *info, 315 struct vm_area_struct *vma) 316{ 317 struct clcd_fb *fb = to_clcd(info); 318 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT; 319 int ret = -EINVAL; 320 321 len = info->fix.smem_len; 322 323 if (off <= len && vma->vm_end - vma->vm_start <= len - off && 324 fb->board->mmap) 325 ret = fb->board->mmap(fb, vma); 326 327 return ret; 328} 329 330static struct fb_ops clcdfb_ops = { 331 .owner = THIS_MODULE, 332 .fb_check_var = clcdfb_check_var, 333 .fb_set_par = clcdfb_set_par, 334 .fb_setcolreg = clcdfb_setcolreg, 335 .fb_blank = clcdfb_blank, 336 .fb_fillrect = cfb_fillrect, 337 .fb_copyarea = cfb_copyarea, 338 .fb_imageblit = cfb_imageblit, 339 .fb_mmap = clcdfb_mmap, 340}; 341 342static int clcdfb_register(struct clcd_fb *fb) 343{ 344 int ret; 345 346 fb->clk = clk_get(&fb->dev->dev, "CLCDCLK"); 347 if (IS_ERR(fb->clk)) { 348 ret = PTR_ERR(fb->clk); 349 goto out; 350 } 351 352 fb->fb.fix.mmio_start = fb->dev->res.start; 353 fb->fb.fix.mmio_len = SZ_4K; 354 355 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len); 356 if (!fb->regs) { 357 printk(KERN_ERR "CLCD: unable to remap registers\n"); 358 ret = -ENOMEM; 359 goto free_clk; 360 } 361 362 fb->fb.fbops = &clcdfb_ops; 363 fb->fb.flags = FBINFO_FLAG_DEFAULT; 364 fb->fb.pseudo_palette = fb->cmap; 365 366 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id)); 367 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; 368 fb->fb.fix.type_aux = 0; 369 fb->fb.fix.xpanstep = 0; 370 fb->fb.fix.ypanstep = 0; 371 fb->fb.fix.ywrapstep = 0; 372 fb->fb.fix.accel = FB_ACCEL_NONE; 373 374 fb->fb.var.xres = fb->panel->mode.xres; 375 fb->fb.var.yres = fb->panel->mode.yres; 376 fb->fb.var.xres_virtual = fb->panel->mode.xres; 377 fb->fb.var.yres_virtual = fb->panel->mode.yres; 378 fb->fb.var.bits_per_pixel = fb->panel->bpp; 379 fb->fb.var.grayscale = fb->panel->grayscale; 380 fb->fb.var.pixclock = fb->panel->mode.pixclock; 381 fb->fb.var.left_margin = fb->panel->mode.left_margin; 382 fb->fb.var.right_margin = fb->panel->mode.right_margin; 383 fb->fb.var.upper_margin = fb->panel->mode.upper_margin; 384 fb->fb.var.lower_margin = fb->panel->mode.lower_margin; 385 fb->fb.var.hsync_len = fb->panel->mode.hsync_len; 386 fb->fb.var.vsync_len = fb->panel->mode.vsync_len; 387 fb->fb.var.sync = fb->panel->mode.sync; 388 fb->fb.var.vmode = fb->panel->mode.vmode; 389 fb->fb.var.activate = FB_ACTIVATE_NOW; 390 fb->fb.var.nonstd = 0; 391 fb->fb.var.height = fb->panel->height; 392 fb->fb.var.width = fb->panel->width; 393 fb->fb.var.accel_flags = 0; 394 395 fb->fb.monspecs.hfmin = 0; 396 fb->fb.monspecs.hfmax = 100000; 397 fb->fb.monspecs.vfmin = 0; 398 fb->fb.monspecs.vfmax = 400; 399 fb->fb.monspecs.dclkmin = 1000000; 400 fb->fb.monspecs.dclkmax = 100000000; 401 402 /* 403 * Make sure that the bitfields are set appropriately. 404 */ 405 clcdfb_set_bitfields(fb, &fb->fb.var); 406 407 /* 408 * Allocate colourmap. 409 */ 410 fb_alloc_cmap(&fb->fb.cmap, 256, 0); 411 412 /* 413 * Ensure interrupts are disabled. 414 */ 415 writel(0, fb->regs + CLCD_IENB); 416 417 fb_set_var(&fb->fb, &fb->fb.var); 418 419 printk(KERN_INFO "CLCD: %s hardware, %s display\n", 420 fb->board->name, fb->panel->mode.name); 421 422 ret = register_framebuffer(&fb->fb); 423 if (ret == 0) 424 goto out; 425 426 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret); 427 428 iounmap(fb->regs); 429 free_clk: 430 clk_put(fb->clk); 431 out: 432 return ret; 433} 434 435static int clcdfb_probe(struct amba_device *dev, void *id) 436{ 437 struct clcd_board *board = dev->dev.platform_data; 438 struct clcd_fb *fb; 439 int ret; 440 441 if (!board) 442 return -EINVAL; 443 444 ret = amba_request_regions(dev, NULL); 445 if (ret) { 446 printk(KERN_ERR "CLCD: unable to reserve regs region\n"); 447 goto out; 448 } 449 450 fb = kmalloc(sizeof(struct clcd_fb), GFP_KERNEL); 451 if (!fb) { 452 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n"); 453 ret = -ENOMEM; 454 goto free_region; 455 } 456 memset(fb, 0, sizeof(struct clcd_fb)); 457 458 fb->dev = dev; 459 fb->board = board; 460 461 ret = fb->board->setup(fb); 462 if (ret) 463 goto free_fb; 464 465 ret = clcdfb_register(fb); 466 if (ret == 0) { 467 amba_set_drvdata(dev, fb); 468 goto out; 469 } 470 471 fb->board->remove(fb); 472 free_fb: 473 kfree(fb); 474 free_region: 475 amba_release_regions(dev); 476 out: 477 return ret; 478} 479 480static int clcdfb_remove(struct amba_device *dev) 481{ 482 struct clcd_fb *fb = amba_get_drvdata(dev); 483 484 amba_set_drvdata(dev, NULL); 485 486 clcdfb_disable(fb); 487 unregister_framebuffer(&fb->fb); 488 iounmap(fb->regs); 489 clk_put(fb->clk); 490 491 fb->board->remove(fb); 492 493 kfree(fb); 494 495 amba_release_regions(dev); 496 497 return 0; 498} 499 500static struct amba_id clcdfb_id_table[] = { 501 { 502 .id = 0x00041110, 503 .mask = 0x000ffffe, 504 }, 505 { 0, 0 }, 506}; 507 508static struct amba_driver clcd_driver = { 509 .drv = { 510 .name = "clcd-pl11x", 511 }, 512 .probe = clcdfb_probe, 513 .remove = clcdfb_remove, 514 .id_table = clcdfb_id_table, 515}; 516 517static int __init amba_clcdfb_init(void) 518{ 519 if (fb_get_options("ambafb", NULL)) 520 return -ENODEV; 521 522 return amba_driver_register(&clcd_driver); 523} 524 525module_init(amba_clcdfb_init); 526 527static void __exit amba_clcdfb_exit(void) 528{ 529 amba_driver_unregister(&clcd_driver); 530} 531 532module_exit(amba_clcdfb_exit); 533 534MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver"); 535MODULE_LICENSE("GPL"); 536