1/* 2 * drivers/serial/serial_txx9.c 3 * 4 * Derived from many drivers using generic_serial interface, 5 * especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c 6 * (was in Linux/VR tree) by Jim Pick. 7 * 8 * Copyright (C) 1999 Harald Koerfgen 9 * Copyright (C) 2000 Jim Pick <jim@jimpick.com> 10 * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) 11 * Copyright (C) 2000-2002 Toshiba Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 * 17 * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller 18 */ 19 20#if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21#define SUPPORT_SYSRQ 22#endif 23 24#include <linux/module.h> 25#include <linux/ioport.h> 26#include <linux/init.h> 27#include <linux/console.h> 28#include <linux/sysrq.h> 29#include <linux/delay.h> 30#include <linux/platform_device.h> 31#include <linux/pci.h> 32#include <linux/tty.h> 33#include <linux/tty_flip.h> 34#include <linux/serial_core.h> 35#include <linux/serial.h> 36#include <linux/mutex.h> 37 38#include <asm/io.h> 39 40static char *serial_version = "1.09"; 41static char *serial_name = "TX39/49 Serial driver"; 42 43#define PASS_LIMIT 256 44 45#if !defined(CONFIG_SERIAL_TXX9_STDSERIAL) 46/* "ttyS" is used for standard serial driver */ 47#define TXX9_TTY_NAME "ttyTX" 48#define TXX9_TTY_MINOR_START 196 49#define TXX9_TTY_MAJOR 204 50#else 51/* acts like standard serial driver */ 52#define TXX9_TTY_NAME "ttyS" 53#define TXX9_TTY_MINOR_START 64 54#define TXX9_TTY_MAJOR TTY_MAJOR 55#endif 56 57/* flag aliases */ 58#define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART 59#define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER 60 61#ifdef CONFIG_PCI 62/* support for Toshiba TC86C001 SIO */ 63#define ENABLE_SERIAL_TXX9_PCI 64#endif 65 66/* 67 * Number of serial ports 68 */ 69#define UART_NR CONFIG_SERIAL_TXX9_NR_UARTS 70 71#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) 72 73struct uart_txx9_port { 74 struct uart_port port; 75 /* No additional info for now */ 76}; 77 78#define TXX9_REGION_SIZE 0x24 79 80/* TXX9 Serial Registers */ 81#define TXX9_SILCR 0x00 82#define TXX9_SIDICR 0x04 83#define TXX9_SIDISR 0x08 84#define TXX9_SICISR 0x0c 85#define TXX9_SIFCR 0x10 86#define TXX9_SIFLCR 0x14 87#define TXX9_SIBGR 0x18 88#define TXX9_SITFIFO 0x1c 89#define TXX9_SIRFIFO 0x20 90 91/* SILCR : Line Control */ 92#define TXX9_SILCR_SCS_MASK 0x00000060 93#define TXX9_SILCR_SCS_IMCLK 0x00000000 94#define TXX9_SILCR_SCS_IMCLK_BG 0x00000020 95#define TXX9_SILCR_SCS_SCLK 0x00000040 96#define TXX9_SILCR_SCS_SCLK_BG 0x00000060 97#define TXX9_SILCR_UEPS 0x00000010 98#define TXX9_SILCR_UPEN 0x00000008 99#define TXX9_SILCR_USBL_MASK 0x00000004 100#define TXX9_SILCR_USBL_1BIT 0x00000000 101#define TXX9_SILCR_USBL_2BIT 0x00000004 102#define TXX9_SILCR_UMODE_MASK 0x00000003 103#define TXX9_SILCR_UMODE_8BIT 0x00000000 104#define TXX9_SILCR_UMODE_7BIT 0x00000001 105 106/* SIDICR : DMA/Int. Control */ 107#define TXX9_SIDICR_TDE 0x00008000 108#define TXX9_SIDICR_RDE 0x00004000 109#define TXX9_SIDICR_TIE 0x00002000 110#define TXX9_SIDICR_RIE 0x00001000 111#define TXX9_SIDICR_SPIE 0x00000800 112#define TXX9_SIDICR_CTSAC 0x00000600 113#define TXX9_SIDICR_STIE_MASK 0x0000003f 114#define TXX9_SIDICR_STIE_OERS 0x00000020 115#define TXX9_SIDICR_STIE_CTSS 0x00000010 116#define TXX9_SIDICR_STIE_RBRKD 0x00000008 117#define TXX9_SIDICR_STIE_TRDY 0x00000004 118#define TXX9_SIDICR_STIE_TXALS 0x00000002 119#define TXX9_SIDICR_STIE_UBRKD 0x00000001 120 121/* SIDISR : DMA/Int. Status */ 122#define TXX9_SIDISR_UBRK 0x00008000 123#define TXX9_SIDISR_UVALID 0x00004000 124#define TXX9_SIDISR_UFER 0x00002000 125#define TXX9_SIDISR_UPER 0x00001000 126#define TXX9_SIDISR_UOER 0x00000800 127#define TXX9_SIDISR_ERI 0x00000400 128#define TXX9_SIDISR_TOUT 0x00000200 129#define TXX9_SIDISR_TDIS 0x00000100 130#define TXX9_SIDISR_RDIS 0x00000080 131#define TXX9_SIDISR_STIS 0x00000040 132#define TXX9_SIDISR_RFDN_MASK 0x0000001f 133 134/* SICISR : Change Int. Status */ 135#define TXX9_SICISR_OERS 0x00000020 136#define TXX9_SICISR_CTSS 0x00000010 137#define TXX9_SICISR_RBRKD 0x00000008 138#define TXX9_SICISR_TRDY 0x00000004 139#define TXX9_SICISR_TXALS 0x00000002 140#define TXX9_SICISR_UBRKD 0x00000001 141 142/* SIFCR : FIFO Control */ 143#define TXX9_SIFCR_SWRST 0x00008000 144#define TXX9_SIFCR_RDIL_MASK 0x00000180 145#define TXX9_SIFCR_RDIL_1 0x00000000 146#define TXX9_SIFCR_RDIL_4 0x00000080 147#define TXX9_SIFCR_RDIL_8 0x00000100 148#define TXX9_SIFCR_RDIL_12 0x00000180 149#define TXX9_SIFCR_RDIL_MAX 0x00000180 150#define TXX9_SIFCR_TDIL_MASK 0x00000018 151#define TXX9_SIFCR_TDIL_MASK 0x00000018 152#define TXX9_SIFCR_TDIL_1 0x00000000 153#define TXX9_SIFCR_TDIL_4 0x00000001 154#define TXX9_SIFCR_TDIL_8 0x00000010 155#define TXX9_SIFCR_TDIL_MAX 0x00000010 156#define TXX9_SIFCR_TFRST 0x00000004 157#define TXX9_SIFCR_RFRST 0x00000002 158#define TXX9_SIFCR_FRSTE 0x00000001 159#define TXX9_SIO_TX_FIFO 8 160#define TXX9_SIO_RX_FIFO 16 161 162/* SIFLCR : Flow Control */ 163#define TXX9_SIFLCR_RCS 0x00001000 164#define TXX9_SIFLCR_TES 0x00000800 165#define TXX9_SIFLCR_RTSSC 0x00000200 166#define TXX9_SIFLCR_RSDE 0x00000100 167#define TXX9_SIFLCR_TSDE 0x00000080 168#define TXX9_SIFLCR_RTSTL_MASK 0x0000001e 169#define TXX9_SIFLCR_RTSTL_MAX 0x0000001e 170#define TXX9_SIFLCR_TBRK 0x00000001 171 172/* SIBGR : Baudrate Control */ 173#define TXX9_SIBGR_BCLK_MASK 0x00000300 174#define TXX9_SIBGR_BCLK_T0 0x00000000 175#define TXX9_SIBGR_BCLK_T2 0x00000100 176#define TXX9_SIBGR_BCLK_T4 0x00000200 177#define TXX9_SIBGR_BCLK_T6 0x00000300 178#define TXX9_SIBGR_BRD_MASK 0x000000ff 179 180static inline unsigned int sio_in(struct uart_txx9_port *up, int offset) 181{ 182 switch (up->port.iotype) { 183 default: 184 return __raw_readl(up->port.membase + offset); 185 case UPIO_PORT: 186 return inl(up->port.iobase + offset); 187 } 188} 189 190static inline void 191sio_out(struct uart_txx9_port *up, int offset, int value) 192{ 193 switch (up->port.iotype) { 194 default: 195 __raw_writel(value, up->port.membase + offset); 196 break; 197 case UPIO_PORT: 198 outl(value, up->port.iobase + offset); 199 break; 200 } 201} 202 203static inline void 204sio_mask(struct uart_txx9_port *up, int offset, unsigned int value) 205{ 206 sio_out(up, offset, sio_in(up, offset) & ~value); 207} 208static inline void 209sio_set(struct uart_txx9_port *up, int offset, unsigned int value) 210{ 211 sio_out(up, offset, sio_in(up, offset) | value); 212} 213 214static inline void 215sio_quot_set(struct uart_txx9_port *up, int quot) 216{ 217 quot >>= 1; 218 if (quot < 256) 219 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0); 220 else if (quot < (256 << 2)) 221 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2); 222 else if (quot < (256 << 4)) 223 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4); 224 else if (quot < (256 << 6)) 225 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6); 226 else 227 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6); 228} 229 230static void serial_txx9_stop_tx(struct uart_port *port) 231{ 232 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 233 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE); 234} 235 236static void serial_txx9_start_tx(struct uart_port *port) 237{ 238 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 239 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE); 240} 241 242static void serial_txx9_stop_rx(struct uart_port *port) 243{ 244 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 245 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS; 246} 247 248static void serial_txx9_enable_ms(struct uart_port *port) 249{ 250 /* TXX9-SIO can not control DTR... */ 251} 252 253static void serial_txx9_initialize(struct uart_port *port) 254{ 255 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 256 unsigned int tmout = 10000; 257 258 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST); 259 mmiowb(); 260 udelay(1); 261 while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout) 262 udelay(1); 263 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */ 264 sio_set(up, TXX9_SIFCR, 265 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1); 266 /* initial settings */ 267 sio_out(up, TXX9_SILCR, 268 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT | 269 ((up->port.flags & UPF_TXX9_USE_SCLK) ? 270 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG)); 271 sio_quot_set(up, uart_get_divisor(port, 9600)); 272 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */); 273 sio_out(up, TXX9_SIDICR, 0); 274} 275 276static inline void 277receive_chars(struct uart_txx9_port *up, unsigned int *status) 278{ 279 struct tty_struct *tty = up->port.info->tty; 280 unsigned char ch; 281 unsigned int disr = *status; 282 int max_count = 256; 283 char flag; 284 unsigned int next_ignore_status_mask; 285 286 do { 287 ch = sio_in(up, TXX9_SIRFIFO); 288 flag = TTY_NORMAL; 289 up->port.icount.rx++; 290 291 /* mask out RFDN_MASK bit added by previous overrun */ 292 next_ignore_status_mask = 293 up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK; 294 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER | 295 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) { 296 /* 297 * For statistics only 298 */ 299 if (disr & TXX9_SIDISR_UBRK) { 300 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER); 301 up->port.icount.brk++; 302 /* 303 * We do the SysRQ and SAK checking 304 * here because otherwise the break 305 * may get masked by ignore_status_mask 306 * or read_status_mask. 307 */ 308 if (uart_handle_break(&up->port)) 309 goto ignore_char; 310 } else if (disr & TXX9_SIDISR_UPER) 311 up->port.icount.parity++; 312 else if (disr & TXX9_SIDISR_UFER) 313 up->port.icount.frame++; 314 if (disr & TXX9_SIDISR_UOER) { 315 up->port.icount.overrun++; 316 /* 317 * The receiver read buffer still hold 318 * a char which caused overrun. 319 * Ignore next char by adding RFDN_MASK 320 * to ignore_status_mask temporarily. 321 */ 322 next_ignore_status_mask |= 323 TXX9_SIDISR_RFDN_MASK; 324 } 325 326 /* 327 * Mask off conditions which should be ingored. 328 */ 329 disr &= up->port.read_status_mask; 330 331 if (disr & TXX9_SIDISR_UBRK) { 332 flag = TTY_BREAK; 333 } else if (disr & TXX9_SIDISR_UPER) 334 flag = TTY_PARITY; 335 else if (disr & TXX9_SIDISR_UFER) 336 flag = TTY_FRAME; 337 } 338 if (uart_handle_sysrq_char(&up->port, ch)) 339 goto ignore_char; 340 341 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag); 342 343 ignore_char: 344 up->port.ignore_status_mask = next_ignore_status_mask; 345 disr = sio_in(up, TXX9_SIDISR); 346 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0)); 347 spin_unlock(&up->port.lock); 348 tty_flip_buffer_push(tty); 349 spin_lock(&up->port.lock); 350 *status = disr; 351} 352 353static inline void transmit_chars(struct uart_txx9_port *up) 354{ 355 struct circ_buf *xmit = &up->port.info->xmit; 356 int count; 357 358 if (up->port.x_char) { 359 sio_out(up, TXX9_SITFIFO, up->port.x_char); 360 up->port.icount.tx++; 361 up->port.x_char = 0; 362 return; 363 } 364 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 365 serial_txx9_stop_tx(&up->port); 366 return; 367 } 368 369 count = TXX9_SIO_TX_FIFO; 370 do { 371 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]); 372 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 373 up->port.icount.tx++; 374 if (uart_circ_empty(xmit)) 375 break; 376 } while (--count > 0); 377 378 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 379 uart_write_wakeup(&up->port); 380 381 if (uart_circ_empty(xmit)) 382 serial_txx9_stop_tx(&up->port); 383} 384 385static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id) 386{ 387 int pass_counter = 0; 388 struct uart_txx9_port *up = dev_id; 389 unsigned int status; 390 391 while (1) { 392 spin_lock(&up->port.lock); 393 status = sio_in(up, TXX9_SIDISR); 394 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE)) 395 status &= ~TXX9_SIDISR_TDIS; 396 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS | 397 TXX9_SIDISR_TOUT))) { 398 spin_unlock(&up->port.lock); 399 break; 400 } 401 402 if (status & TXX9_SIDISR_RDIS) 403 receive_chars(up, &status); 404 if (status & TXX9_SIDISR_TDIS) 405 transmit_chars(up); 406 /* Clear TX/RX Int. Status */ 407 sio_mask(up, TXX9_SIDISR, 408 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS | 409 TXX9_SIDISR_TOUT); 410 spin_unlock(&up->port.lock); 411 412 if (pass_counter++ > PASS_LIMIT) 413 break; 414 } 415 416 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 417} 418 419static unsigned int serial_txx9_tx_empty(struct uart_port *port) 420{ 421 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 422 unsigned long flags; 423 unsigned int ret; 424 425 spin_lock_irqsave(&up->port.lock, flags); 426 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0; 427 spin_unlock_irqrestore(&up->port.lock, flags); 428 429 return ret; 430} 431 432static unsigned int serial_txx9_get_mctrl(struct uart_port *port) 433{ 434 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 435 unsigned int ret; 436 437 ret = ((sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS) 438 | ((sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS); 439 440 return ret; 441} 442 443static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl) 444{ 445 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 446 447 if (mctrl & TIOCM_RTS) 448 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC); 449 else 450 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC); 451} 452 453static void serial_txx9_break_ctl(struct uart_port *port, int break_state) 454{ 455 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 456 unsigned long flags; 457 458 spin_lock_irqsave(&up->port.lock, flags); 459 if (break_state == -1) 460 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK); 461 else 462 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK); 463 spin_unlock_irqrestore(&up->port.lock, flags); 464} 465 466static int serial_txx9_startup(struct uart_port *port) 467{ 468 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 469 unsigned long flags; 470 int retval; 471 472 /* 473 * Clear the FIFO buffers and disable them. 474 * (they will be reenabled in set_termios()) 475 */ 476 sio_set(up, TXX9_SIFCR, 477 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE); 478 /* clear reset */ 479 sio_mask(up, TXX9_SIFCR, 480 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE); 481 sio_out(up, TXX9_SIDICR, 0); 482 483 /* 484 * Clear the interrupt registers. 485 */ 486 sio_out(up, TXX9_SIDISR, 0); 487 488 retval = request_irq(up->port.irq, serial_txx9_interrupt, 489 IRQF_SHARED, "serial_txx9", up); 490 if (retval) 491 return retval; 492 493 /* 494 * Now, initialize the UART 495 */ 496 spin_lock_irqsave(&up->port.lock, flags); 497 serial_txx9_set_mctrl(&up->port, up->port.mctrl); 498 spin_unlock_irqrestore(&up->port.lock, flags); 499 500 /* Enable RX/TX */ 501 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE); 502 503 /* 504 * Finally, enable interrupts. 505 */ 506 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE); 507 508 return 0; 509} 510 511static void serial_txx9_shutdown(struct uart_port *port) 512{ 513 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 514 unsigned long flags; 515 516 /* 517 * Disable interrupts from this port 518 */ 519 sio_out(up, TXX9_SIDICR, 0); /* disable all intrs */ 520 521 spin_lock_irqsave(&up->port.lock, flags); 522 serial_txx9_set_mctrl(&up->port, up->port.mctrl); 523 spin_unlock_irqrestore(&up->port.lock, flags); 524 525 /* 526 * Disable break condition 527 */ 528 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK); 529 530#ifdef CONFIG_SERIAL_TXX9_CONSOLE 531 if (up->port.cons && up->port.line == up->port.cons->index) { 532 free_irq(up->port.irq, up); 533 return; 534 } 535#endif 536 /* reset FIFOs */ 537 sio_set(up, TXX9_SIFCR, 538 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE); 539 /* clear reset */ 540 sio_mask(up, TXX9_SIFCR, 541 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE); 542 543 /* Disable RX/TX */ 544 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE); 545 546 free_irq(up->port.irq, up); 547} 548 549static void 550serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios, 551 struct ktermios *old) 552{ 553 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 554 unsigned int cval, fcr = 0; 555 unsigned long flags; 556 unsigned int baud, quot; 557 558 cval = sio_in(up, TXX9_SILCR); 559 /* byte size and parity */ 560 cval &= ~TXX9_SILCR_UMODE_MASK; 561 switch (termios->c_cflag & CSIZE) { 562 case CS7: 563 cval |= TXX9_SILCR_UMODE_7BIT; 564 break; 565 default: 566 case CS5: /* not supported */ 567 case CS6: /* not supported */ 568 case CS8: 569 cval |= TXX9_SILCR_UMODE_8BIT; 570 break; 571 } 572 573 cval &= ~TXX9_SILCR_USBL_MASK; 574 if (termios->c_cflag & CSTOPB) 575 cval |= TXX9_SILCR_USBL_2BIT; 576 else 577 cval |= TXX9_SILCR_USBL_1BIT; 578 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS); 579 if (termios->c_cflag & PARENB) 580 cval |= TXX9_SILCR_UPEN; 581 if (!(termios->c_cflag & PARODD)) 582 cval |= TXX9_SILCR_UEPS; 583 584 /* 585 * Ask the core to calculate the divisor for us. 586 */ 587 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2); 588 quot = uart_get_divisor(port, baud); 589 590 /* Set up FIFOs */ 591 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */ 592 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1; 593 594 /* 595 * Ok, we're now changing the port state. Do it with 596 * interrupts disabled. 597 */ 598 spin_lock_irqsave(&up->port.lock, flags); 599 600 /* 601 * Update the per-port timeout. 602 */ 603 uart_update_timeout(port, termios->c_cflag, baud); 604 605 up->port.read_status_mask = TXX9_SIDISR_UOER | 606 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS; 607 if (termios->c_iflag & INPCK) 608 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER; 609 if (termios->c_iflag & (BRKINT | PARMRK)) 610 up->port.read_status_mask |= TXX9_SIDISR_UBRK; 611 612 /* 613 * Characteres to ignore 614 */ 615 up->port.ignore_status_mask = 0; 616 if (termios->c_iflag & IGNPAR) 617 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER; 618 if (termios->c_iflag & IGNBRK) { 619 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK; 620 /* 621 * If we're ignoring parity and break indicators, 622 * ignore overruns too (for real raw support). 623 */ 624 if (termios->c_iflag & IGNPAR) 625 up->port.ignore_status_mask |= TXX9_SIDISR_UOER; 626 } 627 628 /* 629 * ignore all characters if CREAD is not set 630 */ 631 if ((termios->c_cflag & CREAD) == 0) 632 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS; 633 634 /* CTS flow control flag */ 635 if ((termios->c_cflag & CRTSCTS) && 636 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) { 637 sio_set(up, TXX9_SIFLCR, 638 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES); 639 } else { 640 sio_mask(up, TXX9_SIFLCR, 641 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES); 642 } 643 644 sio_out(up, TXX9_SILCR, cval); 645 sio_quot_set(up, quot); 646 sio_out(up, TXX9_SIFCR, fcr); 647 648 serial_txx9_set_mctrl(&up->port, up->port.mctrl); 649 spin_unlock_irqrestore(&up->port.lock, flags); 650} 651 652static void 653serial_txx9_pm(struct uart_port *port, unsigned int state, 654 unsigned int oldstate) 655{ 656 if (state == 0) 657 serial_txx9_initialize(port); 658} 659 660static int serial_txx9_request_resource(struct uart_txx9_port *up) 661{ 662 unsigned int size = TXX9_REGION_SIZE; 663 int ret = 0; 664 665 switch (up->port.iotype) { 666 default: 667 if (!up->port.mapbase) 668 break; 669 670 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) { 671 ret = -EBUSY; 672 break; 673 } 674 675 if (up->port.flags & UPF_IOREMAP) { 676 up->port.membase = ioremap(up->port.mapbase, size); 677 if (!up->port.membase) { 678 release_mem_region(up->port.mapbase, size); 679 ret = -ENOMEM; 680 } 681 } 682 break; 683 684 case UPIO_PORT: 685 if (!request_region(up->port.iobase, size, "serial_txx9")) 686 ret = -EBUSY; 687 break; 688 } 689 return ret; 690} 691 692static void serial_txx9_release_resource(struct uart_txx9_port *up) 693{ 694 unsigned int size = TXX9_REGION_SIZE; 695 696 switch (up->port.iotype) { 697 default: 698 if (!up->port.mapbase) 699 break; 700 701 if (up->port.flags & UPF_IOREMAP) { 702 iounmap(up->port.membase); 703 up->port.membase = NULL; 704 } 705 706 release_mem_region(up->port.mapbase, size); 707 break; 708 709 case UPIO_PORT: 710 release_region(up->port.iobase, size); 711 break; 712 } 713} 714 715static void serial_txx9_release_port(struct uart_port *port) 716{ 717 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 718 serial_txx9_release_resource(up); 719} 720 721static int serial_txx9_request_port(struct uart_port *port) 722{ 723 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 724 return serial_txx9_request_resource(up); 725} 726 727static void serial_txx9_config_port(struct uart_port *port, int uflags) 728{ 729 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 730 int ret; 731 732 /* 733 * Find the region that we can probe for. This in turn 734 * tells us whether we can probe for the type of port. 735 */ 736 ret = serial_txx9_request_resource(up); 737 if (ret < 0) 738 return; 739 port->type = PORT_TXX9; 740 up->port.fifosize = TXX9_SIO_TX_FIFO; 741 742#ifdef CONFIG_SERIAL_TXX9_CONSOLE 743 if (up->port.line == up->port.cons->index) 744 return; 745#endif 746 serial_txx9_initialize(port); 747} 748 749static int 750serial_txx9_verify_port(struct uart_port *port, struct serial_struct *ser) 751{ 752 unsigned long new_port = ser->port; 753 if (HIGH_BITS_OFFSET) 754 new_port += (unsigned long)ser->port_high << HIGH_BITS_OFFSET; 755 if (ser->type != port->type || 756 ser->irq != port->irq || 757 ser->io_type != port->iotype || 758 new_port != port->iobase || 759 (unsigned long)ser->iomem_base != port->mapbase) 760 return -EINVAL; 761 return 0; 762} 763 764static const char * 765serial_txx9_type(struct uart_port *port) 766{ 767 return "txx9"; 768} 769 770static struct uart_ops serial_txx9_pops = { 771 .tx_empty = serial_txx9_tx_empty, 772 .set_mctrl = serial_txx9_set_mctrl, 773 .get_mctrl = serial_txx9_get_mctrl, 774 .stop_tx = serial_txx9_stop_tx, 775 .start_tx = serial_txx9_start_tx, 776 .stop_rx = serial_txx9_stop_rx, 777 .enable_ms = serial_txx9_enable_ms, 778 .break_ctl = serial_txx9_break_ctl, 779 .startup = serial_txx9_startup, 780 .shutdown = serial_txx9_shutdown, 781 .set_termios = serial_txx9_set_termios, 782 .pm = serial_txx9_pm, 783 .type = serial_txx9_type, 784 .release_port = serial_txx9_release_port, 785 .request_port = serial_txx9_request_port, 786 .config_port = serial_txx9_config_port, 787 .verify_port = serial_txx9_verify_port, 788}; 789 790static struct uart_txx9_port serial_txx9_ports[UART_NR]; 791 792static void __init serial_txx9_register_ports(struct uart_driver *drv, 793 struct device *dev) 794{ 795 int i; 796 797 for (i = 0; i < UART_NR; i++) { 798 struct uart_txx9_port *up = &serial_txx9_ports[i]; 799 800 up->port.line = i; 801 up->port.ops = &serial_txx9_pops; 802 up->port.dev = dev; 803 if (up->port.iobase || up->port.mapbase) 804 uart_add_one_port(drv, &up->port); 805 } 806} 807 808#ifdef CONFIG_SERIAL_TXX9_CONSOLE 809 810/* 811 * Wait for transmitter & holding register to empty 812 */ 813static inline void wait_for_xmitr(struct uart_txx9_port *up) 814{ 815 unsigned int tmout = 10000; 816 817 /* Wait up to 10ms for the character(s) to be sent. */ 818 while (--tmout && 819 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS)) 820 udelay(1); 821 822 /* Wait up to 1s for flow control if necessary */ 823 if (up->port.flags & UPF_CONS_FLOW) { 824 tmout = 1000000; 825 while (--tmout && 826 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS)) 827 udelay(1); 828 } 829} 830 831static void serial_txx9_console_putchar(struct uart_port *port, int ch) 832{ 833 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 834 835 wait_for_xmitr(up); 836 sio_out(up, TXX9_SITFIFO, ch); 837} 838 839/* 840 * Print a string to the serial port trying not to disturb 841 * any possible real use of the port... 842 * 843 * The console_lock must be held when we get here. 844 */ 845static void 846serial_txx9_console_write(struct console *co, const char *s, unsigned int count) 847{ 848 struct uart_txx9_port *up = &serial_txx9_ports[co->index]; 849 unsigned int ier, flcr; 850 851 /* 852 * First save the UER then disable the interrupts 853 */ 854 ier = sio_in(up, TXX9_SIDICR); 855 sio_out(up, TXX9_SIDICR, 0); 856 /* 857 * Disable flow-control if enabled (and unnecessary) 858 */ 859 flcr = sio_in(up, TXX9_SIFLCR); 860 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES)) 861 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES); 862 863 uart_console_write(&up->port, s, count, serial_txx9_console_putchar); 864 865 /* 866 * Finally, wait for transmitter to become empty 867 * and restore the IER 868 */ 869 wait_for_xmitr(up); 870 sio_out(up, TXX9_SIFLCR, flcr); 871 sio_out(up, TXX9_SIDICR, ier); 872} 873 874static int __init serial_txx9_console_setup(struct console *co, char *options) 875{ 876 struct uart_port *port; 877 struct uart_txx9_port *up; 878 int baud = 9600; 879 int bits = 8; 880 int parity = 'n'; 881 int flow = 'n'; 882 883 /* 884 * Check whether an invalid uart number has been specified, and 885 * if so, search for the first available port that does have 886 * console support. 887 */ 888 if (co->index >= UART_NR) 889 co->index = 0; 890 up = &serial_txx9_ports[co->index]; 891 port = &up->port; 892 if (!port->ops) 893 return -ENODEV; 894 895 serial_txx9_initialize(&up->port); 896 897 if (options) 898 uart_parse_options(options, &baud, &parity, &bits, &flow); 899 900 return uart_set_options(port, co, baud, parity, bits, flow); 901} 902 903static struct uart_driver serial_txx9_reg; 904static struct console serial_txx9_console = { 905 .name = TXX9_TTY_NAME, 906 .write = serial_txx9_console_write, 907 .device = uart_console_device, 908 .setup = serial_txx9_console_setup, 909 .flags = CON_PRINTBUFFER, 910 .index = -1, 911 .data = &serial_txx9_reg, 912}; 913 914static int __init serial_txx9_console_init(void) 915{ 916 register_console(&serial_txx9_console); 917 return 0; 918} 919console_initcall(serial_txx9_console_init); 920 921#define SERIAL_TXX9_CONSOLE &serial_txx9_console 922#else 923#define SERIAL_TXX9_CONSOLE NULL 924#endif 925 926static struct uart_driver serial_txx9_reg = { 927 .owner = THIS_MODULE, 928 .driver_name = "serial_txx9", 929 .dev_name = TXX9_TTY_NAME, 930 .major = TXX9_TTY_MAJOR, 931 .minor = TXX9_TTY_MINOR_START, 932 .nr = UART_NR, 933 .cons = SERIAL_TXX9_CONSOLE, 934}; 935 936int __init early_serial_txx9_setup(struct uart_port *port) 937{ 938 if (port->line >= ARRAY_SIZE(serial_txx9_ports)) 939 return -ENODEV; 940 941 serial_txx9_ports[port->line].port = *port; 942 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops; 943 serial_txx9_ports[port->line].port.flags |= UPF_BOOT_AUTOCONF; 944 return 0; 945} 946 947static DEFINE_MUTEX(serial_txx9_mutex); 948 949/** 950 * serial_txx9_register_port - register a serial port 951 * @port: serial port template 952 * 953 * Configure the serial port specified by the request. 954 * 955 * The port is then probed and if necessary the IRQ is autodetected 956 * If this fails an error is returned. 957 * 958 * On success the port is ready to use and the line number is returned. 959 */ 960static int __devinit serial_txx9_register_port(struct uart_port *port) 961{ 962 int i; 963 struct uart_txx9_port *uart; 964 int ret = -ENOSPC; 965 966 mutex_lock(&serial_txx9_mutex); 967 for (i = 0; i < UART_NR; i++) { 968 uart = &serial_txx9_ports[i]; 969 if (uart_match_port(&uart->port, port)) { 970 uart_remove_one_port(&serial_txx9_reg, &uart->port); 971 break; 972 } 973 } 974 if (i == UART_NR) { 975 /* Find unused port */ 976 for (i = 0; i < UART_NR; i++) { 977 uart = &serial_txx9_ports[i]; 978 if (!(uart->port.iobase || uart->port.mapbase)) 979 break; 980 } 981 } 982 if (i < UART_NR) { 983 uart->port.iobase = port->iobase; 984 uart->port.membase = port->membase; 985 uart->port.irq = port->irq; 986 uart->port.uartclk = port->uartclk; 987 uart->port.iotype = port->iotype; 988 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; 989 uart->port.mapbase = port->mapbase; 990 if (port->dev) 991 uart->port.dev = port->dev; 992 ret = uart_add_one_port(&serial_txx9_reg, &uart->port); 993 if (ret == 0) 994 ret = uart->port.line; 995 } 996 mutex_unlock(&serial_txx9_mutex); 997 return ret; 998} 999 1000/** 1001 * serial_txx9_unregister_port - remove a txx9 serial port at runtime 1002 * @line: serial line number 1003 * 1004 * Remove one serial port. This may not be called from interrupt 1005 * context. We hand the port back to the our control. 1006 */ 1007static void __devexit serial_txx9_unregister_port(int line) 1008{ 1009 struct uart_txx9_port *uart = &serial_txx9_ports[line]; 1010 1011 mutex_lock(&serial_txx9_mutex); 1012 uart_remove_one_port(&serial_txx9_reg, &uart->port); 1013 uart->port.flags = 0; 1014 uart->port.type = PORT_UNKNOWN; 1015 uart->port.iobase = 0; 1016 uart->port.mapbase = 0; 1017 uart->port.membase = NULL; 1018 uart->port.dev = NULL; 1019 mutex_unlock(&serial_txx9_mutex); 1020} 1021 1022/* 1023 * Register a set of serial devices attached to a platform device. 1024 */ 1025static int __devinit serial_txx9_probe(struct platform_device *dev) 1026{ 1027 struct uart_port *p = dev->dev.platform_data; 1028 struct uart_port port; 1029 int ret, i; 1030 1031 memset(&port, 0, sizeof(struct uart_port)); 1032 for (i = 0; p && p->uartclk != 0; p++, i++) { 1033 port.iobase = p->iobase; 1034 port.membase = p->membase; 1035 port.irq = p->irq; 1036 port.uartclk = p->uartclk; 1037 port.iotype = p->iotype; 1038 port.flags = p->flags; 1039 port.mapbase = p->mapbase; 1040 port.dev = &dev->dev; 1041 ret = serial_txx9_register_port(&port); 1042 if (ret < 0) { 1043 dev_err(&dev->dev, "unable to register port at index %d " 1044 "(IO%x MEM%lx IRQ%d): %d\n", i, 1045 p->iobase, p->mapbase, p->irq, ret); 1046 } 1047 } 1048 return 0; 1049} 1050 1051/* 1052 * Remove serial ports registered against a platform device. 1053 */ 1054static int __devexit serial_txx9_remove(struct platform_device *dev) 1055{ 1056 int i; 1057 1058 for (i = 0; i < UART_NR; i++) { 1059 struct uart_txx9_port *up = &serial_txx9_ports[i]; 1060 1061 if (up->port.dev == &dev->dev) 1062 serial_txx9_unregister_port(i); 1063 } 1064 return 0; 1065} 1066 1067#ifdef CONFIG_PM 1068static int serial_txx9_suspend(struct platform_device *dev, pm_message_t state) 1069{ 1070 int i; 1071 1072 for (i = 0; i < UART_NR; i++) { 1073 struct uart_txx9_port *up = &serial_txx9_ports[i]; 1074 1075 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) 1076 uart_suspend_port(&serial_txx9_reg, &up->port); 1077 } 1078 1079 return 0; 1080} 1081 1082static int serial_txx9_resume(struct platform_device *dev) 1083{ 1084 int i; 1085 1086 for (i = 0; i < UART_NR; i++) { 1087 struct uart_txx9_port *up = &serial_txx9_ports[i]; 1088 1089 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) 1090 uart_resume_port(&serial_txx9_reg, &up->port); 1091 } 1092 1093 return 0; 1094} 1095#endif 1096 1097static struct platform_driver serial_txx9_plat_driver = { 1098 .probe = serial_txx9_probe, 1099 .remove = __devexit_p(serial_txx9_remove), 1100#ifdef CONFIG_PM 1101 .suspend = serial_txx9_suspend, 1102 .resume = serial_txx9_resume, 1103#endif 1104 .driver = { 1105 .name = "serial_txx9", 1106 .owner = THIS_MODULE, 1107 }, 1108}; 1109 1110#ifdef ENABLE_SERIAL_TXX9_PCI 1111/* 1112 * Probe one serial board. Unfortunately, there is no rhyme nor reason 1113 * to the arrangement of serial ports on a PCI card. 1114 */ 1115static int __devinit 1116pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 1117{ 1118 struct uart_port port; 1119 int line; 1120 int rc; 1121 1122 rc = pci_enable_device(dev); 1123 if (rc) 1124 return rc; 1125 1126 memset(&port, 0, sizeof(port)); 1127 port.ops = &serial_txx9_pops; 1128 port.flags |= UPF_TXX9_HAVE_CTS_LINE; 1129 port.uartclk = 66670000; 1130 port.irq = dev->irq; 1131 port.iotype = UPIO_PORT; 1132 port.iobase = pci_resource_start(dev, 1); 1133 port.dev = &dev->dev; 1134 line = serial_txx9_register_port(&port); 1135 if (line < 0) { 1136 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line); 1137 pci_disable_device(dev); 1138 return line; 1139 } 1140 pci_set_drvdata(dev, &serial_txx9_ports[line]); 1141 1142 return 0; 1143} 1144 1145static void __devexit pciserial_txx9_remove_one(struct pci_dev *dev) 1146{ 1147 struct uart_txx9_port *up = pci_get_drvdata(dev); 1148 1149 pci_set_drvdata(dev, NULL); 1150 1151 if (up) { 1152 serial_txx9_unregister_port(up->port.line); 1153 pci_disable_device(dev); 1154 } 1155} 1156 1157#ifdef CONFIG_PM 1158static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state) 1159{ 1160 struct uart_txx9_port *up = pci_get_drvdata(dev); 1161 1162 if (up) 1163 uart_suspend_port(&serial_txx9_reg, &up->port); 1164 pci_save_state(dev); 1165 pci_set_power_state(dev, pci_choose_state(dev, state)); 1166 return 0; 1167} 1168 1169static int pciserial_txx9_resume_one(struct pci_dev *dev) 1170{ 1171 struct uart_txx9_port *up = pci_get_drvdata(dev); 1172 1173 pci_set_power_state(dev, PCI_D0); 1174 pci_restore_state(dev); 1175 if (up) 1176 uart_resume_port(&serial_txx9_reg, &up->port); 1177 return 0; 1178} 1179#endif 1180 1181static const struct pci_device_id serial_txx9_pci_tbl[] = { 1182 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC) }, 1183 { 0, } 1184}; 1185 1186static struct pci_driver serial_txx9_pci_driver = { 1187 .name = "serial_txx9", 1188 .probe = pciserial_txx9_init_one, 1189 .remove = __devexit_p(pciserial_txx9_remove_one), 1190#ifdef CONFIG_PM 1191 .suspend = pciserial_txx9_suspend_one, 1192 .resume = pciserial_txx9_resume_one, 1193#endif 1194 .id_table = serial_txx9_pci_tbl, 1195}; 1196 1197MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl); 1198#endif /* ENABLE_SERIAL_TXX9_PCI */ 1199 1200static struct platform_device *serial_txx9_plat_devs; 1201 1202static int __init serial_txx9_init(void) 1203{ 1204 int ret; 1205 1206 printk(KERN_INFO "%s version %s\n", serial_name, serial_version); 1207 1208 ret = uart_register_driver(&serial_txx9_reg); 1209 if (ret) 1210 goto out; 1211 1212 serial_txx9_plat_devs = platform_device_alloc("serial_txx9", -1); 1213 if (!serial_txx9_plat_devs) { 1214 ret = -ENOMEM; 1215 goto unreg_uart_drv; 1216 } 1217 1218 ret = platform_device_add(serial_txx9_plat_devs); 1219 if (ret) 1220 goto put_dev; 1221 1222 serial_txx9_register_ports(&serial_txx9_reg, 1223 &serial_txx9_plat_devs->dev); 1224 1225 ret = platform_driver_register(&serial_txx9_plat_driver); 1226 if (ret) 1227 goto del_dev; 1228 1229#ifdef ENABLE_SERIAL_TXX9_PCI 1230 ret = pci_register_driver(&serial_txx9_pci_driver); 1231#endif 1232 if (ret == 0) 1233 goto out; 1234 1235 del_dev: 1236 platform_device_del(serial_txx9_plat_devs); 1237 put_dev: 1238 platform_device_put(serial_txx9_plat_devs); 1239 unreg_uart_drv: 1240 uart_unregister_driver(&serial_txx9_reg); 1241 out: 1242 return ret; 1243} 1244 1245static void __exit serial_txx9_exit(void) 1246{ 1247 int i; 1248 1249#ifdef ENABLE_SERIAL_TXX9_PCI 1250 pci_unregister_driver(&serial_txx9_pci_driver); 1251#endif 1252 platform_driver_unregister(&serial_txx9_plat_driver); 1253 platform_device_unregister(serial_txx9_plat_devs); 1254 for (i = 0; i < UART_NR; i++) { 1255 struct uart_txx9_port *up = &serial_txx9_ports[i]; 1256 if (up->port.iobase || up->port.mapbase) 1257 uart_remove_one_port(&serial_txx9_reg, &up->port); 1258 } 1259 1260 uart_unregister_driver(&serial_txx9_reg); 1261} 1262 1263module_init(serial_txx9_init); 1264module_exit(serial_txx9_exit); 1265 1266MODULE_LICENSE("GPL"); 1267MODULE_DESCRIPTION("TX39/49 serial driver"); 1268 1269MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR); 1270