1/* 2 * linux/drivers/serial/cpm_uart.c 3 * 4 * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions 5 * 6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) 7 * Pantelis Antoniou (panto@intracom.gr) (CPM1) 8 * 9 * Copyright (C) 2004 Freescale Semiconductor, Inc. 10 * (C) 2004 Intracom, S.A. 11 * (C) 2006 MontaVista Software, Inc. 12 * Vitaly Bordug <vbordug@ru.mvista.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 27 * 28 */ 29 30#include <linux/module.h> 31#include <linux/tty.h> 32#include <linux/ioport.h> 33#include <linux/init.h> 34#include <linux/serial.h> 35#include <linux/console.h> 36#include <linux/sysrq.h> 37#include <linux/device.h> 38#include <linux/bootmem.h> 39#include <linux/dma-mapping.h> 40 41#include <asm/io.h> 42#include <asm/irq.h> 43#include <asm/fs_pd.h> 44 45#include <linux/serial_core.h> 46#include <linux/kernel.h> 47 48#include "cpm_uart.h" 49 50/**************************************************************/ 51 52void cpm_line_cr_cmd(int line, int cmd) 53{ 54 ushort val; 55 volatile cpm8xx_t *cp = cpmp; 56 57 switch (line) { 58 case UART_SMC1: 59 val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG; 60 break; 61 case UART_SMC2: 62 val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG; 63 break; 64 case UART_SCC1: 65 val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG; 66 break; 67 case UART_SCC2: 68 val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG; 69 break; 70 case UART_SCC3: 71 val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG; 72 break; 73 case UART_SCC4: 74 val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG; 75 break; 76 default: 77 return; 78 79 } 80 cp->cp_cpcr = val; 81 while (cp->cp_cpcr & CPM_CR_FLG) ; 82} 83 84void smc1_lineif(struct uart_cpm_port *pinfo) 85{ 86 pinfo->brg = 1; 87} 88 89void smc2_lineif(struct uart_cpm_port *pinfo) 90{ 91 pinfo->brg = 2; 92} 93 94void scc1_lineif(struct uart_cpm_port *pinfo) 95{ 96 pinfo->brg = 1; 97} 98 99void scc2_lineif(struct uart_cpm_port *pinfo) 100{ 101 pinfo->brg = 2; 102} 103 104void scc3_lineif(struct uart_cpm_port *pinfo) 105{ 106 pinfo->brg = 3; 107} 108 109void scc4_lineif(struct uart_cpm_port *pinfo) 110{ 111 pinfo->brg = 4; 112} 113 114/* 115 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and 116 * receive buffer descriptors from dual port ram, and a character 117 * buffer area from host mem. If we are allocating for the console we need 118 * to do it from bootmem 119 */ 120int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con) 121{ 122 int dpmemsz, memsz; 123 u8 *dp_mem; 124 unsigned long dp_offset; 125 u8 *mem_addr; 126 dma_addr_t dma_addr = 0; 127 128 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line); 129 130 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos); 131 dp_offset = cpm_dpalloc(dpmemsz, 8); 132 if (IS_ERR_VALUE(dp_offset)) { 133 printk(KERN_ERR 134 "cpm_uart_cpm1.c: could not allocate buffer descriptors\n"); 135 return -ENOMEM; 136 } 137 dp_mem = cpm_dpram_addr(dp_offset); 138 139 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) + 140 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize); 141 if (is_con) { 142 /* was hostalloc but changed cause it blows away the */ 143 /* large tlb mapping when pinning the kernel area */ 144 mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8)); 145 dma_addr = (u32)cpm_dpram_phys(mem_addr); 146 } else 147 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr, 148 GFP_KERNEL); 149 150 if (mem_addr == NULL) { 151 cpm_dpfree(dp_offset); 152 printk(KERN_ERR 153 "cpm_uart_cpm1.c: could not allocate coherent memory\n"); 154 return -ENOMEM; 155 } 156 157 pinfo->dp_addr = dp_offset; 158 pinfo->mem_addr = mem_addr; /* virtual address*/ 159 pinfo->dma_addr = dma_addr; /* physical address*/ 160 pinfo->mem_size = memsz; 161 162 pinfo->rx_buf = mem_addr; 163 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos 164 * pinfo->rx_fifosize); 165 166 pinfo->rx_bd_base = (volatile cbd_t *)dp_mem; 167 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos; 168 169 return 0; 170} 171 172void cpm_uart_freebuf(struct uart_cpm_port *pinfo) 173{ 174 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos * 175 pinfo->rx_fifosize) + 176 L1_CACHE_ALIGN(pinfo->tx_nrfifos * 177 pinfo->tx_fifosize), pinfo->mem_addr, 178 pinfo->dma_addr); 179 180 cpm_dpfree(pinfo->dp_addr); 181} 182 183/* Setup any dynamic params in the uart desc */ 184int cpm_uart_init_portdesc(void) 185{ 186 pr_debug("CPM uart[-]:init portdesc\n"); 187 188 cpm_uart_nr = 0; 189#ifdef CONFIG_SERIAL_CPM_SMC1 190 cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0]; 191/* 192 * Is SMC1 being relocated? 193 */ 194# ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH 195 cpm_uart_ports[UART_SMC1].smcup = 196 (smc_uart_t *) & cpmp->cp_dparam[0x3C0]; 197# else 198 cpm_uart_ports[UART_SMC1].smcup = 199 (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1]; 200# endif 201 cpm_uart_ports[UART_SMC1].port.mapbase = 202 (unsigned long)&cpmp->cp_smc[0]; 203 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX); 204 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); 205 cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock(); 206 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1; 207#endif 208 209#ifdef CONFIG_SERIAL_CPM_SMC2 210 cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1]; 211 cpm_uart_ports[UART_SMC2].smcup = 212 (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2]; 213 cpm_uart_ports[UART_SMC2].port.mapbase = 214 (unsigned long)&cpmp->cp_smc[1]; 215 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX); 216 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); 217 cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock(); 218 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2; 219#endif 220 221#ifdef CONFIG_SERIAL_CPM_SCC1 222 cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0]; 223 cpm_uart_ports[UART_SCC1].sccup = 224 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1]; 225 cpm_uart_ports[UART_SCC1].port.mapbase = 226 (unsigned long)&cpmp->cp_scc[0]; 227 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &= 228 ~(UART_SCCM_TX | UART_SCCM_RX); 229 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &= 230 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); 231 cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock(); 232 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1; 233#endif 234 235#ifdef CONFIG_SERIAL_CPM_SCC2 236 cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1]; 237 cpm_uart_ports[UART_SCC2].sccup = 238 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2]; 239 cpm_uart_ports[UART_SCC2].port.mapbase = 240 (unsigned long)&cpmp->cp_scc[1]; 241 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &= 242 ~(UART_SCCM_TX | UART_SCCM_RX); 243 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &= 244 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); 245 cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock(); 246 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2; 247#endif 248 249#ifdef CONFIG_SERIAL_CPM_SCC3 250 cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2]; 251 cpm_uart_ports[UART_SCC3].sccup = 252 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3]; 253 cpm_uart_ports[UART_SCC3].port.mapbase = 254 (unsigned long)&cpmp->cp_scc[2]; 255 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &= 256 ~(UART_SCCM_TX | UART_SCCM_RX); 257 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &= 258 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); 259 cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock(); 260 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3; 261#endif 262 263#ifdef CONFIG_SERIAL_CPM_SCC4 264 cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3]; 265 cpm_uart_ports[UART_SCC4].sccup = 266 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4]; 267 cpm_uart_ports[UART_SCC4].port.mapbase = 268 (unsigned long)&cpmp->cp_scc[3]; 269 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &= 270 ~(UART_SCCM_TX | UART_SCCM_RX); 271 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &= 272 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); 273 cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock(); 274 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4; 275#endif 276 return 0; 277} 278