1/* 2 * linux/drivers/char/8250.c 3 * 4 * Driver for 8250/16550-type serial ports 5 * 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * Copyright (C) 2001 Russell King. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * $Id: 8250.c,v 1.1.1.1 2007/08/03 18:53:00 Exp $ 16 * 17 * A note about mapbase / membase 18 * 19 * mapbase is the physical address of the IO port. 20 * membase is an 'ioremapped' cookie. 21 */ 22 23#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24#define SUPPORT_SYSRQ 25#endif 26 27#include <linux/module.h> 28#include <linux/moduleparam.h> 29#include <linux/ioport.h> 30#include <linux/init.h> 31#include <linux/console.h> 32#include <linux/sysrq.h> 33#include <linux/delay.h> 34#include <linux/platform_device.h> 35#include <linux/tty.h> 36#include <linux/tty_flip.h> 37#include <linux/serial_reg.h> 38#include <linux/serial_core.h> 39#include <linux/serial.h> 40#include <linux/serial_8250.h> 41#include <linux/nmi.h> 42#include <linux/mutex.h> 43 44#include <asm/io.h> 45#include <asm/irq.h> 46 47#include "8250.h" 48 49/* 50 * Configuration: 51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option 52 * is unsafe when used on edge-triggered interrupts. 53 */ 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; 55 56static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; 57 58/* 59 * Debugging. 60 */ 61#define DEBUG_AUTOCONF(fmt...) do { } while (0) 62 63#define DEBUG_INTR(fmt...) do { } while (0) 64 65#define PASS_LIMIT 256 66 67/* 68 * We default to IRQ0 for the "no irq" hack. Some 69 * machine types want others as well - they're free 70 * to redefine this in their header file. 71 */ 72#define is_real_interrupt(irq) ((irq) != 0) 73 74#ifdef CONFIG_SERIAL_8250_DETECT_IRQ 75#define CONFIG_SERIAL_DETECT_IRQ 1 76#endif 77#ifdef CONFIG_SERIAL_8250_MANY_PORTS 78#define CONFIG_SERIAL_MANY_PORTS 1 79#endif 80 81/* 82 * HUB6 is always on. This will be removed once the header 83 * files have been cleaned. 84 */ 85#define CONFIG_HUB6 1 86 87#include <asm/serial.h> 88 89/* 90 * SERIAL_PORT_DFNS tells us about built-in ports that have no 91 * standard enumeration mechanism. Platforms that can find all 92 * serial ports via mechanisms like ACPI or PCI need not supply it. 93 */ 94#ifndef SERIAL_PORT_DFNS 95#define SERIAL_PORT_DFNS 96#endif 97 98static const struct old_serial_port old_serial_port[] = { 99 SERIAL_PORT_DFNS /* defined in asm/serial.h */ 100}; 101 102#define UART_NR CONFIG_SERIAL_8250_NR_UARTS 103 104#ifdef CONFIG_SERIAL_8250_RSA 105 106#define PORT_RSA_MAX 4 107static unsigned long probe_rsa[PORT_RSA_MAX]; 108static unsigned int probe_rsa_count; 109#endif /* CONFIG_SERIAL_8250_RSA */ 110 111struct uart_8250_port { 112 struct uart_port port; 113 struct timer_list timer; /* "no irq" timer */ 114 struct list_head list; /* ports on this IRQ */ 115 unsigned short capabilities; /* port capabilities */ 116 unsigned short bugs; /* port bugs */ 117 unsigned int tx_loadsz; /* transmit fifo load size */ 118 unsigned char acr; 119 unsigned char ier; 120 unsigned char lcr; 121 unsigned char mcr; 122 unsigned char mcr_mask; /* mask of user bits */ 123 unsigned char mcr_force; /* mask of forced bits */ 124 unsigned char lsr_break_flag; 125 126 /* 127 * We provide a per-port pm hook. 128 */ 129 void (*pm)(struct uart_port *port, 130 unsigned int state, unsigned int old); 131}; 132 133struct irq_info { 134 spinlock_t lock; 135 struct list_head *head; 136}; 137 138static struct irq_info irq_lists[NR_IRQS]; 139 140/* 141 * Here we define the default xmit fifo size used for each type of UART. 142 */ 143static const struct serial8250_config uart_config[] = { 144 [PORT_UNKNOWN] = { 145 .name = "unknown", 146 .fifo_size = 1, 147 .tx_loadsz = 1, 148 }, 149 [PORT_8250] = { 150 .name = "8250", 151 .fifo_size = 1, 152 .tx_loadsz = 1, 153 }, 154 [PORT_16450] = { 155 .name = "16450", 156 .fifo_size = 1, 157 .tx_loadsz = 1, 158 }, 159 [PORT_16550] = { 160 .name = "16550", 161 .fifo_size = 1, 162 .tx_loadsz = 1, 163 }, 164 [PORT_16550A] = { 165 .name = "16550A", 166 .fifo_size = 16, 167 .tx_loadsz = 16, 168 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 169 .flags = UART_CAP_FIFO, 170 }, 171 [PORT_CIRRUS] = { 172 .name = "Cirrus", 173 .fifo_size = 1, 174 .tx_loadsz = 1, 175 }, 176 [PORT_16650] = { 177 .name = "ST16650", 178 .fifo_size = 1, 179 .tx_loadsz = 1, 180 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 181 }, 182 [PORT_16650V2] = { 183 .name = "ST16650V2", 184 .fifo_size = 32, 185 .tx_loadsz = 16, 186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 187 UART_FCR_T_TRIG_00, 188 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 189 }, 190 [PORT_16750] = { 191 .name = "TI16750", 192 .fifo_size = 64, 193 .tx_loadsz = 64, 194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 195 UART_FCR7_64BYTE, 196 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, 197 }, 198 [PORT_STARTECH] = { 199 .name = "Startech", 200 .fifo_size = 1, 201 .tx_loadsz = 1, 202 }, 203 [PORT_16C950] = { 204 .name = "16C950/954", 205 .fifo_size = 128, 206 .tx_loadsz = 128, 207 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 208 .flags = UART_CAP_FIFO, 209 }, 210 [PORT_16654] = { 211 .name = "ST16654", 212 .fifo_size = 64, 213 .tx_loadsz = 32, 214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 215 UART_FCR_T_TRIG_10, 216 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 217 }, 218 [PORT_16850] = { 219 .name = "XR16850", 220 .fifo_size = 128, 221 .tx_loadsz = 128, 222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 223 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 224 }, 225 [PORT_RSA] = { 226 .name = "RSA", 227 .fifo_size = 2048, 228 .tx_loadsz = 2048, 229 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, 230 .flags = UART_CAP_FIFO, 231 }, 232 [PORT_NS16550A] = { 233 .name = "NS16550A", 234 .fifo_size = 16, 235 .tx_loadsz = 16, 236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 237 .flags = UART_CAP_FIFO | UART_NATSEMI, 238 }, 239 [PORT_XSCALE] = { 240 .name = "XScale", 241 .fifo_size = 32, 242 .tx_loadsz = 32, 243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 244 .flags = UART_CAP_FIFO | UART_CAP_UUE, 245 }, 246 [PORT_RM9000] = { 247 .name = "RM9000", 248 .fifo_size = 16, 249 .tx_loadsz = 16, 250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 251 .flags = UART_CAP_FIFO, 252 }, 253}; 254 255#if defined(CONFIG_SERIAL_8250_AU1X00) 256 257/* Au1x00 UART hardware has a weird register layout */ 258static const u8 au_io_in_map[] = { 259 [UART_RX] = 0, 260 [UART_IER] = 2, 261 [UART_IIR] = 3, 262 [UART_LCR] = 5, 263 [UART_MCR] = 6, 264 [UART_LSR] = 7, 265 [UART_MSR] = 8, 266}; 267 268static const u8 au_io_out_map[] = { 269 [UART_TX] = 1, 270 [UART_IER] = 2, 271 [UART_FCR] = 4, 272 [UART_LCR] = 5, 273 [UART_MCR] = 6, 274}; 275 276/* sane hardware needs no mapping */ 277static inline int map_8250_in_reg(struct uart_8250_port *up, int offset) 278{ 279 if (up->port.iotype != UPIO_AU) 280 return offset; 281 return au_io_in_map[offset]; 282} 283 284static inline int map_8250_out_reg(struct uart_8250_port *up, int offset) 285{ 286 if (up->port.iotype != UPIO_AU) 287 return offset; 288 return au_io_out_map[offset]; 289} 290 291#elif defined(CONFIG_SERIAL_8250_RM9K) 292 293static const u8 294 regmap_in[8] = { 295 [UART_RX] = 0x00, 296 [UART_IER] = 0x0c, 297 [UART_IIR] = 0x14, 298 [UART_LCR] = 0x1c, 299 [UART_MCR] = 0x20, 300 [UART_LSR] = 0x24, 301 [UART_MSR] = 0x28, 302 [UART_SCR] = 0x2c 303 }, 304 regmap_out[8] = { 305 [UART_TX] = 0x04, 306 [UART_IER] = 0x0c, 307 [UART_FCR] = 0x18, 308 [UART_LCR] = 0x1c, 309 [UART_MCR] = 0x20, 310 [UART_LSR] = 0x24, 311 [UART_MSR] = 0x28, 312 [UART_SCR] = 0x2c 313 }; 314 315static inline int map_8250_in_reg(struct uart_8250_port *up, int offset) 316{ 317 if (up->port.iotype != UPIO_RM9000) 318 return offset; 319 return regmap_in[offset]; 320} 321 322static inline int map_8250_out_reg(struct uart_8250_port *up, int offset) 323{ 324 if (up->port.iotype != UPIO_RM9000) 325 return offset; 326 return regmap_out[offset]; 327} 328 329#else 330 331/* sane hardware needs no mapping */ 332#define map_8250_in_reg(up, offset) (offset) 333#define map_8250_out_reg(up, offset) (offset) 334 335#endif 336 337static unsigned int serial_in(struct uart_8250_port *up, int offset) 338{ 339 unsigned int tmp; 340 offset = map_8250_in_reg(up, offset) << up->port.regshift; 341 342 switch (up->port.iotype) { 343 case UPIO_HUB6: 344 outb(up->port.hub6 - 1 + offset, up->port.iobase); 345 return inb(up->port.iobase + 1); 346 347 case UPIO_MEM: 348 case UPIO_DWAPB: 349 return readb(up->port.membase + offset); 350 351 case UPIO_RM9000: 352 case UPIO_MEM32: 353 return readl(up->port.membase + offset); 354 355#ifdef CONFIG_SERIAL_8250_AU1X00 356 case UPIO_AU: 357 return __raw_readl(up->port.membase + offset); 358#endif 359 360 case UPIO_TSI: 361 if (offset == UART_IIR) { 362 tmp = readl(up->port.membase + (UART_IIR & ~3)); 363 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */ 364 } else 365 return readb(up->port.membase + offset); 366 367 default: 368 return inb(up->port.iobase + offset); 369 } 370} 371 372static void 373serial_out(struct uart_8250_port *up, int offset, int value) 374{ 375 /* Save the offset before it's remapped */ 376 int save_offset = offset; 377 offset = map_8250_out_reg(up, offset) << up->port.regshift; 378 379 switch (up->port.iotype) { 380 case UPIO_HUB6: 381 outb(up->port.hub6 - 1 + offset, up->port.iobase); 382 outb(value, up->port.iobase + 1); 383 break; 384 385 case UPIO_MEM: 386 writeb(value, up->port.membase + offset); 387 break; 388 389 case UPIO_RM9000: 390 case UPIO_MEM32: 391 writel(value, up->port.membase + offset); 392 break; 393 394#ifdef CONFIG_SERIAL_8250_AU1X00 395 case UPIO_AU: 396 __raw_writel(value, up->port.membase + offset); 397 break; 398#endif 399 case UPIO_TSI: 400 if (!((offset == UART_IER) && (value & UART_IER_UUE))) 401 writeb(value, up->port.membase + offset); 402 break; 403 404 case UPIO_DWAPB: 405 /* Save the LCR value so it can be re-written when a 406 * Busy Detect interrupt occurs. */ 407 if (save_offset == UART_LCR) 408 up->lcr = value; 409 writeb(value, up->port.membase + offset); 410 /* Read the IER to ensure any interrupt is cleared before 411 * returning from ISR. */ 412 if (save_offset == UART_TX || save_offset == UART_IER) 413 value = serial_in(up, UART_IER); 414 break; 415 416 default: 417 outb(value, up->port.iobase + offset); 418 } 419} 420 421static void 422serial_out_sync(struct uart_8250_port *up, int offset, int value) 423{ 424 switch (up->port.iotype) { 425 case UPIO_MEM: 426 case UPIO_MEM32: 427#ifdef CONFIG_SERIAL_8250_AU1X00 428 case UPIO_AU: 429#endif 430 case UPIO_DWAPB: 431 serial_out(up, offset, value); 432 serial_in(up, UART_LCR); /* safe, no side-effects */ 433 break; 434 default: 435 serial_out(up, offset, value); 436 } 437} 438 439/* 440 * We used to support using pause I/O for certain machines. We 441 * haven't supported this for a while, but just in case it's badly 442 * needed for certain old 386 machines, I've left these #define's 443 * in.... 444 */ 445#define serial_inp(up, offset) serial_in(up, offset) 446#define serial_outp(up, offset, value) serial_out(up, offset, value) 447 448/* Uart divisor latch read */ 449static inline int _serial_dl_read(struct uart_8250_port *up) 450{ 451 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; 452} 453 454/* Uart divisor latch write */ 455static inline void _serial_dl_write(struct uart_8250_port *up, int value) 456{ 457 serial_outp(up, UART_DLL, value & 0xff); 458 serial_outp(up, UART_DLM, value >> 8 & 0xff); 459} 460 461#if defined(CONFIG_SERIAL_8250_AU1X00) 462/* Au1x00 haven't got a standard divisor latch */ 463static int serial_dl_read(struct uart_8250_port *up) 464{ 465 if (up->port.iotype == UPIO_AU) 466 return __raw_readl(up->port.membase + 0x28); 467 else 468 return _serial_dl_read(up); 469} 470 471static void serial_dl_write(struct uart_8250_port *up, int value) 472{ 473 if (up->port.iotype == UPIO_AU) 474 __raw_writel(value, up->port.membase + 0x28); 475 else 476 _serial_dl_write(up, value); 477} 478#elif defined(CONFIG_SERIAL_8250_RM9K) 479static int serial_dl_read(struct uart_8250_port *up) 480{ 481 return (up->port.iotype == UPIO_RM9000) ? 482 (((__raw_readl(up->port.membase + 0x10) << 8) | 483 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) : 484 _serial_dl_read(up); 485} 486 487static void serial_dl_write(struct uart_8250_port *up, int value) 488{ 489 if (up->port.iotype == UPIO_RM9000) { 490 __raw_writel(value, up->port.membase + 0x08); 491 __raw_writel(value >> 8, up->port.membase + 0x10); 492 } else { 493 _serial_dl_write(up, value); 494 } 495} 496#else 497#define serial_dl_read(up) _serial_dl_read(up) 498#define serial_dl_write(up, value) _serial_dl_write(up, value) 499#endif 500 501/* 502 * For the 16C950 503 */ 504static void serial_icr_write(struct uart_8250_port *up, int offset, int value) 505{ 506 serial_out(up, UART_SCR, offset); 507 serial_out(up, UART_ICR, value); 508} 509 510static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) 511{ 512 unsigned int value; 513 514 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); 515 serial_out(up, UART_SCR, offset); 516 value = serial_in(up, UART_ICR); 517 serial_icr_write(up, UART_ACR, up->acr); 518 519 return value; 520} 521 522/* 523 * FIFO support. 524 */ 525static inline void serial8250_clear_fifos(struct uart_8250_port *p) 526{ 527 if (p->capabilities & UART_CAP_FIFO) { 528 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); 529 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | 530 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 531 serial_outp(p, UART_FCR, 0); 532 } 533} 534 535/* 536 * IER sleep support. UARTs which have EFRs need the "extended 537 * capability" bit enabled. Note that on XR16C850s, we need to 538 * reset LCR to write to IER. 539 */ 540static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep) 541{ 542 if (p->capabilities & UART_CAP_SLEEP) { 543 if (p->capabilities & UART_CAP_EFR) { 544 serial_outp(p, UART_LCR, 0xBF); 545 serial_outp(p, UART_EFR, UART_EFR_ECB); 546 serial_outp(p, UART_LCR, 0); 547 } 548 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); 549 if (p->capabilities & UART_CAP_EFR) { 550 serial_outp(p, UART_LCR, 0xBF); 551 serial_outp(p, UART_EFR, 0); 552 serial_outp(p, UART_LCR, 0); 553 } 554 } 555} 556 557#ifdef CONFIG_SERIAL_8250_RSA 558/* 559 * Attempts to turn on the RSA FIFO. Returns zero on failure. 560 * We set the port uart clock rate if we succeed. 561 */ 562static int __enable_rsa(struct uart_8250_port *up) 563{ 564 unsigned char mode; 565 int result; 566 567 mode = serial_inp(up, UART_RSA_MSR); 568 result = mode & UART_RSA_MSR_FIFO; 569 570 if (!result) { 571 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); 572 mode = serial_inp(up, UART_RSA_MSR); 573 result = mode & UART_RSA_MSR_FIFO; 574 } 575 576 if (result) 577 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; 578 579 return result; 580} 581 582static void enable_rsa(struct uart_8250_port *up) 583{ 584 if (up->port.type == PORT_RSA) { 585 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 586 spin_lock_irq(&up->port.lock); 587 __enable_rsa(up); 588 spin_unlock_irq(&up->port.lock); 589 } 590 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 591 serial_outp(up, UART_RSA_FRR, 0); 592 } 593} 594 595/* 596 * Attempts to turn off the RSA FIFO. Returns zero on failure. 597 * It is unknown why interrupts were disabled in here. However, 598 * the caller is expected to preserve this behaviour by grabbing 599 * the spinlock before calling this function. 600 */ 601static void disable_rsa(struct uart_8250_port *up) 602{ 603 unsigned char mode; 604 int result; 605 606 if (up->port.type == PORT_RSA && 607 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 608 spin_lock_irq(&up->port.lock); 609 610 mode = serial_inp(up, UART_RSA_MSR); 611 result = !(mode & UART_RSA_MSR_FIFO); 612 613 if (!result) { 614 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); 615 mode = serial_inp(up, UART_RSA_MSR); 616 result = !(mode & UART_RSA_MSR_FIFO); 617 } 618 619 if (result) 620 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 621 spin_unlock_irq(&up->port.lock); 622 } 623} 624#endif /* CONFIG_SERIAL_8250_RSA */ 625 626/* 627 * This is a quickie test to see how big the FIFO is. 628 * It doesn't work at all the time, more's the pity. 629 */ 630static int size_fifo(struct uart_8250_port *up) 631{ 632 unsigned char old_fcr, old_mcr, old_lcr; 633 unsigned short old_dl; 634 int count; 635 636 old_lcr = serial_inp(up, UART_LCR); 637 serial_outp(up, UART_LCR, 0); 638 old_fcr = serial_inp(up, UART_FCR); 639 old_mcr = serial_inp(up, UART_MCR); 640 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | 641 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 642 serial_outp(up, UART_MCR, UART_MCR_LOOP); 643 serial_outp(up, UART_LCR, UART_LCR_DLAB); 644 old_dl = serial_dl_read(up); 645 serial_dl_write(up, 0x0001); 646 serial_outp(up, UART_LCR, 0x03); 647 for (count = 0; count < 256; count++) 648 serial_outp(up, UART_TX, count); 649 mdelay(20); 650 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && 651 (count < 256); count++) 652 serial_inp(up, UART_RX); 653 serial_outp(up, UART_FCR, old_fcr); 654 serial_outp(up, UART_MCR, old_mcr); 655 serial_outp(up, UART_LCR, UART_LCR_DLAB); 656 serial_dl_write(up, old_dl); 657 serial_outp(up, UART_LCR, old_lcr); 658 659 return count; 660} 661 662/* 663 * Read UART ID using the divisor method - set DLL and DLM to zero 664 * and the revision will be in DLL and device type in DLM. We 665 * preserve the device state across this. 666 */ 667static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) 668{ 669 unsigned char old_dll, old_dlm, old_lcr; 670 unsigned int id; 671 672 old_lcr = serial_inp(p, UART_LCR); 673 serial_outp(p, UART_LCR, UART_LCR_DLAB); 674 675 old_dll = serial_inp(p, UART_DLL); 676 old_dlm = serial_inp(p, UART_DLM); 677 678 serial_outp(p, UART_DLL, 0); 679 serial_outp(p, UART_DLM, 0); 680 681 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; 682 683 serial_outp(p, UART_DLL, old_dll); 684 serial_outp(p, UART_DLM, old_dlm); 685 serial_outp(p, UART_LCR, old_lcr); 686 687 return id; 688} 689 690/* 691 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. 692 * When this function is called we know it is at least a StarTech 693 * 16650 V2, but it might be one of several StarTech UARTs, or one of 694 * its clones. (We treat the broken original StarTech 16650 V1 as a 695 * 16550, and why not? Startech doesn't seem to even acknowledge its 696 * existence.) 697 * 698 * What evil have men's minds wrought... 699 */ 700static void autoconfig_has_efr(struct uart_8250_port *up) 701{ 702 unsigned int id1, id2, id3, rev; 703 704 /* 705 * Everything with an EFR has SLEEP 706 */ 707 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 708 709 /* 710 * First we check to see if it's an Oxford Semiconductor UART. 711 * 712 * If we have to do this here because some non-National 713 * Semiconductor clone chips lock up if you try writing to the 714 * LSR register (which serial_icr_read does) 715 */ 716 717 /* 718 * Check for Oxford Semiconductor 16C950. 719 * 720 * EFR [4] must be set else this test fails. 721 * 722 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) 723 * claims that it's needed for 952 dual UART's (which are not 724 * recommended for new designs). 725 */ 726 up->acr = 0; 727 serial_out(up, UART_LCR, 0xBF); 728 serial_out(up, UART_EFR, UART_EFR_ECB); 729 serial_out(up, UART_LCR, 0x00); 730 id1 = serial_icr_read(up, UART_ID1); 731 id2 = serial_icr_read(up, UART_ID2); 732 id3 = serial_icr_read(up, UART_ID3); 733 rev = serial_icr_read(up, UART_REV); 734 735 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); 736 737 if (id1 == 0x16 && id2 == 0xC9 && 738 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { 739 up->port.type = PORT_16C950; 740 741 if (id3 == 0x52 && rev == 0x01) 742 up->bugs |= UART_BUG_QUOT; 743 return; 744 } 745 746 /* 747 * We check for a XR16C850 by setting DLL and DLM to 0, and then 748 * reading back DLL and DLM. The chip type depends on the DLM 749 * value read back: 750 * 0x10 - XR16C850 and the DLL contains the chip revision. 751 * 0x12 - XR16C2850. 752 * 0x14 - XR16C854. 753 */ 754 id1 = autoconfig_read_divisor_id(up); 755 DEBUG_AUTOCONF("850id=%04x ", id1); 756 757 id2 = id1 >> 8; 758 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { 759 up->port.type = PORT_16850; 760 return; 761 } 762 763 /* 764 * It wasn't an XR16C850. 765 * 766 * We distinguish between the '654 and the '650 by counting 767 * how many bytes are in the FIFO. I'm using this for now, 768 * since that's the technique that was sent to me in the 769 * serial driver update, but I'm not convinced this works. 770 * I've had problems doing this in the past. -TYT 771 */ 772 if (size_fifo(up) == 64) 773 up->port.type = PORT_16654; 774 else 775 up->port.type = PORT_16650V2; 776} 777 778/* 779 * We detected a chip without a FIFO. Only two fall into 780 * this category - the original 8250 and the 16450. The 781 * 16450 has a scratch register (accessible with LCR=0) 782 */ 783static void autoconfig_8250(struct uart_8250_port *up) 784{ 785 unsigned char scratch, status1, status2; 786 787 up->port.type = PORT_8250; 788 789 scratch = serial_in(up, UART_SCR); 790 serial_outp(up, UART_SCR, 0xa5); 791 status1 = serial_in(up, UART_SCR); 792 serial_outp(up, UART_SCR, 0x5a); 793 status2 = serial_in(up, UART_SCR); 794 serial_outp(up, UART_SCR, scratch); 795 796 if (status1 == 0xa5 && status2 == 0x5a) 797 up->port.type = PORT_16450; 798} 799 800static int broken_efr(struct uart_8250_port *up) 801{ 802 /* 803 * Exar ST16C2550 "A2" devices incorrectly detect as 804 * having an EFR, and report an ID of 0x0201. See 805 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf 806 */ 807 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) 808 return 1; 809 810 return 0; 811} 812 813/* 814 * We know that the chip has FIFOs. Does it have an EFR? The 815 * EFR is located in the same register position as the IIR and 816 * we know the top two bits of the IIR are currently set. The 817 * EFR should contain zero. Try to read the EFR. 818 */ 819static void autoconfig_16550a(struct uart_8250_port *up) 820{ 821 unsigned char status1, status2; 822 unsigned int iersave; 823 824 up->port.type = PORT_16550A; 825 up->capabilities |= UART_CAP_FIFO; 826 827 /* 828 * Check for presence of the EFR when DLAB is set. 829 * Only ST16C650V1 UARTs pass this test. 830 */ 831 serial_outp(up, UART_LCR, UART_LCR_DLAB); 832 if (serial_in(up, UART_EFR) == 0) { 833 serial_outp(up, UART_EFR, 0xA8); 834 if (serial_in(up, UART_EFR) != 0) { 835 DEBUG_AUTOCONF("EFRv1 "); 836 up->port.type = PORT_16650; 837 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 838 } else { 839 DEBUG_AUTOCONF("Motorola 8xxx DUART "); 840 } 841 serial_outp(up, UART_EFR, 0); 842 return; 843 } 844 845 /* 846 * Maybe it requires 0xbf to be written to the LCR. 847 * (other ST16C650V2 UARTs, TI16C752A, etc) 848 */ 849 serial_outp(up, UART_LCR, 0xBF); 850 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { 851 DEBUG_AUTOCONF("EFRv2 "); 852 autoconfig_has_efr(up); 853 return; 854 } 855 856 /* 857 * Check for a National Semiconductor SuperIO chip. 858 * Attempt to switch to bank 2, read the value of the LOOP bit 859 * from EXCR1. Switch back to bank 0, change it in MCR. Then 860 * switch back to bank 2, read it from EXCR1 again and check 861 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 862 */ 863 serial_outp(up, UART_LCR, 0); 864 status1 = serial_in(up, UART_MCR); 865 serial_outp(up, UART_LCR, 0xE0); 866 status2 = serial_in(up, 0x02); /* EXCR1 */ 867 868 if (!((status2 ^ status1) & UART_MCR_LOOP)) { 869 serial_outp(up, UART_LCR, 0); 870 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP); 871 serial_outp(up, UART_LCR, 0xE0); 872 status2 = serial_in(up, 0x02); /* EXCR1 */ 873 serial_outp(up, UART_LCR, 0); 874 serial_outp(up, UART_MCR, status1); 875 876 if ((status2 ^ status1) & UART_MCR_LOOP) { 877 unsigned short quot; 878 879 serial_outp(up, UART_LCR, 0xE0); 880 881 quot = serial_dl_read(up); 882 quot <<= 3; 883 884 status1 = serial_in(up, 0x04); /* EXCR2 */ 885 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ 886 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ 887 serial_outp(up, 0x04, status1); 888 889 serial_dl_write(up, quot); 890 891 serial_outp(up, UART_LCR, 0); 892 893 up->port.uartclk = 921600*16; 894 up->port.type = PORT_NS16550A; 895 up->capabilities |= UART_NATSEMI; 896 return; 897 } 898 } 899 900 /* 901 * No EFR. Try to detect a TI16750, which only sets bit 5 of 902 * the IIR when 64 byte FIFO mode is enabled when DLAB is set. 903 * Try setting it with and without DLAB set. Cheap clones 904 * set bit 5 without DLAB set. 905 */ 906 serial_outp(up, UART_LCR, 0); 907 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 908 status1 = serial_in(up, UART_IIR) >> 5; 909 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 910 serial_outp(up, UART_LCR, UART_LCR_DLAB); 911 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 912 status2 = serial_in(up, UART_IIR) >> 5; 913 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 914 serial_outp(up, UART_LCR, 0); 915 916 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); 917 918 if (status1 == 6 && status2 == 7) { 919 up->port.type = PORT_16750; 920 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; 921 return; 922 } 923 924 /* 925 * Try writing and reading the UART_IER_UUE bit (b6). 926 * If it works, this is probably one of the Xscale platform's 927 * internal UARTs. 928 * We're going to explicitly set the UUE bit to 0 before 929 * trying to write and read a 1 just to make sure it's not 930 * already a 1 and maybe locked there before we even start start. 931 */ 932 iersave = serial_in(up, UART_IER); 933 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE); 934 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { 935 /* 936 * OK it's in a known zero state, try writing and reading 937 * without disturbing the current state of the other bits. 938 */ 939 serial_outp(up, UART_IER, iersave | UART_IER_UUE); 940 if (serial_in(up, UART_IER) & UART_IER_UUE) { 941 /* 942 * It's an Xscale. 943 * We'll leave the UART_IER_UUE bit set to 1 (enabled). 944 */ 945 DEBUG_AUTOCONF("Xscale "); 946 up->port.type = PORT_XSCALE; 947 up->capabilities |= UART_CAP_UUE; 948 return; 949 } 950 } else { 951 /* 952 * If we got here we couldn't force the IER_UUE bit to 0. 953 * Log it and continue. 954 */ 955 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); 956 } 957 serial_outp(up, UART_IER, iersave); 958} 959 960/* 961 * This routine is called by rs_init() to initialize a specific serial 962 * port. It determines what type of UART chip this serial port is 963 * using: 8250, 16450, 16550, 16550A. The important question is 964 * whether or not this UART is a 16550A or not, since this will 965 * determine whether or not we can use its FIFO features or not. 966 */ 967static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) 968{ 969 unsigned char status1, scratch, scratch2, scratch3; 970 unsigned char save_lcr, save_mcr; 971 unsigned long flags; 972 973 if (!up->port.iobase && !up->port.mapbase && !up->port.membase) 974 return; 975 976 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ", 977 up->port.line, up->port.iobase, up->port.membase); 978 979 /* 980 * We really do need global IRQs disabled here - we're going to 981 * be frobbing the chips IRQ enable register to see if it exists. 982 */ 983 spin_lock_irqsave(&up->port.lock, flags); 984 985 up->capabilities = 0; 986 up->bugs = 0; 987 988 if (!(up->port.flags & UPF_BUGGY_UART)) { 989 /* 990 * Do a simple existence test first; if we fail this, 991 * there's no point trying anything else. 992 * 993 * 0x80 is used as a nonsense port to prevent against 994 * false positives due to ISA bus float. The 995 * assumption is that 0x80 is a non-existent port; 996 * which should be safe since include/asm/io.h also 997 * makes this assumption. 998 * 999 * Note: this is safe as long as MCR bit 4 is clear 1000 * and the device is in "PC" mode. 1001 */ 1002 scratch = serial_inp(up, UART_IER); 1003 serial_outp(up, UART_IER, 0); 1004#ifdef __i386__ 1005 outb(0xff, 0x080); 1006#endif 1007 /* 1008 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL 1009 * 16C754B) allow only to modify them if an EFR bit is set. 1010 */ 1011 scratch2 = serial_inp(up, UART_IER) & 0x0f; 1012 serial_outp(up, UART_IER, 0x0F); 1013#ifdef __i386__ 1014 outb(0, 0x080); 1015#endif 1016 scratch3 = serial_inp(up, UART_IER) & 0x0f; 1017 serial_outp(up, UART_IER, scratch); 1018 if (scratch2 != 0 || scratch3 != 0x0F) { 1019 /* 1020 * We failed; there's nothing here 1021 */ 1022 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", 1023 scratch2, scratch3); 1024 goto out; 1025 } 1026 } 1027 1028 save_mcr = serial_in(up, UART_MCR); 1029 save_lcr = serial_in(up, UART_LCR); 1030 1031 /* 1032 * Check to see if a UART is really there. Certain broken 1033 * internal modems based on the Rockwell chipset fail this 1034 * test, because they apparently don't implement the loopback 1035 * test mode. So this test is skipped on the COM 1 through 1036 * COM 4 ports. This *should* be safe, since no board 1037 * manufacturer would be stupid enough to design a board 1038 * that conflicts with COM 1-4 --- we hope! 1039 */ 1040 if (!(up->port.flags & UPF_SKIP_TEST)) { 1041 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); 1042 status1 = serial_inp(up, UART_MSR) & 0xF0; 1043 serial_outp(up, UART_MCR, save_mcr); 1044 if (status1 != 0x90) { 1045 DEBUG_AUTOCONF("LOOP test failed (%02x) ", 1046 status1); 1047 goto out; 1048 } 1049 } 1050 1051 /* 1052 * We're pretty sure there's a port here. Lets find out what 1053 * type of port it is. The IIR top two bits allows us to find 1054 * out if it's 8250 or 16450, 16550, 16550A or later. This 1055 * determines what we test for next. 1056 * 1057 * We also initialise the EFR (if any) to zero for later. The 1058 * EFR occupies the same register location as the FCR and IIR. 1059 */ 1060 serial_outp(up, UART_LCR, 0xBF); 1061 serial_outp(up, UART_EFR, 0); 1062 serial_outp(up, UART_LCR, 0); 1063 1064 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1065 scratch = serial_in(up, UART_IIR) >> 6; 1066 1067 DEBUG_AUTOCONF("iir=%d ", scratch); 1068 1069 switch (scratch) { 1070 case 0: 1071 autoconfig_8250(up); 1072 break; 1073 case 1: 1074 up->port.type = PORT_UNKNOWN; 1075 break; 1076 case 2: 1077 up->port.type = PORT_16550; 1078 break; 1079 case 3: 1080 autoconfig_16550a(up); 1081 break; 1082 } 1083 1084#ifdef CONFIG_SERIAL_8250_RSA 1085 /* 1086 * Only probe for RSA ports if we got the region. 1087 */ 1088 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) { 1089 int i; 1090 1091 for (i = 0 ; i < probe_rsa_count; ++i) { 1092 if (probe_rsa[i] == up->port.iobase && 1093 __enable_rsa(up)) { 1094 up->port.type = PORT_RSA; 1095 break; 1096 } 1097 } 1098 } 1099#endif 1100 1101#ifdef CONFIG_SERIAL_8250_AU1X00 1102 /* if access method is AU, it is a 16550 with a quirk */ 1103 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU) 1104 up->bugs |= UART_BUG_NOMSR; 1105#endif 1106 1107 serial_outp(up, UART_LCR, save_lcr); 1108 1109 if (up->capabilities != uart_config[up->port.type].flags) { 1110 printk(KERN_WARNING 1111 "ttyS%d: detected caps %08x should be %08x\n", 1112 up->port.line, up->capabilities, 1113 uart_config[up->port.type].flags); 1114 } 1115 1116 up->port.fifosize = uart_config[up->port.type].fifo_size; 1117 up->capabilities = uart_config[up->port.type].flags; 1118 up->tx_loadsz = uart_config[up->port.type].tx_loadsz; 1119 1120 if (up->port.type == PORT_UNKNOWN) 1121 goto out; 1122 1123 /* 1124 * Reset the UART. 1125 */ 1126#ifdef CONFIG_SERIAL_8250_RSA 1127 if (up->port.type == PORT_RSA) 1128 serial_outp(up, UART_RSA_FRR, 0); 1129#endif 1130 serial_outp(up, UART_MCR, save_mcr); 1131 serial8250_clear_fifos(up); 1132 serial_in(up, UART_RX); 1133 if (up->capabilities & UART_CAP_UUE) 1134 serial_outp(up, UART_IER, UART_IER_UUE); 1135 else 1136 serial_outp(up, UART_IER, 0); 1137 1138 out: 1139 spin_unlock_irqrestore(&up->port.lock, flags); 1140 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name); 1141} 1142 1143static void autoconfig_irq(struct uart_8250_port *up) 1144{ 1145 unsigned char save_mcr, save_ier; 1146 unsigned char save_ICP = 0; 1147 unsigned int ICP = 0; 1148 unsigned long irqs; 1149 int irq; 1150 1151 if (up->port.flags & UPF_FOURPORT) { 1152 ICP = (up->port.iobase & 0xfe0) | 0x1f; 1153 save_ICP = inb_p(ICP); 1154 outb_p(0x80, ICP); 1155 (void) inb_p(ICP); 1156 } 1157 1158 /* forget possible initially masked and pending IRQ */ 1159 probe_irq_off(probe_irq_on()); 1160 save_mcr = serial_inp(up, UART_MCR); 1161 save_ier = serial_inp(up, UART_IER); 1162 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); 1163 1164 irqs = probe_irq_on(); 1165 serial_outp(up, UART_MCR, 0); 1166 udelay (10); 1167 if (up->port.flags & UPF_FOURPORT) { 1168 serial_outp(up, UART_MCR, 1169 UART_MCR_DTR | UART_MCR_RTS); 1170 } else { 1171 serial_outp(up, UART_MCR, 1172 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); 1173 } 1174 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */ 1175 (void)serial_inp(up, UART_LSR); 1176 (void)serial_inp(up, UART_RX); 1177 (void)serial_inp(up, UART_IIR); 1178 (void)serial_inp(up, UART_MSR); 1179 serial_outp(up, UART_TX, 0xFF); 1180 udelay (20); 1181 irq = probe_irq_off(irqs); 1182 1183 serial_outp(up, UART_MCR, save_mcr); 1184 serial_outp(up, UART_IER, save_ier); 1185 1186 if (up->port.flags & UPF_FOURPORT) 1187 outb_p(save_ICP, ICP); 1188 1189 up->port.irq = (irq > 0) ? irq : 0; 1190} 1191 1192static inline void __stop_tx(struct uart_8250_port *p) 1193{ 1194 if (p->ier & UART_IER_THRI) { 1195 p->ier &= ~UART_IER_THRI; 1196 serial_out(p, UART_IER, p->ier); 1197 } 1198} 1199 1200static void serial8250_stop_tx(struct uart_port *port) 1201{ 1202 struct uart_8250_port *up = (struct uart_8250_port *)port; 1203 1204 __stop_tx(up); 1205 1206 /* 1207 * We really want to stop the transmitter from sending. 1208 */ 1209 if (up->port.type == PORT_16C950) { 1210 up->acr |= UART_ACR_TXDIS; 1211 serial_icr_write(up, UART_ACR, up->acr); 1212 } 1213} 1214 1215static void transmit_chars(struct uart_8250_port *up); 1216 1217static void serial8250_start_tx(struct uart_port *port) 1218{ 1219 struct uart_8250_port *up = (struct uart_8250_port *)port; 1220 1221 if (!(up->ier & UART_IER_THRI)) { 1222 up->ier |= UART_IER_THRI; 1223 serial_out(up, UART_IER, up->ier); 1224 1225 if (up->bugs & UART_BUG_TXEN) { 1226 unsigned char lsr, iir; 1227 lsr = serial_in(up, UART_LSR); 1228 iir = serial_in(up, UART_IIR) & 0x0f; 1229 if ((up->port.type == PORT_RM9000) ? 1230 (lsr & UART_LSR_THRE && 1231 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) : 1232 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)) 1233 transmit_chars(up); 1234 } 1235 } 1236 1237 /* 1238 * Re-enable the transmitter if we disabled it. 1239 */ 1240 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 1241 up->acr &= ~UART_ACR_TXDIS; 1242 serial_icr_write(up, UART_ACR, up->acr); 1243 } 1244} 1245 1246static void serial8250_stop_rx(struct uart_port *port) 1247{ 1248 struct uart_8250_port *up = (struct uart_8250_port *)port; 1249 1250 up->ier &= ~UART_IER_RLSI; 1251 up->port.read_status_mask &= ~UART_LSR_DR; 1252 serial_out(up, UART_IER, up->ier); 1253} 1254 1255static void serial8250_enable_ms(struct uart_port *port) 1256{ 1257 struct uart_8250_port *up = (struct uart_8250_port *)port; 1258 1259 /* no MSR capabilities */ 1260 if (up->bugs & UART_BUG_NOMSR) 1261 return; 1262 1263 up->ier |= UART_IER_MSI; 1264 serial_out(up, UART_IER, up->ier); 1265} 1266 1267static void 1268receive_chars(struct uart_8250_port *up, unsigned int *status) 1269{ 1270 struct tty_struct *tty = up->port.info->tty; 1271 unsigned char ch, lsr = *status; 1272 int max_count = 256; 1273 char flag; 1274 1275 do { 1276 ch = serial_inp(up, UART_RX); 1277 flag = TTY_NORMAL; 1278 up->port.icount.rx++; 1279 1280#ifdef CONFIG_SERIAL_8250_CONSOLE 1281 /* 1282 * Recover the break flag from console xmit 1283 */ 1284 if (up->port.line == up->port.cons->index) { 1285 lsr |= up->lsr_break_flag; 1286 up->lsr_break_flag = 0; 1287 } 1288#endif 1289 1290 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | 1291 UART_LSR_FE | UART_LSR_OE))) { 1292 /* 1293 * For statistics only 1294 */ 1295 if (lsr & UART_LSR_BI) { 1296 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 1297 up->port.icount.brk++; 1298 /* 1299 * We do the SysRQ and SAK checking 1300 * here because otherwise the break 1301 * may get masked by ignore_status_mask 1302 * or read_status_mask. 1303 */ 1304 if (uart_handle_break(&up->port)) 1305 goto ignore_char; 1306 } else if (lsr & UART_LSR_PE) 1307 up->port.icount.parity++; 1308 else if (lsr & UART_LSR_FE) 1309 up->port.icount.frame++; 1310 if (lsr & UART_LSR_OE) 1311 up->port.icount.overrun++; 1312 1313 /* 1314 * Mask off conditions which should be ignored. 1315 */ 1316 lsr &= up->port.read_status_mask; 1317 1318 if (lsr & UART_LSR_BI) { 1319 DEBUG_INTR("handling break...."); 1320 flag = TTY_BREAK; 1321 } else if (lsr & UART_LSR_PE) 1322 flag = TTY_PARITY; 1323 else if (lsr & UART_LSR_FE) 1324 flag = TTY_FRAME; 1325 } 1326 if (uart_handle_sysrq_char(&up->port, ch)) 1327 goto ignore_char; 1328 1329 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 1330 1331 ignore_char: 1332 lsr = serial_inp(up, UART_LSR); 1333 } while ((lsr & UART_LSR_DR) && (max_count-- > 0)); 1334 spin_unlock(&up->port.lock); 1335 tty_flip_buffer_push(tty); 1336 spin_lock(&up->port.lock); 1337 *status = lsr; 1338} 1339 1340static void transmit_chars(struct uart_8250_port *up) 1341{ 1342 struct circ_buf *xmit = &up->port.info->xmit; 1343 int count; 1344 1345 if (up->port.x_char) { 1346 serial_outp(up, UART_TX, up->port.x_char); 1347 up->port.icount.tx++; 1348 up->port.x_char = 0; 1349 return; 1350 } 1351 if (uart_tx_stopped(&up->port)) { 1352 serial8250_stop_tx(&up->port); 1353 return; 1354 } 1355 if (uart_circ_empty(xmit)) { 1356 __stop_tx(up); 1357 return; 1358 } 1359 1360 count = up->tx_loadsz; 1361 do { 1362 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 1363 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1364 up->port.icount.tx++; 1365 if (uart_circ_empty(xmit)) 1366 break; 1367 } while (--count > 0); 1368 1369 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1370 uart_write_wakeup(&up->port); 1371 1372 DEBUG_INTR("THRE..."); 1373 1374 if (uart_circ_empty(xmit)) 1375 __stop_tx(up); 1376} 1377 1378static unsigned int check_modem_status(struct uart_8250_port *up) 1379{ 1380 unsigned int status = serial_in(up, UART_MSR); 1381 1382 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 1383 up->port.info != NULL) { 1384 if (status & UART_MSR_TERI) 1385 up->port.icount.rng++; 1386 if (status & UART_MSR_DDSR) 1387 up->port.icount.dsr++; 1388 if (status & UART_MSR_DDCD) 1389 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 1390 if (status & UART_MSR_DCTS) 1391 uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 1392 1393 wake_up_interruptible(&up->port.info->delta_msr_wait); 1394 } 1395 1396 return status; 1397} 1398 1399/* 1400 * This handles the interrupt from one port. 1401 */ 1402static inline void 1403serial8250_handle_port(struct uart_8250_port *up) 1404{ 1405 unsigned int status; 1406 unsigned long flags; 1407 1408 spin_lock_irqsave(&up->port.lock, flags); 1409 1410 status = serial_inp(up, UART_LSR); 1411 1412 DEBUG_INTR("status = %x...", status); 1413 1414 if (status & UART_LSR_DR) 1415 receive_chars(up, &status); 1416 check_modem_status(up); 1417 if (status & UART_LSR_THRE) 1418 transmit_chars(up); 1419 1420 spin_unlock_irqrestore(&up->port.lock, flags); 1421} 1422 1423/* 1424 * This is the serial driver's interrupt routine. 1425 * 1426 * Arjan thinks the old way was overly complex, so it got simplified. 1427 * Alan disagrees, saying that need the complexity to handle the weird 1428 * nature of ISA shared interrupts. (This is a special exception.) 1429 * 1430 * In order to handle ISA shared interrupts properly, we need to check 1431 * that all ports have been serviced, and therefore the ISA interrupt 1432 * line has been de-asserted. 1433 * 1434 * This means we need to loop through all ports. checking that they 1435 * don't have an interrupt pending. 1436 */ 1437static irqreturn_t serial8250_interrupt(int irq, void *dev_id) 1438{ 1439 struct irq_info *i = dev_id; 1440 struct list_head *l, *end = NULL; 1441 int pass_counter = 0, handled = 0; 1442 1443 DEBUG_INTR("serial8250_interrupt(%d)...", irq); 1444 1445 spin_lock(&i->lock); 1446 1447 l = i->head; 1448 do { 1449 struct uart_8250_port *up; 1450 unsigned int iir; 1451 1452 up = list_entry(l, struct uart_8250_port, list); 1453 1454 iir = serial_in(up, UART_IIR); 1455 if (!(iir & UART_IIR_NO_INT)) { 1456 serial8250_handle_port(up); 1457 1458 handled = 1; 1459 1460 end = NULL; 1461 } else if (up->port.iotype == UPIO_DWAPB && 1462 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 1463 /* The DesignWare APB UART has an Busy Detect (0x07) 1464 * interrupt meaning an LCR write attempt occured while the 1465 * UART was busy. The interrupt must be cleared by reading 1466 * the UART status register (USR) and the LCR re-written. */ 1467 unsigned int status; 1468 status = *(volatile u32 *)up->port.private_data; 1469 serial_out(up, UART_LCR, up->lcr); 1470 1471 handled = 1; 1472 1473 end = NULL; 1474 } else if (end == NULL) 1475 end = l; 1476 1477 l = l->next; 1478 1479 if (l == i->head && pass_counter++ > PASS_LIMIT) { 1480 /* If we hit this, we're dead. */ 1481 printk(KERN_ERR "serial8250: too much work for " 1482 "irq%d\n", irq); 1483 break; 1484 } 1485 } while (l != end); 1486 1487 spin_unlock(&i->lock); 1488 1489 DEBUG_INTR("end.\n"); 1490 1491 return IRQ_RETVAL(handled); 1492} 1493 1494/* 1495 * To support ISA shared interrupts, we need to have one interrupt 1496 * handler that ensures that the IRQ line has been deasserted 1497 * before returning. Failing to do this will result in the IRQ 1498 * line being stuck active, and, since ISA irqs are edge triggered, 1499 * no more IRQs will be seen. 1500 */ 1501static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) 1502{ 1503 spin_lock_irq(&i->lock); 1504 1505 if (!list_empty(i->head)) { 1506 if (i->head == &up->list) 1507 i->head = i->head->next; 1508 list_del(&up->list); 1509 } else { 1510 BUG_ON(i->head != &up->list); 1511 i->head = NULL; 1512 } 1513 1514 spin_unlock_irq(&i->lock); 1515} 1516 1517static int serial_link_irq_chain(struct uart_8250_port *up) 1518{ 1519 struct irq_info *i = irq_lists + up->port.irq; 1520 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; 1521 1522 spin_lock_irq(&i->lock); 1523 1524 if (i->head) { 1525 list_add(&up->list, i->head); 1526 spin_unlock_irq(&i->lock); 1527 1528 ret = 0; 1529 } else { 1530 INIT_LIST_HEAD(&up->list); 1531 i->head = &up->list; 1532 spin_unlock_irq(&i->lock); 1533 1534 ret = request_irq(up->port.irq, serial8250_interrupt, 1535 irq_flags, "serial", i); 1536 if (ret < 0) 1537 serial_do_unlink(i, up); 1538 } 1539 1540 return ret; 1541} 1542 1543static void serial_unlink_irq_chain(struct uart_8250_port *up) 1544{ 1545 struct irq_info *i = irq_lists + up->port.irq; 1546 1547 BUG_ON(i->head == NULL); 1548 1549 if (list_empty(i->head)) 1550 free_irq(up->port.irq, i); 1551 1552 serial_do_unlink(i, up); 1553} 1554 1555/* Base timer interval for polling */ 1556static inline int poll_timeout(int timeout) 1557{ 1558 return timeout > 6 ? (timeout / 2 - 2) : 1; 1559} 1560 1561/* 1562 * This function is used to handle ports that do not have an 1563 * interrupt. This doesn't work very well for 16450's, but gives 1564 * barely passable results for a 16550A. (Although at the expense 1565 * of much CPU overhead). 1566 */ 1567static void serial8250_timeout(unsigned long data) 1568{ 1569 struct uart_8250_port *up = (struct uart_8250_port *)data; 1570 unsigned int iir; 1571 1572 iir = serial_in(up, UART_IIR); 1573 if (!(iir & UART_IIR_NO_INT)) 1574 serial8250_handle_port(up); 1575 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); 1576} 1577 1578static void serial8250_backup_timeout(unsigned long data) 1579{ 1580 struct uart_8250_port *up = (struct uart_8250_port *)data; 1581 unsigned int iir, ier = 0; 1582 1583 /* 1584 * Must disable interrupts or else we risk racing with the interrupt 1585 * based handler. 1586 */ 1587 if (is_real_interrupt(up->port.irq)) { 1588 ier = serial_in(up, UART_IER); 1589 serial_out(up, UART_IER, 0); 1590 } 1591 1592 iir = serial_in(up, UART_IIR); 1593 1594 /* 1595 * This should be a safe test for anyone who doesn't trust the 1596 * IIR bits on their UART, but it's specifically designed for 1597 * the "Diva" UART used on the management processor on many HP 1598 * ia64 and parisc boxes. 1599 */ 1600 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && 1601 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) && 1602 (serial_in(up, UART_LSR) & UART_LSR_THRE)) { 1603 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); 1604 iir |= UART_IIR_THRI; 1605 } 1606 1607 if (!(iir & UART_IIR_NO_INT)) 1608 serial8250_handle_port(up); 1609 1610 if (is_real_interrupt(up->port.irq)) 1611 serial_out(up, UART_IER, ier); 1612 1613 /* Standard timer interval plus 0.2s to keep the port running */ 1614 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout) + HZ/5); 1615} 1616 1617static unsigned int serial8250_tx_empty(struct uart_port *port) 1618{ 1619 struct uart_8250_port *up = (struct uart_8250_port *)port; 1620 unsigned long flags; 1621 unsigned int ret; 1622 1623 spin_lock_irqsave(&up->port.lock, flags); 1624 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 1625 spin_unlock_irqrestore(&up->port.lock, flags); 1626 1627 return ret; 1628} 1629 1630static unsigned int serial8250_get_mctrl(struct uart_port *port) 1631{ 1632 struct uart_8250_port *up = (struct uart_8250_port *)port; 1633 unsigned int status; 1634 unsigned int ret; 1635 1636 status = check_modem_status(up); 1637 1638 ret = 0; 1639 if (status & UART_MSR_DCD) 1640 ret |= TIOCM_CAR; 1641 if (status & UART_MSR_RI) 1642 ret |= TIOCM_RNG; 1643 if (status & UART_MSR_DSR) 1644 ret |= TIOCM_DSR; 1645 if (status & UART_MSR_CTS) 1646 ret |= TIOCM_CTS; 1647 return ret; 1648} 1649 1650static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 1651{ 1652 struct uart_8250_port *up = (struct uart_8250_port *)port; 1653 unsigned char mcr = 0; 1654 1655 if (mctrl & TIOCM_RTS) 1656 mcr |= UART_MCR_RTS; 1657 if (mctrl & TIOCM_DTR) 1658 mcr |= UART_MCR_DTR; 1659 if (mctrl & TIOCM_OUT1) 1660 mcr |= UART_MCR_OUT1; 1661 if (mctrl & TIOCM_OUT2) 1662 mcr |= UART_MCR_OUT2; 1663 if (mctrl & TIOCM_LOOP) 1664 mcr |= UART_MCR_LOOP; 1665 1666 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; 1667 1668 serial_out(up, UART_MCR, mcr); 1669} 1670 1671static void serial8250_break_ctl(struct uart_port *port, int break_state) 1672{ 1673 struct uart_8250_port *up = (struct uart_8250_port *)port; 1674 unsigned long flags; 1675 1676 spin_lock_irqsave(&up->port.lock, flags); 1677 if (break_state == -1) 1678 up->lcr |= UART_LCR_SBC; 1679 else 1680 up->lcr &= ~UART_LCR_SBC; 1681 serial_out(up, UART_LCR, up->lcr); 1682 spin_unlock_irqrestore(&up->port.lock, flags); 1683} 1684 1685#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1686 1687/* 1688 * Wait for transmitter & holding register to empty 1689 */ 1690static inline void wait_for_xmitr(struct uart_8250_port *up, int bits) 1691{ 1692 unsigned int status, tmout = 10000; 1693 1694 /* Wait up to 10ms for the character(s) to be sent. */ 1695 do { 1696 status = serial_in(up, UART_LSR); 1697 1698 if (status & UART_LSR_BI) 1699 up->lsr_break_flag = UART_LSR_BI; 1700 1701 if (--tmout == 0) 1702 break; 1703 udelay(1); 1704 } while ((status & bits) != bits); 1705 1706 /* Wait up to 1s for flow control if necessary */ 1707 if (up->port.flags & UPF_CONS_FLOW) { 1708 tmout = 1000000; 1709 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) { 1710 udelay(1); 1711 touch_nmi_watchdog(); 1712 } 1713 } 1714} 1715 1716static int serial8250_startup(struct uart_port *port) 1717{ 1718 struct uart_8250_port *up = (struct uart_8250_port *)port; 1719 unsigned long flags; 1720 unsigned char lsr, iir; 1721 int retval; 1722 1723 up->capabilities = uart_config[up->port.type].flags; 1724 up->mcr = 0; 1725 1726 if (up->port.type == PORT_16C950) { 1727 /* Wake up and initialize UART */ 1728 up->acr = 0; 1729 serial_outp(up, UART_LCR, 0xBF); 1730 serial_outp(up, UART_EFR, UART_EFR_ECB); 1731 serial_outp(up, UART_IER, 0); 1732 serial_outp(up, UART_LCR, 0); 1733 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 1734 serial_outp(up, UART_LCR, 0xBF); 1735 serial_outp(up, UART_EFR, UART_EFR_ECB); 1736 serial_outp(up, UART_LCR, 0); 1737 } 1738 1739#ifdef CONFIG_SERIAL_8250_RSA 1740 /* 1741 * If this is an RSA port, see if we can kick it up to the 1742 * higher speed clock. 1743 */ 1744 enable_rsa(up); 1745#endif 1746 1747 /* 1748 * Clear the FIFO buffers and disable them. 1749 * (they will be reenabled in set_termios()) 1750 */ 1751 serial8250_clear_fifos(up); 1752 1753 /* 1754 * Clear the interrupt registers. 1755 */ 1756 (void) serial_inp(up, UART_LSR); 1757 (void) serial_inp(up, UART_RX); 1758 (void) serial_inp(up, UART_IIR); 1759 (void) serial_inp(up, UART_MSR); 1760 1761 /* 1762 * At this point, there's no way the LSR could still be 0xff; 1763 * if it is, then bail out, because there's likely no UART 1764 * here. 1765 */ 1766 if (!(up->port.flags & UPF_BUGGY_UART) && 1767 (serial_inp(up, UART_LSR) == 0xff)) { 1768 printk("ttyS%d: LSR safety check engaged!\n", up->port.line); 1769 return -ENODEV; 1770 } 1771 1772 /* 1773 * For a XR16C850, we need to set the trigger levels 1774 */ 1775 if (up->port.type == PORT_16850) { 1776 unsigned char fctr; 1777 1778 serial_outp(up, UART_LCR, 0xbf); 1779 1780 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); 1781 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); 1782 serial_outp(up, UART_TRG, UART_TRG_96); 1783 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX); 1784 serial_outp(up, UART_TRG, UART_TRG_96); 1785 1786 serial_outp(up, UART_LCR, 0); 1787 } 1788 1789 if (is_real_interrupt(up->port.irq)) { 1790 /* 1791 * Test for UARTs that do not reassert THRE when the 1792 * transmitter is idle and the interrupt has already 1793 * been cleared. Real 16550s should always reassert 1794 * this interrupt whenever the transmitter is idle and 1795 * the interrupt is enabled. Delays are necessary to 1796 * allow register changes to become visible. 1797 */ 1798 spin_lock_irqsave(&up->port.lock, flags); 1799 1800 wait_for_xmitr(up, UART_LSR_THRE); 1801 serial_out_sync(up, UART_IER, UART_IER_THRI); 1802 udelay(1); /* allow THRE to set */ 1803 serial_in(up, UART_IIR); 1804 serial_out(up, UART_IER, 0); 1805 serial_out_sync(up, UART_IER, UART_IER_THRI); 1806 udelay(1); /* allow a working UART time to re-assert THRE */ 1807 iir = serial_in(up, UART_IIR); 1808 serial_out(up, UART_IER, 0); 1809 1810 spin_unlock_irqrestore(&up->port.lock, flags); 1811 1812 /* 1813 * If the interrupt is not reasserted, setup a timer to 1814 * kick the UART on a regular basis. 1815 */ 1816 if (iir & UART_IIR_NO_INT) { 1817 pr_debug("ttyS%d - using backup timer\n", port->line); 1818 up->timer.function = serial8250_backup_timeout; 1819 up->timer.data = (unsigned long)up; 1820 mod_timer(&up->timer, jiffies + 1821 poll_timeout(up->port.timeout) + HZ/5); 1822 } 1823 } 1824 1825 /* 1826 * If the "interrupt" for this port doesn't correspond with any 1827 * hardware interrupt, we use a timer-based system. The original 1828 * driver used to do this with IRQ0. 1829 */ 1830 if (!is_real_interrupt(up->port.irq)) { 1831 up->timer.data = (unsigned long)up; 1832 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); 1833 } else { 1834 retval = serial_link_irq_chain(up); 1835 if (retval) 1836 return retval; 1837 } 1838 1839 /* 1840 * Now, initialize the UART 1841 */ 1842 serial_outp(up, UART_LCR, UART_LCR_WLEN8); 1843 1844 spin_lock_irqsave(&up->port.lock, flags); 1845 if (up->port.flags & UPF_FOURPORT) { 1846 if (!is_real_interrupt(up->port.irq)) 1847 up->port.mctrl |= TIOCM_OUT1; 1848 } else 1849 /* 1850 * Most PC uarts need OUT2 raised to enable interrupts. 1851 */ 1852 if (is_real_interrupt(up->port.irq)) 1853 up->port.mctrl |= TIOCM_OUT2; 1854 1855 serial8250_set_mctrl(&up->port, up->port.mctrl); 1856 1857 /* 1858 * Do a quick test to see if we receive an 1859 * interrupt when we enable the TX irq. 1860 */ 1861 serial_outp(up, UART_IER, UART_IER_THRI); 1862 lsr = serial_in(up, UART_LSR); 1863 iir = serial_in(up, UART_IIR); 1864 serial_outp(up, UART_IER, 0); 1865 1866 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { 1867 if (!(up->bugs & UART_BUG_TXEN)) { 1868 up->bugs |= UART_BUG_TXEN; 1869 pr_debug("ttyS%d - enabling bad tx status workarounds\n", 1870 port->line); 1871 } 1872 } else { 1873 up->bugs &= ~UART_BUG_TXEN; 1874 } 1875 1876 spin_unlock_irqrestore(&up->port.lock, flags); 1877 1878 /* 1879 * Finally, enable interrupts. Note: Modem status interrupts 1880 * are set via set_termios(), which will be occurring imminently 1881 * anyway, so we don't enable them here. 1882 */ 1883 up->ier = UART_IER_RLSI | UART_IER_RDI; 1884 serial_outp(up, UART_IER, up->ier); 1885 1886 if (up->port.flags & UPF_FOURPORT) { 1887 unsigned int icp; 1888 /* 1889 * Enable interrupts on the AST Fourport board 1890 */ 1891 icp = (up->port.iobase & 0xfe0) | 0x01f; 1892 outb_p(0x80, icp); 1893 (void) inb_p(icp); 1894 } 1895 1896 /* 1897 * And clear the interrupt registers again for luck. 1898 */ 1899 (void) serial_inp(up, UART_LSR); 1900 (void) serial_inp(up, UART_RX); 1901 (void) serial_inp(up, UART_IIR); 1902 (void) serial_inp(up, UART_MSR); 1903 1904 return 0; 1905} 1906 1907static void serial8250_shutdown(struct uart_port *port) 1908{ 1909 struct uart_8250_port *up = (struct uart_8250_port *)port; 1910 unsigned long flags; 1911 1912 /* 1913 * Disable interrupts from this port 1914 */ 1915 up->ier = 0; 1916 serial_outp(up, UART_IER, 0); 1917 1918 spin_lock_irqsave(&up->port.lock, flags); 1919 if (up->port.flags & UPF_FOURPORT) { 1920 /* reset interrupts on the AST Fourport board */ 1921 inb((up->port.iobase & 0xfe0) | 0x1f); 1922 up->port.mctrl |= TIOCM_OUT1; 1923 } else 1924 up->port.mctrl &= ~TIOCM_OUT2; 1925 1926 serial8250_set_mctrl(&up->port, up->port.mctrl); 1927 spin_unlock_irqrestore(&up->port.lock, flags); 1928 1929 /* 1930 * Disable break condition and FIFOs 1931 */ 1932 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); 1933 serial8250_clear_fifos(up); 1934 1935#ifdef CONFIG_SERIAL_8250_RSA 1936 /* 1937 * Reset the RSA board back to 115kbps compat mode. 1938 */ 1939 disable_rsa(up); 1940#endif 1941 1942 /* 1943 * Read data port to reset things, and then unlink from 1944 * the IRQ chain. 1945 */ 1946 (void) serial_in(up, UART_RX); 1947 1948 del_timer_sync(&up->timer); 1949 up->timer.function = serial8250_timeout; 1950 if (is_real_interrupt(up->port.irq)) 1951 serial_unlink_irq_chain(up); 1952} 1953 1954static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) 1955{ 1956 unsigned int quot; 1957 1958 /* 1959 * Handle magic divisors for baud rates above baud_base on 1960 * SMSC SuperIO chips. 1961 */ 1962 if ((port->flags & UPF_MAGIC_MULTIPLIER) && 1963 baud == (port->uartclk/4)) 1964 quot = 0x8001; 1965 else if ((port->flags & UPF_MAGIC_MULTIPLIER) && 1966 baud == (port->uartclk/8)) 1967 quot = 0x8002; 1968 else 1969 quot = uart_get_divisor(port, baud); 1970 1971 return quot; 1972} 1973 1974static void 1975serial8250_set_termios(struct uart_port *port, struct ktermios *termios, 1976 struct ktermios *old) 1977{ 1978 struct uart_8250_port *up = (struct uart_8250_port *)port; 1979 unsigned char cval, fcr = 0; 1980 unsigned long flags; 1981 unsigned int baud, quot; 1982 1983 switch (termios->c_cflag & CSIZE) { 1984 case CS5: 1985 cval = UART_LCR_WLEN5; 1986 break; 1987 case CS6: 1988 cval = UART_LCR_WLEN6; 1989 break; 1990 case CS7: 1991 cval = UART_LCR_WLEN7; 1992 break; 1993 default: 1994 case CS8: 1995 cval = UART_LCR_WLEN8; 1996 break; 1997 } 1998 1999 if (termios->c_cflag & CSTOPB) 2000 cval |= UART_LCR_STOP; 2001 if (termios->c_cflag & PARENB) 2002 cval |= UART_LCR_PARITY; 2003 if (!(termios->c_cflag & PARODD)) 2004 cval |= UART_LCR_EPAR; 2005#ifdef CMSPAR 2006 if (termios->c_cflag & CMSPAR) 2007 cval |= UART_LCR_SPAR; 2008#endif 2009 2010 /* 2011 * Ask the core to calculate the divisor for us. 2012 */ 2013 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 2014 quot = serial8250_get_divisor(port, baud); 2015 2016 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) 2017 quot ++; 2018 2019 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) { 2020 if (baud < 2400) 2021 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; 2022 else 2023 fcr = uart_config[up->port.type].fcr; 2024 } 2025 2026 /* 2027 * MCR-based auto flow control. When AFE is enabled, RTS will be 2028 * deasserted when the receive FIFO contains more characters than 2029 * the trigger, or the MCR RTS bit is cleared. In the case where 2030 * the remote UART is not using CTS auto flow control, we must 2031 * have sufficient FIFO entries for the latency of the remote 2032 * UART to respond. IOW, at least 32 bytes of FIFO. 2033 */ 2034 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { 2035 up->mcr &= ~UART_MCR_AFE; 2036 if (termios->c_cflag & CRTSCTS) 2037 up->mcr |= UART_MCR_AFE; 2038 } 2039 2040 /* 2041 * Ok, we're now changing the port state. Do it with 2042 * interrupts disabled. 2043 */ 2044 spin_lock_irqsave(&up->port.lock, flags); 2045 2046 /* 2047 * Update the per-port timeout. 2048 */ 2049 uart_update_timeout(port, termios->c_cflag, baud); 2050 2051 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 2052 if (termios->c_iflag & INPCK) 2053 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 2054 if (termios->c_iflag & (BRKINT | PARMRK)) 2055 up->port.read_status_mask |= UART_LSR_BI; 2056 2057 /* 2058 * Characteres to ignore 2059 */ 2060 up->port.ignore_status_mask = 0; 2061 if (termios->c_iflag & IGNPAR) 2062 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 2063 if (termios->c_iflag & IGNBRK) { 2064 up->port.ignore_status_mask |= UART_LSR_BI; 2065 /* 2066 * If we're ignoring parity and break indicators, 2067 * ignore overruns too (for real raw support). 2068 */ 2069 if (termios->c_iflag & IGNPAR) 2070 up->port.ignore_status_mask |= UART_LSR_OE; 2071 } 2072 2073 /* 2074 * ignore all characters if CREAD is not set 2075 */ 2076 if ((termios->c_cflag & CREAD) == 0) 2077 up->port.ignore_status_mask |= UART_LSR_DR; 2078 2079 /* 2080 * CTS flow control flag and modem status interrupts 2081 */ 2082 up->ier &= ~UART_IER_MSI; 2083 if (!(up->bugs & UART_BUG_NOMSR) && 2084 UART_ENABLE_MS(&up->port, termios->c_cflag)) 2085 up->ier |= UART_IER_MSI; 2086 if (up->capabilities & UART_CAP_UUE) 2087 up->ier |= UART_IER_UUE | UART_IER_RTOIE; 2088 2089 serial_out(up, UART_IER, up->ier); 2090 2091 if (up->capabilities & UART_CAP_EFR) { 2092 unsigned char efr = 0; 2093 if (termios->c_cflag & CRTSCTS) 2094 efr |= UART_EFR_CTS; 2095 2096 serial_outp(up, UART_LCR, 0xBF); 2097 serial_outp(up, UART_EFR, efr); 2098 } 2099 2100#ifdef CONFIG_ARCH_OMAP15XX 2101 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) { 2102 if (baud == 115200) { 2103 quot = 1; 2104 serial_out(up, UART_OMAP_OSC_12M_SEL, 1); 2105 } else 2106 serial_out(up, UART_OMAP_OSC_12M_SEL, 0); 2107 } 2108#endif 2109 2110 if (up->capabilities & UART_NATSEMI) { 2111 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ 2112 serial_outp(up, UART_LCR, 0xe0); 2113 } else { 2114 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ 2115 } 2116 2117 serial_dl_write(up, quot); 2118 2119 /* 2120 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR 2121 * is written without DLAB set, this mode will be disabled. 2122 */ 2123 if (up->port.type == PORT_16750) 2124 serial_outp(up, UART_FCR, fcr); 2125 2126 serial_outp(up, UART_LCR, cval); /* reset DLAB */ 2127 up->lcr = cval; /* Save LCR */ 2128 if (up->port.type != PORT_16750) { 2129 if (fcr & UART_FCR_ENABLE_FIFO) { 2130 /* emulated UARTs (Lucent Venus 167x) need two steps */ 2131 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 2132 } 2133 serial_outp(up, UART_FCR, fcr); /* set fcr */ 2134 } 2135 serial8250_set_mctrl(&up->port, up->port.mctrl); 2136 spin_unlock_irqrestore(&up->port.lock, flags); 2137} 2138 2139static void 2140serial8250_pm(struct uart_port *port, unsigned int state, 2141 unsigned int oldstate) 2142{ 2143 struct uart_8250_port *p = (struct uart_8250_port *)port; 2144 2145 serial8250_set_sleep(p, state != 0); 2146 2147 if (p->pm) 2148 p->pm(port, state, oldstate); 2149} 2150 2151/* 2152 * Resource handling. 2153 */ 2154static int serial8250_request_std_resource(struct uart_8250_port *up) 2155{ 2156 unsigned int size = 8 << up->port.regshift; 2157 int ret = 0; 2158 2159 switch (up->port.iotype) { 2160 case UPIO_AU: 2161 size = 0x100000; 2162 /* fall thru */ 2163 case UPIO_TSI: 2164 case UPIO_MEM32: 2165 case UPIO_MEM: 2166 case UPIO_DWAPB: 2167 if (!up->port.mapbase) 2168 break; 2169 2170 if (!request_mem_region(up->port.mapbase, size, "serial")) { 2171 ret = -EBUSY; 2172 break; 2173 } 2174 2175 if (up->port.flags & UPF_IOREMAP) { 2176 up->port.membase = ioremap(up->port.mapbase, size); 2177 if (!up->port.membase) { 2178 release_mem_region(up->port.mapbase, size); 2179 ret = -ENOMEM; 2180 } 2181 } 2182 break; 2183 2184 case UPIO_HUB6: 2185 case UPIO_PORT: 2186 if (!request_region(up->port.iobase, size, "serial")) 2187 ret = -EBUSY; 2188 break; 2189 } 2190 return ret; 2191} 2192 2193static void serial8250_release_std_resource(struct uart_8250_port *up) 2194{ 2195 unsigned int size = 8 << up->port.regshift; 2196 2197 switch (up->port.iotype) { 2198 case UPIO_AU: 2199 size = 0x100000; 2200 /* fall thru */ 2201 case UPIO_TSI: 2202 case UPIO_MEM32: 2203 case UPIO_MEM: 2204 case UPIO_DWAPB: 2205 if (!up->port.mapbase) 2206 break; 2207 2208 if (up->port.flags & UPF_IOREMAP) { 2209 iounmap(up->port.membase); 2210 up->port.membase = NULL; 2211 } 2212 2213 release_mem_region(up->port.mapbase, size); 2214 break; 2215 2216 case UPIO_HUB6: 2217 case UPIO_PORT: 2218 release_region(up->port.iobase, size); 2219 break; 2220 } 2221} 2222 2223static int serial8250_request_rsa_resource(struct uart_8250_port *up) 2224{ 2225 unsigned long start = UART_RSA_BASE << up->port.regshift; 2226 unsigned int size = 8 << up->port.regshift; 2227 int ret = -EINVAL; 2228 2229 switch (up->port.iotype) { 2230 case UPIO_HUB6: 2231 case UPIO_PORT: 2232 start += up->port.iobase; 2233 if (request_region(start, size, "serial-rsa")) 2234 ret = 0; 2235 else 2236 ret = -EBUSY; 2237 break; 2238 } 2239 2240 return ret; 2241} 2242 2243static void serial8250_release_rsa_resource(struct uart_8250_port *up) 2244{ 2245 unsigned long offset = UART_RSA_BASE << up->port.regshift; 2246 unsigned int size = 8 << up->port.regshift; 2247 2248 switch (up->port.iotype) { 2249 case UPIO_HUB6: 2250 case UPIO_PORT: 2251 release_region(up->port.iobase + offset, size); 2252 break; 2253 } 2254} 2255 2256static void serial8250_release_port(struct uart_port *port) 2257{ 2258 struct uart_8250_port *up = (struct uart_8250_port *)port; 2259 2260 serial8250_release_std_resource(up); 2261 if (up->port.type == PORT_RSA) 2262 serial8250_release_rsa_resource(up); 2263} 2264 2265static int serial8250_request_port(struct uart_port *port) 2266{ 2267 struct uart_8250_port *up = (struct uart_8250_port *)port; 2268 int ret = 0; 2269 2270 ret = serial8250_request_std_resource(up); 2271 if (ret == 0 && up->port.type == PORT_RSA) { 2272 ret = serial8250_request_rsa_resource(up); 2273 if (ret < 0) 2274 serial8250_release_std_resource(up); 2275 } 2276 2277 return ret; 2278} 2279 2280static void serial8250_config_port(struct uart_port *port, int flags) 2281{ 2282 struct uart_8250_port *up = (struct uart_8250_port *)port; 2283 int probeflags = PROBE_ANY; 2284 int ret; 2285 2286 /* 2287 * Find the region that we can probe for. This in turn 2288 * tells us whether we can probe for the type of port. 2289 */ 2290 ret = serial8250_request_std_resource(up); 2291 if (ret < 0) 2292 return; 2293 2294 ret = serial8250_request_rsa_resource(up); 2295 if (ret < 0) 2296 probeflags &= ~PROBE_RSA; 2297 2298 if (flags & UART_CONFIG_TYPE) 2299 autoconfig(up, probeflags); 2300 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) 2301 autoconfig_irq(up); 2302 2303 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA) 2304 serial8250_release_rsa_resource(up); 2305 if (up->port.type == PORT_UNKNOWN) 2306 serial8250_release_std_resource(up); 2307} 2308 2309static int 2310serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) 2311{ 2312 if (ser->irq >= NR_IRQS || ser->irq < 0 || 2313 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || 2314 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || 2315 ser->type == PORT_STARTECH) 2316 return -EINVAL; 2317 return 0; 2318} 2319 2320static const char * 2321serial8250_type(struct uart_port *port) 2322{ 2323 int type = port->type; 2324 2325 if (type >= ARRAY_SIZE(uart_config)) 2326 type = 0; 2327 return uart_config[type].name; 2328} 2329 2330static struct uart_ops serial8250_pops = { 2331 .tx_empty = serial8250_tx_empty, 2332 .set_mctrl = serial8250_set_mctrl, 2333 .get_mctrl = serial8250_get_mctrl, 2334 .stop_tx = serial8250_stop_tx, 2335 .start_tx = serial8250_start_tx, 2336 .stop_rx = serial8250_stop_rx, 2337 .enable_ms = serial8250_enable_ms, 2338 .break_ctl = serial8250_break_ctl, 2339 .startup = serial8250_startup, 2340 .shutdown = serial8250_shutdown, 2341 .set_termios = serial8250_set_termios, 2342 .pm = serial8250_pm, 2343 .type = serial8250_type, 2344 .release_port = serial8250_release_port, 2345 .request_port = serial8250_request_port, 2346 .config_port = serial8250_config_port, 2347 .verify_port = serial8250_verify_port, 2348}; 2349 2350static struct uart_8250_port serial8250_ports[UART_NR]; 2351 2352static void __init serial8250_isa_init_ports(void) 2353{ 2354 struct uart_8250_port *up; 2355 static int first = 1; 2356 int i; 2357 2358 if (!first) 2359 return; 2360 first = 0; 2361 2362 for (i = 0; i < nr_uarts; i++) { 2363 struct uart_8250_port *up = &serial8250_ports[i]; 2364 2365 up->port.line = i; 2366 spin_lock_init(&up->port.lock); 2367 2368 init_timer(&up->timer); 2369 up->timer.function = serial8250_timeout; 2370 2371 /* 2372 * ALPHA_KLUDGE_MCR needs to be killed. 2373 */ 2374 up->mcr_mask = ~ALPHA_KLUDGE_MCR; 2375 up->mcr_force = ALPHA_KLUDGE_MCR; 2376 2377 up->port.ops = &serial8250_pops; 2378 } 2379 2380 for (i = 0, up = serial8250_ports; 2381 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; 2382 i++, up++) { 2383 up->port.iobase = old_serial_port[i].port; 2384 up->port.irq = irq_canonicalize(old_serial_port[i].irq); 2385 up->port.uartclk = old_serial_port[i].baud_base * 16; 2386 up->port.flags = old_serial_port[i].flags; 2387 up->port.hub6 = old_serial_port[i].hub6; 2388 up->port.membase = old_serial_port[i].iomem_base; 2389 up->port.iotype = old_serial_port[i].io_type; 2390 up->port.regshift = old_serial_port[i].iomem_reg_shift; 2391 if (share_irqs) 2392 up->port.flags |= UPF_SHARE_IRQ; 2393 } 2394} 2395 2396static void __init 2397serial8250_register_ports(struct uart_driver *drv, struct device *dev) 2398{ 2399 int i; 2400 2401 serial8250_isa_init_ports(); 2402 2403 for (i = 0; i < nr_uarts; i++) { 2404 struct uart_8250_port *up = &serial8250_ports[i]; 2405 2406 up->port.dev = dev; 2407 uart_add_one_port(drv, &up->port); 2408 } 2409} 2410 2411#ifdef CONFIG_SERIAL_8250_CONSOLE 2412 2413static void serial8250_console_putchar(struct uart_port *port, int ch) 2414{ 2415 struct uart_8250_port *up = (struct uart_8250_port *)port; 2416 2417 wait_for_xmitr(up, UART_LSR_THRE); 2418 serial_out(up, UART_TX, ch); 2419} 2420 2421/* 2422 * Print a string to the serial port trying not to disturb 2423 * any possible real use of the port... 2424 * 2425 * The console_lock must be held when we get here. 2426 */ 2427static void 2428serial8250_console_write(struct console *co, const char *s, unsigned int count) 2429{ 2430 struct uart_8250_port *up = &serial8250_ports[co->index]; 2431 unsigned long flags; 2432 unsigned int ier; 2433 int locked = 1; 2434 2435 touch_nmi_watchdog(); 2436 2437 local_irq_save(flags); 2438 if (up->port.sysrq) { 2439 /* serial8250_handle_port() already took the lock */ 2440 locked = 0; 2441 } else if (oops_in_progress) { 2442 locked = spin_trylock(&up->port.lock); 2443 } else 2444 spin_lock(&up->port.lock); 2445 2446 /* 2447 * First save the IER then disable the interrupts 2448 */ 2449 ier = serial_in(up, UART_IER); 2450 2451 if (up->capabilities & UART_CAP_UUE) 2452 serial_out(up, UART_IER, UART_IER_UUE); 2453 else 2454 serial_out(up, UART_IER, 0); 2455 2456 uart_console_write(&up->port, s, count, serial8250_console_putchar); 2457 2458 /* 2459 * Finally, wait for transmitter to become empty 2460 * and restore the IER 2461 */ 2462 wait_for_xmitr(up, BOTH_EMPTY); 2463 serial_out(up, UART_IER, ier); 2464 2465 if (locked) 2466 spin_unlock(&up->port.lock); 2467 local_irq_restore(flags); 2468} 2469 2470static int __init serial8250_console_setup(struct console *co, char *options) 2471{ 2472 struct uart_port *port; 2473 int baud = 9600; 2474 int bits = 8; 2475 int parity = 'n'; 2476 int flow = 'n'; 2477 2478 /* 2479 * Check whether an invalid uart number has been specified, and 2480 * if so, search for the first available port that does have 2481 * console support. 2482 */ 2483 if (co->index >= nr_uarts) 2484 co->index = 0; 2485 port = &serial8250_ports[co->index].port; 2486 if (!port->iobase && !port->membase) 2487 return -ENODEV; 2488 2489 if (options) 2490 uart_parse_options(options, &baud, &parity, &bits, &flow); 2491 2492 return uart_set_options(port, co, baud, parity, bits, flow); 2493} 2494 2495static struct uart_driver serial8250_reg; 2496static struct console serial8250_console = { 2497 .name = "ttyS", 2498 .write = serial8250_console_write, 2499 .device = uart_console_device, 2500 .setup = serial8250_console_setup, 2501 .flags = CON_PRINTBUFFER, 2502 .index = -1, 2503 .data = &serial8250_reg, 2504}; 2505 2506static int __init serial8250_console_init(void) 2507{ 2508 serial8250_isa_init_ports(); 2509 register_console(&serial8250_console); 2510 return 0; 2511} 2512console_initcall(serial8250_console_init); 2513 2514static int __init find_port(struct uart_port *p) 2515{ 2516 int line; 2517 struct uart_port *port; 2518 2519 for (line = 0; line < nr_uarts; line++) { 2520 port = &serial8250_ports[line].port; 2521 if (uart_match_port(p, port)) 2522 return line; 2523 } 2524 return -ENODEV; 2525} 2526 2527int __init serial8250_start_console(struct uart_port *port, char *options) 2528{ 2529 int line; 2530 2531 line = find_port(port); 2532 if (line < 0) 2533 return -ENODEV; 2534 2535 add_preferred_console("ttyS", line, options); 2536 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n", 2537 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port", 2538 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase : 2539 (unsigned long) port->iobase, options); 2540 if (!(serial8250_console.flags & CON_ENABLED)) { 2541 serial8250_console.flags &= ~CON_PRINTBUFFER; 2542 register_console(&serial8250_console); 2543 } 2544 return line; 2545} 2546 2547#define SERIAL8250_CONSOLE &serial8250_console 2548#else 2549#define SERIAL8250_CONSOLE NULL 2550#endif 2551 2552static struct uart_driver serial8250_reg = { 2553 .owner = THIS_MODULE, 2554 .driver_name = "serial", 2555 .dev_name = "ttyS", 2556 .major = TTY_MAJOR, 2557 .minor = 64, 2558 .nr = UART_NR, 2559 .cons = SERIAL8250_CONSOLE, 2560}; 2561 2562/* 2563 * early_serial_setup - early registration for 8250 ports 2564 * 2565 * Setup an 8250 port structure prior to console initialisation. Use 2566 * after console initialisation will cause undefined behaviour. 2567 */ 2568int __init early_serial_setup(struct uart_port *port) 2569{ 2570 if (port->line >= ARRAY_SIZE(serial8250_ports)) 2571 return -ENODEV; 2572 2573 serial8250_isa_init_ports(); 2574 serial8250_ports[port->line].port = *port; 2575 serial8250_ports[port->line].port.ops = &serial8250_pops; 2576 return 0; 2577} 2578 2579/** 2580 * serial8250_suspend_port - suspend one serial port 2581 * @line: serial line number 2582 * 2583 * Suspend one serial port. 2584 */ 2585void serial8250_suspend_port(int line) 2586{ 2587 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); 2588} 2589 2590/** 2591 * serial8250_resume_port - resume one serial port 2592 * @line: serial line number 2593 * 2594 * Resume one serial port. 2595 */ 2596void serial8250_resume_port(int line) 2597{ 2598 struct uart_8250_port *up = &serial8250_ports[line]; 2599 2600 if (up->capabilities & UART_NATSEMI) { 2601 unsigned char tmp; 2602 2603 /* Ensure it's still in high speed mode */ 2604 serial_outp(up, UART_LCR, 0xE0); 2605 2606 tmp = serial_in(up, 0x04); /* EXCR2 */ 2607 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ 2608 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ 2609 serial_outp(up, 0x04, tmp); 2610 2611 serial_outp(up, UART_LCR, 0); 2612 } 2613 uart_resume_port(&serial8250_reg, &up->port); 2614} 2615 2616/* 2617 * Register a set of serial devices attached to a platform device. The 2618 * list is terminated with a zero flags entry, which means we expect 2619 * all entries to have at least UPF_BOOT_AUTOCONF set. 2620 */ 2621static int __devinit serial8250_probe(struct platform_device *dev) 2622{ 2623 struct plat_serial8250_port *p = dev->dev.platform_data; 2624 struct uart_port port; 2625 int ret, i; 2626 2627 memset(&port, 0, sizeof(struct uart_port)); 2628 2629 for (i = 0; p && p->flags != 0; p++, i++) { 2630 port.iobase = p->iobase; 2631 port.membase = p->membase; 2632 port.irq = p->irq; 2633 port.uartclk = p->uartclk; 2634 port.regshift = p->regshift; 2635 port.iotype = p->iotype; 2636 port.flags = p->flags; 2637 port.mapbase = p->mapbase; 2638 port.hub6 = p->hub6; 2639 port.dev = &dev->dev; 2640 if (share_irqs) 2641 port.flags |= UPF_SHARE_IRQ; 2642 ret = serial8250_register_port(&port); 2643 if (ret < 0) { 2644 dev_err(&dev->dev, "unable to register port at index %d " 2645 "(IO%lx MEM%lx IRQ%d): %d\n", i, 2646 p->iobase, p->mapbase, p->irq, ret); 2647 } 2648 } 2649 return 0; 2650} 2651 2652/* 2653 * Remove serial ports registered against a platform device. 2654 */ 2655static int __devexit serial8250_remove(struct platform_device *dev) 2656{ 2657 int i; 2658 2659 for (i = 0; i < nr_uarts; i++) { 2660 struct uart_8250_port *up = &serial8250_ports[i]; 2661 2662 if (up->port.dev == &dev->dev) 2663 serial8250_unregister_port(i); 2664 } 2665 return 0; 2666} 2667 2668static int serial8250_suspend(struct platform_device *dev, pm_message_t state) 2669{ 2670 int i; 2671 2672 for (i = 0; i < UART_NR; i++) { 2673 struct uart_8250_port *up = &serial8250_ports[i]; 2674 2675 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) 2676 uart_suspend_port(&serial8250_reg, &up->port); 2677 } 2678 2679 return 0; 2680} 2681 2682static int serial8250_resume(struct platform_device *dev) 2683{ 2684 int i; 2685 2686 for (i = 0; i < UART_NR; i++) { 2687 struct uart_8250_port *up = &serial8250_ports[i]; 2688 2689 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) 2690 serial8250_resume_port(i); 2691 } 2692 2693 return 0; 2694} 2695 2696static struct platform_driver serial8250_isa_driver = { 2697 .probe = serial8250_probe, 2698 .remove = __devexit_p(serial8250_remove), 2699 .suspend = serial8250_suspend, 2700 .resume = serial8250_resume, 2701 .driver = { 2702 .name = "serial8250", 2703 .owner = THIS_MODULE, 2704 }, 2705}; 2706 2707/* 2708 * This "device" covers _all_ ISA 8250-compatible serial devices listed 2709 * in the table in include/asm/serial.h 2710 */ 2711static struct platform_device *serial8250_isa_devs; 2712 2713/* 2714 * serial8250_register_port and serial8250_unregister_port allows for 2715 * 16x50 serial ports to be configured at run-time, to support PCMCIA 2716 * modems and PCI multiport cards. 2717 */ 2718static DEFINE_MUTEX(serial_mutex); 2719 2720static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) 2721{ 2722 int i; 2723 2724 /* 2725 * First, find a port entry which matches. 2726 */ 2727 for (i = 0; i < nr_uarts; i++) 2728 if (uart_match_port(&serial8250_ports[i].port, port)) 2729 return &serial8250_ports[i]; 2730 2731 /* 2732 * We didn't find a matching entry, so look for the first 2733 * free entry. We look for one which hasn't been previously 2734 * used (indicated by zero iobase). 2735 */ 2736 for (i = 0; i < nr_uarts; i++) 2737 if (serial8250_ports[i].port.type == PORT_UNKNOWN && 2738 serial8250_ports[i].port.iobase == 0) 2739 return &serial8250_ports[i]; 2740 2741 /* 2742 * That also failed. Last resort is to find any entry which 2743 * doesn't have a real port associated with it. 2744 */ 2745 for (i = 0; i < nr_uarts; i++) 2746 if (serial8250_ports[i].port.type == PORT_UNKNOWN) 2747 return &serial8250_ports[i]; 2748 2749 return NULL; 2750} 2751 2752/** 2753 * serial8250_register_port - register a serial port 2754 * @port: serial port template 2755 * 2756 * Configure the serial port specified by the request. If the 2757 * port exists and is in use, it is hung up and unregistered 2758 * first. 2759 * 2760 * The port is then probed and if necessary the IRQ is autodetected 2761 * If this fails an error is returned. 2762 * 2763 * On success the port is ready to use and the line number is returned. 2764 */ 2765int serial8250_register_port(struct uart_port *port) 2766{ 2767 struct uart_8250_port *uart; 2768 int ret = -ENOSPC; 2769 2770 if (port->uartclk == 0) 2771 return -EINVAL; 2772 2773 mutex_lock(&serial_mutex); 2774 2775 uart = serial8250_find_match_or_unused(port); 2776 if (uart) { 2777 uart_remove_one_port(&serial8250_reg, &uart->port); 2778 2779 uart->port.iobase = port->iobase; 2780 uart->port.membase = port->membase; 2781 uart->port.irq = port->irq; 2782 uart->port.uartclk = port->uartclk; 2783 uart->port.fifosize = port->fifosize; 2784 uart->port.regshift = port->regshift; 2785 uart->port.iotype = port->iotype; 2786 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; 2787 uart->port.mapbase = port->mapbase; 2788 if (port->dev) 2789 uart->port.dev = port->dev; 2790 2791 ret = uart_add_one_port(&serial8250_reg, &uart->port); 2792 if (ret == 0) 2793 ret = uart->port.line; 2794 } 2795 mutex_unlock(&serial_mutex); 2796 2797 return ret; 2798} 2799EXPORT_SYMBOL(serial8250_register_port); 2800 2801/** 2802 * serial8250_unregister_port - remove a 16x50 serial port at runtime 2803 * @line: serial line number 2804 * 2805 * Remove one serial port. This may not be called from interrupt 2806 * context. We hand the port back to the our control. 2807 */ 2808void serial8250_unregister_port(int line) 2809{ 2810 struct uart_8250_port *uart = &serial8250_ports[line]; 2811 2812 mutex_lock(&serial_mutex); 2813 uart_remove_one_port(&serial8250_reg, &uart->port); 2814 if (serial8250_isa_devs) { 2815 uart->port.flags &= ~UPF_BOOT_AUTOCONF; 2816 uart->port.type = PORT_UNKNOWN; 2817 uart->port.dev = &serial8250_isa_devs->dev; 2818 uart_add_one_port(&serial8250_reg, &uart->port); 2819 } else { 2820 uart->port.dev = NULL; 2821 } 2822 mutex_unlock(&serial_mutex); 2823} 2824EXPORT_SYMBOL(serial8250_unregister_port); 2825 2826static int __init serial8250_init(void) 2827{ 2828 int ret, i; 2829 2830 if (nr_uarts > UART_NR) 2831 nr_uarts = UART_NR; 2832 2833 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.1.1.1 $ " 2834 "%d ports, IRQ sharing %sabled\n", nr_uarts, 2835 share_irqs ? "en" : "dis"); 2836 2837 for (i = 0; i < NR_IRQS; i++) 2838 spin_lock_init(&irq_lists[i].lock); 2839 2840 ret = uart_register_driver(&serial8250_reg); 2841 if (ret) 2842 goto out; 2843 2844 serial8250_isa_devs = platform_device_alloc("serial8250", 2845 PLAT8250_DEV_LEGACY); 2846 if (!serial8250_isa_devs) { 2847 ret = -ENOMEM; 2848 goto unreg_uart_drv; 2849 } 2850 2851 ret = platform_device_add(serial8250_isa_devs); 2852 if (ret) 2853 goto put_dev; 2854 2855 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); 2856 2857 ret = platform_driver_register(&serial8250_isa_driver); 2858 if (ret == 0) 2859 goto out; 2860 2861 platform_device_del(serial8250_isa_devs); 2862 put_dev: 2863 platform_device_put(serial8250_isa_devs); 2864 unreg_uart_drv: 2865 uart_unregister_driver(&serial8250_reg); 2866 out: 2867 return ret; 2868} 2869 2870static void __exit serial8250_exit(void) 2871{ 2872 struct platform_device *isa_dev = serial8250_isa_devs; 2873 2874 /* 2875 * This tells serial8250_unregister_port() not to re-register 2876 * the ports (thereby making serial8250_isa_driver permanently 2877 * in use.) 2878 */ 2879 serial8250_isa_devs = NULL; 2880 2881 platform_driver_unregister(&serial8250_isa_driver); 2882 platform_device_unregister(isa_dev); 2883 2884 uart_unregister_driver(&serial8250_reg); 2885} 2886 2887module_init(serial8250_init); 2888module_exit(serial8250_exit); 2889 2890EXPORT_SYMBOL(serial8250_suspend_port); 2891EXPORT_SYMBOL(serial8250_resume_port); 2892 2893MODULE_LICENSE("GPL"); 2894MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.1.1.1 $"); 2895 2896module_param(share_irqs, uint, 0644); 2897MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" 2898 " (unsafe)"); 2899 2900module_param(nr_uarts, uint, 0644); 2901MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); 2902 2903#ifdef CONFIG_SERIAL_8250_RSA 2904module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); 2905MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); 2906#endif 2907MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); 2908