1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2005 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#include "qla_def.h" 8 9#include <linux/delay.h> 10#include <asm/uaccess.h> 11 12static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t); 13static void qla2x00_nv_deselect(scsi_qla_host_t *); 14static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t); 15 16/* 17 * NVRAM support routines 18 */ 19 20/** 21 * qla2x00_lock_nvram_access() - 22 * @ha: HA context 23 */ 24void 25qla2x00_lock_nvram_access(scsi_qla_host_t *ha) 26{ 27 uint16_t data; 28 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 29 30 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 31 data = RD_REG_WORD(®->nvram); 32 while (data & NVR_BUSY) { 33 udelay(100); 34 data = RD_REG_WORD(®->nvram); 35 } 36 37 /* Lock resource */ 38 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 39 RD_REG_WORD(®->u.isp2300.host_semaphore); 40 udelay(5); 41 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 42 while ((data & BIT_0) == 0) { 43 /* Lock failed */ 44 udelay(100); 45 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 46 RD_REG_WORD(®->u.isp2300.host_semaphore); 47 udelay(5); 48 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 49 } 50 } 51} 52 53/** 54 * qla2x00_unlock_nvram_access() - 55 * @ha: HA context 56 */ 57void 58qla2x00_unlock_nvram_access(scsi_qla_host_t *ha) 59{ 60 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 61 62 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 63 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); 64 RD_REG_WORD(®->u.isp2300.host_semaphore); 65 } 66} 67 68/** 69 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 70 * request routine to get the word from NVRAM. 71 * @ha: HA context 72 * @addr: Address in NVRAM to read 73 * 74 * Returns the word read from nvram @addr. 75 */ 76uint16_t 77qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr) 78{ 79 uint16_t data; 80 uint32_t nv_cmd; 81 82 nv_cmd = addr << 16; 83 nv_cmd |= NV_READ_OP; 84 data = qla2x00_nvram_request(ha, nv_cmd); 85 86 return (data); 87} 88 89/** 90 * qla2x00_write_nvram_word() - Write NVRAM data. 91 * @ha: HA context 92 * @addr: Address in NVRAM to write 93 * @data: word to program 94 */ 95void 96qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data) 97{ 98 int count; 99 uint16_t word; 100 uint32_t nv_cmd, wait_cnt; 101 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 102 103 qla2x00_nv_write(ha, NVR_DATA_OUT); 104 qla2x00_nv_write(ha, 0); 105 qla2x00_nv_write(ha, 0); 106 107 for (word = 0; word < 8; word++) 108 qla2x00_nv_write(ha, NVR_DATA_OUT); 109 110 qla2x00_nv_deselect(ha); 111 112 /* Write data */ 113 nv_cmd = (addr << 16) | NV_WRITE_OP; 114 nv_cmd |= data; 115 nv_cmd <<= 5; 116 for (count = 0; count < 27; count++) { 117 if (nv_cmd & BIT_31) 118 qla2x00_nv_write(ha, NVR_DATA_OUT); 119 else 120 qla2x00_nv_write(ha, 0); 121 122 nv_cmd <<= 1; 123 } 124 125 qla2x00_nv_deselect(ha); 126 127 /* Wait for NVRAM to become ready */ 128 WRT_REG_WORD(®->nvram, NVR_SELECT); 129 RD_REG_WORD(®->nvram); /* PCI Posting. */ 130 wait_cnt = NVR_WAIT_CNT; 131 do { 132 if (!--wait_cnt) { 133 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", 134 __func__, ha->host_no)); 135 break; 136 } 137 NVRAM_DELAY(); 138 word = RD_REG_WORD(®->nvram); 139 } while ((word & NVR_DATA_IN) == 0); 140 141 qla2x00_nv_deselect(ha); 142 143 /* Disable writes */ 144 qla2x00_nv_write(ha, NVR_DATA_OUT); 145 for (count = 0; count < 10; count++) 146 qla2x00_nv_write(ha, 0); 147 148 qla2x00_nv_deselect(ha); 149} 150 151static int 152qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data, 153 uint32_t tmo) 154{ 155 int ret, count; 156 uint16_t word; 157 uint32_t nv_cmd; 158 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 159 160 ret = QLA_SUCCESS; 161 162 qla2x00_nv_write(ha, NVR_DATA_OUT); 163 qla2x00_nv_write(ha, 0); 164 qla2x00_nv_write(ha, 0); 165 166 for (word = 0; word < 8; word++) 167 qla2x00_nv_write(ha, NVR_DATA_OUT); 168 169 qla2x00_nv_deselect(ha); 170 171 /* Write data */ 172 nv_cmd = (addr << 16) | NV_WRITE_OP; 173 nv_cmd |= data; 174 nv_cmd <<= 5; 175 for (count = 0; count < 27; count++) { 176 if (nv_cmd & BIT_31) 177 qla2x00_nv_write(ha, NVR_DATA_OUT); 178 else 179 qla2x00_nv_write(ha, 0); 180 181 nv_cmd <<= 1; 182 } 183 184 qla2x00_nv_deselect(ha); 185 186 /* Wait for NVRAM to become ready */ 187 WRT_REG_WORD(®->nvram, NVR_SELECT); 188 RD_REG_WORD(®->nvram); /* PCI Posting. */ 189 do { 190 NVRAM_DELAY(); 191 word = RD_REG_WORD(®->nvram); 192 if (!--tmo) { 193 ret = QLA_FUNCTION_FAILED; 194 break; 195 } 196 } while ((word & NVR_DATA_IN) == 0); 197 198 qla2x00_nv_deselect(ha); 199 200 /* Disable writes */ 201 qla2x00_nv_write(ha, NVR_DATA_OUT); 202 for (count = 0; count < 10; count++) 203 qla2x00_nv_write(ha, 0); 204 205 qla2x00_nv_deselect(ha); 206 207 return ret; 208} 209 210/** 211 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 212 * NVRAM. 213 * @ha: HA context 214 * @nv_cmd: NVRAM command 215 * 216 * Bit definitions for NVRAM command: 217 * 218 * Bit 26 = start bit 219 * Bit 25, 24 = opcode 220 * Bit 23-16 = address 221 * Bit 15-0 = write data 222 * 223 * Returns the word read from nvram @addr. 224 */ 225static uint16_t 226qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd) 227{ 228 uint8_t cnt; 229 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 230 uint16_t data = 0; 231 uint16_t reg_data; 232 233 /* Send command to NVRAM. */ 234 nv_cmd <<= 5; 235 for (cnt = 0; cnt < 11; cnt++) { 236 if (nv_cmd & BIT_31) 237 qla2x00_nv_write(ha, NVR_DATA_OUT); 238 else 239 qla2x00_nv_write(ha, 0); 240 nv_cmd <<= 1; 241 } 242 243 /* Read data from NVRAM. */ 244 for (cnt = 0; cnt < 16; cnt++) { 245 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); 246 RD_REG_WORD(®->nvram); /* PCI Posting. */ 247 NVRAM_DELAY(); 248 data <<= 1; 249 reg_data = RD_REG_WORD(®->nvram); 250 if (reg_data & NVR_DATA_IN) 251 data |= BIT_0; 252 WRT_REG_WORD(®->nvram, NVR_SELECT); 253 RD_REG_WORD(®->nvram); /* PCI Posting. */ 254 NVRAM_DELAY(); 255 } 256 257 /* Deselect chip. */ 258 WRT_REG_WORD(®->nvram, NVR_DESELECT); 259 RD_REG_WORD(®->nvram); /* PCI Posting. */ 260 NVRAM_DELAY(); 261 262 return (data); 263} 264 265/** 266 * qla2x00_nv_write() - Clean NVRAM operations. 267 * @ha: HA context 268 */ 269static void 270qla2x00_nv_deselect(scsi_qla_host_t *ha) 271{ 272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 273 274 WRT_REG_WORD(®->nvram, NVR_DESELECT); 275 RD_REG_WORD(®->nvram); /* PCI Posting. */ 276 NVRAM_DELAY(); 277} 278 279/** 280 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 281 * @ha: HA context 282 * @data: Serial interface selector 283 */ 284static void 285qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data) 286{ 287 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 288 289 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 290 RD_REG_WORD(®->nvram); /* PCI Posting. */ 291 NVRAM_DELAY(); 292 WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK | 293 NVR_WRT_ENABLE); 294 RD_REG_WORD(®->nvram); /* PCI Posting. */ 295 NVRAM_DELAY(); 296 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 297 RD_REG_WORD(®->nvram); /* PCI Posting. */ 298 NVRAM_DELAY(); 299} 300 301/** 302 * qla2x00_clear_nvram_protection() - 303 * @ha: HA context 304 */ 305static int 306qla2x00_clear_nvram_protection(scsi_qla_host_t *ha) 307{ 308 int ret, stat; 309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 310 uint32_t word, wait_cnt; 311 uint16_t wprot, wprot_old; 312 313 /* Clear NVRAM write protection. */ 314 ret = QLA_FUNCTION_FAILED; 315 316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 318 __constant_cpu_to_le16(0x1234), 100000); 319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 320 if (stat != QLA_SUCCESS || wprot != 0x1234) { 321 /* Write enable. */ 322 qla2x00_nv_write(ha, NVR_DATA_OUT); 323 qla2x00_nv_write(ha, 0); 324 qla2x00_nv_write(ha, 0); 325 for (word = 0; word < 8; word++) 326 qla2x00_nv_write(ha, NVR_DATA_OUT); 327 328 qla2x00_nv_deselect(ha); 329 330 /* Enable protection register. */ 331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 332 qla2x00_nv_write(ha, NVR_PR_ENABLE); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 for (word = 0; word < 8; word++) 335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 336 337 qla2x00_nv_deselect(ha); 338 339 /* Clear protection register (ffff is cleared). */ 340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 for (word = 0; word < 8; word++) 344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 345 346 qla2x00_nv_deselect(ha); 347 348 /* Wait for NVRAM to become ready. */ 349 WRT_REG_WORD(®->nvram, NVR_SELECT); 350 RD_REG_WORD(®->nvram); /* PCI Posting. */ 351 wait_cnt = NVR_WAIT_CNT; 352 do { 353 if (!--wait_cnt) { 354 DEBUG9_10(printk("%s(%ld): NVRAM didn't go " 355 "ready...\n", __func__, 356 ha->host_no)); 357 break; 358 } 359 NVRAM_DELAY(); 360 word = RD_REG_WORD(®->nvram); 361 } while ((word & NVR_DATA_IN) == 0); 362 363 if (wait_cnt) 364 ret = QLA_SUCCESS; 365 } else 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 367 368 return ret; 369} 370 371static void 372qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat) 373{ 374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 375 uint32_t word, wait_cnt; 376 377 if (stat != QLA_SUCCESS) 378 return; 379 380 /* Set NVRAM write protection. */ 381 /* Write enable. */ 382 qla2x00_nv_write(ha, NVR_DATA_OUT); 383 qla2x00_nv_write(ha, 0); 384 qla2x00_nv_write(ha, 0); 385 for (word = 0; word < 8; word++) 386 qla2x00_nv_write(ha, NVR_DATA_OUT); 387 388 qla2x00_nv_deselect(ha); 389 390 /* Enable protection register. */ 391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 392 qla2x00_nv_write(ha, NVR_PR_ENABLE); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 for (word = 0; word < 8; word++) 395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 396 397 qla2x00_nv_deselect(ha); 398 399 /* Enable protection register. */ 400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 401 qla2x00_nv_write(ha, NVR_PR_ENABLE); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 403 for (word = 0; word < 8; word++) 404 qla2x00_nv_write(ha, NVR_PR_ENABLE); 405 406 qla2x00_nv_deselect(ha); 407 408 /* Wait for NVRAM to become ready. */ 409 WRT_REG_WORD(®->nvram, NVR_SELECT); 410 RD_REG_WORD(®->nvram); /* PCI Posting. */ 411 wait_cnt = NVR_WAIT_CNT; 412 do { 413 if (!--wait_cnt) { 414 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", 415 __func__, ha->host_no)); 416 break; 417 } 418 NVRAM_DELAY(); 419 word = RD_REG_WORD(®->nvram); 420 } while ((word & NVR_DATA_IN) == 0); 421} 422 423 424/*****************************************************************************/ 425/* Flash Manipulation Routines */ 426/*****************************************************************************/ 427 428static inline uint32_t 429flash_conf_to_access_addr(uint32_t faddr) 430{ 431 return FARX_ACCESS_FLASH_CONF | faddr; 432} 433 434static inline uint32_t 435flash_data_to_access_addr(uint32_t faddr) 436{ 437 return FARX_ACCESS_FLASH_DATA | faddr; 438} 439 440static inline uint32_t 441nvram_conf_to_access_addr(uint32_t naddr) 442{ 443 return FARX_ACCESS_NVRAM_CONF | naddr; 444} 445 446static inline uint32_t 447nvram_data_to_access_addr(uint32_t naddr) 448{ 449 return FARX_ACCESS_NVRAM_DATA | naddr; 450} 451 452static uint32_t 453qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr) 454{ 455 int rval; 456 uint32_t cnt, data; 457 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 458 459 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); 460 /* Wait for READ cycle to complete. */ 461 rval = QLA_SUCCESS; 462 for (cnt = 3000; 463 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && 464 rval == QLA_SUCCESS; cnt--) { 465 if (cnt) 466 udelay(10); 467 else 468 rval = QLA_FUNCTION_TIMEOUT; 469 cond_resched(); 470 } 471 472 /* TODO: What happens if we time out? */ 473 data = 0xDEADDEAD; 474 if (rval == QLA_SUCCESS) 475 data = RD_REG_DWORD(®->flash_data); 476 477 return data; 478} 479 480uint32_t * 481qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, 482 uint32_t dwords) 483{ 484 uint32_t i; 485 486 /* Dword reads to flash. */ 487 for (i = 0; i < dwords; i++, faddr++) 488 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 489 flash_data_to_access_addr(faddr))); 490 491 return dwptr; 492} 493 494static int 495qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data) 496{ 497 int rval; 498 uint32_t cnt; 499 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 500 501 WRT_REG_DWORD(®->flash_data, data); 502 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ 503 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); 504 /* Wait for Write cycle to complete. */ 505 rval = QLA_SUCCESS; 506 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && 507 rval == QLA_SUCCESS; cnt--) { 508 if (cnt) 509 udelay(10); 510 else 511 rval = QLA_FUNCTION_TIMEOUT; 512 cond_resched(); 513 } 514 return rval; 515} 516 517static void 518qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, 519 uint8_t *flash_id) 520{ 521 uint32_t ids; 522 523 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab)); 524 *man_id = LSB(ids); 525 *flash_id = MSB(ids); 526 527 /* Check if man_id and flash_id are valid. */ 528 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 529 /* Read information using 0x9f opcode 530 * Device ID, Mfg ID would be read in the format: 531 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 532 * Example: ATMEL 0x00 01 45 1F 533 * Extract MFG and Dev ID from last two bytes. 534 */ 535 ids = qla24xx_read_flash_dword(ha, 536 flash_data_to_access_addr(0xd009f)); 537 *man_id = LSB(ids); 538 *flash_id = MSB(ids); 539 } 540} 541 542static int 543qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, 544 uint32_t dwords) 545{ 546 int ret; 547 uint32_t liter; 548 uint32_t sec_mask, rest_addr, conf_addr, sec_end_mask; 549 uint32_t fdata, findex ; 550 uint8_t man_id, flash_id; 551 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 552 553 ret = QLA_SUCCESS; 554 555 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 556 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__, 557 ha->host_no, man_id, flash_id)); 558 559 sec_end_mask = 0; 560 conf_addr = flash_conf_to_access_addr(0x03d8); 561 switch (man_id) { 562 case 0xbf: /* STT flash. */ 563 rest_addr = 0x1fff; 564 sec_mask = 0x3e000; 565 if (flash_id == 0x80) 566 conf_addr = flash_conf_to_access_addr(0x0352); 567 break; 568 case 0x13: /* ST M25P80. */ 569 rest_addr = 0x3fff; 570 sec_mask = 0x3c000; 571 break; 572 case 0x1f: // Atmel 26DF081A 573 rest_addr = 0x0fff; 574 sec_mask = 0xff000; 575 sec_end_mask = 0x003ff; 576 conf_addr = flash_conf_to_access_addr(0x0320); 577 break; 578 default: 579 /* Default to 64 kb sector size. */ 580 rest_addr = 0x3fff; 581 sec_mask = 0x3c000; 582 break; 583 } 584 585 /* Enable flash write. */ 586 WRT_REG_DWORD(®->ctrl_status, 587 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 588 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 589 590 /* Disable flash write-protection. */ 591 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); 592 /* Some flash parts need an additional zero-write to clear bits.*/ 593 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); 594 595 do { /* Loop once to provide quick error exit. */ 596 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 597 if (man_id == 0x1f) { 598 findex = faddr << 2; 599 fdata = findex & sec_mask; 600 } else { 601 findex = faddr; 602 fdata = (findex & sec_mask) << 2; 603 } 604 605 /* Are we at the beginning of a sector? */ 606 if ((findex & rest_addr) == 0) { 607 /* 608 * Do sector unprotect at 4K boundry for Atmel 609 * part. 610 */ 611 if (man_id == 0x1f) 612 qla24xx_write_flash_dword(ha, 613 flash_conf_to_access_addr(0x0339), 614 (fdata & 0xff00) | ((fdata << 16) & 615 0xff0000) | ((fdata >> 16) & 0xff)); 616 ret = qla24xx_write_flash_dword(ha, conf_addr, 617 (fdata & 0xff00) |((fdata << 16) & 618 0xff0000) | ((fdata >> 16) & 0xff)); 619 if (ret != QLA_SUCCESS) { 620 DEBUG9(printk("%s(%ld) Unable to flash " 621 "sector: address=%x.\n", __func__, 622 ha->host_no, faddr)); 623 break; 624 } 625 } 626 ret = qla24xx_write_flash_dword(ha, 627 flash_data_to_access_addr(faddr), 628 cpu_to_le32(*dwptr)); 629 if (ret != QLA_SUCCESS) { 630 DEBUG9(printk("%s(%ld) Unable to program flash " 631 "address=%x data=%x.\n", __func__, 632 ha->host_no, faddr, *dwptr)); 633 break; 634 } 635 636 /* Do sector protect at 4K boundry for Atmel part. */ 637 if (man_id == 0x1f && 638 ((faddr & sec_end_mask) == 0x3ff)) 639 qla24xx_write_flash_dword(ha, 640 flash_conf_to_access_addr(0x0336), 641 (fdata & 0xff00) | ((fdata << 16) & 642 0xff0000) | ((fdata >> 16) & 0xff)); 643 } 644 } while (0); 645 646 /* Enable flash write-protection. */ 647 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c); 648 649 /* Disable flash write. */ 650 WRT_REG_DWORD(®->ctrl_status, 651 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 652 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 653 654 return ret; 655} 656 657uint8_t * 658qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 659 uint32_t bytes) 660{ 661 uint32_t i; 662 uint16_t *wptr; 663 664 /* Word reads to NVRAM via registers. */ 665 wptr = (uint16_t *)buf; 666 qla2x00_lock_nvram_access(ha); 667 for (i = 0; i < bytes >> 1; i++, naddr++) 668 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 669 naddr)); 670 qla2x00_unlock_nvram_access(ha); 671 672 return buf; 673} 674 675uint8_t * 676qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 677 uint32_t bytes) 678{ 679 uint32_t i; 680 uint32_t *dwptr; 681 682 /* Dword reads to flash. */ 683 dwptr = (uint32_t *)buf; 684 for (i = 0; i < bytes >> 2; i++, naddr++) 685 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 686 nvram_data_to_access_addr(naddr))); 687 688 return buf; 689} 690 691int 692qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 693 uint32_t bytes) 694{ 695 int ret, stat; 696 uint32_t i; 697 uint16_t *wptr; 698 699 ret = QLA_SUCCESS; 700 701 qla2x00_lock_nvram_access(ha); 702 703 /* Disable NVRAM write-protection. */ 704 stat = qla2x00_clear_nvram_protection(ha); 705 706 wptr = (uint16_t *)buf; 707 for (i = 0; i < bytes >> 1; i++, naddr++) { 708 qla2x00_write_nvram_word(ha, naddr, 709 cpu_to_le16(*wptr)); 710 wptr++; 711 } 712 713 /* Enable NVRAM write-protection. */ 714 qla2x00_set_nvram_protection(ha, stat); 715 716 qla2x00_unlock_nvram_access(ha); 717 718 return ret; 719} 720 721int 722qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 723 uint32_t bytes) 724{ 725 int ret; 726 uint32_t i; 727 uint32_t *dwptr; 728 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 729 730 ret = QLA_SUCCESS; 731 732 /* Enable flash write. */ 733 WRT_REG_DWORD(®->ctrl_status, 734 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 735 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 736 737 /* Disable NVRAM write-protection. */ 738 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 739 0); 740 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 741 0); 742 743 /* Dword writes to flash. */ 744 dwptr = (uint32_t *)buf; 745 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { 746 ret = qla24xx_write_flash_dword(ha, 747 nvram_data_to_access_addr(naddr), 748 cpu_to_le32(*dwptr)); 749 if (ret != QLA_SUCCESS) { 750 DEBUG9(printk("%s(%ld) Unable to program " 751 "nvram address=%x data=%x.\n", __func__, 752 ha->host_no, naddr, *dwptr)); 753 break; 754 } 755 } 756 757 /* Enable NVRAM write-protection. */ 758 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 759 0x8c); 760 761 /* Disable flash write. */ 762 WRT_REG_DWORD(®->ctrl_status, 763 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 764 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 765 766 return ret; 767} 768 769 770static inline void 771qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) 772{ 773 if (IS_QLA2322(ha)) { 774 /* Flip all colors. */ 775 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 776 /* Turn off. */ 777 ha->beacon_color_state = 0; 778 *pflags = GPIO_LED_ALL_OFF; 779 } else { 780 /* Turn on. */ 781 ha->beacon_color_state = QLA_LED_ALL_ON; 782 *pflags = GPIO_LED_RGA_ON; 783 } 784 } else { 785 /* Flip green led only. */ 786 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 787 /* Turn off. */ 788 ha->beacon_color_state = 0; 789 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 790 } else { 791 /* Turn on. */ 792 ha->beacon_color_state = QLA_LED_GRN_ON; 793 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 794 } 795 } 796} 797 798void 799qla2x00_beacon_blink(struct scsi_qla_host *ha) 800{ 801 uint16_t gpio_enable; 802 uint16_t gpio_data; 803 uint16_t led_color = 0; 804 unsigned long flags; 805 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 806 807 if (ha->pio_address) 808 reg = (struct device_reg_2xxx __iomem *)ha->pio_address; 809 810 spin_lock_irqsave(&ha->hardware_lock, flags); 811 812 /* Save the Original GPIOE. */ 813 if (ha->pio_address) { 814 gpio_enable = RD_REG_WORD_PIO(®->gpioe); 815 gpio_data = RD_REG_WORD_PIO(®->gpiod); 816 } else { 817 gpio_enable = RD_REG_WORD(®->gpioe); 818 gpio_data = RD_REG_WORD(®->gpiod); 819 } 820 821 /* Set the modified gpio_enable values */ 822 gpio_enable |= GPIO_LED_MASK; 823 824 if (ha->pio_address) { 825 WRT_REG_WORD_PIO(®->gpioe, gpio_enable); 826 } else { 827 WRT_REG_WORD(®->gpioe, gpio_enable); 828 RD_REG_WORD(®->gpioe); 829 } 830 831 qla2x00_flip_colors(ha, &led_color); 832 833 /* Clear out any previously set LED color. */ 834 gpio_data &= ~GPIO_LED_MASK; 835 836 /* Set the new input LED color to GPIOD. */ 837 gpio_data |= led_color; 838 839 /* Set the modified gpio_data values */ 840 if (ha->pio_address) { 841 WRT_REG_WORD_PIO(®->gpiod, gpio_data); 842 } else { 843 WRT_REG_WORD(®->gpiod, gpio_data); 844 RD_REG_WORD(®->gpiod); 845 } 846 847 spin_unlock_irqrestore(&ha->hardware_lock, flags); 848} 849 850int 851qla2x00_beacon_on(struct scsi_qla_host *ha) 852{ 853 uint16_t gpio_enable; 854 uint16_t gpio_data; 855 unsigned long flags; 856 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 857 858 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 859 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 860 861 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 862 qla_printk(KERN_WARNING, ha, 863 "Unable to update fw options (beacon on).\n"); 864 return QLA_FUNCTION_FAILED; 865 } 866 867 if (ha->pio_address) 868 reg = (struct device_reg_2xxx __iomem *)ha->pio_address; 869 870 /* Turn off LEDs. */ 871 spin_lock_irqsave(&ha->hardware_lock, flags); 872 if (ha->pio_address) { 873 gpio_enable = RD_REG_WORD_PIO(®->gpioe); 874 gpio_data = RD_REG_WORD_PIO(®->gpiod); 875 } else { 876 gpio_enable = RD_REG_WORD(®->gpioe); 877 gpio_data = RD_REG_WORD(®->gpiod); 878 } 879 gpio_enable |= GPIO_LED_MASK; 880 881 /* Set the modified gpio_enable values. */ 882 if (ha->pio_address) { 883 WRT_REG_WORD_PIO(®->gpioe, gpio_enable); 884 } else { 885 WRT_REG_WORD(®->gpioe, gpio_enable); 886 RD_REG_WORD(®->gpioe); 887 } 888 889 /* Clear out previously set LED colour. */ 890 gpio_data &= ~GPIO_LED_MASK; 891 if (ha->pio_address) { 892 WRT_REG_WORD_PIO(®->gpiod, gpio_data); 893 } else { 894 WRT_REG_WORD(®->gpiod, gpio_data); 895 RD_REG_WORD(®->gpiod); 896 } 897 spin_unlock_irqrestore(&ha->hardware_lock, flags); 898 899 /* 900 * Let the per HBA timer kick off the blinking process based on 901 * the following flags. No need to do anything else now. 902 */ 903 ha->beacon_blink_led = 1; 904 ha->beacon_color_state = 0; 905 906 return QLA_SUCCESS; 907} 908 909int 910qla2x00_beacon_off(struct scsi_qla_host *ha) 911{ 912 int rval = QLA_SUCCESS; 913 914 ha->beacon_blink_led = 0; 915 916 /* Set the on flag so when it gets flipped it will be off. */ 917 if (IS_QLA2322(ha)) 918 ha->beacon_color_state = QLA_LED_ALL_ON; 919 else 920 ha->beacon_color_state = QLA_LED_GRN_ON; 921 922 ha->isp_ops.beacon_blink(ha); /* This turns green LED off */ 923 924 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 925 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 926 927 rval = qla2x00_set_fw_options(ha, ha->fw_options); 928 if (rval != QLA_SUCCESS) 929 qla_printk(KERN_WARNING, ha, 930 "Unable to update fw options (beacon off).\n"); 931 return rval; 932} 933 934 935static inline void 936qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) 937{ 938 /* Flip all colors. */ 939 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 940 /* Turn off. */ 941 ha->beacon_color_state = 0; 942 *pflags = 0; 943 } else { 944 /* Turn on. */ 945 ha->beacon_color_state = QLA_LED_ALL_ON; 946 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 947 } 948} 949 950void 951qla24xx_beacon_blink(struct scsi_qla_host *ha) 952{ 953 uint16_t led_color = 0; 954 uint32_t gpio_data; 955 unsigned long flags; 956 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 957 958 /* Save the Original GPIOD. */ 959 spin_lock_irqsave(&ha->hardware_lock, flags); 960 gpio_data = RD_REG_DWORD(®->gpiod); 961 962 /* Enable the gpio_data reg for update. */ 963 gpio_data |= GPDX_LED_UPDATE_MASK; 964 965 WRT_REG_DWORD(®->gpiod, gpio_data); 966 gpio_data = RD_REG_DWORD(®->gpiod); 967 968 /* Set the color bits. */ 969 qla24xx_flip_colors(ha, &led_color); 970 971 /* Clear out any previously set LED color. */ 972 gpio_data &= ~GPDX_LED_COLOR_MASK; 973 974 /* Set the new input LED color to GPIOD. */ 975 gpio_data |= led_color; 976 977 /* Set the modified gpio_data values. */ 978 WRT_REG_DWORD(®->gpiod, gpio_data); 979 gpio_data = RD_REG_DWORD(®->gpiod); 980 spin_unlock_irqrestore(&ha->hardware_lock, flags); 981} 982 983int 984qla24xx_beacon_on(struct scsi_qla_host *ha) 985{ 986 uint32_t gpio_data; 987 unsigned long flags; 988 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 989 990 if (ha->beacon_blink_led == 0) { 991 /* Enable firmware for update */ 992 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 993 994 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) 995 return QLA_FUNCTION_FAILED; 996 997 if (qla2x00_get_fw_options(ha, ha->fw_options) != 998 QLA_SUCCESS) { 999 qla_printk(KERN_WARNING, ha, 1000 "Unable to update fw options (beacon on).\n"); 1001 return QLA_FUNCTION_FAILED; 1002 } 1003 1004 spin_lock_irqsave(&ha->hardware_lock, flags); 1005 gpio_data = RD_REG_DWORD(®->gpiod); 1006 1007 /* Enable the gpio_data reg for update. */ 1008 gpio_data |= GPDX_LED_UPDATE_MASK; 1009 WRT_REG_DWORD(®->gpiod, gpio_data); 1010 RD_REG_DWORD(®->gpiod); 1011 1012 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1013 } 1014 1015 /* So all colors blink together. */ 1016 ha->beacon_color_state = 0; 1017 1018 /* Let the per HBA timer kick off the blinking process. */ 1019 ha->beacon_blink_led = 1; 1020 1021 return QLA_SUCCESS; 1022} 1023 1024int 1025qla24xx_beacon_off(struct scsi_qla_host *ha) 1026{ 1027 uint32_t gpio_data; 1028 unsigned long flags; 1029 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1030 1031 ha->beacon_blink_led = 0; 1032 ha->beacon_color_state = QLA_LED_ALL_ON; 1033 1034 ha->isp_ops.beacon_blink(ha); /* Will flip to all off. */ 1035 1036 /* Give control back to firmware. */ 1037 spin_lock_irqsave(&ha->hardware_lock, flags); 1038 gpio_data = RD_REG_DWORD(®->gpiod); 1039 1040 /* Disable the gpio_data reg for update. */ 1041 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1042 WRT_REG_DWORD(®->gpiod, gpio_data); 1043 RD_REG_DWORD(®->gpiod); 1044 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1045 1046 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1047 1048 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 1049 qla_printk(KERN_WARNING, ha, 1050 "Unable to update fw options (beacon off).\n"); 1051 return QLA_FUNCTION_FAILED; 1052 } 1053 1054 if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 1055 qla_printk(KERN_WARNING, ha, 1056 "Unable to get fw options (beacon off).\n"); 1057 return QLA_FUNCTION_FAILED; 1058 } 1059 1060 return QLA_SUCCESS; 1061} 1062 1063 1064/* 1065 * Flash support routines 1066 */ 1067 1068/** 1069 * qla2x00_flash_enable() - Setup flash for reading and writing. 1070 * @ha: HA context 1071 */ 1072static void 1073qla2x00_flash_enable(scsi_qla_host_t *ha) 1074{ 1075 uint16_t data; 1076 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1077 1078 data = RD_REG_WORD(®->ctrl_status); 1079 data |= CSR_FLASH_ENABLE; 1080 WRT_REG_WORD(®->ctrl_status, data); 1081 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1082} 1083 1084/** 1085 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1086 * @ha: HA context 1087 */ 1088static void 1089qla2x00_flash_disable(scsi_qla_host_t *ha) 1090{ 1091 uint16_t data; 1092 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1093 1094 data = RD_REG_WORD(®->ctrl_status); 1095 data &= ~(CSR_FLASH_ENABLE); 1096 WRT_REG_WORD(®->ctrl_status, data); 1097 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1098} 1099 1100/** 1101 * qla2x00_read_flash_byte() - Reads a byte from flash 1102 * @ha: HA context 1103 * @addr: Address in flash to read 1104 * 1105 * A word is read from the chip, but, only the lower byte is valid. 1106 * 1107 * Returns the byte read from flash @addr. 1108 */ 1109static uint8_t 1110qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr) 1111{ 1112 uint16_t data; 1113 uint16_t bank_select; 1114 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1115 1116 bank_select = RD_REG_WORD(®->ctrl_status); 1117 1118 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1119 /* Specify 64K address range: */ 1120 /* clear out Module Select and Flash Address bits [19:16]. */ 1121 bank_select &= ~0xf8; 1122 bank_select |= addr >> 12 & 0xf0; 1123 bank_select |= CSR_FLASH_64K_BANK; 1124 WRT_REG_WORD(®->ctrl_status, bank_select); 1125 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1126 1127 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1128 data = RD_REG_WORD(®->flash_data); 1129 1130 return (uint8_t)data; 1131 } 1132 1133 /* Setup bit 16 of flash address. */ 1134 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1135 bank_select |= CSR_FLASH_64K_BANK; 1136 WRT_REG_WORD(®->ctrl_status, bank_select); 1137 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1138 } else if (((addr & BIT_16) == 0) && 1139 (bank_select & CSR_FLASH_64K_BANK)) { 1140 bank_select &= ~(CSR_FLASH_64K_BANK); 1141 WRT_REG_WORD(®->ctrl_status, bank_select); 1142 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1143 } 1144 1145 /* Always perform IO mapped accesses to the FLASH registers. */ 1146 if (ha->pio_address) { 1147 uint16_t data2; 1148 1149 reg = (struct device_reg_2xxx __iomem *)ha->pio_address; 1150 WRT_REG_WORD_PIO(®->flash_address, (uint16_t)addr); 1151 do { 1152 data = RD_REG_WORD_PIO(®->flash_data); 1153 barrier(); 1154 cpu_relax(); 1155 data2 = RD_REG_WORD_PIO(®->flash_data); 1156 } while (data != data2); 1157 } else { 1158 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1159 data = qla2x00_debounce_register(®->flash_data); 1160 } 1161 1162 return (uint8_t)data; 1163} 1164 1165/** 1166 * qla2x00_write_flash_byte() - Write a byte to flash 1167 * @ha: HA context 1168 * @addr: Address in flash to write 1169 * @data: Data to write 1170 */ 1171static void 1172qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) 1173{ 1174 uint16_t bank_select; 1175 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1176 1177 bank_select = RD_REG_WORD(®->ctrl_status); 1178 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1179 /* Specify 64K address range: */ 1180 /* clear out Module Select and Flash Address bits [19:16]. */ 1181 bank_select &= ~0xf8; 1182 bank_select |= addr >> 12 & 0xf0; 1183 bank_select |= CSR_FLASH_64K_BANK; 1184 WRT_REG_WORD(®->ctrl_status, bank_select); 1185 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1186 1187 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1188 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1189 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1190 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1191 1192 return; 1193 } 1194 1195 /* Setup bit 16 of flash address. */ 1196 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1197 bank_select |= CSR_FLASH_64K_BANK; 1198 WRT_REG_WORD(®->ctrl_status, bank_select); 1199 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1200 } else if (((addr & BIT_16) == 0) && 1201 (bank_select & CSR_FLASH_64K_BANK)) { 1202 bank_select &= ~(CSR_FLASH_64K_BANK); 1203 WRT_REG_WORD(®->ctrl_status, bank_select); 1204 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1205 } 1206 1207 /* Always perform IO mapped accesses to the FLASH registers. */ 1208 if (ha->pio_address) { 1209 reg = (struct device_reg_2xxx __iomem *)ha->pio_address; 1210 WRT_REG_WORD_PIO(®->flash_address, (uint16_t)addr); 1211 WRT_REG_WORD_PIO(®->flash_data, (uint16_t)data); 1212 } else { 1213 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1214 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1215 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1216 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1217 } 1218} 1219 1220/** 1221 * qla2x00_poll_flash() - Polls flash for completion. 1222 * @ha: HA context 1223 * @addr: Address in flash to poll 1224 * @poll_data: Data to be polled 1225 * @man_id: Flash manufacturer ID 1226 * @flash_id: Flash ID 1227 * 1228 * This function polls the device until bit 7 of what is read matches data 1229 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 1230 * out (a fatal error). The flash book recommeds reading bit 7 again after 1231 * reading bit 5 as a 1. 1232 * 1233 * Returns 0 on success, else non-zero. 1234 */ 1235static int 1236qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data, 1237 uint8_t man_id, uint8_t flash_id) 1238{ 1239 int status; 1240 uint8_t flash_data; 1241 uint32_t cnt; 1242 1243 status = 1; 1244 1245 /* Wait for 30 seconds for command to finish. */ 1246 poll_data &= BIT_7; 1247 for (cnt = 3000000; cnt; cnt--) { 1248 flash_data = qla2x00_read_flash_byte(ha, addr); 1249 if ((flash_data & BIT_7) == poll_data) { 1250 status = 0; 1251 break; 1252 } 1253 1254 if (man_id != 0x40 && man_id != 0xda) { 1255 if ((flash_data & BIT_5) && cnt > 2) 1256 cnt = 2; 1257 } 1258 udelay(10); 1259 barrier(); 1260 cond_resched(); 1261 } 1262 return status; 1263} 1264 1265/** 1266 * qla2x00_program_flash_address() - Programs a flash address 1267 * @ha: HA context 1268 * @addr: Address in flash to program 1269 * @data: Data to be written in flash 1270 * @man_id: Flash manufacturer ID 1271 * @flash_id: Flash ID 1272 * 1273 * Returns 0 on success, else non-zero. 1274 */ 1275static int 1276qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data, 1277 uint8_t man_id, uint8_t flash_id) 1278{ 1279 /* Write Program Command Sequence. */ 1280 if (IS_OEM_001(ha)) { 1281 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1282 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1283 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 1284 qla2x00_write_flash_byte(ha, addr, data); 1285 } else { 1286 if (man_id == 0xda && flash_id == 0xc1) { 1287 qla2x00_write_flash_byte(ha, addr, data); 1288 if (addr & 0x7e) 1289 return 0; 1290 } else { 1291 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1292 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1293 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 1294 qla2x00_write_flash_byte(ha, addr, data); 1295 } 1296 } 1297 1298 udelay(150); 1299 1300 /* Wait for write to complete. */ 1301 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 1302} 1303 1304/** 1305 * qla2x00_erase_flash() - Erase the flash. 1306 * @ha: HA context 1307 * @man_id: Flash manufacturer ID 1308 * @flash_id: Flash ID 1309 * 1310 * Returns 0 on success, else non-zero. 1311 */ 1312static int 1313qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id) 1314{ 1315 /* Individual Sector Erase Command Sequence */ 1316 if (IS_OEM_001(ha)) { 1317 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1318 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1319 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 1320 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1321 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1322 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 1323 } else { 1324 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1325 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1326 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1327 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1328 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1329 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 1330 } 1331 1332 udelay(150); 1333 1334 /* Wait for erase to complete. */ 1335 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 1336} 1337 1338/** 1339 * qla2x00_erase_flash_sector() - Erase a flash sector. 1340 * @ha: HA context 1341 * @addr: Flash sector to erase 1342 * @sec_mask: Sector address mask 1343 * @man_id: Flash manufacturer ID 1344 * @flash_id: Flash ID 1345 * 1346 * Returns 0 on success, else non-zero. 1347 */ 1348static int 1349qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr, 1350 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 1351{ 1352 /* Individual Sector Erase Command Sequence */ 1353 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1354 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1355 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1356 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1357 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1358 if (man_id == 0x1f && flash_id == 0x13) 1359 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 1360 else 1361 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 1362 1363 udelay(150); 1364 1365 /* Wait for erase to complete. */ 1366 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 1367} 1368 1369/** 1370 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 1371 * @man_id: Flash manufacturer ID 1372 * @flash_id: Flash ID 1373 */ 1374static void 1375qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, 1376 uint8_t *flash_id) 1377{ 1378 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1379 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1380 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 1381 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 1382 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 1383 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1384 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1385 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 1386} 1387 1388static void 1389qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr, 1390 uint32_t length) 1391{ 1392 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1393 uint32_t midpoint, ilength; 1394 uint8_t data; 1395 1396 midpoint = length / 2; 1397 1398 WRT_REG_WORD(®->nvram, 0); 1399 RD_REG_WORD(®->nvram); 1400 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 1401 if (ilength == midpoint) { 1402 WRT_REG_WORD(®->nvram, NVR_SELECT); 1403 RD_REG_WORD(®->nvram); 1404 } 1405 data = qla2x00_read_flash_byte(ha, saddr); 1406 if (saddr % 100) 1407 udelay(10); 1408 *tmp_buf = data; 1409 cond_resched(); 1410 } 1411} 1412 1413static inline void 1414qla2x00_suspend_hba(struct scsi_qla_host *ha) 1415{ 1416 int cnt; 1417 unsigned long flags; 1418 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1419 1420 /* Suspend HBA. */ 1421 scsi_block_requests(ha->host); 1422 ha->isp_ops.disable_intrs(ha); 1423 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1424 1425 /* Pause RISC. */ 1426 spin_lock_irqsave(&ha->hardware_lock, flags); 1427 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 1428 RD_REG_WORD(®->hccr); 1429 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1430 for (cnt = 0; cnt < 30000; cnt++) { 1431 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 1432 break; 1433 udelay(100); 1434 } 1435 } else { 1436 udelay(10); 1437 } 1438 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1439} 1440 1441static inline void 1442qla2x00_resume_hba(struct scsi_qla_host *ha) 1443{ 1444 /* Resume HBA. */ 1445 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1446 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 1447 qla2xxx_wake_dpc(ha); 1448 qla2x00_wait_for_hba_online(ha); 1449 scsi_unblock_requests(ha->host); 1450} 1451 1452uint8_t * 1453qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1454 uint32_t offset, uint32_t length) 1455{ 1456 uint32_t addr, midpoint; 1457 uint8_t *data; 1458 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1459 1460 /* Suspend HBA. */ 1461 qla2x00_suspend_hba(ha); 1462 1463 /* Go with read. */ 1464 midpoint = ha->optrom_size / 2; 1465 1466 qla2x00_flash_enable(ha); 1467 WRT_REG_WORD(®->nvram, 0); 1468 RD_REG_WORD(®->nvram); /* PCI Posting. */ 1469 for (addr = offset, data = buf; addr < length; addr++, data++) { 1470 if (addr == midpoint) { 1471 WRT_REG_WORD(®->nvram, NVR_SELECT); 1472 RD_REG_WORD(®->nvram); /* PCI Posting. */ 1473 } 1474 1475 *data = qla2x00_read_flash_byte(ha, addr); 1476 } 1477 qla2x00_flash_disable(ha); 1478 1479 /* Resume HBA. */ 1480 qla2x00_resume_hba(ha); 1481 1482 return buf; 1483} 1484 1485int 1486qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1487 uint32_t offset, uint32_t length) 1488{ 1489 1490 int rval; 1491 uint8_t man_id, flash_id, sec_number, data; 1492 uint16_t wd; 1493 uint32_t addr, liter, sec_mask, rest_addr; 1494 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1495 1496 /* Suspend HBA. */ 1497 qla2x00_suspend_hba(ha); 1498 1499 rval = QLA_SUCCESS; 1500 sec_number = 0; 1501 1502 /* Reset ISP chip. */ 1503 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 1504 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 1505 1506 /* Go with write. */ 1507 qla2x00_flash_enable(ha); 1508 do { /* Loop once to provide quick error exit */ 1509 /* Structure of flash memory based on manufacturer */ 1510 if (IS_OEM_001(ha)) { 1511 /* OEM variant with special flash part. */ 1512 man_id = flash_id = 0; 1513 rest_addr = 0xffff; 1514 sec_mask = 0x10000; 1515 goto update_flash; 1516 } 1517 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 1518 switch (man_id) { 1519 case 0x20: /* ST flash. */ 1520 if (flash_id == 0xd2 || flash_id == 0xe3) { 1521 /* 1522 * ST m29w008at part - 64kb sector size with 1523 * 32kb,8kb,8kb,16kb sectors at memory address 1524 * 0xf0000. 1525 */ 1526 rest_addr = 0xffff; 1527 sec_mask = 0x10000; 1528 break; 1529 } 1530 /* 1531 * ST m29w010b part - 16kb sector size 1532 * Default to 16kb sectors 1533 */ 1534 rest_addr = 0x3fff; 1535 sec_mask = 0x1c000; 1536 break; 1537 case 0x40: /* Mostel flash. */ 1538 /* Mostel v29c51001 part - 512 byte sector size. */ 1539 rest_addr = 0x1ff; 1540 sec_mask = 0x1fe00; 1541 break; 1542 case 0xbf: /* SST flash. */ 1543 /* SST39sf10 part - 4kb sector size. */ 1544 rest_addr = 0xfff; 1545 sec_mask = 0x1f000; 1546 break; 1547 case 0xda: /* Winbond flash. */ 1548 /* Winbond W29EE011 part - 256 byte sector size. */ 1549 rest_addr = 0x7f; 1550 sec_mask = 0x1ff80; 1551 break; 1552 case 0xc2: /* Macronix flash. */ 1553 /* 64k sector size. */ 1554 if (flash_id == 0x38 || flash_id == 0x4f) { 1555 rest_addr = 0xffff; 1556 sec_mask = 0x10000; 1557 break; 1558 } 1559 /* Fall through... */ 1560 1561 case 0x1f: /* Atmel flash. */ 1562 /* 512k sector size. */ 1563 if (flash_id == 0x13) { 1564 rest_addr = 0x7fffffff; 1565 sec_mask = 0x80000000; 1566 break; 1567 } 1568 /* Fall through... */ 1569 1570 case 0x01: /* AMD flash. */ 1571 if (flash_id == 0x38 || flash_id == 0x40 || 1572 flash_id == 0x4f) { 1573 /* Am29LV081 part - 64kb sector size. */ 1574 /* Am29LV002BT part - 64kb sector size. */ 1575 rest_addr = 0xffff; 1576 sec_mask = 0x10000; 1577 break; 1578 } else if (flash_id == 0x3e) { 1579 /* 1580 * Am29LV008b part - 64kb sector size with 1581 * 32kb,8kb,8kb,16kb sector at memory address 1582 * h0xf0000. 1583 */ 1584 rest_addr = 0xffff; 1585 sec_mask = 0x10000; 1586 break; 1587 } else if (flash_id == 0x20 || flash_id == 0x6e) { 1588 /* 1589 * Am29LV010 part or AM29f010 - 16kb sector 1590 * size. 1591 */ 1592 rest_addr = 0x3fff; 1593 sec_mask = 0x1c000; 1594 break; 1595 } else if (flash_id == 0x6d) { 1596 /* Am29LV001 part - 8kb sector size. */ 1597 rest_addr = 0x1fff; 1598 sec_mask = 0x1e000; 1599 break; 1600 } 1601 default: 1602 /* Default to 16 kb sector size. */ 1603 rest_addr = 0x3fff; 1604 sec_mask = 0x1c000; 1605 break; 1606 } 1607 1608update_flash: 1609 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1610 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 1611 rval = QLA_FUNCTION_FAILED; 1612 break; 1613 } 1614 } 1615 1616 for (addr = offset, liter = 0; liter < length; liter++, 1617 addr++) { 1618 data = buf[liter]; 1619 /* Are we at the beginning of a sector? */ 1620 if ((addr & rest_addr) == 0) { 1621 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1622 if (addr >= 0x10000UL) { 1623 if (((addr >> 12) & 0xf0) && 1624 ((man_id == 0x01 && 1625 flash_id == 0x3e) || 1626 (man_id == 0x20 && 1627 flash_id == 0xd2))) { 1628 sec_number++; 1629 if (sec_number == 1) { 1630 rest_addr = 1631 0x7fff; 1632 sec_mask = 1633 0x18000; 1634 } else if ( 1635 sec_number == 2 || 1636 sec_number == 3) { 1637 rest_addr = 1638 0x1fff; 1639 sec_mask = 1640 0x1e000; 1641 } else if ( 1642 sec_number == 4) { 1643 rest_addr = 1644 0x3fff; 1645 sec_mask = 1646 0x1c000; 1647 } 1648 } 1649 } 1650 } else if (addr == ha->optrom_size / 2) { 1651 WRT_REG_WORD(®->nvram, NVR_SELECT); 1652 RD_REG_WORD(®->nvram); 1653 } 1654 1655 if (flash_id == 0xda && man_id == 0xc1) { 1656 qla2x00_write_flash_byte(ha, 0x5555, 1657 0xaa); 1658 qla2x00_write_flash_byte(ha, 0x2aaa, 1659 0x55); 1660 qla2x00_write_flash_byte(ha, 0x5555, 1661 0xa0); 1662 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 1663 /* Then erase it */ 1664 if (qla2x00_erase_flash_sector(ha, 1665 addr, sec_mask, man_id, 1666 flash_id)) { 1667 rval = QLA_FUNCTION_FAILED; 1668 break; 1669 } 1670 if (man_id == 0x01 && flash_id == 0x6d) 1671 sec_number++; 1672 } 1673 } 1674 1675 if (man_id == 0x01 && flash_id == 0x6d) { 1676 if (sec_number == 1 && 1677 addr == (rest_addr - 1)) { 1678 rest_addr = 0x0fff; 1679 sec_mask = 0x1f000; 1680 } else if (sec_number == 3 && (addr & 0x7ffe)) { 1681 rest_addr = 0x3fff; 1682 sec_mask = 0x1c000; 1683 } 1684 } 1685 1686 if (qla2x00_program_flash_address(ha, addr, data, 1687 man_id, flash_id)) { 1688 rval = QLA_FUNCTION_FAILED; 1689 break; 1690 } 1691 cond_resched(); 1692 } 1693 } while (0); 1694 qla2x00_flash_disable(ha); 1695 1696 /* Resume HBA. */ 1697 qla2x00_resume_hba(ha); 1698 1699 return rval; 1700} 1701 1702uint8_t * 1703qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1704 uint32_t offset, uint32_t length) 1705{ 1706 /* Suspend HBA. */ 1707 scsi_block_requests(ha->host); 1708 ha->isp_ops.disable_intrs(ha); 1709 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1710 1711 /* Go with read. */ 1712 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2); 1713 1714 /* Resume HBA. */ 1715 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1716 ha->isp_ops.enable_intrs(ha); 1717 scsi_unblock_requests(ha->host); 1718 1719 return buf; 1720} 1721 1722int 1723qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1724 uint32_t offset, uint32_t length) 1725{ 1726 int rval; 1727 1728 /* Suspend HBA. */ 1729 scsi_block_requests(ha->host); 1730 ha->isp_ops.disable_intrs(ha); 1731 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1732 1733 /* Go with write. */ 1734 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2, 1735 length >> 2); 1736 1737 /* Resume HBA -- RISC reset needed. */ 1738 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1739 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 1740 qla2xxx_wake_dpc(ha); 1741 qla2x00_wait_for_hba_online(ha); 1742 scsi_unblock_requests(ha->host); 1743 1744 return rval; 1745} 1746 1747/** 1748 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 1749 * @ha: HA context 1750 * @pcids: Pointer to the FCODE PCI data structure 1751 * 1752 * The process of retrieving the FCODE version information is at best 1753 * described as interesting. 1754 * 1755 * Within the first 100h bytes of the image an ASCII string is present 1756 * which contains several pieces of information including the FCODE 1757 * version. Unfortunately it seems the only reliable way to retrieve 1758 * the version is by scanning for another sentinel within the string, 1759 * the FCODE build date: 1760 * 1761 * ... 2.00.02 10/17/02 ... 1762 * 1763 * Returns QLA_SUCCESS on successful retrieval of version. 1764 */ 1765static void 1766qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids) 1767{ 1768 int ret = QLA_FUNCTION_FAILED; 1769 uint32_t istart, iend, iter, vend; 1770 uint8_t do_next, rbyte, *vbyte; 1771 1772 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 1773 1774 /* Skip the PCI data structure. */ 1775 istart = pcids + 1776 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 1777 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 1778 iend = istart + 0x100; 1779 do { 1780 /* Scan for the sentinel date string...eeewww. */ 1781 do_next = 0; 1782 iter = istart; 1783 while ((iter < iend) && !do_next) { 1784 iter++; 1785 if (qla2x00_read_flash_byte(ha, iter) == '/') { 1786 if (qla2x00_read_flash_byte(ha, iter + 2) == 1787 '/') 1788 do_next++; 1789 else if (qla2x00_read_flash_byte(ha, 1790 iter + 3) == '/') 1791 do_next++; 1792 } 1793 } 1794 if (!do_next) 1795 break; 1796 1797 /* Backtrack to previous ' ' (space). */ 1798 do_next = 0; 1799 while ((iter > istart) && !do_next) { 1800 iter--; 1801 if (qla2x00_read_flash_byte(ha, iter) == ' ') 1802 do_next++; 1803 } 1804 if (!do_next) 1805 break; 1806 1807 /* 1808 * Mark end of version tag, and find previous ' ' (space) or 1809 * string length (recent FCODE images -- major hack ahead!!!). 1810 */ 1811 vend = iter - 1; 1812 do_next = 0; 1813 while ((iter > istart) && !do_next) { 1814 iter--; 1815 rbyte = qla2x00_read_flash_byte(ha, iter); 1816 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 1817 do_next++; 1818 } 1819 if (!do_next) 1820 break; 1821 1822 /* Mark beginning of version tag, and copy data. */ 1823 iter++; 1824 if ((vend - iter) && 1825 ((vend - iter) < sizeof(ha->fcode_revision))) { 1826 vbyte = ha->fcode_revision; 1827 while (iter <= vend) { 1828 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 1829 iter++; 1830 } 1831 ret = QLA_SUCCESS; 1832 } 1833 } while (0); 1834 1835 if (ret != QLA_SUCCESS) 1836 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 1837} 1838 1839int 1840qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf) 1841{ 1842 int ret = QLA_SUCCESS; 1843 uint8_t code_type, last_image; 1844 uint32_t pcihdr, pcids; 1845 uint8_t *dbyte; 1846 uint16_t *dcode; 1847 1848 if (!ha->pio_address || !mbuf) 1849 return QLA_FUNCTION_FAILED; 1850 1851 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 1852 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 1853 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 1854 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 1855 1856 qla2x00_flash_enable(ha); 1857 1858 /* Begin with first PCI expansion ROM header. */ 1859 pcihdr = 0; 1860 last_image = 1; 1861 do { 1862 /* Verify PCI expansion ROM header. */ 1863 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 1864 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 1865 /* No signature */ 1866 DEBUG2(printk("scsi(%ld): No matching ROM " 1867 "signature.\n", ha->host_no)); 1868 ret = QLA_FUNCTION_FAILED; 1869 break; 1870 } 1871 1872 /* Locate PCI data structure. */ 1873 pcids = pcihdr + 1874 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 1875 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 1876 1877 /* Validate signature of PCI data structure. */ 1878 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 1879 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 1880 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 1881 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 1882 /* Incorrect header. */ 1883 DEBUG2(printk("%s(): PCI data struct not found " 1884 "pcir_adr=%x.\n", __func__, pcids)); 1885 ret = QLA_FUNCTION_FAILED; 1886 break; 1887 } 1888 1889 /* Read version */ 1890 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 1891 switch (code_type) { 1892 case ROM_CODE_TYPE_BIOS: 1893 /* Intel x86, PC-AT compatible. */ 1894 ha->bios_revision[0] = 1895 qla2x00_read_flash_byte(ha, pcids + 0x12); 1896 ha->bios_revision[1] = 1897 qla2x00_read_flash_byte(ha, pcids + 0x13); 1898 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, 1899 ha->bios_revision[1], ha->bios_revision[0])); 1900 break; 1901 case ROM_CODE_TYPE_FCODE: 1902 /* Open Firmware standard for PCI (FCode). */ 1903 /* Eeeewww... */ 1904 qla2x00_get_fcode_version(ha, pcids); 1905 break; 1906 case ROM_CODE_TYPE_EFI: 1907 /* Extensible Firmware Interface (EFI). */ 1908 ha->efi_revision[0] = 1909 qla2x00_read_flash_byte(ha, pcids + 0x12); 1910 ha->efi_revision[1] = 1911 qla2x00_read_flash_byte(ha, pcids + 0x13); 1912 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, 1913 ha->efi_revision[1], ha->efi_revision[0])); 1914 break; 1915 default: 1916 DEBUG2(printk("%s(): Unrecognized code type %x at " 1917 "pcids %x.\n", __func__, code_type, pcids)); 1918 break; 1919 } 1920 1921 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 1922 1923 /* Locate next PCI expansion ROM. */ 1924 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 1925 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 1926 } while (!last_image); 1927 1928 if (IS_QLA2322(ha)) { 1929 /* Read firmware image information. */ 1930 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 1931 dbyte = mbuf; 1932 memset(dbyte, 0, 8); 1933 dcode = (uint16_t *)dbyte; 1934 1935 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10, 1936 8); 1937 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n", 1938 __func__, ha->host_no)); 1939 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8)); 1940 1941 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 1942 dcode[2] == 0xffff && dcode[3] == 0xffff) || 1943 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 1944 dcode[3] == 0)) { 1945 DEBUG2(printk("%s(): Unrecognized fw revision at " 1946 "%x.\n", __func__, FA_RISC_CODE_ADDR * 4)); 1947 } else { 1948 /* values are in big endian */ 1949 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 1950 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 1951 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 1952 } 1953 } 1954 1955 qla2x00_flash_disable(ha); 1956 1957 return ret; 1958} 1959 1960int 1961qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf) 1962{ 1963 int ret = QLA_SUCCESS; 1964 uint32_t pcihdr, pcids; 1965 uint32_t *dcode; 1966 uint8_t *bcode; 1967 uint8_t code_type, last_image; 1968 int i; 1969 1970 if (!mbuf) 1971 return QLA_FUNCTION_FAILED; 1972 1973 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 1974 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 1975 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 1976 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 1977 1978 dcode = mbuf; 1979 1980 /* Begin with first PCI expansion ROM header. */ 1981 pcihdr = 0; 1982 last_image = 1; 1983 do { 1984 /* Verify PCI expansion ROM header. */ 1985 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20); 1986 bcode = mbuf + (pcihdr % 4); 1987 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { 1988 /* No signature */ 1989 DEBUG2(printk("scsi(%ld): No matching ROM " 1990 "signature.\n", ha->host_no)); 1991 ret = QLA_FUNCTION_FAILED; 1992 break; 1993 } 1994 1995 /* Locate PCI data structure. */ 1996 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 1997 1998 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20); 1999 bcode = mbuf + (pcihdr % 4); 2000 2001 /* Validate signature of PCI data structure. */ 2002 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 2003 bcode[0x2] != 'I' || bcode[0x3] != 'R') { 2004 /* Incorrect header. */ 2005 DEBUG2(printk("%s(): PCI data struct not found " 2006 "pcir_adr=%x.\n", __func__, pcids)); 2007 ret = QLA_FUNCTION_FAILED; 2008 break; 2009 } 2010 2011 /* Read version */ 2012 code_type = bcode[0x14]; 2013 switch (code_type) { 2014 case ROM_CODE_TYPE_BIOS: 2015 /* Intel x86, PC-AT compatible. */ 2016 ha->bios_revision[0] = bcode[0x12]; 2017 ha->bios_revision[1] = bcode[0x13]; 2018 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, 2019 ha->bios_revision[1], ha->bios_revision[0])); 2020 break; 2021 case ROM_CODE_TYPE_FCODE: 2022 /* Open Firmware standard for PCI (FCode). */ 2023 ha->fcode_revision[0] = bcode[0x12]; 2024 ha->fcode_revision[1] = bcode[0x13]; 2025 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__, 2026 ha->fcode_revision[1], ha->fcode_revision[0])); 2027 break; 2028 case ROM_CODE_TYPE_EFI: 2029 /* Extensible Firmware Interface (EFI). */ 2030 ha->efi_revision[0] = bcode[0x12]; 2031 ha->efi_revision[1] = bcode[0x13]; 2032 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, 2033 ha->efi_revision[1], ha->efi_revision[0])); 2034 break; 2035 default: 2036 DEBUG2(printk("%s(): Unrecognized code type %x at " 2037 "pcids %x.\n", __func__, code_type, pcids)); 2038 break; 2039 } 2040 2041 last_image = bcode[0x15] & BIT_7; 2042 2043 /* Locate next PCI expansion ROM. */ 2044 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 2045 } while (!last_image); 2046 2047 /* Read firmware image information. */ 2048 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2049 dcode = mbuf; 2050 2051 qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4); 2052 for (i = 0; i < 4; i++) 2053 dcode[i] = be32_to_cpu(dcode[i]); 2054 2055 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 2056 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 2057 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2058 dcode[3] == 0)) { 2059 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n", 2060 __func__, FA_RISC_CODE_ADDR)); 2061 } else { 2062 ha->fw_revision[0] = dcode[0]; 2063 ha->fw_revision[1] = dcode[1]; 2064 ha->fw_revision[2] = dcode[2]; 2065 ha->fw_revision[3] = dcode[3]; 2066 } 2067 2068 return ret; 2069} 2070