1/* 2 * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver 3 * Basic data header 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14*/ 15 16#ifndef _NSP32_H 17#define _NSP32_H 18 19#include <linux/version.h> 20//#define NSP32_DEBUG 9 21 22/* 23 * VENDOR/DEVICE ID 24 */ 25#define PCI_VENDOR_ID_IODATA 0x10fc 26#define PCI_VENDOR_ID_WORKBIT 0x1145 27 28#define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005 29#define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007 30#define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007 31#define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010 32#define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011 33#define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012 34#define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013 35#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015 36#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009 37 38/* 39 * MODEL 40 */ 41enum { 42 MODEL_IODATA = 0, 43 MODEL_KME = 1, 44 MODEL_WORKBIT = 2, 45 MODEL_LOGITEC = 3, 46 MODEL_PCI_WORKBIT = 4, 47 MODEL_PCI_LOGITEC = 5, 48 MODEL_PCI_MELCO = 6, 49}; 50 51static char * nsp32_model[] = { 52 "I-O DATA CBSC-II CardBus card", 53 "KME SCSI CardBus card", 54 "Workbit duo SCSI CardBus card", 55 "Logitec CardBus card with external ROM", 56 "Workbit / I-O DATA PCI card", 57 "Logitec PCI card with external ROM", 58 "Melco CardBus/PCI card with external ROM", 59}; 60 61 62/* 63 * SCSI Generic Definitions 64 */ 65#define EXTENDED_SDTR_LEN 0x03 66 67/* Little Endian */ 68typedef u32 u32_le; 69typedef u16 u16_le; 70 71/* 72 * MACRO 73 */ 74#define BIT(x) (1UL << (x)) 75 76/* 77 * BASIC Definitions 78 */ 79#ifndef TRUE 80# define TRUE 1 81#endif 82#ifndef FALSE 83# define FALSE 0 84#endif 85#define ASSERT 1 86#define NEGATE 0 87 88 89/*******************/ 90/* normal register */ 91/*******************/ 92/* 93 * Don't access below register with Double Word: 94 * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0. 95 */ 96#define IRQ_CONTROL 0x00 /* BASE+00, W, W */ 97#define IRQ_STATUS 0x00 /* BASE+00, W, R */ 98# define IRQSTATUS_LATCHED_MSG BIT(0) 99# define IRQSTATUS_LATCHED_IO BIT(1) 100# define IRQSTATUS_LATCHED_CD BIT(2) 101# define IRQSTATUS_LATCHED_BUS_FREE BIT(3) 102# define IRQSTATUS_RESELECT_OCCUER BIT(4) 103# define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5) 104# define IRQSTATUS_SCSIRESET_IRQ BIT(6) 105# define IRQSTATUS_TIMER_IRQ BIT(7) 106# define IRQSTATUS_FIFO_SHLD_IRQ BIT(8) 107# define IRQSTATUS_PCI_IRQ BIT(9) 108# define IRQSTATUS_BMCNTERR_IRQ BIT(10) 109# define IRQSTATUS_AUTOSCSI_IRQ BIT(11) 110# define PCI_IRQ_MASK BIT(12) 111# define TIMER_IRQ_MASK BIT(13) 112# define FIFO_IRQ_MASK BIT(14) 113# define SCSI_IRQ_MASK BIT(15) 114# define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \ 115 TIMER_IRQ_MASK | \ 116 FIFO_IRQ_MASK | \ 117 SCSI_IRQ_MASK ) 118# define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \ 119 IRQSTATUS_PHASE_CHANGE_IRQ | \ 120 IRQSTATUS_SCSIRESET_IRQ | \ 121 IRQSTATUS_TIMER_IRQ | \ 122 IRQSTATUS_FIFO_SHLD_IRQ | \ 123 IRQSTATUS_PCI_IRQ | \ 124 IRQSTATUS_BMCNTERR_IRQ | \ 125 IRQSTATUS_AUTOSCSI_IRQ ) 126 127#define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */ 128#define TRANSFER_STATUS 0x02 /* BASE+02, W, R */ 129# define CB_MMIO_MODE BIT(0) 130# define CB_IO_MODE BIT(1) 131# define BM_TEST BIT(2) 132# define BM_TEST_DIR BIT(3) 133# define DUAL_EDGE_ENABLE BIT(4) 134# define NO_TRANSFER_TO_HOST BIT(5) 135# define TRANSFER_GO BIT(7) 136# define BLIEND_MODE BIT(8) 137# define BM_START BIT(9) 138# define ADVANCED_BM_WRITE BIT(10) 139# define BM_SINGLE_MODE BIT(11) 140# define FIFO_TRUE_FULL BIT(12) 141# define FIFO_TRUE_EMPTY BIT(13) 142# define ALL_COUNTER_CLR BIT(14) 143# define FIFOTEST BIT(15) 144 145#define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */ 146 147#define TIMER_SET 0x06 /* BASE+06, W, R/W */ 148# define TIMER_CNT_MASK (0xff) 149# define TIMER_STOP BIT(8) 150 151#define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */ 152#define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */ 153 154#define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */ 155# define FIFO_REST_MASK 0x1ff 156# define FIFO_EMPTY_SHLD_FLAG BIT(14) 157# define FIFO_FULL_SHLD_FLAG BIT(15) 158 159#define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */ 160# define SREQSMPLRATE_RATE0 BIT(0) 161# define SREQSMPLRATE_RATE1 BIT(1) 162# define SAMPLING_ENABLE BIT(2) 163# define SMPL_40M (0) /* 40MHz: 0-100ns/period */ 164# define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */ 165# define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */ 166 167#define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */ 168# define BUSCTL_SEL BIT(0) 169# define BUSCTL_RST BIT(1) 170# define BUSCTL_DATAOUT_ENB BIT(2) 171# define BUSCTL_ATN BIT(3) 172# define BUSCTL_ACK BIT(4) 173# define BUSCTL_BSY BIT(5) 174# define AUTODIRECTION BIT(6) 175# define ACKENB BIT(7) 176 177#define CLR_COUNTER 0x12 /* BASE+12, B, W */ 178# define ACK_COUNTER_CLR BIT(0) 179# define SREQ_COUNTER_CLR BIT(1) 180# define FIFO_HOST_POINTER_CLR BIT(2) 181# define FIFO_REST_COUNT_CLR BIT(3) 182# define BM_COUNTER_CLR BIT(4) 183# define SAVED_ACK_CLR BIT(5) 184# define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \ 185 SREQ_COUNTER_CLR | \ 186 FIFO_HOST_POINTER_CLR | \ 187 FIFO_REST_COUNT_CLR | \ 188 BM_COUNTER_CLR | \ 189 SAVED_ACK_CLR ) 190 191#define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */ 192# define BUSMON_MSG BIT(0) 193# define BUSMON_IO BIT(1) 194# define BUSMON_CD BIT(2) 195# define BUSMON_BSY BIT(3) 196# define BUSMON_ACK BIT(4) 197# define BUSMON_REQ BIT(5) 198# define BUSMON_SEL BIT(6) 199# define BUSMON_ATN BIT(7) 200 201#define COMMAND_DATA 0x14 /* BASE+14, B, R/W */ 202 203#define PARITY_CONTROL 0x16 /* BASE+16, B, W */ 204# define PARITY_CHECK_ENABLE BIT(0) 205# define PARITY_ERROR_CLEAR BIT(1) 206#define PARITY_STATUS 0x16 /* BASE+16, B, R */ 207//# define PARITY_CHECK_ENABLE BIT(0) 208# define PARITY_ERROR_NORMAL BIT(1) 209# define PARITY_ERROR_LSB BIT(1) 210# define PARITY_ERROR_MSB BIT(2) 211 212#define RESELECT_ID 0x18 /* BASE+18, B, R */ 213 214#define COMMAND_CONTROL 0x18 /* BASE+18, W, W */ 215# define CLEAR_CDB_FIFO_POINTER BIT(0) 216# define AUTO_COMMAND_PHASE BIT(1) 217# define AUTOSCSI_START BIT(2) 218# define AUTOSCSI_RESTART BIT(3) 219# define AUTO_PARAMETER BIT(4) 220# define AUTO_ATN BIT(5) 221# define AUTO_MSGIN_00_OR_04 BIT(6) 222# define AUTO_MSGIN_02 BIT(7) 223# define AUTO_MSGIN_03 BIT(8) 224 225#define SET_ARBIT 0x1a /* BASE+1a, B, W */ 226# define ARBIT_GO BIT(0) 227# define ARBIT_CLEAR BIT(1) 228 229#define ARBIT_STATUS 0x1a /* BASE+1a, B, R */ 230//# define ARBIT_GO BIT(0) 231# define ARBIT_WIN BIT(1) 232# define ARBIT_FAIL BIT(2) 233# define AUTO_PARAMETER_VALID BIT(3) 234# define SGT_VALID BIT(4) 235 236#define SYNC_REG 0x1c /* BASE+1c, B, R/W */ 237 238#define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */ 239 240#define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */ 241#define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */ 242#define SCSI_DATA_IN 0x22 /* BASE+22, B, R */ 243 244#define SCAM_CONTROL 0x24 /* BASE+24, B, W */ 245#define SCAM_STATUS 0x24 /* BASE+24, B, R */ 246# define SCAM_MSG BIT(0) 247# define SCAM_IO BIT(1) 248# define SCAM_CD BIT(2) 249# define SCAM_BSY BIT(3) 250# define SCAM_SEL BIT(4) 251# define SCAM_XFEROK BIT(5) 252 253#define SCAM_DATA 0x26 /* BASE+26, B, R/W */ 254# define SD0 BIT(0) 255# define SD1 BIT(1) 256# define SD2 BIT(2) 257# define SD3 BIT(3) 258# define SD4 BIT(4) 259# define SD5 BIT(5) 260# define SD6 BIT(6) 261# define SD7 BIT(7) 262 263#define SACK_CNT 0x28 /* BASE+28, DW, R/W */ 264#define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */ 265 266#define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */ 267#define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */ 268#define BM_START_ADR 0x34 /* BASE+34, DW, R/W */ 269 270#define BM_CNT 0x38 /* BASE+38, DW, R/W */ 271# define BM_COUNT_MASK 0x0001ffffUL 272# define SGTEND BIT(31) /* Last SGT marker */ 273 274#define SGT_ADR 0x3c /* BASE+3c, DW, R/W */ 275#define WAIT_REG 0x40 /* Bi only */ 276 277#define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */ 278# define COMMAND_PHASE BIT(0) 279# define DATA_IN_PHASE BIT(1) 280# define DATA_OUT_PHASE BIT(2) 281# define MSGOUT_PHASE BIT(3) 282# define STATUS_PHASE BIT(4) 283# define ILLEGAL_PHASE BIT(5) 284# define BUS_FREE_OCCUER BIT(6) 285# define MSG_IN_OCCUER BIT(7) 286# define MSG_OUT_OCCUER BIT(8) 287# define SELECTION_TIMEOUT BIT(9) 288# define MSGIN_00_VALID BIT(10) 289# define MSGIN_02_VALID BIT(11) 290# define MSGIN_03_VALID BIT(12) 291# define MSGIN_04_VALID BIT(13) 292# define AUTOSCSI_BUSY BIT(15) 293 294#define SCSI_CSB_IN 0x42 /* BASE+42, B, R */ 295 296#define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */ 297# define MSGOUT_COUNT_MASK (BIT(0)|BIT(1)) 298# define MV_VALID BIT(7) 299 300#define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */ 301#define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */ 302 303#define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */ 304#define STOHDATADELAY 0x54 /* BASE+54, B, R/W */ 305#define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */ 306#define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */ 307 308 309/********************/ 310/* indexed register */ 311/********************/ 312 313#define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */ 314# define CLOCK_2 BIT(0) /* MCLK/2 */ 315# define CLOCK_4 BIT(1) /* MCLK/4 */ 316# define PCICLK BIT(7) /* PCICLK (33MHz) */ 317 318#define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */ 319# define BPWR BIT(0) 320# define SENSE BIT(1) /* Read Only */ 321 322#define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */ 323#define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */ 324# define LED_ON (0) 325# define LED_OFF BIT(0) 326 327#define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */ 328# define IRQSELECT_RESELECT_IRQ BIT(0) 329# define IRQSELECT_PHASE_CHANGE_IRQ BIT(1) 330# define IRQSELECT_SCSIRESET_IRQ BIT(2) 331# define IRQSELECT_TIMER_IRQ BIT(3) 332# define IRQSELECT_FIFO_SHLD_IRQ BIT(4) 333# define IRQSELECT_TARGET_ABORT_IRQ BIT(5) 334# define IRQSELECT_MASTER_ABORT_IRQ BIT(6) 335# define IRQSELECT_SERR_IRQ BIT(7) 336# define IRQSELECT_PERR_IRQ BIT(8) 337# define IRQSELECT_BMCNTERR_IRQ BIT(9) 338# define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10) 339 340#define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */ 341# define OLD_MSG BIT(0) 342# define OLD_IO BIT(1) 343# define OLD_CD BIT(2) 344# define OLD_BUSY BIT(3) 345 346#define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */ 347#define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */ 348 349#define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */ 350# define ROM_WRITE_ENB BIT(0) 351# define IO_ACCESS_ENB BIT(1) 352# define ROM_ADR_CLEAR BIT(2) 353 354#define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */ 355 356#define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */ 357 358#define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */ 359# define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */ 360# define OEM1 BIT(2) /* OEM select */ 361# define OPTB BIT(3) /* KME mode select */ 362# define OPTC BIT(4) /* KME mode select */ 363# define OPTD BIT(5) /* KME mode select */ 364# define OPTE BIT(6) /* KME mode select */ 365# define OPTF BIT(7) /* Power management */ 366 367#define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */ 368#define MISC_RD 0x0c 369# define SCSI_DIRECTION_DETECTOR_SELECT BIT(0) 370# define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */ 371# define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */ 372# define DELAYED_BMSTART BIT(3) 373# define MASTER_TERMINATION_SELECT BIT(4) 374# define BMREQ_NEGATE_TIMING_SEL BIT(5) 375# define AUTOSEL_TIMING_SEL BIT(6) 376# define MISC_MABORT_MASK BIT(7) 377# define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8) 378 379#define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */ 380# define BM_CYCLE0 BIT(0) 381# define BM_CYCLE1 BIT(1) 382# define BM_FRAME_ASSERT_TIMING BIT(2) 383# define BM_IRDY_ASSERT_TIMING BIT(3) 384# define BM_SINGLE_BUS_MASTER BIT(4) 385# define MEMRD_CMD0 BIT(5) 386# define SGT_AUTO_PARA_MEMED_CMD BIT(6) 387# define MEMRD_CMD1 BIT(7) 388 389 390#define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */ 391# define SREQ_EDGH_SELECT BIT(0) 392 393#define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */ 394# define REQCNT_UP BIT(0) 395# define ACKCNT_UP BIT(1) 396# define BMADR_UP BIT(4) 397# define BMCNT_UP BIT(5) 398# define SGT_CNT_UP BIT(7) 399 400#define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */ 401#define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */ 402#define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */ 403#define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */ 404#define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */ 405 406#define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */ 407# define SCL BIT(0) 408# define ENA BIT(1) 409# define SDA BIT(2) 410 411#define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */ 412#define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */ 413#define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */ 414#define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */ 415#define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */ 416#define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */ 417#define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */ 418#define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */ 419#define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */ 420#define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */ 421#define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */ 422#define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */ 423#define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */ 424#define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */ 425 426 427/* 428 * Useful Bus Monitor status combinations. 429 */ 430#define BUSMON_BUS_FREE 0 431#define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ ) 432#define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ ) 433#define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ ) 434#define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ ) 435#define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ ) 436#define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ ) 437#define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL) 438#define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL) 439 440#define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK ) 441#define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK ) 442#define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK ) 443#define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK ) 444#define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK ) 445#define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK ) 446#define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO ) 447 448 449/************************************************************************ 450 * structure for DMA/Scatter Gather list 451 */ 452#define NSP32_SG_SIZE SG_ALL 453 454typedef struct _nsp32_sgtable { 455 /* values must be little endian */ 456 u32_le addr; /* transfer address */ 457 u32_le len; /* transfer length. BIT(31) is for SGT_END mark */ 458} __attribute__ ((packed)) nsp32_sgtable; 459 460typedef struct _nsp32_sglun { 461 nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */ 462} __attribute__ ((packed)) nsp32_sglun; 463#define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN) 464 465/* Auto parameter mode memory map. */ 466/* All values must be little endian. */ 467typedef struct _nsp32_autoparam { 468 u8 cdb[4 * 0x10]; /* SCSI Command */ 469 u32_le msgout; /* outgoing messages */ 470 u8 syncreg; /* sync register value */ 471 u8 ackwidth; /* ack width register value */ 472 u8 target_id; /* target/host device id */ 473 u8 sample_reg; /* hazard killer sampling rate */ 474 u16_le command_control; /* command control register */ 475 u16_le transfer_control; /* transfer control register */ 476 u32_le sgt_pointer; /* SG table physical address for DMA */ 477 u32_le dummy[2]; 478} __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */ 479 480/* 481 * host data structure 482 */ 483/* message in/out buffer */ 484#define MSGOUTBUF_MAX 20 485#define MSGINBUF_MAX 20 486 487/* flag for trans_method */ 488#define NSP32_TRANSFER_BUSMASTER BIT(0) 489#define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */ 490#define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */ 491 492 493/* 494 * structure for connected LUN dynamic data 495 * 496 * Note: Currently tagged queuing is disabled, each nsp32_lunt holds 497 * one SCSI command and one state. 498 */ 499#define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */ 500#define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */ 501 502typedef struct _nsp32_lunt { 503 struct scsi_cmnd *SCpnt; /* Current Handling struct scsi_cmnd */ 504 unsigned long save_datp; /* Save Data Pointer - saved position from initial address */ 505 int msgin03; /* auto msg in 03 flag */ 506 unsigned int sg_num; /* Total number of SG entries */ 507 int cur_entry; /* Current SG entry number */ 508 nsp32_sglun *sglun; /* sg table per lun */ 509 dma_addr_t sglun_paddr; /* sglun physical address */ 510} nsp32_lunt; 511 512 513/* 514 * SCSI TARGET/LUN definition 515 */ 516#define NSP32_HOST_SCSIID 7 /* SCSI initiator is everytime defined as 7 */ 517#define MAX_TARGET 8 518#define MAX_LUN 8 519 520 521typedef struct _nsp32_sync_table { 522 unsigned char period_num; /* period number */ 523 unsigned char ackwidth; /* ack width designated by period */ 524 unsigned char start_period; /* search range - start period */ 525 unsigned char end_period; /* search range - end period */ 526 unsigned char sample_rate; /* hazard killer parameter */ 527} nsp32_sync_table; 528 529 530/* 531 * structure for target device static data 532 */ 533/* flag for nsp32_target.sync_flag */ 534#define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */ 535#define SDTR_TARGET BIT(1) /* sending SDTR from target */ 536#define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */ 537 538/* syncronous period value for nsp32_target.config_max */ 539#define FAST5M 0x32 540#define FAST10M 0x19 541#define ULTRA20M 0x0c 542 543/* flag for nsp32_target.{sync_offset}, period */ 544#define ASYNC_OFFSET 0 /* asynchronous transfer */ 545#define SYNC_OFFSET 0xf /* synchronous transfer max offset */ 546 547/* syncreg: 548 bit:07 06 05 04 03 02 01 00 549 ---PERIOD-- ---OFFSET-- */ 550#define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f)) 551 552typedef struct _nsp32_target { 553 unsigned char syncreg; /* value for SYNCREG */ 554 unsigned char ackwidth; /* value for ACKWIDTH */ 555 unsigned char period; /* sync period (0-255) */ 556 unsigned char offset; /* sync offset (0-15) */ 557 int sync_flag; /* SDTR_*, 0 */ 558 int limit_entry; /* max speed limit entry designated 559 by EEPROM configuration */ 560 unsigned char sample_reg; /* SREQ hazard killer register */ 561} nsp32_target; 562 563typedef struct _nsp32_hw_data { 564 int IrqNumber; 565 int BaseAddress; 566 int NumAddress; 567 void __iomem *MmioAddress; 568#define NSP32_MMIO_OFFSET 0x0800 569 unsigned long MmioLength; 570 571 struct scsi_cmnd *CurrentSC; 572 573 struct pci_dev *Pci; 574 const struct pci_device_id *pci_devid; 575 struct Scsi_Host *Host; 576 spinlock_t Lock; 577 578 char info_str[100]; 579 580 /* allocated memory region */ 581 nsp32_sglun *sg_list; /* sglist virtuxal address */ 582 dma_addr_t sg_paddr; /* physical address of hw_sg_table */ 583 nsp32_autoparam *autoparam; /* auto parameter transfer region */ 584 dma_addr_t auto_paddr; /* physical address of autoparam */ 585 int cur_entry; /* current sgt entry */ 586 587 /* target/LUN */ 588 nsp32_lunt *cur_lunt; /* Current connected LUN table */ 589 nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */ 590 591 nsp32_target *cur_target; /* Current connected SCSI ID */ 592 nsp32_target target[MAX_TARGET]; /* SCSI ID */ 593 int cur_id; /* Current connected target ID */ 594 int cur_lun; /* Current connected target LUN */ 595 596 /* behavior setting parameters */ 597 int trans_method; /* transfer method flag */ 598 int resettime; /* Reset time */ 599 int clock; /* clock dividing flag */ 600 nsp32_sync_table *synct; /* sync_table determined by clock */ 601 int syncnum; /* the max number of synct element */ 602 603 /* message buffer */ 604 unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */ 605 char msgout_len; /* msgoutbuf length */ 606 unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */ 607 char msgin_len; /* msginbuf length */ 608 609} nsp32_hw_data; 610 611/* 612 * TIME definition 613 */ 614#define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the 615 minimum is 25us) */ 616#define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification 617 (25.6us/1unit) */ 618#define ARBIT_TIMEOUT_TIME 100 /* 100us */ 619#define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion 620 or negation, 10000us == 10ms */ 621 622#endif /* _NSP32_H */ 623/* end */ 624