1/*****************************************************************************/ 2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */ 3/* */ 4/* Written By: Keith Mitchell, IBM Corporation */ 5/* Jack Hammer, Adaptec, Inc. */ 6/* David Jeffery, Adaptec, Inc. */ 7/* */ 8/* Copyright (C) 2000 IBM Corporation */ 9/* Copyright (C) 2002,2003 Adaptec, Inc. */ 10/* */ 11/* This program is free software; you can redistribute it and/or modify */ 12/* it under the terms of the GNU General Public License as published by */ 13/* the Free Software Foundation; either version 2 of the License, or */ 14/* (at your option) any later version. */ 15/* */ 16/* This program is distributed in the hope that it will be useful, */ 17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ 18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ 19/* GNU General Public License for more details. */ 20/* */ 21/* NO WARRANTY */ 22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */ 23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */ 24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */ 25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */ 26/* solely responsible for determining the appropriateness of using and */ 27/* distributing the Program and assumes all risks associated with its */ 28/* exercise of rights under this Agreement, including but not limited to */ 29/* the risks and costs of program errors, damage to or loss of data, */ 30/* programs or equipment, and unavailability or interruption of operations. */ 31/* */ 32/* DISCLAIMER OF LIABILITY */ 33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */ 34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */ 35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */ 36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */ 37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */ 38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */ 39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */ 40/* */ 41/* You should have received a copy of the GNU General Public License */ 42/* along with this program; if not, write to the Free Software */ 43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ 44/* */ 45/* Bugs/Comments/Suggestions about this driver should be mailed to: */ 46/* ipslinux@adaptec.com */ 47/* */ 48/* For system support issues, contact your local IBM Customer support. */ 49/* Directions to find IBM Customer Support for each country can be found at: */ 50/* http://www.ibm.com/planetwide/ */ 51/* */ 52/*****************************************************************************/ 53 54/*****************************************************************************/ 55/* Change Log */ 56/* */ 57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */ 58/* 0.99.03 - Make interrupt routine handle all completed request on the */ 59/* adapter not just the first one */ 60/* - Make sure passthru commands get woken up if we run out of */ 61/* SCBs */ 62/* - Send all of the commands on the queue at once rather than */ 63/* one at a time since the card will support it. */ 64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */ 65/* the interface to the utilities to change */ 66/* - Fix error recovery code */ 67/* 0.99.05 - Fix an oops when we get certain passthru commands */ 68/* 1.00.00 - Initial Public Release */ 69/* Functionally equivalent to 0.99.05 */ 70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */ 71/* - Change version to 3.60 to coincide with release numbering. */ 72/* 3.60.01 - Remove bogus error check in passthru routine */ 73/* 3.60.02 - Make DCDB direction based on lookup table */ 74/* - Only allow one DCDB command to a SCSI ID at a time */ 75/* 4.00.00 - Add support for ServeRAID 4 */ 76/* 4.00.01 - Add support for First Failure Data Capture */ 77/* 4.00.02 - Fix problem with PT DCDB with no buffer */ 78/* 4.00.03 - Add alternative passthru interface */ 79/* - Add ability to flash BIOS */ 80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */ 81/* 4.00.05 - Remove wish_block from init routine */ 82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */ 83/* 2.3.18 and later */ 84/* - Sync with other changes from the 2.3 kernels */ 85/* 4.00.06 - Fix timeout with initial FFDC command */ 86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */ 87/* 4.10.00 - Add support for ServeRAID 4M/4L */ 88/* 4.10.13 - Fix for dynamic unload and proc file system */ 89/* 4.20.03 - Rename version to coincide with new release schedules */ 90/* Performance fixes */ 91/* Fix truncation of /proc files with cat */ 92/* Merge in changes through kernel 2.4.0test1ac21 */ 93/* 4.20.13 - Fix some failure cases / reset code */ 94/* - Hook into the reboot_notifier to flush the controller cache */ 95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */ 96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */ 97/* - Add IPSSEND Flash Support */ 98/* - Set Sense Data for Unknown SCSI Command */ 99/* - Use Slot Number from NVRAM Page 5 */ 100/* - Restore caller's DCDB Structure */ 101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/ 102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */ 103/* - Don't release HA Lock in ips_next() until SC taken off queue */ 104/* - Unregister SCSI device in ips_release() */ 105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */ 106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */ 107/* Code Clean-Up for 2.4.x kernel */ 108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */ 109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */ 110/* - Don't Issue Internal FFDC Command if there are Active Commands */ 111/* - Close Window for getting too many IOCTL's active */ 112/* 4.80.00 - Make ia64 Safe */ 113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */ 114/* - Adjustments to Device Queue Depth */ 115/* 4.80.14 - Take all semaphores off stack */ 116/* - Clean Up New_IOCTL path */ 117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */ 118/* - 5 second delay needed after resetting an i960 adapter */ 119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */ 120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */ 121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */ 122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */ 123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */ 124/* 4.90.11 - Don't actually RESET unless it's physically required */ 125/* - Remove unused compile options */ 126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */ 127/* - Get rid on IOCTL_NEW_COMMAND code */ 128/* - Add Extended DCDB Commands for Tape Support in 5I */ 129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */ 130/* 5.10.15 - remove unused code (sem, macros, etc.) */ 131/* 5.30.00 - use __devexit_p() */ 132/* 6.00.00 - Add 6x Adapters and Battery Flash */ 133/* 6.10.00 - Remove 1G Addressing Limitations */ 134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */ 135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */ 136/* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */ 137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */ 138/* - Fix sort order of 7k */ 139/* - Remove 3 unused "inline" functions */ 140/* 7.12.xx - Use STATIC functions whereever possible */ 141/* - Clean up deprecated MODULE_PARM calls */ 142/* 7.12.05 - Remove Version Matching per IBM request */ 143/*****************************************************************************/ 144 145/* 146 * Conditional Compilation directives for this driver: 147 * 148 * IPS_DEBUG - Turn on debugging info 149 * 150 * Parameters: 151 * 152 * debug:<number> - Set debug level to <number> 153 * NOTE: only works when IPS_DEBUG compile directive is used. 154 * 1 - Normal debug messages 155 * 2 - Verbose debug messages 156 * 11 - Method trace (non interrupt) 157 * 12 - Method trace (includes interrupt) 158 * 159 * noi2o - Don't use I2O Queues (ServeRAID 4 only) 160 * nommap - Don't use memory mapped I/O 161 * ioctlsize - Initial size of the IOCTL buffer 162 */ 163 164#include <asm/io.h> 165#include <asm/byteorder.h> 166#include <asm/page.h> 167#include <linux/stddef.h> 168#include <linux/version.h> 169#include <linux/string.h> 170#include <linux/errno.h> 171#include <linux/kernel.h> 172#include <linux/ioport.h> 173#include <linux/slab.h> 174#include <linux/delay.h> 175#include <linux/pci.h> 176#include <linux/proc_fs.h> 177#include <linux/reboot.h> 178#include <linux/interrupt.h> 179 180#include <linux/blkdev.h> 181#include <linux/types.h> 182#include <linux/dma-mapping.h> 183 184#include <scsi/sg.h> 185#include "scsi.h" 186#include <scsi/scsi_host.h> 187 188#include "ips.h" 189 190#include <linux/module.h> 191 192#include <linux/stat.h> 193 194#include <linux/spinlock.h> 195#include <linux/init.h> 196 197#include <linux/smp.h> 198 199#ifdef MODULE 200static char *ips = NULL; 201module_param(ips, charp, 0); 202#endif 203 204/* 205 * DRIVER_VER 206 */ 207#define IPS_VERSION_HIGH "7.12" 208#define IPS_VERSION_LOW ".05 " 209 210#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__) 211#warning "This driver has only been tested on the x86/ia64/x86_64 platforms" 212#endif 213 214#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0) 215#include <linux/blk.h> 216#include "sd.h" 217#define IPS_LOCK_SAVE(lock,flags) spin_lock_irqsave(&io_request_lock,flags) 218#define IPS_UNLOCK_RESTORE(lock,flags) spin_unlock_irqrestore(&io_request_lock,flags) 219#ifndef __devexit_p 220#define __devexit_p(x) x 221#endif 222#else 223#define IPS_LOCK_SAVE(lock,flags) do{spin_lock(lock);(void)flags;}while(0) 224#define IPS_UNLOCK_RESTORE(lock,flags) do{spin_unlock(lock);(void)flags;}while(0) 225#endif 226 227#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \ 228 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \ 229 PCI_DMA_BIDIRECTIONAL : \ 230 scb->scsi_cmd->sc_data_direction) 231 232#ifdef IPS_DEBUG 233#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n"); 234#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n"); 235#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v); 236#else 237#define METHOD_TRACE(s, i) 238#define DEBUG(i, s) 239#define DEBUG_VAR(i, s, v...) 240#endif 241 242/* 243 * Function prototypes 244 */ 245static int ips_detect(struct scsi_host_template *); 246static int ips_release(struct Scsi_Host *); 247static int ips_eh_abort(struct scsi_cmnd *); 248static int ips_eh_reset(struct scsi_cmnd *); 249static int ips_queue(struct scsi_cmnd *, void (*)(struct scsi_cmnd *)); 250static const char *ips_info(struct Scsi_Host *); 251static irqreturn_t do_ipsintr(int, void *); 252static int ips_hainit(ips_ha_t *); 253static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *); 254static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int); 255static int ips_send_cmd(ips_ha_t *, ips_scb_t *); 256static int ips_online(ips_ha_t *, ips_scb_t *); 257static int ips_inquiry(ips_ha_t *, ips_scb_t *); 258static int ips_rdcap(ips_ha_t *, ips_scb_t *); 259static int ips_msense(ips_ha_t *, ips_scb_t *); 260static int ips_reqsen(ips_ha_t *, ips_scb_t *); 261static int ips_deallocatescbs(ips_ha_t *, int); 262static int ips_allocatescbs(ips_ha_t *); 263static int ips_reset_copperhead(ips_ha_t *); 264static int ips_reset_copperhead_memio(ips_ha_t *); 265static int ips_reset_morpheus(ips_ha_t *); 266static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *); 267static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *); 268static int ips_issue_i2o(ips_ha_t *, ips_scb_t *); 269static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *); 270static int ips_isintr_copperhead(ips_ha_t *); 271static int ips_isintr_copperhead_memio(ips_ha_t *); 272static int ips_isintr_morpheus(ips_ha_t *); 273static int ips_wait(ips_ha_t *, int, int); 274static int ips_write_driver_status(ips_ha_t *, int); 275static int ips_read_adapter_status(ips_ha_t *, int); 276static int ips_read_subsystem_parameters(ips_ha_t *, int); 277static int ips_read_config(ips_ha_t *, int); 278static int ips_clear_adapter(ips_ha_t *, int); 279static int ips_readwrite_page5(ips_ha_t *, int, int); 280static int ips_init_copperhead(ips_ha_t *); 281static int ips_init_copperhead_memio(ips_ha_t *); 282static int ips_init_morpheus(ips_ha_t *); 283static int ips_isinit_copperhead(ips_ha_t *); 284static int ips_isinit_copperhead_memio(ips_ha_t *); 285static int ips_isinit_morpheus(ips_ha_t *); 286static int ips_erase_bios(ips_ha_t *); 287static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t); 288static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t); 289static int ips_erase_bios_memio(ips_ha_t *); 290static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); 291static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); 292static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 293static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 294static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 295static void ips_free_flash_copperhead(ips_ha_t * ha); 296static void ips_get_bios_version(ips_ha_t *, int); 297static void ips_identify_controller(ips_ha_t *); 298static void ips_chkstatus(ips_ha_t *, IPS_STATUS *); 299static void ips_enable_int_copperhead(ips_ha_t *); 300static void ips_enable_int_copperhead_memio(ips_ha_t *); 301static void ips_enable_int_morpheus(ips_ha_t *); 302static int ips_intr_copperhead(ips_ha_t *); 303static int ips_intr_morpheus(ips_ha_t *); 304static void ips_next(ips_ha_t *, int); 305static void ipsintr_blocking(ips_ha_t *, struct ips_scb *); 306static void ipsintr_done(ips_ha_t *, struct ips_scb *); 307static void ips_done(ips_ha_t *, ips_scb_t *); 308static void ips_free(ips_ha_t *); 309static void ips_init_scb(ips_ha_t *, ips_scb_t *); 310static void ips_freescb(ips_ha_t *, ips_scb_t *); 311static void ips_setup_funclist(ips_ha_t *); 312static void ips_statinit(ips_ha_t *); 313static void ips_statinit_memio(ips_ha_t *); 314static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t); 315static void ips_ffdc_reset(ips_ha_t *, int); 316static void ips_ffdc_time(ips_ha_t *); 317static uint32_t ips_statupd_copperhead(ips_ha_t *); 318static uint32_t ips_statupd_copperhead_memio(ips_ha_t *); 319static uint32_t ips_statupd_morpheus(ips_ha_t *); 320static ips_scb_t *ips_getscb(ips_ha_t *); 321static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *); 322static void ips_putq_wait_tail(ips_wait_queue_t *, struct scsi_cmnd *); 323static void ips_putq_copp_tail(ips_copp_queue_t *, 324 ips_copp_wait_item_t *); 325static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *); 326static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *); 327static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *); 328static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *, 329 struct scsi_cmnd *); 330static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *, 331 ips_copp_wait_item_t *); 332static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *); 333 334static int ips_is_passthru(struct scsi_cmnd *); 335static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int); 336static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 337static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *); 338static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data, 339 unsigned int count); 340static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data, 341 unsigned int count); 342 343static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int); 344static int ips_host_info(ips_ha_t *, char *, off_t, int); 345static void copy_mem_info(IPS_INFOSTR *, char *, int); 346static int copy_info(IPS_INFOSTR *, char *, ...); 347static int ips_abort_init(ips_ha_t * ha, int index); 348static int ips_init_phase2(int index); 349 350static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr); 351static int ips_register_scsi(int index); 352 353static int ips_poll_for_flush_complete(ips_ha_t * ha); 354static void ips_flush_and_reset(ips_ha_t *ha); 355 356/* 357 * global variables 358 */ 359static const char ips_name[] = "ips"; 360static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */ 361static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */ 362static unsigned int ips_next_controller; 363static unsigned int ips_num_controllers; 364static unsigned int ips_released_controllers; 365static int ips_hotplug; 366static int ips_cmd_timeout = 60; 367static int ips_reset_timeout = 60 * 5; 368static int ips_force_memio = 1; /* Always use Memory Mapped I/O */ 369static int ips_force_i2o = 1; /* Always use I2O command delivery */ 370static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */ 371static int ips_cd_boot; /* Booting from Manager CD */ 372static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */ 373static dma_addr_t ips_flashbusaddr; 374static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */ 375static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */ 376static struct scsi_host_template ips_driver_template = { 377 .detect = ips_detect, 378 .release = ips_release, 379 .info = ips_info, 380 .queuecommand = ips_queue, 381 .eh_abort_handler = ips_eh_abort, 382 .eh_host_reset_handler = ips_eh_reset, 383 .proc_name = "ips", 384#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) 385 .proc_info = ips_proc_info, 386 .slave_configure = ips_slave_configure, 387#else 388 .proc_info = ips_proc24_info, 389 .select_queue_depths = ips_select_queue_depth, 390#endif 391 .bios_param = ips_biosparam, 392 .this_id = -1, 393 .sg_tablesize = IPS_MAX_SG, 394 .cmd_per_lun = 3, 395 .use_clustering = ENABLE_CLUSTERING, 396#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 397 .use_new_eh_code = 1, 398#endif 399#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && LINUX_VERSION_CODE < \ 400 KERNEL_VERSION(2,5,0) 401 .highmem_io = 1, 402#endif 403}; 404 405 406/* This table describes all ServeRAID Adapters */ 407static struct pci_device_id ips_pci_table[] = { 408 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 409 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 410 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 411 { 0, } 412}; 413 414MODULE_DEVICE_TABLE( pci, ips_pci_table ); 415 416static char ips_hot_plug_name[] = "ips"; 417 418static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent); 419static void __devexit ips_remove_device(struct pci_dev *pci_dev); 420 421static struct pci_driver ips_pci_driver = { 422 .name = ips_hot_plug_name, 423 .id_table = ips_pci_table, 424 .probe = ips_insert_device, 425 .remove = __devexit_p(ips_remove_device), 426}; 427 428 429/* 430 * Necessary forward function protoypes 431 */ 432static int ips_halt(struct notifier_block *nb, ulong event, void *buf); 433 434#define MAX_ADAPTER_NAME 15 435 436static char ips_adapter_name[][30] = { 437 "ServeRAID", 438 "ServeRAID II", 439 "ServeRAID on motherboard", 440 "ServeRAID on motherboard", 441 "ServeRAID 3H", 442 "ServeRAID 3L", 443 "ServeRAID 4H", 444 "ServeRAID 4M", 445 "ServeRAID 4L", 446 "ServeRAID 4Mx", 447 "ServeRAID 4Lx", 448 "ServeRAID 5i", 449 "ServeRAID 5i", 450 "ServeRAID 6M", 451 "ServeRAID 6i", 452 "ServeRAID 7t", 453 "ServeRAID 7k", 454 "ServeRAID 7M" 455}; 456 457static struct notifier_block ips_notifier = { 458 ips_halt, NULL, 0 459}; 460 461/* 462 * Direction table 463 */ 464static char ips_command_direction[] = { 465 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, 466 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, 467 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 468 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, 469 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT, 470 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, 471 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN, 472 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, 473 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK, 474 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, 475 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, 476 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, 477 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, 478 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE, 479 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, 480 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, 481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 482 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 483 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 487 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 490 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 491 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 492 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 493 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 494 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 495 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 496 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 497 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 498 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE, 499 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT, 500 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE, 501 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, 502 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 503 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 504 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 505 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 506 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 507 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 508 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 509 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 510 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 511 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT, 512 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 513 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 514 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 515 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK 516}; 517 518 519/****************************************************************************/ 520/* */ 521/* Routine Name: ips_setup */ 522/* */ 523/* Routine Description: */ 524/* */ 525/* setup parameters to the driver */ 526/* */ 527/****************************************************************************/ 528static int 529ips_setup(char *ips_str) 530{ 531 532 int i; 533 char *key; 534 char *value; 535 IPS_OPTION options[] = { 536 {"noi2o", &ips_force_i2o, 0}, 537 {"nommap", &ips_force_memio, 0}, 538 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE}, 539 {"cdboot", &ips_cd_boot, 0}, 540 {"maxcmds", &MaxLiteCmds, 32}, 541 }; 542 543 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */ 544 /* Search for value */ 545 while ((key = strsep(&ips_str, ",."))) { 546 if (!*key) 547 continue; 548 value = strchr(key, ':'); 549 if (value) 550 *value++ = '\0'; 551 /* 552 * We now have key/value pairs. 553 * Update the variables 554 */ 555 for (i = 0; i < ARRAY_SIZE(options); i++) { 556 if (strnicmp 557 (key, options[i].option_name, 558 strlen(options[i].option_name)) == 0) { 559 if (value) 560 *options[i].option_flag = 561 simple_strtoul(value, NULL, 0); 562 else 563 *options[i].option_flag = 564 options[i].option_value; 565 break; 566 } 567 } 568 } 569 570 return (1); 571} 572 573__setup("ips=", ips_setup); 574 575/****************************************************************************/ 576/* */ 577/* Routine Name: ips_detect */ 578/* */ 579/* Routine Description: */ 580/* */ 581/* Detect and initialize the driver */ 582/* */ 583/* NOTE: this routine is called under the io_request_lock spinlock */ 584/* */ 585/****************************************************************************/ 586static int 587ips_detect(struct scsi_host_template * SHT) 588{ 589 int i; 590 591 METHOD_TRACE("ips_detect", 1); 592 593#ifdef MODULE 594 if (ips) 595 ips_setup(ips); 596#endif 597 598 for (i = 0; i < ips_num_controllers; i++) { 599 if (ips_register_scsi(i)) 600 ips_free(ips_ha[i]); 601 ips_released_controllers++; 602 } 603 ips_hotplug = 1; 604 return (ips_num_controllers); 605} 606 607/****************************************************************************/ 608/* configure the function pointers to use the functions that will work */ 609/* with the found version of the adapter */ 610/****************************************************************************/ 611static void 612ips_setup_funclist(ips_ha_t * ha) 613{ 614 615 /* 616 * Setup Functions 617 */ 618 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) { 619 /* morpheus / marco / sebring */ 620 ha->func.isintr = ips_isintr_morpheus; 621 ha->func.isinit = ips_isinit_morpheus; 622 ha->func.issue = ips_issue_i2o_memio; 623 ha->func.init = ips_init_morpheus; 624 ha->func.statupd = ips_statupd_morpheus; 625 ha->func.reset = ips_reset_morpheus; 626 ha->func.intr = ips_intr_morpheus; 627 ha->func.enableint = ips_enable_int_morpheus; 628 } else if (IPS_USE_MEMIO(ha)) { 629 /* copperhead w/MEMIO */ 630 ha->func.isintr = ips_isintr_copperhead_memio; 631 ha->func.isinit = ips_isinit_copperhead_memio; 632 ha->func.init = ips_init_copperhead_memio; 633 ha->func.statupd = ips_statupd_copperhead_memio; 634 ha->func.statinit = ips_statinit_memio; 635 ha->func.reset = ips_reset_copperhead_memio; 636 ha->func.intr = ips_intr_copperhead; 637 ha->func.erasebios = ips_erase_bios_memio; 638 ha->func.programbios = ips_program_bios_memio; 639 ha->func.verifybios = ips_verify_bios_memio; 640 ha->func.enableint = ips_enable_int_copperhead_memio; 641 if (IPS_USE_I2O_DELIVER(ha)) 642 ha->func.issue = ips_issue_i2o_memio; 643 else 644 ha->func.issue = ips_issue_copperhead_memio; 645 } else { 646 /* copperhead */ 647 ha->func.isintr = ips_isintr_copperhead; 648 ha->func.isinit = ips_isinit_copperhead; 649 ha->func.init = ips_init_copperhead; 650 ha->func.statupd = ips_statupd_copperhead; 651 ha->func.statinit = ips_statinit; 652 ha->func.reset = ips_reset_copperhead; 653 ha->func.intr = ips_intr_copperhead; 654 ha->func.erasebios = ips_erase_bios; 655 ha->func.programbios = ips_program_bios; 656 ha->func.verifybios = ips_verify_bios; 657 ha->func.enableint = ips_enable_int_copperhead; 658 659 if (IPS_USE_I2O_DELIVER(ha)) 660 ha->func.issue = ips_issue_i2o; 661 else 662 ha->func.issue = ips_issue_copperhead; 663 } 664} 665 666/****************************************************************************/ 667/* */ 668/* Routine Name: ips_release */ 669/* */ 670/* Routine Description: */ 671/* */ 672/* Remove a driver */ 673/* */ 674/****************************************************************************/ 675static int 676ips_release(struct Scsi_Host *sh) 677{ 678 ips_scb_t *scb; 679 ips_ha_t *ha; 680 int i; 681 682 METHOD_TRACE("ips_release", 1); 683 684 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ; 685 686 if (i == IPS_MAX_ADAPTERS) { 687 printk(KERN_WARNING 688 "(%s) release, invalid Scsi_Host pointer.\n", ips_name); 689 BUG(); 690 return (FALSE); 691 } 692 693 ha = IPS_HA(sh); 694 695 if (!ha) 696 return (FALSE); 697 698 /* flush the cache on the controller */ 699 scb = &ha->scbs[ha->max_cmds - 1]; 700 701 ips_init_scb(ha, scb); 702 703 scb->timeout = ips_cmd_timeout; 704 scb->cdb[0] = IPS_CMD_FLUSH; 705 706 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 707 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 708 scb->cmd.flush_cache.state = IPS_NORM_STATE; 709 scb->cmd.flush_cache.reserved = 0; 710 scb->cmd.flush_cache.reserved2 = 0; 711 scb->cmd.flush_cache.reserved3 = 0; 712 scb->cmd.flush_cache.reserved4 = 0; 713 714 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); 715 716 /* send command */ 717 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE) 718 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n"); 719 720 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n"); 721 722 ips_sh[i] = NULL; 723 ips_ha[i] = NULL; 724 725 /* free extra memory */ 726 ips_free(ha); 727 728 /* Free I/O Region */ 729 if (ha->io_addr) 730 release_region(ha->io_addr, ha->io_len); 731 732 /* free IRQ */ 733 free_irq(ha->irq, ha); 734 735 IPS_REMOVE_HOST(sh); 736 scsi_host_put(sh); 737 738 ips_released_controllers++; 739 740 return (FALSE); 741} 742 743/****************************************************************************/ 744/* */ 745/* Routine Name: ips_halt */ 746/* */ 747/* Routine Description: */ 748/* */ 749/* Perform cleanup when the system reboots */ 750/* */ 751/****************************************************************************/ 752static int 753ips_halt(struct notifier_block *nb, ulong event, void *buf) 754{ 755 ips_scb_t *scb; 756 ips_ha_t *ha; 757 int i; 758 759 if ((event != SYS_RESTART) && (event != SYS_HALT) && 760 (event != SYS_POWER_OFF)) 761 return (NOTIFY_DONE); 762 763 for (i = 0; i < ips_next_controller; i++) { 764 ha = (ips_ha_t *) ips_ha[i]; 765 766 if (!ha) 767 continue; 768 769 if (!ha->active) 770 continue; 771 772 /* flush the cache on the controller */ 773 scb = &ha->scbs[ha->max_cmds - 1]; 774 775 ips_init_scb(ha, scb); 776 777 scb->timeout = ips_cmd_timeout; 778 scb->cdb[0] = IPS_CMD_FLUSH; 779 780 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 781 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 782 scb->cmd.flush_cache.state = IPS_NORM_STATE; 783 scb->cmd.flush_cache.reserved = 0; 784 scb->cmd.flush_cache.reserved2 = 0; 785 scb->cmd.flush_cache.reserved3 = 0; 786 scb->cmd.flush_cache.reserved4 = 0; 787 788 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); 789 790 /* send command */ 791 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == 792 IPS_FAILURE) 793 IPS_PRINTK(KERN_WARNING, ha->pcidev, 794 "Incomplete Flush.\n"); 795 else 796 IPS_PRINTK(KERN_WARNING, ha->pcidev, 797 "Flushing Complete.\n"); 798 } 799 800 return (NOTIFY_OK); 801} 802 803/****************************************************************************/ 804/* */ 805/* Routine Name: ips_eh_abort */ 806/* */ 807/* Routine Description: */ 808/* */ 809/* Abort a command (using the new error code stuff) */ 810/* Note: this routine is called under the io_request_lock */ 811/****************************************************************************/ 812int ips_eh_abort(struct scsi_cmnd *SC) 813{ 814 ips_ha_t *ha; 815 ips_copp_wait_item_t *item; 816 int ret; 817 unsigned long cpu_flags; 818 struct Scsi_Host *host; 819 820 METHOD_TRACE("ips_eh_abort", 1); 821 822 if (!SC) 823 return (FAILED); 824 825 host = SC->device->host; 826 ha = (ips_ha_t *) SC->device->host->hostdata; 827 828 if (!ha) 829 return (FAILED); 830 831 if (!ha->active) 832 return (FAILED); 833 834 IPS_LOCK_SAVE(host->host_lock, cpu_flags); 835 836 /* See if the command is on the copp queue */ 837 item = ha->copp_waitlist.head; 838 while ((item) && (item->scsi_cmd != SC)) 839 item = item->next; 840 841 if (item) { 842 /* Found it */ 843 ips_removeq_copp(&ha->copp_waitlist, item); 844 ret = (SUCCESS); 845 846 /* See if the command is on the wait queue */ 847 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) { 848 /* command not sent yet */ 849 ret = (SUCCESS); 850 } else { 851 /* command must have already been sent */ 852 ret = (FAILED); 853 } 854 855 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); 856 return ret; 857} 858 859/****************************************************************************/ 860/* */ 861/* Routine Name: ips_eh_reset */ 862/* */ 863/* Routine Description: */ 864/* */ 865/* Reset the controller (with new eh error code) */ 866/* */ 867/* NOTE: this routine is called under the io_request_lock spinlock */ 868/* */ 869/****************************************************************************/ 870static int __ips_eh_reset(struct scsi_cmnd *SC) 871{ 872 int ret; 873 int i; 874 ips_ha_t *ha; 875 ips_scb_t *scb; 876 ips_copp_wait_item_t *item; 877 878 METHOD_TRACE("ips_eh_reset", 1); 879 880#ifdef NO_IPS_RESET 881 return (FAILED); 882#else 883 884 if (!SC) { 885 DEBUG(1, "Reset called with NULL scsi command"); 886 887 return (FAILED); 888 } 889 890 ha = (ips_ha_t *) SC->device->host->hostdata; 891 892 if (!ha) { 893 DEBUG(1, "Reset called with NULL ha struct"); 894 895 return (FAILED); 896 } 897 898 if (!ha->active) 899 return (FAILED); 900 901 /* See if the command is on the copp queue */ 902 item = ha->copp_waitlist.head; 903 while ((item) && (item->scsi_cmd != SC)) 904 item = item->next; 905 906 if (item) { 907 /* Found it */ 908 ips_removeq_copp(&ha->copp_waitlist, item); 909 return (SUCCESS); 910 } 911 912 /* See if the command is on the wait queue */ 913 if (ips_removeq_wait(&ha->scb_waitlist, SC)) { 914 /* command not sent yet */ 915 return (SUCCESS); 916 } 917 918 /* An explanation for the casual observer: */ 919 /* Part of the function of a RAID controller is automatic error */ 920 /* detection and recovery. As such, the only problem that physically */ 921 /* resetting an adapter will ever fix is when, for some reason, */ 922 /* the driver is not successfully communicating with the adapter. */ 923 /* Therefore, we will attempt to flush this adapter. If that succeeds, */ 924 /* then there's no real purpose in a physical reset. This will complete */ 925 /* much faster and avoids any problems that might be caused by a */ 926 /* physical reset ( such as having to fail all the outstanding I/O's ). */ 927 928 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */ 929 scb = &ha->scbs[ha->max_cmds - 1]; 930 931 ips_init_scb(ha, scb); 932 933 scb->timeout = ips_cmd_timeout; 934 scb->cdb[0] = IPS_CMD_FLUSH; 935 936 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 937 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 938 scb->cmd.flush_cache.state = IPS_NORM_STATE; 939 scb->cmd.flush_cache.reserved = 0; 940 scb->cmd.flush_cache.reserved2 = 0; 941 scb->cmd.flush_cache.reserved3 = 0; 942 scb->cmd.flush_cache.reserved4 = 0; 943 944 /* Attempt the flush command */ 945 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL); 946 if (ret == IPS_SUCCESS) { 947 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 948 "Reset Request - Flushed Cache\n"); 949 return (SUCCESS); 950 } 951 } 952 953 /* Either we can't communicate with the adapter or it's an IOCTL request */ 954 /* from a utility. A physical reset is needed at this point. */ 955 956 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */ 957 958 /* 959 * command must have already been sent 960 * reset the controller 961 */ 962 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n"); 963 ret = (*ha->func.reset) (ha); 964 965 if (!ret) { 966 struct scsi_cmnd *scsi_cmd; 967 968 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 969 "Controller reset failed - controller now offline.\n"); 970 971 /* Now fail all of the active commands */ 972 DEBUG_VAR(1, "(%s%d) Failing active commands", 973 ips_name, ha->host_num); 974 975 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 976 scb->scsi_cmd->result = DID_ERROR << 16; 977 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 978 ips_freescb(ha, scb); 979 } 980 981 /* Now fail all of the pending commands */ 982 DEBUG_VAR(1, "(%s%d) Failing pending commands", 983 ips_name, ha->host_num); 984 985 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { 986 scsi_cmd->result = DID_ERROR; 987 scsi_cmd->scsi_done(scsi_cmd); 988 } 989 990 ha->active = FALSE; 991 return (FAILED); 992 } 993 994 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) { 995 struct scsi_cmnd *scsi_cmd; 996 997 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 998 "Controller reset failed - controller now offline.\n"); 999 1000 /* Now fail all of the active commands */ 1001 DEBUG_VAR(1, "(%s%d) Failing active commands", 1002 ips_name, ha->host_num); 1003 1004 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 1005 scb->scsi_cmd->result = DID_ERROR << 16; 1006 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 1007 ips_freescb(ha, scb); 1008 } 1009 1010 /* Now fail all of the pending commands */ 1011 DEBUG_VAR(1, "(%s%d) Failing pending commands", 1012 ips_name, ha->host_num); 1013 1014 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { 1015 scsi_cmd->result = DID_ERROR << 16; 1016 scsi_cmd->scsi_done(scsi_cmd); 1017 } 1018 1019 ha->active = FALSE; 1020 return (FAILED); 1021 } 1022 1023 /* FFDC */ 1024 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) { 1025 struct timeval tv; 1026 1027 do_gettimeofday(&tv); 1028 ha->last_ffdc = tv.tv_sec; 1029 ha->reset_count++; 1030 ips_ffdc_reset(ha, IPS_INTR_IORL); 1031 } 1032 1033 /* Now fail all of the active commands */ 1034 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num); 1035 1036 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 1037 scb->scsi_cmd->result = 1038 (DID_RESET << 16) | (SUGGEST_RETRY << 24); 1039 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 1040 ips_freescb(ha, scb); 1041 } 1042 1043 /* Reset DCDB active command bits */ 1044 for (i = 1; i < ha->nbus; i++) 1045 ha->dcdb_active[i - 1] = 0; 1046 1047 /* Reset the number of active IOCTLs */ 1048 ha->num_ioctl = 0; 1049 1050 ips_next(ha, IPS_INTR_IORL); 1051 1052 return (SUCCESS); 1053#endif /* NO_IPS_RESET */ 1054 1055} 1056 1057static int ips_eh_reset(struct scsi_cmnd *SC) 1058{ 1059 int rc; 1060 1061 spin_lock_irq(SC->device->host->host_lock); 1062 rc = __ips_eh_reset(SC); 1063 spin_unlock_irq(SC->device->host->host_lock); 1064 1065 return rc; 1066} 1067 1068/****************************************************************************/ 1069/* */ 1070/* Routine Name: ips_queue */ 1071/* */ 1072/* Routine Description: */ 1073/* */ 1074/* Send a command to the controller */ 1075/* */ 1076/* NOTE: */ 1077/* Linux obtains io_request_lock before calling this function */ 1078/* */ 1079/****************************************************************************/ 1080static int ips_queue(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *)) 1081{ 1082 ips_ha_t *ha; 1083 ips_passthru_t *pt; 1084 1085 METHOD_TRACE("ips_queue", 1); 1086 1087 ha = (ips_ha_t *) SC->device->host->hostdata; 1088 1089 if (!ha) 1090 return (1); 1091 1092 if (!ha->active) 1093 return (DID_ERROR); 1094 1095 if (ips_is_passthru(SC)) { 1096 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) { 1097 SC->result = DID_BUS_BUSY << 16; 1098 done(SC); 1099 1100 return (0); 1101 } 1102 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) { 1103 SC->result = DID_BUS_BUSY << 16; 1104 done(SC); 1105 1106 return (0); 1107 } 1108 1109 SC->scsi_done = done; 1110 1111 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)", 1112 ips_name, 1113 ha->host_num, 1114 SC->cmnd[0], 1115 SC->device->channel, SC->device->id, SC->device->lun); 1116 1117 /* Check for command to initiator IDs */ 1118 if ((scmd_channel(SC) > 0) 1119 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) { 1120 SC->result = DID_NO_CONNECT << 16; 1121 done(SC); 1122 1123 return (0); 1124 } 1125 1126 if (ips_is_passthru(SC)) { 1127 1128 ips_copp_wait_item_t *scratch; 1129 1130 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */ 1131 /* There can never be any system activity ( network or disk ), but check */ 1132 /* anyway just as a good practice. */ 1133 pt = (ips_passthru_t *) SC->request_buffer; 1134 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) && 1135 (pt->CoppCP.cmd.reset.adapter_flag == 1)) { 1136 if (ha->scb_activelist.count != 0) { 1137 SC->result = DID_BUS_BUSY << 16; 1138 done(SC); 1139 return (0); 1140 } 1141 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */ 1142 __ips_eh_reset(SC); 1143 SC->result = DID_OK << 16; 1144 SC->scsi_done(SC); 1145 return (0); 1146 } 1147 1148 /* allocate space for the scribble */ 1149 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC); 1150 1151 if (!scratch) { 1152 SC->result = DID_ERROR << 16; 1153 done(SC); 1154 1155 return (0); 1156 } 1157 1158 scratch->scsi_cmd = SC; 1159 scratch->next = NULL; 1160 1161 ips_putq_copp_tail(&ha->copp_waitlist, scratch); 1162 } else { 1163 ips_putq_wait_tail(&ha->scb_waitlist, SC); 1164 } 1165 1166 ips_next(ha, IPS_INTR_IORL); 1167 1168 return (0); 1169} 1170 1171/****************************************************************************/ 1172/* */ 1173/* Routine Name: ips_biosparam */ 1174/* */ 1175/* Routine Description: */ 1176/* */ 1177/* Set bios geometry for the controller */ 1178/* */ 1179/****************************************************************************/ 1180static int 1181#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 1182ips_biosparam(Disk * disk, kdev_t dev, int geom[]) 1183{ 1184 ips_ha_t *ha = (ips_ha_t *) disk->device->host->hostdata; 1185 unsigned long capacity = disk->capacity; 1186#else 1187ips_biosparam(struct scsi_device *sdev, struct block_device *bdev, 1188 sector_t capacity, int geom[]) 1189{ 1190 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata; 1191#endif 1192 int heads; 1193 int sectors; 1194 int cylinders; 1195 1196 METHOD_TRACE("ips_biosparam", 1); 1197 1198 if (!ha) 1199 /* ?!?! host adater info invalid */ 1200 return (0); 1201 1202 if (!ha->active) 1203 return (0); 1204 1205 if (!ips_read_adapter_status(ha, IPS_INTR_ON)) 1206 /* ?!?! Enquiry command failed */ 1207 return (0); 1208 1209 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) { 1210 heads = IPS_NORM_HEADS; 1211 sectors = IPS_NORM_SECTORS; 1212 } else { 1213 heads = IPS_COMP_HEADS; 1214 sectors = IPS_COMP_SECTORS; 1215 } 1216 1217 cylinders = (unsigned long) capacity / (heads * sectors); 1218 1219 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d", 1220 heads, sectors, cylinders); 1221 1222 geom[0] = heads; 1223 geom[1] = sectors; 1224 geom[2] = cylinders; 1225 1226 return (0); 1227} 1228 1229#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 1230 1231/* ips_proc24_info is a wrapper around ips_proc_info * 1232 * for compatibility with the 2.4 scsi parameters */ 1233static int 1234ips_proc24_info(char *buffer, char **start, off_t offset, int length, 1235 int hostno, int func) 1236{ 1237 int i; 1238 1239 for (i = 0; i < ips_next_controller; i++) { 1240 if (ips_sh[i] && ips_sh[i]->host_no == hostno) { 1241 return ips_proc_info(ips_sh[i], buffer, start, 1242 offset, length, func); 1243 } 1244 } 1245 return -EINVAL; 1246} 1247 1248/****************************************************************************/ 1249/* */ 1250/* Routine Name: ips_select_queue_depth */ 1251/* */ 1252/* Routine Description: */ 1253/* */ 1254/* Select queue depths for the devices on the contoller */ 1255/* */ 1256/****************************************************************************/ 1257static void 1258ips_select_queue_depth(struct Scsi_Host *host, struct scsi_device * scsi_devs) 1259{ 1260 struct scsi_device *device; 1261 ips_ha_t *ha; 1262 int count = 0; 1263 int min; 1264 1265 ha = IPS_HA(host); 1266 min = ha->max_cmds / 4; 1267 1268 for (device = scsi_devs; device; device = device->next) { 1269 if (device->host == host) { 1270 if ((device->channel == 0) && (device->type == 0)) 1271 count++; 1272 } 1273 } 1274 1275 for (device = scsi_devs; device; device = device->next) { 1276 if (device->host == host) { 1277 if ((device->channel == 0) && (device->type == 0)) { 1278 device->queue_depth = 1279 (ha->max_cmds - 1) / count; 1280 if (device->queue_depth < min) 1281 device->queue_depth = min; 1282 } else { 1283 device->queue_depth = 2; 1284 } 1285 1286 if (device->queue_depth < 2) 1287 device->queue_depth = 2; 1288 } 1289 } 1290} 1291 1292#else 1293/****************************************************************************/ 1294/* */ 1295/* Routine Name: ips_slave_configure */ 1296/* */ 1297/* Routine Description: */ 1298/* */ 1299/* Set queue depths on devices once scan is complete */ 1300/* */ 1301/****************************************************************************/ 1302static int 1303ips_slave_configure(struct scsi_device * SDptr) 1304{ 1305 ips_ha_t *ha; 1306 int min; 1307 1308 ha = IPS_HA(SDptr->host); 1309 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) { 1310 min = ha->max_cmds / 2; 1311 if (ha->enq->ucLogDriveCount <= 2) 1312 min = ha->max_cmds - 1; 1313 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min); 1314 } 1315 1316 SDptr->skip_ms_page_8 = 1; 1317 SDptr->skip_ms_page_3f = 1; 1318 return 0; 1319} 1320#endif 1321 1322/****************************************************************************/ 1323/* */ 1324/* Routine Name: do_ipsintr */ 1325/* */ 1326/* Routine Description: */ 1327/* */ 1328/* Wrapper for the interrupt handler */ 1329/* */ 1330/****************************************************************************/ 1331static irqreturn_t 1332do_ipsintr(int irq, void *dev_id) 1333{ 1334 ips_ha_t *ha; 1335 unsigned long cpu_flags; 1336 struct Scsi_Host *host; 1337 int irqstatus; 1338 1339 METHOD_TRACE("do_ipsintr", 2); 1340 1341 ha = (ips_ha_t *) dev_id; 1342 if (!ha) 1343 return IRQ_NONE; 1344 host = ips_sh[ha->host_num]; 1345 /* interrupt during initialization */ 1346 if (!host) { 1347 (*ha->func.intr) (ha); 1348 return IRQ_HANDLED; 1349 } 1350 1351 IPS_LOCK_SAVE(host->host_lock, cpu_flags); 1352 1353 if (!ha->active) { 1354 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); 1355 return IRQ_HANDLED; 1356 } 1357 1358 irqstatus = (*ha->func.intr) (ha); 1359 1360 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); 1361 1362 /* start the next command */ 1363 ips_next(ha, IPS_INTR_ON); 1364 return IRQ_RETVAL(irqstatus); 1365} 1366 1367/****************************************************************************/ 1368/* */ 1369/* Routine Name: ips_intr_copperhead */ 1370/* */ 1371/* Routine Description: */ 1372/* */ 1373/* Polling interrupt handler */ 1374/* */ 1375/* ASSUMES interrupts are disabled */ 1376/* */ 1377/****************************************************************************/ 1378int 1379ips_intr_copperhead(ips_ha_t * ha) 1380{ 1381 ips_stat_t *sp; 1382 ips_scb_t *scb; 1383 IPS_STATUS cstatus; 1384 int intrstatus; 1385 1386 METHOD_TRACE("ips_intr", 2); 1387 1388 if (!ha) 1389 return 0; 1390 1391 if (!ha->active) 1392 return 0; 1393 1394 intrstatus = (*ha->func.isintr) (ha); 1395 1396 if (!intrstatus) { 1397 /* 1398 * Unexpected/Shared interrupt 1399 */ 1400 1401 return 0; 1402 } 1403 1404 while (TRUE) { 1405 sp = &ha->sp; 1406 1407 intrstatus = (*ha->func.isintr) (ha); 1408 1409 if (!intrstatus) 1410 break; 1411 else 1412 cstatus.value = (*ha->func.statupd) (ha); 1413 1414 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { 1415 /* Spurious Interupt ? */ 1416 continue; 1417 } 1418 1419 ips_chkstatus(ha, &cstatus); 1420 scb = (ips_scb_t *) sp->scb_addr; 1421 1422 /* 1423 * use the callback function to finish things up 1424 * NOTE: interrupts are OFF for this 1425 */ 1426 (*scb->callback) (ha, scb); 1427 } /* end while */ 1428 return 1; 1429} 1430 1431/****************************************************************************/ 1432/* */ 1433/* Routine Name: ips_intr_morpheus */ 1434/* */ 1435/* Routine Description: */ 1436/* */ 1437/* Polling interrupt handler */ 1438/* */ 1439/* ASSUMES interrupts are disabled */ 1440/* */ 1441/****************************************************************************/ 1442int 1443ips_intr_morpheus(ips_ha_t * ha) 1444{ 1445 ips_stat_t *sp; 1446 ips_scb_t *scb; 1447 IPS_STATUS cstatus; 1448 int intrstatus; 1449 1450 METHOD_TRACE("ips_intr_morpheus", 2); 1451 1452 if (!ha) 1453 return 0; 1454 1455 if (!ha->active) 1456 return 0; 1457 1458 intrstatus = (*ha->func.isintr) (ha); 1459 1460 if (!intrstatus) { 1461 /* 1462 * Unexpected/Shared interrupt 1463 */ 1464 1465 return 0; 1466 } 1467 1468 while (TRUE) { 1469 sp = &ha->sp; 1470 1471 intrstatus = (*ha->func.isintr) (ha); 1472 1473 if (!intrstatus) 1474 break; 1475 else 1476 cstatus.value = (*ha->func.statupd) (ha); 1477 1478 if (cstatus.value == 0xffffffff) 1479 /* No more to process */ 1480 break; 1481 1482 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { 1483 IPS_PRINTK(KERN_WARNING, ha->pcidev, 1484 "Spurious interrupt; no ccb.\n"); 1485 1486 continue; 1487 } 1488 1489 ips_chkstatus(ha, &cstatus); 1490 scb = (ips_scb_t *) sp->scb_addr; 1491 1492 /* 1493 * use the callback function to finish things up 1494 * NOTE: interrupts are OFF for this 1495 */ 1496 (*scb->callback) (ha, scb); 1497 } /* end while */ 1498 return 1; 1499} 1500 1501/****************************************************************************/ 1502/* */ 1503/* Routine Name: ips_info */ 1504/* */ 1505/* Routine Description: */ 1506/* */ 1507/* Return info about the driver */ 1508/* */ 1509/****************************************************************************/ 1510static const char * 1511ips_info(struct Scsi_Host *SH) 1512{ 1513 static char buffer[256]; 1514 char *bp; 1515 ips_ha_t *ha; 1516 1517 METHOD_TRACE("ips_info", 1); 1518 1519 ha = IPS_HA(SH); 1520 1521 if (!ha) 1522 return (NULL); 1523 1524 bp = &buffer[0]; 1525 memset(bp, 0, sizeof (buffer)); 1526 1527 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ", 1528 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT); 1529 1530 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) { 1531 strcat(bp, " <"); 1532 strcat(bp, ips_adapter_name[ha->ad_type - 1]); 1533 strcat(bp, ">"); 1534 } 1535 1536 return (bp); 1537} 1538 1539/****************************************************************************/ 1540/* */ 1541/* Routine Name: ips_proc_info */ 1542/* */ 1543/* Routine Description: */ 1544/* */ 1545/* The passthru interface for the driver */ 1546/* */ 1547/****************************************************************************/ 1548static int 1549ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset, 1550 int length, int func) 1551{ 1552 int i; 1553 int ret; 1554 ips_ha_t *ha = NULL; 1555 1556 METHOD_TRACE("ips_proc_info", 1); 1557 1558 /* Find our host structure */ 1559 for (i = 0; i < ips_next_controller; i++) { 1560 if (ips_sh[i]) { 1561 if (ips_sh[i] == host) { 1562 ha = (ips_ha_t *) ips_sh[i]->hostdata; 1563 break; 1564 } 1565 } 1566 } 1567 1568 if (!ha) 1569 return (-EINVAL); 1570 1571 if (func) { 1572 /* write */ 1573 return (0); 1574 } else { 1575 /* read */ 1576 if (start) 1577 *start = buffer; 1578 1579 ret = ips_host_info(ha, buffer, offset, length); 1580 1581 return (ret); 1582 } 1583} 1584 1585/*--------------------------------------------------------------------------*/ 1586/* Helper Functions */ 1587/*--------------------------------------------------------------------------*/ 1588 1589/****************************************************************************/ 1590/* */ 1591/* Routine Name: ips_is_passthru */ 1592/* */ 1593/* Routine Description: */ 1594/* */ 1595/* Determine if the specified SCSI command is really a passthru command */ 1596/* */ 1597/****************************************************************************/ 1598static int ips_is_passthru(struct scsi_cmnd *SC) 1599{ 1600 unsigned long flags; 1601 1602 METHOD_TRACE("ips_is_passthru", 1); 1603 1604 if (!SC) 1605 return (0); 1606 1607 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) && 1608 (SC->device->channel == 0) && 1609 (SC->device->id == IPS_ADAPTER_ID) && 1610 (SC->device->lun == 0) && SC->request_buffer) { 1611 if ((!SC->use_sg) && SC->request_bufflen && 1612 (((char *) SC->request_buffer)[0] == 'C') && 1613 (((char *) SC->request_buffer)[1] == 'O') && 1614 (((char *) SC->request_buffer)[2] == 'P') && 1615 (((char *) SC->request_buffer)[3] == 'P')) 1616 return 1; 1617 else if (SC->use_sg) { 1618 struct scatterlist *sg = SC->request_buffer; 1619 char *buffer; 1620 1621 /* kmap_atomic() ensures addressability of the user buffer.*/ 1622 /* local_irq_save() protects the KM_IRQ0 address slot. */ 1623 local_irq_save(flags); 1624 buffer = kmap_atomic(sg->page, KM_IRQ0) + sg->offset; 1625 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' && 1626 buffer[2] == 'P' && buffer[3] == 'P') { 1627 kunmap_atomic(buffer - sg->offset, KM_IRQ0); 1628 local_irq_restore(flags); 1629 return 1; 1630 } 1631 kunmap_atomic(buffer - sg->offset, KM_IRQ0); 1632 local_irq_restore(flags); 1633 } 1634 } 1635 return 0; 1636} 1637 1638/****************************************************************************/ 1639/* */ 1640/* Routine Name: ips_alloc_passthru_buffer */ 1641/* */ 1642/* Routine Description: */ 1643/* allocate a buffer large enough for the ioctl data if the ioctl buffer */ 1644/* is too small or doesn't exist */ 1645/****************************************************************************/ 1646static int 1647ips_alloc_passthru_buffer(ips_ha_t * ha, int length) 1648{ 1649 void *bigger_buf; 1650 dma_addr_t dma_busaddr; 1651 1652 if (ha->ioctl_data && length <= ha->ioctl_len) 1653 return 0; 1654 /* there is no buffer or it's not big enough, allocate a new one */ 1655 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr); 1656 if (bigger_buf) { 1657 /* free the old memory */ 1658 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data, 1659 ha->ioctl_busaddr); 1660 /* use the new memory */ 1661 ha->ioctl_data = (char *) bigger_buf; 1662 ha->ioctl_len = length; 1663 ha->ioctl_busaddr = dma_busaddr; 1664 } else { 1665 return -1; 1666 } 1667 return 0; 1668} 1669 1670/****************************************************************************/ 1671/* */ 1672/* Routine Name: ips_make_passthru */ 1673/* */ 1674/* Routine Description: */ 1675/* */ 1676/* Make a passthru command out of the info in the Scsi block */ 1677/* */ 1678/****************************************************************************/ 1679static int 1680ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr) 1681{ 1682 ips_passthru_t *pt; 1683 int length = 0; 1684 int ret; 1685 1686 METHOD_TRACE("ips_make_passthru", 1); 1687 1688 if (!SC->use_sg) { 1689 length = SC->request_bufflen; 1690 } else { 1691 struct scatterlist *sg = SC->request_buffer; 1692 int i; 1693 for (i = 0; i < SC->use_sg; i++) 1694 length += sg[i].length; 1695 } 1696 if (length < sizeof (ips_passthru_t)) { 1697 /* wrong size */ 1698 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size", 1699 ips_name, ha->host_num); 1700 return (IPS_FAILURE); 1701 } 1702 if (ips_alloc_passthru_buffer(ha, length)) { 1703 /* allocation failure! If ha->ioctl_data exists, use it to return 1704 some error codes. Return a failed command to the scsi layer. */ 1705 if (ha->ioctl_data) { 1706 pt = (ips_passthru_t *) ha->ioctl_data; 1707 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t)); 1708 pt->BasicStatus = 0x0B; 1709 pt->ExtendedStatus = 0x00; 1710 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t)); 1711 } 1712 return IPS_FAILURE; 1713 } 1714 ha->ioctl_datasize = length; 1715 1716 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize); 1717 pt = (ips_passthru_t *) ha->ioctl_data; 1718 1719 /* 1720 * Some notes about the passthru interface used 1721 * 1722 * IF the scsi op_code == 0x0d then we assume 1723 * that the data came along with/goes with the 1724 * packet we received from the sg driver. In this 1725 * case the CmdBSize field of the pt structure is 1726 * used for the size of the buffer. 1727 */ 1728 1729 switch (pt->CoppCmd) { 1730 case IPS_NUMCTRLS: 1731 memcpy(ha->ioctl_data + sizeof (ips_passthru_t), 1732 &ips_num_controllers, sizeof (int)); 1733 ips_scmd_buf_write(SC, ha->ioctl_data, 1734 sizeof (ips_passthru_t) + sizeof (int)); 1735 SC->result = DID_OK << 16; 1736 1737 return (IPS_SUCCESS_IMM); 1738 1739 case IPS_COPPUSRCMD: 1740 case IPS_COPPIOCCMD: 1741 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) { 1742 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) { 1743 /* wrong size */ 1744 DEBUG_VAR(1, 1745 "(%s%d) Passthru structure wrong size", 1746 ips_name, ha->host_num); 1747 1748 return (IPS_FAILURE); 1749 } 1750 1751 if (ha->device_id == IPS_DEVICEID_COPPERHEAD && 1752 pt->CoppCP.cmd.flashfw.op_code == 1753 IPS_CMD_RW_BIOSFW) { 1754 ret = ips_flash_copperhead(ha, pt, scb); 1755 ips_scmd_buf_write(SC, ha->ioctl_data, 1756 sizeof (ips_passthru_t)); 1757 return ret; 1758 } 1759 if (ips_usrcmd(ha, pt, scb)) 1760 return (IPS_SUCCESS); 1761 else 1762 return (IPS_FAILURE); 1763 } 1764 1765 break; 1766 1767 } /* end switch */ 1768 1769 return (IPS_FAILURE); 1770} 1771 1772/****************************************************************************/ 1773/* Routine Name: ips_flash_copperhead */ 1774/* Routine Description: */ 1775/* Flash the BIOS/FW on a Copperhead style controller */ 1776/****************************************************************************/ 1777static int 1778ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1779{ 1780 int datasize; 1781 1782 /* Trombone is the only copperhead that can do packet flash, but only 1783 * for firmware. No one said it had to make sence. */ 1784 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) { 1785 if (ips_usrcmd(ha, pt, scb)) 1786 return IPS_SUCCESS; 1787 else 1788 return IPS_FAILURE; 1789 } 1790 pt->BasicStatus = 0x0B; 1791 pt->ExtendedStatus = 0; 1792 scb->scsi_cmd->result = DID_OK << 16; 1793 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */ 1794 /* avoid allocating a huge buffer per adapter ( which can fail ). */ 1795 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1796 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { 1797 pt->BasicStatus = 0; 1798 return ips_flash_bios(ha, pt, scb); 1799 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) { 1800 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){ 1801 ha->flash_data = ips_FlashData; 1802 ha->flash_busaddr = ips_flashbusaddr; 1803 ha->flash_len = PAGE_SIZE << 7; 1804 ha->flash_datasize = 0; 1805 } else if (!ha->flash_data) { 1806 datasize = pt->CoppCP.cmd.flashfw.total_packets * 1807 pt->CoppCP.cmd.flashfw.count; 1808 ha->flash_data = pci_alloc_consistent(ha->pcidev, 1809 datasize, 1810 &ha->flash_busaddr); 1811 if (!ha->flash_data){ 1812 printk(KERN_WARNING "Unable to allocate a flash buffer\n"); 1813 return IPS_FAILURE; 1814 } 1815 ha->flash_datasize = 0; 1816 ha->flash_len = datasize; 1817 } else 1818 return IPS_FAILURE; 1819 } else { 1820 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize > 1821 ha->flash_len) { 1822 ips_free_flash_copperhead(ha); 1823 IPS_PRINTK(KERN_WARNING, ha->pcidev, 1824 "failed size sanity check\n"); 1825 return IPS_FAILURE; 1826 } 1827 } 1828 if (!ha->flash_data) 1829 return IPS_FAILURE; 1830 pt->BasicStatus = 0; 1831 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1, 1832 pt->CoppCP.cmd.flashfw.count); 1833 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count; 1834 if (pt->CoppCP.cmd.flashfw.packet_num == 1835 pt->CoppCP.cmd.flashfw.total_packets - 1) { 1836 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE) 1837 return ips_flash_bios(ha, pt, scb); 1838 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) 1839 return ips_flash_firmware(ha, pt, scb); 1840 } 1841 return IPS_SUCCESS_IMM; 1842} 1843 1844/****************************************************************************/ 1845/* Routine Name: ips_flash_bios */ 1846/* Routine Description: */ 1847/* flashes the bios of a copperhead adapter */ 1848/****************************************************************************/ 1849static int 1850ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1851{ 1852 1853 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1854 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) { 1855 if ((!ha->func.programbios) || (!ha->func.erasebios) || 1856 (!ha->func.verifybios)) 1857 goto error; 1858 if ((*ha->func.erasebios) (ha)) { 1859 DEBUG_VAR(1, 1860 "(%s%d) flash bios failed - unable to erase flash", 1861 ips_name, ha->host_num); 1862 goto error; 1863 } else 1864 if ((*ha->func.programbios) (ha, 1865 ha->flash_data + 1866 IPS_BIOS_HEADER, 1867 ha->flash_datasize - 1868 IPS_BIOS_HEADER, 0)) { 1869 DEBUG_VAR(1, 1870 "(%s%d) flash bios failed - unable to flash", 1871 ips_name, ha->host_num); 1872 goto error; 1873 } else 1874 if ((*ha->func.verifybios) (ha, 1875 ha->flash_data + 1876 IPS_BIOS_HEADER, 1877 ha->flash_datasize - 1878 IPS_BIOS_HEADER, 0)) { 1879 DEBUG_VAR(1, 1880 "(%s%d) flash bios failed - unable to verify flash", 1881 ips_name, ha->host_num); 1882 goto error; 1883 } 1884 ips_free_flash_copperhead(ha); 1885 return IPS_SUCCESS_IMM; 1886 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1887 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { 1888 if (!ha->func.erasebios) 1889 goto error; 1890 if ((*ha->func.erasebios) (ha)) { 1891 DEBUG_VAR(1, 1892 "(%s%d) flash bios failed - unable to erase flash", 1893 ips_name, ha->host_num); 1894 goto error; 1895 } 1896 return IPS_SUCCESS_IMM; 1897 } 1898 error: 1899 pt->BasicStatus = 0x0B; 1900 pt->ExtendedStatus = 0x00; 1901 ips_free_flash_copperhead(ha); 1902 return IPS_FAILURE; 1903} 1904 1905/****************************************************************************/ 1906/* */ 1907/* Routine Name: ips_fill_scb_sg_single */ 1908/* */ 1909/* Routine Description: */ 1910/* Fill in a single scb sg_list element from an address */ 1911/* return a -1 if a breakup occurred */ 1912/****************************************************************************/ 1913static int 1914ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr, 1915 ips_scb_t * scb, int indx, unsigned int e_len) 1916{ 1917 1918 int ret_val = 0; 1919 1920 if ((scb->data_len + e_len) > ha->max_xfer) { 1921 e_len = ha->max_xfer - scb->data_len; 1922 scb->breakup = indx; 1923 ++scb->sg_break; 1924 ret_val = -1; 1925 } else { 1926 scb->breakup = 0; 1927 scb->sg_break = 0; 1928 } 1929 if (IPS_USE_ENH_SGLIST(ha)) { 1930 scb->sg_list.enh_list[indx].address_lo = 1931 cpu_to_le32(pci_dma_lo32(busaddr)); 1932 scb->sg_list.enh_list[indx].address_hi = 1933 cpu_to_le32(pci_dma_hi32(busaddr)); 1934 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len); 1935 } else { 1936 scb->sg_list.std_list[indx].address = 1937 cpu_to_le32(pci_dma_lo32(busaddr)); 1938 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len); 1939 } 1940 1941 ++scb->sg_len; 1942 scb->data_len += e_len; 1943 return ret_val; 1944} 1945 1946/****************************************************************************/ 1947/* Routine Name: ips_flash_firmware */ 1948/* Routine Description: */ 1949/* flashes the firmware of a copperhead adapter */ 1950/****************************************************************************/ 1951static int 1952ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1953{ 1954 IPS_SG_LIST sg_list; 1955 uint32_t cmd_busaddr; 1956 1957 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE && 1958 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) { 1959 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND)); 1960 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD; 1961 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize); 1962 } else { 1963 pt->BasicStatus = 0x0B; 1964 pt->ExtendedStatus = 0x00; 1965 ips_free_flash_copperhead(ha); 1966 return IPS_FAILURE; 1967 } 1968 /* Save the S/G list pointer so it doesn't get clobbered */ 1969 sg_list.list = scb->sg_list.list; 1970 cmd_busaddr = scb->scb_busaddr; 1971 /* copy in the CP */ 1972 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); 1973 /* FIX stuff that might be wrong */ 1974 scb->sg_list.list = sg_list.list; 1975 scb->scb_busaddr = cmd_busaddr; 1976 scb->bus = scb->scsi_cmd->device->channel; 1977 scb->target_id = scb->scsi_cmd->device->id; 1978 scb->lun = scb->scsi_cmd->device->lun; 1979 scb->sg_len = 0; 1980 scb->data_len = 0; 1981 scb->flags = 0; 1982 scb->op_code = 0; 1983 scb->callback = ipsintr_done; 1984 scb->timeout = ips_cmd_timeout; 1985 1986 scb->data_len = ha->flash_datasize; 1987 scb->data_busaddr = 1988 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len, 1989 IPS_DMA_DIR(scb)); 1990 scb->flags |= IPS_SCB_MAP_SINGLE; 1991 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); 1992 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr); 1993 if (pt->TimeOut) 1994 scb->timeout = pt->TimeOut; 1995 scb->scsi_cmd->result = DID_OK << 16; 1996 return IPS_SUCCESS; 1997} 1998 1999/****************************************************************************/ 2000/* Routine Name: ips_free_flash_copperhead */ 2001/* Routine Description: */ 2002/* release the memory resources used to hold the flash image */ 2003/****************************************************************************/ 2004static void 2005ips_free_flash_copperhead(ips_ha_t * ha) 2006{ 2007 if (ha->flash_data == ips_FlashData) 2008 test_and_clear_bit(0, &ips_FlashDataInUse); 2009 else if (ha->flash_data) 2010 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data, 2011 ha->flash_busaddr); 2012 ha->flash_data = NULL; 2013} 2014 2015/****************************************************************************/ 2016/* */ 2017/* Routine Name: ips_usrcmd */ 2018/* */ 2019/* Routine Description: */ 2020/* */ 2021/* Process a user command and make it ready to send */ 2022/* */ 2023/****************************************************************************/ 2024static int 2025ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 2026{ 2027 IPS_SG_LIST sg_list; 2028 uint32_t cmd_busaddr; 2029 2030 METHOD_TRACE("ips_usrcmd", 1); 2031 2032 if ((!scb) || (!pt) || (!ha)) 2033 return (0); 2034 2035 /* Save the S/G list pointer so it doesn't get clobbered */ 2036 sg_list.list = scb->sg_list.list; 2037 cmd_busaddr = scb->scb_busaddr; 2038 /* copy in the CP */ 2039 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); 2040 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE)); 2041 2042 /* FIX stuff that might be wrong */ 2043 scb->sg_list.list = sg_list.list; 2044 scb->scb_busaddr = cmd_busaddr; 2045 scb->bus = scb->scsi_cmd->device->channel; 2046 scb->target_id = scb->scsi_cmd->device->id; 2047 scb->lun = scb->scsi_cmd->device->lun; 2048 scb->sg_len = 0; 2049 scb->data_len = 0; 2050 scb->flags = 0; 2051 scb->op_code = 0; 2052 scb->callback = ipsintr_done; 2053 scb->timeout = ips_cmd_timeout; 2054 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 2055 2056 /* we don't support DCDB/READ/WRITE Scatter Gather */ 2057 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) || 2058 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) || 2059 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG)) 2060 return (0); 2061 2062 if (pt->CmdBSize) { 2063 scb->data_len = pt->CmdBSize; 2064 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t); 2065 } else { 2066 scb->data_busaddr = 0L; 2067 } 2068 2069 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) 2070 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + 2071 (unsigned long) &scb-> 2072 dcdb - 2073 (unsigned long) scb); 2074 2075 if (pt->CmdBSize) { 2076 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) 2077 scb->dcdb.buffer_pointer = 2078 cpu_to_le32(scb->data_busaddr); 2079 else 2080 scb->cmd.basic_io.sg_addr = 2081 cpu_to_le32(scb->data_busaddr); 2082 } 2083 2084 /* set timeouts */ 2085 if (pt->TimeOut) { 2086 scb->timeout = pt->TimeOut; 2087 2088 if (pt->TimeOut <= 10) 2089 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; 2090 else if (pt->TimeOut <= 60) 2091 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; 2092 else 2093 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; 2094 } 2095 2096 /* assume success */ 2097 scb->scsi_cmd->result = DID_OK << 16; 2098 2099 /* success */ 2100 return (1); 2101} 2102 2103/****************************************************************************/ 2104/* */ 2105/* Routine Name: ips_cleanup_passthru */ 2106/* */ 2107/* Routine Description: */ 2108/* */ 2109/* Cleanup after a passthru command */ 2110/* */ 2111/****************************************************************************/ 2112static void 2113ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb) 2114{ 2115 ips_passthru_t *pt; 2116 2117 METHOD_TRACE("ips_cleanup_passthru", 1); 2118 2119 if ((!scb) || (!scb->scsi_cmd) || (!scb->scsi_cmd->request_buffer)) { 2120 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru", 2121 ips_name, ha->host_num); 2122 2123 return; 2124 } 2125 pt = (ips_passthru_t *) ha->ioctl_data; 2126 2127 /* Copy data back to the user */ 2128 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */ 2129 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE)); 2130 2131 pt->BasicStatus = scb->basic_status; 2132 pt->ExtendedStatus = scb->extended_status; 2133 pt->AdapterType = ha->ad_type; 2134 2135 if (ha->device_id == IPS_DEVICEID_COPPERHEAD && 2136 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || 2137 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) 2138 ips_free_flash_copperhead(ha); 2139 2140 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize); 2141} 2142 2143/****************************************************************************/ 2144/* */ 2145/* Routine Name: ips_host_info */ 2146/* */ 2147/* Routine Description: */ 2148/* */ 2149/* The passthru interface for the driver */ 2150/* */ 2151/****************************************************************************/ 2152static int 2153ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len) 2154{ 2155 IPS_INFOSTR info; 2156 2157 METHOD_TRACE("ips_host_info", 1); 2158 2159 info.buffer = ptr; 2160 info.length = len; 2161 info.offset = offset; 2162 info.pos = 0; 2163 info.localpos = 0; 2164 2165 copy_info(&info, "\nIBM ServeRAID General Information:\n\n"); 2166 2167 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) && 2168 (le16_to_cpu(ha->nvram->adapter_type) != 0)) 2169 copy_info(&info, "\tController Type : %s\n", 2170 ips_adapter_name[ha->ad_type - 1]); 2171 else 2172 copy_info(&info, 2173 "\tController Type : Unknown\n"); 2174 2175 if (ha->io_addr) 2176 copy_info(&info, 2177 "\tIO region : 0x%lx (%d bytes)\n", 2178 ha->io_addr, ha->io_len); 2179 2180 if (ha->mem_addr) { 2181 copy_info(&info, 2182 "\tMemory region : 0x%lx (%d bytes)\n", 2183 ha->mem_addr, ha->mem_len); 2184 copy_info(&info, 2185 "\tShared memory address : 0x%lx\n", 2186 ha->mem_ptr); 2187 } 2188 2189 copy_info(&info, "\tIRQ number : %d\n", ha->irq); 2190 2191 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ 2192 /* That keeps everything happy for "text" operations on the proc file. */ 2193 2194 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) { 2195 if (ha->nvram->bios_low[3] == 0) { 2196 copy_info(&info, 2197 "\tBIOS Version : %c%c%c%c%c%c%c\n", 2198 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2199 ha->nvram->bios_high[2], ha->nvram->bios_high[3], 2200 ha->nvram->bios_low[0], ha->nvram->bios_low[1], 2201 ha->nvram->bios_low[2]); 2202 2203 } else { 2204 copy_info(&info, 2205 "\tBIOS Version : %c%c%c%c%c%c%c%c\n", 2206 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2207 ha->nvram->bios_high[2], ha->nvram->bios_high[3], 2208 ha->nvram->bios_low[0], ha->nvram->bios_low[1], 2209 ha->nvram->bios_low[2], ha->nvram->bios_low[3]); 2210 } 2211 2212 } 2213 2214 if (ha->enq->CodeBlkVersion[7] == 0) { 2215 copy_info(&info, 2216 "\tFirmware Version : %c%c%c%c%c%c%c\n", 2217 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], 2218 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], 2219 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], 2220 ha->enq->CodeBlkVersion[6]); 2221 } else { 2222 copy_info(&info, 2223 "\tFirmware Version : %c%c%c%c%c%c%c%c\n", 2224 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], 2225 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], 2226 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], 2227 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]); 2228 } 2229 2230 if (ha->enq->BootBlkVersion[7] == 0) { 2231 copy_info(&info, 2232 "\tBoot Block Version : %c%c%c%c%c%c%c\n", 2233 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], 2234 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], 2235 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], 2236 ha->enq->BootBlkVersion[6]); 2237 } else { 2238 copy_info(&info, 2239 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n", 2240 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], 2241 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], 2242 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], 2243 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]); 2244 } 2245 2246 copy_info(&info, "\tDriver Version : %s%s\n", 2247 IPS_VERSION_HIGH, IPS_VERSION_LOW); 2248 2249 copy_info(&info, "\tDriver Build : %d\n", 2250 IPS_BUILD_IDENT); 2251 2252 copy_info(&info, "\tMax Physical Devices : %d\n", 2253 ha->enq->ucMaxPhysicalDevices); 2254 copy_info(&info, "\tMax Active Commands : %d\n", 2255 ha->max_cmds); 2256 copy_info(&info, "\tCurrent Queued Commands : %d\n", 2257 ha->scb_waitlist.count); 2258 copy_info(&info, "\tCurrent Active Commands : %d\n", 2259 ha->scb_activelist.count - ha->num_ioctl); 2260 copy_info(&info, "\tCurrent Queued PT Commands : %d\n", 2261 ha->copp_waitlist.count); 2262 copy_info(&info, "\tCurrent Active PT Commands : %d\n", 2263 ha->num_ioctl); 2264 2265 copy_info(&info, "\n"); 2266 2267 return (info.localpos); 2268} 2269 2270/****************************************************************************/ 2271/* */ 2272/* Routine Name: copy_mem_info */ 2273/* */ 2274/* Routine Description: */ 2275/* */ 2276/* Copy data into an IPS_INFOSTR structure */ 2277/* */ 2278/****************************************************************************/ 2279static void 2280copy_mem_info(IPS_INFOSTR * info, char *data, int len) 2281{ 2282 METHOD_TRACE("copy_mem_info", 1); 2283 2284 if (info->pos + len < info->offset) { 2285 info->pos += len; 2286 return; 2287 } 2288 2289 if (info->pos < info->offset) { 2290 data += (info->offset - info->pos); 2291 len -= (info->offset - info->pos); 2292 info->pos += (info->offset - info->pos); 2293 } 2294 2295 if (info->localpos + len > info->length) 2296 len = info->length - info->localpos; 2297 2298 if (len > 0) { 2299 memcpy(info->buffer + info->localpos, data, len); 2300 info->pos += len; 2301 info->localpos += len; 2302 } 2303} 2304 2305/****************************************************************************/ 2306/* */ 2307/* Routine Name: copy_info */ 2308/* */ 2309/* Routine Description: */ 2310/* */ 2311/* printf style wrapper for an info structure */ 2312/* */ 2313/****************************************************************************/ 2314static int 2315copy_info(IPS_INFOSTR * info, char *fmt, ...) 2316{ 2317 va_list args; 2318 char buf[128]; 2319 int len; 2320 2321 METHOD_TRACE("copy_info", 1); 2322 2323 va_start(args, fmt); 2324 len = vsprintf(buf, fmt, args); 2325 va_end(args); 2326 2327 copy_mem_info(info, buf, len); 2328 2329 return (len); 2330} 2331 2332/****************************************************************************/ 2333/* */ 2334/* Routine Name: ips_identify_controller */ 2335/* */ 2336/* Routine Description: */ 2337/* */ 2338/* Identify this controller */ 2339/* */ 2340/****************************************************************************/ 2341static void 2342ips_identify_controller(ips_ha_t * ha) 2343{ 2344 METHOD_TRACE("ips_identify_controller", 1); 2345 2346 switch (ha->device_id) { 2347 case IPS_DEVICEID_COPPERHEAD: 2348 if (ha->revision_id <= IPS_REVID_SERVERAID) { 2349 ha->ad_type = IPS_ADTYPE_SERVERAID; 2350 } else if (ha->revision_id == IPS_REVID_SERVERAID2) { 2351 ha->ad_type = IPS_ADTYPE_SERVERAID2; 2352 } else if (ha->revision_id == IPS_REVID_NAVAJO) { 2353 ha->ad_type = IPS_ADTYPE_NAVAJO; 2354 } else if ((ha->revision_id == IPS_REVID_SERVERAID2) 2355 && (ha->slot_num == 0)) { 2356 ha->ad_type = IPS_ADTYPE_KIOWA; 2357 } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) && 2358 (ha->revision_id <= IPS_REVID_CLARINETP3)) { 2359 if (ha->enq->ucMaxPhysicalDevices == 15) 2360 ha->ad_type = IPS_ADTYPE_SERVERAID3L; 2361 else 2362 ha->ad_type = IPS_ADTYPE_SERVERAID3; 2363 } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) && 2364 (ha->revision_id <= IPS_REVID_TROMBONE64)) { 2365 ha->ad_type = IPS_ADTYPE_SERVERAID4H; 2366 } 2367 break; 2368 2369 case IPS_DEVICEID_MORPHEUS: 2370 switch (ha->subdevice_id) { 2371 case IPS_SUBDEVICEID_4L: 2372 ha->ad_type = IPS_ADTYPE_SERVERAID4L; 2373 break; 2374 2375 case IPS_SUBDEVICEID_4M: 2376 ha->ad_type = IPS_ADTYPE_SERVERAID4M; 2377 break; 2378 2379 case IPS_SUBDEVICEID_4MX: 2380 ha->ad_type = IPS_ADTYPE_SERVERAID4MX; 2381 break; 2382 2383 case IPS_SUBDEVICEID_4LX: 2384 ha->ad_type = IPS_ADTYPE_SERVERAID4LX; 2385 break; 2386 2387 case IPS_SUBDEVICEID_5I2: 2388 ha->ad_type = IPS_ADTYPE_SERVERAID5I2; 2389 break; 2390 2391 case IPS_SUBDEVICEID_5I1: 2392 ha->ad_type = IPS_ADTYPE_SERVERAID5I1; 2393 break; 2394 } 2395 2396 break; 2397 2398 case IPS_DEVICEID_MARCO: 2399 switch (ha->subdevice_id) { 2400 case IPS_SUBDEVICEID_6M: 2401 ha->ad_type = IPS_ADTYPE_SERVERAID6M; 2402 break; 2403 case IPS_SUBDEVICEID_6I: 2404 ha->ad_type = IPS_ADTYPE_SERVERAID6I; 2405 break; 2406 case IPS_SUBDEVICEID_7k: 2407 ha->ad_type = IPS_ADTYPE_SERVERAID7k; 2408 break; 2409 case IPS_SUBDEVICEID_7M: 2410 ha->ad_type = IPS_ADTYPE_SERVERAID7M; 2411 break; 2412 } 2413 break; 2414 } 2415} 2416 2417/****************************************************************************/ 2418/* */ 2419/* Routine Name: ips_get_bios_version */ 2420/* */ 2421/* Routine Description: */ 2422/* */ 2423/* Get the BIOS revision number */ 2424/* */ 2425/****************************************************************************/ 2426static void 2427ips_get_bios_version(ips_ha_t * ha, int intr) 2428{ 2429 ips_scb_t *scb; 2430 int ret; 2431 uint8_t major; 2432 uint8_t minor; 2433 uint8_t subminor; 2434 uint8_t *buffer; 2435 char hexDigits[] = 2436 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 2437 'D', 'E', 'F' }; 2438 2439 METHOD_TRACE("ips_get_bios_version", 1); 2440 2441 major = 0; 2442 minor = 0; 2443 2444 strncpy(ha->bios_version, " ?", 8); 2445 2446 if (ha->device_id == IPS_DEVICEID_COPPERHEAD) { 2447 if (IPS_USE_MEMIO(ha)) { 2448 /* Memory Mapped I/O */ 2449 2450 /* test 1st byte */ 2451 writel(0, ha->mem_ptr + IPS_REG_FLAP); 2452 if (ha->revision_id == IPS_REVID_TROMBONE64) 2453 udelay(25); /* 25 us */ 2454 2455 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 2456 return; 2457 2458 writel(1, ha->mem_ptr + IPS_REG_FLAP); 2459 if (ha->revision_id == IPS_REVID_TROMBONE64) 2460 udelay(25); /* 25 us */ 2461 2462 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 2463 return; 2464 2465 /* Get Major version */ 2466 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); 2467 if (ha->revision_id == IPS_REVID_TROMBONE64) 2468 udelay(25); /* 25 us */ 2469 2470 major = readb(ha->mem_ptr + IPS_REG_FLDP); 2471 2472 /* Get Minor version */ 2473 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); 2474 if (ha->revision_id == IPS_REVID_TROMBONE64) 2475 udelay(25); /* 25 us */ 2476 minor = readb(ha->mem_ptr + IPS_REG_FLDP); 2477 2478 /* Get SubMinor version */ 2479 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); 2480 if (ha->revision_id == IPS_REVID_TROMBONE64) 2481 udelay(25); /* 25 us */ 2482 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); 2483 2484 } else { 2485 /* Programmed I/O */ 2486 2487 /* test 1st byte */ 2488 outl(0, ha->io_addr + IPS_REG_FLAP); 2489 if (ha->revision_id == IPS_REVID_TROMBONE64) 2490 udelay(25); /* 25 us */ 2491 2492 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 2493 return; 2494 2495 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); 2496 if (ha->revision_id == IPS_REVID_TROMBONE64) 2497 udelay(25); /* 25 us */ 2498 2499 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 2500 return; 2501 2502 /* Get Major version */ 2503 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP); 2504 if (ha->revision_id == IPS_REVID_TROMBONE64) 2505 udelay(25); /* 25 us */ 2506 2507 major = inb(ha->io_addr + IPS_REG_FLDP); 2508 2509 /* Get Minor version */ 2510 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP); 2511 if (ha->revision_id == IPS_REVID_TROMBONE64) 2512 udelay(25); /* 25 us */ 2513 2514 minor = inb(ha->io_addr + IPS_REG_FLDP); 2515 2516 /* Get SubMinor version */ 2517 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP); 2518 if (ha->revision_id == IPS_REVID_TROMBONE64) 2519 udelay(25); /* 25 us */ 2520 2521 subminor = inb(ha->io_addr + IPS_REG_FLDP); 2522 2523 } 2524 } else { 2525 /* Morpheus Family - Send Command to the card */ 2526 2527 buffer = ha->ioctl_data; 2528 2529 memset(buffer, 0, 0x1000); 2530 2531 scb = &ha->scbs[ha->max_cmds - 1]; 2532 2533 ips_init_scb(ha, scb); 2534 2535 scb->timeout = ips_cmd_timeout; 2536 scb->cdb[0] = IPS_CMD_RW_BIOSFW; 2537 2538 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW; 2539 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); 2540 scb->cmd.flashfw.type = 1; 2541 scb->cmd.flashfw.direction = 0; 2542 scb->cmd.flashfw.count = cpu_to_le32(0x800); 2543 scb->cmd.flashfw.total_packets = 1; 2544 scb->cmd.flashfw.packet_num = 0; 2545 scb->data_len = 0x1000; 2546 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr; 2547 2548 /* issue the command */ 2549 if (((ret = 2550 ips_send_wait(ha, scb, ips_cmd_timeout, 2551 intr)) == IPS_FAILURE) 2552 || (ret == IPS_SUCCESS_IMM) 2553 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 2554 /* Error occurred */ 2555 2556 return; 2557 } 2558 2559 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) { 2560 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */ 2561 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */ 2562 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */ 2563 } else { 2564 return; 2565 } 2566 } 2567 2568 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4]; 2569 ha->bios_version[1] = '.'; 2570 ha->bios_version[2] = hexDigits[major & 0x0F]; 2571 ha->bios_version[3] = hexDigits[subminor]; 2572 ha->bios_version[4] = '.'; 2573 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4]; 2574 ha->bios_version[6] = hexDigits[minor & 0x0F]; 2575 ha->bios_version[7] = 0; 2576} 2577 2578/****************************************************************************/ 2579/* */ 2580/* Routine Name: ips_hainit */ 2581/* */ 2582/* Routine Description: */ 2583/* */ 2584/* Initialize the controller */ 2585/* */ 2586/* NOTE: Assumes to be called from with a lock */ 2587/* */ 2588/****************************************************************************/ 2589static int 2590ips_hainit(ips_ha_t * ha) 2591{ 2592 int i; 2593 struct timeval tv; 2594 2595 METHOD_TRACE("ips_hainit", 1); 2596 2597 if (!ha) 2598 return (0); 2599 2600 if (ha->func.statinit) 2601 (*ha->func.statinit) (ha); 2602 2603 if (ha->func.enableint) 2604 (*ha->func.enableint) (ha); 2605 2606 /* Send FFDC */ 2607 ha->reset_count = 1; 2608 do_gettimeofday(&tv); 2609 ha->last_ffdc = tv.tv_sec; 2610 ips_ffdc_reset(ha, IPS_INTR_IORL); 2611 2612 if (!ips_read_config(ha, IPS_INTR_IORL)) { 2613 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2614 "unable to read config from controller.\n"); 2615 2616 return (0); 2617 } 2618 /* end if */ 2619 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) { 2620 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2621 "unable to read controller status.\n"); 2622 2623 return (0); 2624 } 2625 2626 /* Identify this controller */ 2627 ips_identify_controller(ha); 2628 2629 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) { 2630 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2631 "unable to read subsystem parameters.\n"); 2632 2633 return (0); 2634 } 2635 2636 /* write nvram user page 5 */ 2637 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) { 2638 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2639 "unable to write driver info to controller.\n"); 2640 2641 return (0); 2642 } 2643 2644 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */ 2645 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1)) 2646 ips_clear_adapter(ha, IPS_INTR_IORL); 2647 2648 /* set limits on SID, LUN, BUS */ 2649 ha->ntargets = IPS_MAX_TARGETS + 1; 2650 ha->nlun = 1; 2651 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1; 2652 2653 switch (ha->conf->logical_drive[0].ucStripeSize) { 2654 case 4: 2655 ha->max_xfer = 0x10000; 2656 break; 2657 2658 case 5: 2659 ha->max_xfer = 0x20000; 2660 break; 2661 2662 case 6: 2663 ha->max_xfer = 0x40000; 2664 break; 2665 2666 case 7: 2667 default: 2668 ha->max_xfer = 0x80000; 2669 break; 2670 } 2671 2672 /* setup max concurrent commands */ 2673 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) { 2674 /* Use the new method */ 2675 ha->max_cmds = ha->enq->ucConcurrentCmdCount; 2676 } else { 2677 /* use the old method */ 2678 switch (ha->conf->logical_drive[0].ucStripeSize) { 2679 case 4: 2680 ha->max_cmds = 32; 2681 break; 2682 2683 case 5: 2684 ha->max_cmds = 16; 2685 break; 2686 2687 case 6: 2688 ha->max_cmds = 8; 2689 break; 2690 2691 case 7: 2692 default: 2693 ha->max_cmds = 4; 2694 break; 2695 } 2696 } 2697 2698 /* Limit the Active Commands on a Lite Adapter */ 2699 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) || 2700 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) || 2701 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) { 2702 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds)) 2703 ha->max_cmds = MaxLiteCmds; 2704 } 2705 2706 /* set controller IDs */ 2707 ha->ha_id[0] = IPS_ADAPTER_ID; 2708 for (i = 1; i < ha->nbus; i++) { 2709 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f; 2710 ha->dcdb_active[i - 1] = 0; 2711 } 2712 2713 return (1); 2714} 2715 2716/****************************************************************************/ 2717/* */ 2718/* Routine Name: ips_next */ 2719/* */ 2720/* Routine Description: */ 2721/* */ 2722/* Take the next command off the queue and send it to the controller */ 2723/* */ 2724/****************************************************************************/ 2725static void 2726ips_next(ips_ha_t * ha, int intr) 2727{ 2728 ips_scb_t *scb; 2729 struct scsi_cmnd *SC; 2730 struct scsi_cmnd *p; 2731 struct scsi_cmnd *q; 2732 ips_copp_wait_item_t *item; 2733 int ret; 2734 unsigned long cpu_flags = 0; 2735 struct Scsi_Host *host; 2736 METHOD_TRACE("ips_next", 1); 2737 2738 if (!ha) 2739 return; 2740 host = ips_sh[ha->host_num]; 2741 /* 2742 * Block access to the queue function so 2743 * this command won't time out 2744 */ 2745 if (intr == IPS_INTR_ON) 2746 IPS_LOCK_SAVE(host->host_lock, cpu_flags); 2747 2748 if ((ha->subsys->param[3] & 0x300000) 2749 && (ha->scb_activelist.count == 0)) { 2750 struct timeval tv; 2751 2752 do_gettimeofday(&tv); 2753 2754 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) { 2755 ha->last_ffdc = tv.tv_sec; 2756 ips_ffdc_time(ha); 2757 } 2758 } 2759 2760 /* 2761 * Send passthru commands 2762 * These have priority over normal I/O 2763 * but shouldn't affect performance too much 2764 * since we limit the number that can be active 2765 * on the card at any one time 2766 */ 2767 while ((ha->num_ioctl < IPS_MAX_IOCTL) && 2768 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) { 2769 2770 item = ips_removeq_copp_head(&ha->copp_waitlist); 2771 ha->num_ioctl++; 2772 if (intr == IPS_INTR_ON) 2773 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); 2774 scb->scsi_cmd = item->scsi_cmd; 2775 kfree(item); 2776 2777 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr); 2778 2779 if (intr == IPS_INTR_ON) 2780 IPS_LOCK_SAVE(host->host_lock, cpu_flags); 2781 switch (ret) { 2782 case IPS_FAILURE: 2783 if (scb->scsi_cmd) { 2784 scb->scsi_cmd->result = DID_ERROR << 16; 2785 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2786 } 2787 2788 ips_freescb(ha, scb); 2789 break; 2790 case IPS_SUCCESS_IMM: 2791 if (scb->scsi_cmd) { 2792 scb->scsi_cmd->result = DID_OK << 16; 2793 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2794 } 2795 2796 ips_freescb(ha, scb); 2797 break; 2798 default: 2799 break; 2800 } /* end case */ 2801 2802 if (ret != IPS_SUCCESS) { 2803 ha->num_ioctl--; 2804 continue; 2805 } 2806 2807 ret = ips_send_cmd(ha, scb); 2808 2809 if (ret == IPS_SUCCESS) 2810 ips_putq_scb_head(&ha->scb_activelist, scb); 2811 else 2812 ha->num_ioctl--; 2813 2814 switch (ret) { 2815 case IPS_FAILURE: 2816 if (scb->scsi_cmd) { 2817 scb->scsi_cmd->result = DID_ERROR << 16; 2818 } 2819 2820 ips_freescb(ha, scb); 2821 break; 2822 case IPS_SUCCESS_IMM: 2823 ips_freescb(ha, scb); 2824 break; 2825 default: 2826 break; 2827 } /* end case */ 2828 2829 } 2830 2831 /* 2832 * Send "Normal" I/O commands 2833 */ 2834 2835 p = ha->scb_waitlist.head; 2836 while ((p) && (scb = ips_getscb(ha))) { 2837 if ((scmd_channel(p) > 0) 2838 && (ha-> 2839 dcdb_active[scmd_channel(p) - 2840 1] & (1 << scmd_id(p)))) { 2841 ips_freescb(ha, scb); 2842 p = (struct scsi_cmnd *) p->host_scribble; 2843 continue; 2844 } 2845 2846 q = p; 2847 SC = ips_removeq_wait(&ha->scb_waitlist, q); 2848 2849 if (intr == IPS_INTR_ON) 2850 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); /* Unlock HA after command is taken off queue */ 2851 2852 SC->result = DID_OK; 2853 SC->host_scribble = NULL; 2854 2855 memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer)); 2856 2857 scb->target_id = SC->device->id; 2858 scb->lun = SC->device->lun; 2859 scb->bus = SC->device->channel; 2860 scb->scsi_cmd = SC; 2861 scb->breakup = 0; 2862 scb->data_len = 0; 2863 scb->callback = ipsintr_done; 2864 scb->timeout = ips_cmd_timeout; 2865 memset(&scb->cmd, 0, 16); 2866 2867 /* copy in the CDB */ 2868 memcpy(scb->cdb, SC->cmnd, SC->cmd_len); 2869 2870 /* Now handle the data buffer */ 2871 if (SC->use_sg) { 2872 struct scatterlist *sg; 2873 int i; 2874 2875 sg = SC->request_buffer; 2876 scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg, 2877 SC->sc_data_direction); 2878 scb->flags |= IPS_SCB_MAP_SG; 2879 for (i = 0; i < scb->sg_count; i++) { 2880 if (ips_fill_scb_sg_single 2881 (ha, sg_dma_address(&sg[i]), scb, i, 2882 sg_dma_len(&sg[i])) < 0) 2883 break; 2884 } 2885 scb->dcdb.transfer_length = scb->data_len; 2886 } else { 2887 if (SC->request_bufflen) { 2888 scb->data_busaddr = 2889 pci_map_single(ha->pcidev, 2890 SC->request_buffer, 2891 SC->request_bufflen, 2892 SC->sc_data_direction); 2893 scb->flags |= IPS_SCB_MAP_SINGLE; 2894 ips_fill_scb_sg_single(ha, scb->data_busaddr, 2895 scb, 0, 2896 SC->request_bufflen); 2897 scb->dcdb.transfer_length = scb->data_len; 2898 } else { 2899 scb->data_busaddr = 0L; 2900 scb->sg_len = 0; 2901 scb->data_len = 0; 2902 scb->dcdb.transfer_length = 0; 2903 } 2904 2905 } 2906 2907 scb->dcdb.cmd_attribute = 2908 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 2909 2910 /* Allow a WRITE BUFFER Command to Have no Data */ 2911 /* This is Used by Tape Flash Utilites */ 2912 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0)) 2913 scb->dcdb.cmd_attribute = 0; 2914 2915 if (!(scb->dcdb.cmd_attribute & 0x3)) 2916 scb->dcdb.transfer_length = 0; 2917 2918 if (scb->data_len >= IPS_MAX_XFER) { 2919 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; 2920 scb->dcdb.transfer_length = 0; 2921 } 2922 if (intr == IPS_INTR_ON) 2923 IPS_LOCK_SAVE(host->host_lock, cpu_flags); 2924 2925 ret = ips_send_cmd(ha, scb); 2926 2927 switch (ret) { 2928 case IPS_SUCCESS: 2929 ips_putq_scb_head(&ha->scb_activelist, scb); 2930 break; 2931 case IPS_FAILURE: 2932 if (scb->scsi_cmd) { 2933 scb->scsi_cmd->result = DID_ERROR << 16; 2934 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2935 } 2936 2937 if (scb->bus) 2938 ha->dcdb_active[scb->bus - 1] &= 2939 ~(1 << scb->target_id); 2940 2941 ips_freescb(ha, scb); 2942 break; 2943 case IPS_SUCCESS_IMM: 2944 if (scb->scsi_cmd) 2945 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2946 2947 if (scb->bus) 2948 ha->dcdb_active[scb->bus - 1] &= 2949 ~(1 << scb->target_id); 2950 2951 ips_freescb(ha, scb); 2952 break; 2953 default: 2954 break; 2955 } /* end case */ 2956 2957 p = (struct scsi_cmnd *) p->host_scribble; 2958 2959 } /* end while */ 2960 2961 if (intr == IPS_INTR_ON) 2962 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); 2963} 2964 2965/****************************************************************************/ 2966/* */ 2967/* Routine Name: ips_putq_scb_head */ 2968/* */ 2969/* Routine Description: */ 2970/* */ 2971/* Add an item to the head of the queue */ 2972/* */ 2973/* ASSUMED to be called from within the HA lock */ 2974/* */ 2975/****************************************************************************/ 2976static void 2977ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item) 2978{ 2979 METHOD_TRACE("ips_putq_scb_head", 1); 2980 2981 if (!item) 2982 return; 2983 2984 item->q_next = queue->head; 2985 queue->head = item; 2986 2987 if (!queue->tail) 2988 queue->tail = item; 2989 2990 queue->count++; 2991} 2992 2993/****************************************************************************/ 2994/* */ 2995/* Routine Name: ips_removeq_scb_head */ 2996/* */ 2997/* Routine Description: */ 2998/* */ 2999/* Remove the head of the queue */ 3000/* */ 3001/* ASSUMED to be called from within the HA lock */ 3002/* */ 3003/****************************************************************************/ 3004static ips_scb_t * 3005ips_removeq_scb_head(ips_scb_queue_t * queue) 3006{ 3007 ips_scb_t *item; 3008 3009 METHOD_TRACE("ips_removeq_scb_head", 1); 3010 3011 item = queue->head; 3012 3013 if (!item) { 3014 return (NULL); 3015 } 3016 3017 queue->head = item->q_next; 3018 item->q_next = NULL; 3019 3020 if (queue->tail == item) 3021 queue->tail = NULL; 3022 3023 queue->count--; 3024 3025 return (item); 3026} 3027 3028/****************************************************************************/ 3029/* */ 3030/* Routine Name: ips_removeq_scb */ 3031/* */ 3032/* Routine Description: */ 3033/* */ 3034/* Remove an item from a queue */ 3035/* */ 3036/* ASSUMED to be called from within the HA lock */ 3037/* */ 3038/****************************************************************************/ 3039static ips_scb_t * 3040ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item) 3041{ 3042 ips_scb_t *p; 3043 3044 METHOD_TRACE("ips_removeq_scb", 1); 3045 3046 if (!item) 3047 return (NULL); 3048 3049 if (item == queue->head) { 3050 return (ips_removeq_scb_head(queue)); 3051 } 3052 3053 p = queue->head; 3054 3055 while ((p) && (item != p->q_next)) 3056 p = p->q_next; 3057 3058 if (p) { 3059 /* found a match */ 3060 p->q_next = item->q_next; 3061 3062 if (!item->q_next) 3063 queue->tail = p; 3064 3065 item->q_next = NULL; 3066 queue->count--; 3067 3068 return (item); 3069 } 3070 3071 return (NULL); 3072} 3073 3074/****************************************************************************/ 3075/* */ 3076/* Routine Name: ips_putq_wait_tail */ 3077/* */ 3078/* Routine Description: */ 3079/* */ 3080/* Add an item to the tail of the queue */ 3081/* */ 3082/* ASSUMED to be called from within the HA lock */ 3083/* */ 3084/****************************************************************************/ 3085static void ips_putq_wait_tail(ips_wait_queue_t *queue, struct scsi_cmnd *item) 3086{ 3087 METHOD_TRACE("ips_putq_wait_tail", 1); 3088 3089 if (!item) 3090 return; 3091 3092 item->host_scribble = NULL; 3093 3094 if (queue->tail) 3095 queue->tail->host_scribble = (char *) item; 3096 3097 queue->tail = item; 3098 3099 if (!queue->head) 3100 queue->head = item; 3101 3102 queue->count++; 3103} 3104 3105/****************************************************************************/ 3106/* */ 3107/* Routine Name: ips_removeq_wait_head */ 3108/* */ 3109/* Routine Description: */ 3110/* */ 3111/* Remove the head of the queue */ 3112/* */ 3113/* ASSUMED to be called from within the HA lock */ 3114/* */ 3115/****************************************************************************/ 3116static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *queue) 3117{ 3118 struct scsi_cmnd *item; 3119 3120 METHOD_TRACE("ips_removeq_wait_head", 1); 3121 3122 item = queue->head; 3123 3124 if (!item) { 3125 return (NULL); 3126 } 3127 3128 queue->head = (struct scsi_cmnd *) item->host_scribble; 3129 item->host_scribble = NULL; 3130 3131 if (queue->tail == item) 3132 queue->tail = NULL; 3133 3134 queue->count--; 3135 3136 return (item); 3137} 3138 3139/****************************************************************************/ 3140/* */ 3141/* Routine Name: ips_removeq_wait */ 3142/* */ 3143/* Routine Description: */ 3144/* */ 3145/* Remove an item from a queue */ 3146/* */ 3147/* ASSUMED to be called from within the HA lock */ 3148/* */ 3149/****************************************************************************/ 3150static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *queue, 3151 struct scsi_cmnd *item) 3152{ 3153 struct scsi_cmnd *p; 3154 3155 METHOD_TRACE("ips_removeq_wait", 1); 3156 3157 if (!item) 3158 return (NULL); 3159 3160 if (item == queue->head) { 3161 return (ips_removeq_wait_head(queue)); 3162 } 3163 3164 p = queue->head; 3165 3166 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble)) 3167 p = (struct scsi_cmnd *) p->host_scribble; 3168 3169 if (p) { 3170 /* found a match */ 3171 p->host_scribble = item->host_scribble; 3172 3173 if (!item->host_scribble) 3174 queue->tail = p; 3175 3176 item->host_scribble = NULL; 3177 queue->count--; 3178 3179 return (item); 3180 } 3181 3182 return (NULL); 3183} 3184 3185/****************************************************************************/ 3186/* */ 3187/* Routine Name: ips_putq_copp_tail */ 3188/* */ 3189/* Routine Description: */ 3190/* */ 3191/* Add an item to the tail of the queue */ 3192/* */ 3193/* ASSUMED to be called from within the HA lock */ 3194/* */ 3195/****************************************************************************/ 3196static void 3197ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) 3198{ 3199 METHOD_TRACE("ips_putq_copp_tail", 1); 3200 3201 if (!item) 3202 return; 3203 3204 item->next = NULL; 3205 3206 if (queue->tail) 3207 queue->tail->next = item; 3208 3209 queue->tail = item; 3210 3211 if (!queue->head) 3212 queue->head = item; 3213 3214 queue->count++; 3215} 3216 3217/****************************************************************************/ 3218/* */ 3219/* Routine Name: ips_removeq_copp_head */ 3220/* */ 3221/* Routine Description: */ 3222/* */ 3223/* Remove the head of the queue */ 3224/* */ 3225/* ASSUMED to be called from within the HA lock */ 3226/* */ 3227/****************************************************************************/ 3228static ips_copp_wait_item_t * 3229ips_removeq_copp_head(ips_copp_queue_t * queue) 3230{ 3231 ips_copp_wait_item_t *item; 3232 3233 METHOD_TRACE("ips_removeq_copp_head", 1); 3234 3235 item = queue->head; 3236 3237 if (!item) { 3238 return (NULL); 3239 } 3240 3241 queue->head = item->next; 3242 item->next = NULL; 3243 3244 if (queue->tail == item) 3245 queue->tail = NULL; 3246 3247 queue->count--; 3248 3249 return (item); 3250} 3251 3252/****************************************************************************/ 3253/* */ 3254/* Routine Name: ips_removeq_copp */ 3255/* */ 3256/* Routine Description: */ 3257/* */ 3258/* Remove an item from a queue */ 3259/* */ 3260/* ASSUMED to be called from within the HA lock */ 3261/* */ 3262/****************************************************************************/ 3263static ips_copp_wait_item_t * 3264ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) 3265{ 3266 ips_copp_wait_item_t *p; 3267 3268 METHOD_TRACE("ips_removeq_copp", 1); 3269 3270 if (!item) 3271 return (NULL); 3272 3273 if (item == queue->head) { 3274 return (ips_removeq_copp_head(queue)); 3275 } 3276 3277 p = queue->head; 3278 3279 while ((p) && (item != p->next)) 3280 p = p->next; 3281 3282 if (p) { 3283 /* found a match */ 3284 p->next = item->next; 3285 3286 if (!item->next) 3287 queue->tail = p; 3288 3289 item->next = NULL; 3290 queue->count--; 3291 3292 return (item); 3293 } 3294 3295 return (NULL); 3296} 3297 3298/****************************************************************************/ 3299/* */ 3300/* Routine Name: ipsintr_blocking */ 3301/* */ 3302/* Routine Description: */ 3303/* */ 3304/* Finalize an interrupt for internal commands */ 3305/* */ 3306/****************************************************************************/ 3307static void 3308ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb) 3309{ 3310 METHOD_TRACE("ipsintr_blocking", 2); 3311 3312 ips_freescb(ha, scb); 3313 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) { 3314 ha->waitflag = FALSE; 3315 3316 return; 3317 } 3318} 3319 3320/****************************************************************************/ 3321/* */ 3322/* Routine Name: ipsintr_done */ 3323/* */ 3324/* Routine Description: */ 3325/* */ 3326/* Finalize an interrupt for non-internal commands */ 3327/* */ 3328/****************************************************************************/ 3329static void 3330ipsintr_done(ips_ha_t * ha, ips_scb_t * scb) 3331{ 3332 METHOD_TRACE("ipsintr_done", 2); 3333 3334 if (!scb) { 3335 IPS_PRINTK(KERN_WARNING, ha->pcidev, 3336 "Spurious interrupt; scb NULL.\n"); 3337 3338 return; 3339 } 3340 3341 if (scb->scsi_cmd == NULL) { 3342 /* unexpected interrupt */ 3343 IPS_PRINTK(KERN_WARNING, ha->pcidev, 3344 "Spurious interrupt; scsi_cmd not set.\n"); 3345 3346 return; 3347 } 3348 3349 ips_done(ha, scb); 3350} 3351 3352/****************************************************************************/ 3353/* */ 3354/* Routine Name: ips_done */ 3355/* */ 3356/* Routine Description: */ 3357/* */ 3358/* Do housekeeping on completed commands */ 3359/* ASSUMED to be called form within the request lock */ 3360/****************************************************************************/ 3361static void 3362ips_done(ips_ha_t * ha, ips_scb_t * scb) 3363{ 3364 int ret; 3365 3366 METHOD_TRACE("ips_done", 1); 3367 3368 if (!scb) 3369 return; 3370 3371 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) { 3372 ips_cleanup_passthru(ha, scb); 3373 ha->num_ioctl--; 3374 } else { 3375 /* 3376 * Check to see if this command had too much 3377 * data and had to be broke up. If so, queue 3378 * the rest of the data and continue. 3379 */ 3380 if ((scb->breakup) || (scb->sg_break)) { 3381 /* we had a data breakup */ 3382 scb->data_len = 0; 3383 3384 if (scb->sg_count) { 3385 /* S/G request */ 3386 struct scatterlist *sg; 3387 int ips_sg_index = 0; 3388 int sg_dma_index; 3389 3390 sg = scb->scsi_cmd->request_buffer; 3391 3392 /* Spin forward to last dma chunk */ 3393 sg_dma_index = scb->breakup; 3394 3395 /* Take care of possible partial on last chunk */ 3396 ips_fill_scb_sg_single(ha, 3397 sg_dma_address(&sg 3398 [sg_dma_index]), 3399 scb, ips_sg_index++, 3400 sg_dma_len(&sg 3401 [sg_dma_index])); 3402 3403 for (; sg_dma_index < scb->sg_count; 3404 sg_dma_index++) { 3405 if (ips_fill_scb_sg_single 3406 (ha, 3407 sg_dma_address(&sg[sg_dma_index]), 3408 scb, ips_sg_index++, 3409 sg_dma_len(&sg[sg_dma_index])) < 0) 3410 break; 3411 3412 } 3413 3414 } else { 3415 /* Non S/G Request */ 3416 (void) ips_fill_scb_sg_single(ha, 3417 scb-> 3418 data_busaddr + 3419 (scb->sg_break * 3420 ha->max_xfer), 3421 scb, 0, 3422 scb->scsi_cmd-> 3423 request_bufflen - 3424 (scb->sg_break * 3425 ha->max_xfer)); 3426 } 3427 3428 scb->dcdb.transfer_length = scb->data_len; 3429 scb->dcdb.cmd_attribute |= 3430 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 3431 3432 if (!(scb->dcdb.cmd_attribute & 0x3)) 3433 scb->dcdb.transfer_length = 0; 3434 3435 if (scb->data_len >= IPS_MAX_XFER) { 3436 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; 3437 scb->dcdb.transfer_length = 0; 3438 } 3439 3440 ret = ips_send_cmd(ha, scb); 3441 3442 switch (ret) { 3443 case IPS_FAILURE: 3444 if (scb->scsi_cmd) { 3445 scb->scsi_cmd->result = DID_ERROR << 16; 3446 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3447 } 3448 3449 ips_freescb(ha, scb); 3450 break; 3451 case IPS_SUCCESS_IMM: 3452 if (scb->scsi_cmd) { 3453 scb->scsi_cmd->result = DID_ERROR << 16; 3454 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3455 } 3456 3457 ips_freescb(ha, scb); 3458 break; 3459 default: 3460 break; 3461 } /* end case */ 3462 3463 return; 3464 } 3465 } /* end if passthru */ 3466 3467 if (scb->bus) { 3468 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id); 3469 } 3470 3471 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3472 3473 ips_freescb(ha, scb); 3474} 3475 3476/****************************************************************************/ 3477/* */ 3478/* Routine Name: ips_map_status */ 3479/* */ 3480/* Routine Description: */ 3481/* */ 3482/* Map Controller Error codes to Linux Error Codes */ 3483/* */ 3484/****************************************************************************/ 3485static int 3486ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp) 3487{ 3488 int errcode; 3489 int device_error; 3490 uint32_t transfer_len; 3491 IPS_DCDB_TABLE_TAPE *tapeDCDB; 3492 IPS_SCSI_INQ_DATA inquiryData; 3493 3494 METHOD_TRACE("ips_map_status", 1); 3495 3496 if (scb->bus) { 3497 DEBUG_VAR(2, 3498 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x", 3499 ips_name, ha->host_num, 3500 scb->scsi_cmd->device->channel, 3501 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun, 3502 scb->basic_status, scb->extended_status, 3503 scb->extended_status == 3504 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0, 3505 scb->extended_status == 3506 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0, 3507 scb->extended_status == 3508 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0); 3509 } 3510 3511 /* default driver error */ 3512 errcode = DID_ERROR; 3513 device_error = 0; 3514 3515 switch (scb->basic_status & IPS_GSC_STATUS_MASK) { 3516 case IPS_CMD_TIMEOUT: 3517 errcode = DID_TIME_OUT; 3518 break; 3519 3520 case IPS_INVAL_OPCO: 3521 case IPS_INVAL_CMD_BLK: 3522 case IPS_INVAL_PARM_BLK: 3523 case IPS_LD_ERROR: 3524 case IPS_CMD_CMPLT_WERROR: 3525 break; 3526 3527 case IPS_PHYS_DRV_ERROR: 3528 switch (scb->extended_status) { 3529 case IPS_ERR_SEL_TO: 3530 if (scb->bus) 3531 errcode = DID_NO_CONNECT; 3532 3533 break; 3534 3535 case IPS_ERR_OU_RUN: 3536 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) || 3537 (scb->cmd.dcdb.op_code == 3538 IPS_CMD_EXTENDED_DCDB_SG)) { 3539 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3540 transfer_len = tapeDCDB->transfer_length; 3541 } else { 3542 transfer_len = 3543 (uint32_t) scb->dcdb.transfer_length; 3544 } 3545 3546 if ((scb->bus) && (transfer_len < scb->data_len)) { 3547 /* Underrun - set default to no error */ 3548 errcode = DID_OK; 3549 3550 /* Restrict access to physical DASD */ 3551 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3552 ips_scmd_buf_read(scb->scsi_cmd, 3553 &inquiryData, sizeof (inquiryData)); 3554 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) { 3555 errcode = DID_TIME_OUT; 3556 break; 3557 } 3558 } 3559 } else 3560 errcode = DID_ERROR; 3561 3562 break; 3563 3564 case IPS_ERR_RECOVERY: 3565 /* don't fail recovered errors */ 3566 if (scb->bus) 3567 errcode = DID_OK; 3568 3569 break; 3570 3571 case IPS_ERR_HOST_RESET: 3572 case IPS_ERR_DEV_RESET: 3573 errcode = DID_RESET; 3574 break; 3575 3576 case IPS_ERR_CKCOND: 3577 if (scb->bus) { 3578 if ((scb->cmd.dcdb.op_code == 3579 IPS_CMD_EXTENDED_DCDB) 3580 || (scb->cmd.dcdb.op_code == 3581 IPS_CMD_EXTENDED_DCDB_SG)) { 3582 tapeDCDB = 3583 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3584 memcpy(scb->scsi_cmd->sense_buffer, 3585 tapeDCDB->sense_info, 3586 sizeof (scb->scsi_cmd-> 3587 sense_buffer)); 3588 } else { 3589 memcpy(scb->scsi_cmd->sense_buffer, 3590 scb->dcdb.sense_info, 3591 sizeof (scb->scsi_cmd-> 3592 sense_buffer)); 3593 } 3594 device_error = 2; /* check condition */ 3595 } 3596 3597 errcode = DID_OK; 3598 3599 break; 3600 3601 default: 3602 errcode = DID_ERROR; 3603 break; 3604 3605 } /* end switch */ 3606 } /* end switch */ 3607 3608 scb->scsi_cmd->result = device_error | (errcode << 16); 3609 3610 return (1); 3611} 3612 3613/****************************************************************************/ 3614/* */ 3615/* Routine Name: ips_send_wait */ 3616/* */ 3617/* Routine Description: */ 3618/* */ 3619/* Send a command to the controller and wait for it to return */ 3620/* */ 3621/* The FFDC Time Stamp use this function for the callback, but doesn't */ 3622/* actually need to wait. */ 3623/****************************************************************************/ 3624static int 3625ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr) 3626{ 3627 int ret; 3628 3629 METHOD_TRACE("ips_send_wait", 1); 3630 3631 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */ 3632 ha->waitflag = TRUE; 3633 ha->cmd_in_progress = scb->cdb[0]; 3634 } 3635 scb->callback = ipsintr_blocking; 3636 ret = ips_send_cmd(ha, scb); 3637 3638 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)) 3639 return (ret); 3640 3641 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */ 3642 ret = ips_wait(ha, timeout, intr); 3643 3644 return (ret); 3645} 3646 3647/****************************************************************************/ 3648/* */ 3649/* Routine Name: ips_scmd_buf_write */ 3650/* */ 3651/* Routine Description: */ 3652/* Write data to struct scsi_cmnd request_buffer at proper offsets */ 3653/****************************************************************************/ 3654static void 3655ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count) 3656{ 3657 if (scmd->use_sg) { 3658 int i; 3659 unsigned int min_cnt, xfer_cnt; 3660 char *cdata = (char *) data; 3661 unsigned char *buffer; 3662 unsigned long flags; 3663 struct scatterlist *sg = scmd->request_buffer; 3664 for (i = 0, xfer_cnt = 0; 3665 (i < scmd->use_sg) && (xfer_cnt < count); i++) { 3666 min_cnt = min(count - xfer_cnt, sg[i].length); 3667 3668 /* kmap_atomic() ensures addressability of the data buffer.*/ 3669 /* local_irq_save() protects the KM_IRQ0 address slot. */ 3670 local_irq_save(flags); 3671 buffer = kmap_atomic(sg[i].page, KM_IRQ0) + sg[i].offset; 3672 memcpy(buffer, &cdata[xfer_cnt], min_cnt); 3673 kunmap_atomic(buffer - sg[i].offset, KM_IRQ0); 3674 local_irq_restore(flags); 3675 3676 xfer_cnt += min_cnt; 3677 } 3678 3679 } else { 3680 unsigned int min_cnt = min(count, scmd->request_bufflen); 3681 memcpy(scmd->request_buffer, data, min_cnt); 3682 } 3683} 3684 3685/****************************************************************************/ 3686/* */ 3687/* Routine Name: ips_scmd_buf_read */ 3688/* */ 3689/* Routine Description: */ 3690/* Copy data from a struct scsi_cmnd to a new, linear buffer */ 3691/****************************************************************************/ 3692static void 3693ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count) 3694{ 3695 if (scmd->use_sg) { 3696 int i; 3697 unsigned int min_cnt, xfer_cnt; 3698 char *cdata = (char *) data; 3699 unsigned char *buffer; 3700 unsigned long flags; 3701 struct scatterlist *sg = scmd->request_buffer; 3702 for (i = 0, xfer_cnt = 0; 3703 (i < scmd->use_sg) && (xfer_cnt < count); i++) { 3704 min_cnt = min(count - xfer_cnt, sg[i].length); 3705 3706 /* kmap_atomic() ensures addressability of the data buffer.*/ 3707 /* local_irq_save() protects the KM_IRQ0 address slot. */ 3708 local_irq_save(flags); 3709 buffer = kmap_atomic(sg[i].page, KM_IRQ0) + sg[i].offset; 3710 memcpy(&cdata[xfer_cnt], buffer, min_cnt); 3711 kunmap_atomic(buffer - sg[i].offset, KM_IRQ0); 3712 local_irq_restore(flags); 3713 3714 xfer_cnt += min_cnt; 3715 } 3716 3717 } else { 3718 unsigned int min_cnt = min(count, scmd->request_bufflen); 3719 memcpy(data, scmd->request_buffer, min_cnt); 3720 } 3721} 3722 3723/****************************************************************************/ 3724/* */ 3725/* Routine Name: ips_send_cmd */ 3726/* */ 3727/* Routine Description: */ 3728/* */ 3729/* Map SCSI commands to ServeRAID commands for logical drives */ 3730/* */ 3731/****************************************************************************/ 3732static int 3733ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb) 3734{ 3735 int ret; 3736 char *sp; 3737 int device_error; 3738 IPS_DCDB_TABLE_TAPE *tapeDCDB; 3739 int TimeOut; 3740 3741 METHOD_TRACE("ips_send_cmd", 1); 3742 3743 ret = IPS_SUCCESS; 3744 3745 if (!scb->scsi_cmd) { 3746 /* internal command */ 3747 3748 if (scb->bus > 0) { 3749 /* Controller commands can't be issued */ 3750 /* to real devices -- fail them */ 3751 if ((ha->waitflag == TRUE) && 3752 (ha->cmd_in_progress == scb->cdb[0])) { 3753 ha->waitflag = FALSE; 3754 } 3755 3756 return (1); 3757 } 3758 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) { 3759 /* command to logical bus -- interpret */ 3760 ret = IPS_SUCCESS_IMM; 3761 3762 switch (scb->scsi_cmd->cmnd[0]) { 3763 case ALLOW_MEDIUM_REMOVAL: 3764 case REZERO_UNIT: 3765 case ERASE: 3766 case WRITE_FILEMARKS: 3767 case SPACE: 3768 scb->scsi_cmd->result = DID_ERROR << 16; 3769 break; 3770 3771 case START_STOP: 3772 scb->scsi_cmd->result = DID_OK << 16; 3773 3774 case TEST_UNIT_READY: 3775 case INQUIRY: 3776 if (scb->target_id == IPS_ADAPTER_ID) { 3777 /* 3778 * Either we have a TUR 3779 * or we have a SCSI inquiry 3780 */ 3781 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY) 3782 scb->scsi_cmd->result = DID_OK << 16; 3783 3784 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3785 IPS_SCSI_INQ_DATA inquiry; 3786 3787 memset(&inquiry, 0, 3788 sizeof (IPS_SCSI_INQ_DATA)); 3789 3790 inquiry.DeviceType = 3791 IPS_SCSI_INQ_TYPE_PROCESSOR; 3792 inquiry.DeviceTypeQualifier = 3793 IPS_SCSI_INQ_LU_CONNECTED; 3794 inquiry.Version = IPS_SCSI_INQ_REV2; 3795 inquiry.ResponseDataFormat = 3796 IPS_SCSI_INQ_RD_REV2; 3797 inquiry.AdditionalLength = 31; 3798 inquiry.Flags[0] = 3799 IPS_SCSI_INQ_Address16; 3800 inquiry.Flags[1] = 3801 IPS_SCSI_INQ_WBus16 | 3802 IPS_SCSI_INQ_Sync; 3803 strncpy(inquiry.VendorId, "IBM ", 3804 8); 3805 strncpy(inquiry.ProductId, 3806 "SERVERAID ", 16); 3807 strncpy(inquiry.ProductRevisionLevel, 3808 "1.00", 4); 3809 3810 ips_scmd_buf_write(scb->scsi_cmd, 3811 &inquiry, 3812 sizeof (inquiry)); 3813 3814 scb->scsi_cmd->result = DID_OK << 16; 3815 } 3816 } else { 3817 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; 3818 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); 3819 scb->cmd.logical_info.reserved = 0; 3820 scb->cmd.logical_info.reserved2 = 0; 3821 scb->data_len = sizeof (IPS_LD_INFO); 3822 scb->data_busaddr = ha->logical_drive_info_dma_addr; 3823 scb->flags = 0; 3824 scb->cmd.logical_info.buffer_addr = scb->data_busaddr; 3825 ret = IPS_SUCCESS; 3826 } 3827 3828 break; 3829 3830 case REQUEST_SENSE: 3831 ips_reqsen(ha, scb); 3832 scb->scsi_cmd->result = DID_OK << 16; 3833 break; 3834 3835 case READ_6: 3836 case WRITE_6: 3837 if (!scb->sg_len) { 3838 scb->cmd.basic_io.op_code = 3839 (scb->scsi_cmd->cmnd[0] == 3840 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE; 3841 scb->cmd.basic_io.enhanced_sg = 0; 3842 scb->cmd.basic_io.sg_addr = 3843 cpu_to_le32(scb->data_busaddr); 3844 } else { 3845 scb->cmd.basic_io.op_code = 3846 (scb->scsi_cmd->cmnd[0] == 3847 READ_6) ? IPS_CMD_READ_SG : 3848 IPS_CMD_WRITE_SG; 3849 scb->cmd.basic_io.enhanced_sg = 3850 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3851 scb->cmd.basic_io.sg_addr = 3852 cpu_to_le32(scb->sg_busaddr); 3853 } 3854 3855 scb->cmd.basic_io.segment_4G = 0; 3856 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3857 scb->cmd.basic_io.log_drv = scb->target_id; 3858 scb->cmd.basic_io.sg_count = scb->sg_len; 3859 3860 if (scb->cmd.basic_io.lba) 3861 scb->cmd.basic_io.lba = 3862 cpu_to_le32(le32_to_cpu 3863 (scb->cmd.basic_io.lba) + 3864 le16_to_cpu(scb->cmd.basic_io. 3865 sector_count)); 3866 else 3867 scb->cmd.basic_io.lba = 3868 (((scb->scsi_cmd-> 3869 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd-> 3870 cmnd[2] << 8) | 3871 (scb->scsi_cmd->cmnd[3])); 3872 3873 scb->cmd.basic_io.sector_count = 3874 cpu_to_le16(scb->data_len / IPS_BLKSIZE); 3875 3876 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0) 3877 scb->cmd.basic_io.sector_count = 3878 cpu_to_le16(256); 3879 3880 ret = IPS_SUCCESS; 3881 break; 3882 3883 case READ_10: 3884 case WRITE_10: 3885 if (!scb->sg_len) { 3886 scb->cmd.basic_io.op_code = 3887 (scb->scsi_cmd->cmnd[0] == 3888 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE; 3889 scb->cmd.basic_io.enhanced_sg = 0; 3890 scb->cmd.basic_io.sg_addr = 3891 cpu_to_le32(scb->data_busaddr); 3892 } else { 3893 scb->cmd.basic_io.op_code = 3894 (scb->scsi_cmd->cmnd[0] == 3895 READ_10) ? IPS_CMD_READ_SG : 3896 IPS_CMD_WRITE_SG; 3897 scb->cmd.basic_io.enhanced_sg = 3898 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3899 scb->cmd.basic_io.sg_addr = 3900 cpu_to_le32(scb->sg_busaddr); 3901 } 3902 3903 scb->cmd.basic_io.segment_4G = 0; 3904 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3905 scb->cmd.basic_io.log_drv = scb->target_id; 3906 scb->cmd.basic_io.sg_count = scb->sg_len; 3907 3908 if (scb->cmd.basic_io.lba) 3909 scb->cmd.basic_io.lba = 3910 cpu_to_le32(le32_to_cpu 3911 (scb->cmd.basic_io.lba) + 3912 le16_to_cpu(scb->cmd.basic_io. 3913 sector_count)); 3914 else 3915 scb->cmd.basic_io.lba = 3916 ((scb->scsi_cmd->cmnd[2] << 24) | (scb-> 3917 scsi_cmd-> 3918 cmnd[3] 3919 << 16) | 3920 (scb->scsi_cmd->cmnd[4] << 8) | scb-> 3921 scsi_cmd->cmnd[5]); 3922 3923 scb->cmd.basic_io.sector_count = 3924 cpu_to_le16(scb->data_len / IPS_BLKSIZE); 3925 3926 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) { 3927 /* 3928 * This is a null condition 3929 * we don't have to do anything 3930 * so just return 3931 */ 3932 scb->scsi_cmd->result = DID_OK << 16; 3933 } else 3934 ret = IPS_SUCCESS; 3935 3936 break; 3937 3938 case RESERVE: 3939 case RELEASE: 3940 scb->scsi_cmd->result = DID_OK << 16; 3941 break; 3942 3943 case MODE_SENSE: 3944 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; 3945 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3946 scb->cmd.basic_io.segment_4G = 0; 3947 scb->cmd.basic_io.enhanced_sg = 0; 3948 scb->data_len = sizeof (*ha->enq); 3949 scb->cmd.basic_io.sg_addr = ha->enq_busaddr; 3950 ret = IPS_SUCCESS; 3951 break; 3952 3953 case READ_CAPACITY: 3954 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; 3955 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); 3956 scb->cmd.logical_info.reserved = 0; 3957 scb->cmd.logical_info.reserved2 = 0; 3958 scb->cmd.logical_info.reserved3 = 0; 3959 scb->data_len = sizeof (IPS_LD_INFO); 3960 scb->data_busaddr = ha->logical_drive_info_dma_addr; 3961 scb->flags = 0; 3962 scb->cmd.logical_info.buffer_addr = scb->data_busaddr; 3963 ret = IPS_SUCCESS; 3964 break; 3965 3966 case SEND_DIAGNOSTIC: 3967 case REASSIGN_BLOCKS: 3968 case FORMAT_UNIT: 3969 case SEEK_10: 3970 case VERIFY: 3971 case READ_DEFECT_DATA: 3972 case READ_BUFFER: 3973 case WRITE_BUFFER: 3974 scb->scsi_cmd->result = DID_OK << 16; 3975 break; 3976 3977 default: 3978 /* Set the Return Info to appear like the Command was */ 3979 /* attempted, a Check Condition occurred, and Sense */ 3980 /* Data indicating an Invalid CDB OpCode is returned. */ 3981 sp = (char *) scb->scsi_cmd->sense_buffer; 3982 memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer)); 3983 3984 sp[0] = 0x70; /* Error Code */ 3985 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */ 3986 sp[7] = 0x0A; /* Additional Sense Length */ 3987 sp[12] = 0x20; /* ASC = Invalid OpCode */ 3988 sp[13] = 0x00; /* ASCQ */ 3989 3990 device_error = 2; /* Indicate Check Condition */ 3991 scb->scsi_cmd->result = device_error | (DID_OK << 16); 3992 break; 3993 } /* end switch */ 3994 } 3995 /* end if */ 3996 if (ret == IPS_SUCCESS_IMM) 3997 return (ret); 3998 3999 /* setup DCDB */ 4000 if (scb->bus > 0) { 4001 4002 /* If we already know the Device is Not there, no need to attempt a Command */ 4003 /* This also protects an NT FailOver Controller from getting CDB's sent to it */ 4004 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) { 4005 scb->scsi_cmd->result = DID_NO_CONNECT << 16; 4006 return (IPS_SUCCESS_IMM); 4007 } 4008 4009 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id); 4010 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb); 4011 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + 4012 (unsigned long) &scb-> 4013 dcdb - 4014 (unsigned long) scb); 4015 scb->cmd.dcdb.reserved = 0; 4016 scb->cmd.dcdb.reserved2 = 0; 4017 scb->cmd.dcdb.reserved3 = 0; 4018 scb->cmd.dcdb.segment_4G = 0; 4019 scb->cmd.dcdb.enhanced_sg = 0; 4020 4021 TimeOut = scb->scsi_cmd->timeout_per_command; 4022 4023 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */ 4024 if (!scb->sg_len) { 4025 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB; 4026 } else { 4027 scb->cmd.dcdb.op_code = 4028 IPS_CMD_EXTENDED_DCDB_SG; 4029 scb->cmd.dcdb.enhanced_sg = 4030 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 4031 } 4032 4033 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */ 4034 tapeDCDB->device_address = 4035 ((scb->bus - 1) << 4) | scb->target_id; 4036 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED; 4037 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */ 4038 4039 if (TimeOut) { 4040 if (TimeOut < (10 * HZ)) 4041 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ 4042 else if (TimeOut < (60 * HZ)) 4043 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ 4044 else if (TimeOut < (1200 * HZ)) 4045 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ 4046 } 4047 4048 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len; 4049 tapeDCDB->reserved_for_LUN = 0; 4050 tapeDCDB->transfer_length = scb->data_len; 4051 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG) 4052 tapeDCDB->buffer_pointer = 4053 cpu_to_le32(scb->sg_busaddr); 4054 else 4055 tapeDCDB->buffer_pointer = 4056 cpu_to_le32(scb->data_busaddr); 4057 tapeDCDB->sg_count = scb->sg_len; 4058 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info); 4059 tapeDCDB->scsi_status = 0; 4060 tapeDCDB->reserved = 0; 4061 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd, 4062 scb->scsi_cmd->cmd_len); 4063 } else { 4064 if (!scb->sg_len) { 4065 scb->cmd.dcdb.op_code = IPS_CMD_DCDB; 4066 } else { 4067 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG; 4068 scb->cmd.dcdb.enhanced_sg = 4069 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 4070 } 4071 4072 scb->dcdb.device_address = 4073 ((scb->bus - 1) << 4) | scb->target_id; 4074 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED; 4075 4076 if (TimeOut) { 4077 if (TimeOut < (10 * HZ)) 4078 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ 4079 else if (TimeOut < (60 * HZ)) 4080 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ 4081 else if (TimeOut < (1200 * HZ)) 4082 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ 4083 } 4084 4085 scb->dcdb.transfer_length = scb->data_len; 4086 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K) 4087 scb->dcdb.transfer_length = 0; 4088 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG) 4089 scb->dcdb.buffer_pointer = 4090 cpu_to_le32(scb->sg_busaddr); 4091 else 4092 scb->dcdb.buffer_pointer = 4093 cpu_to_le32(scb->data_busaddr); 4094 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len; 4095 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info); 4096 scb->dcdb.sg_count = scb->sg_len; 4097 scb->dcdb.reserved = 0; 4098 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd, 4099 scb->scsi_cmd->cmd_len); 4100 scb->dcdb.scsi_status = 0; 4101 scb->dcdb.reserved2[0] = 0; 4102 scb->dcdb.reserved2[1] = 0; 4103 scb->dcdb.reserved2[2] = 0; 4104 } 4105 } 4106 4107 return ((*ha->func.issue) (ha, scb)); 4108} 4109 4110/****************************************************************************/ 4111/* */ 4112/* Routine Name: ips_chk_status */ 4113/* */ 4114/* Routine Description: */ 4115/* */ 4116/* Check the status of commands to logical drives */ 4117/* Assumed to be called with the HA lock */ 4118/****************************************************************************/ 4119static void 4120ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus) 4121{ 4122 ips_scb_t *scb; 4123 ips_stat_t *sp; 4124 uint8_t basic_status; 4125 uint8_t ext_status; 4126 int errcode; 4127 IPS_SCSI_INQ_DATA inquiryData; 4128 4129 METHOD_TRACE("ips_chkstatus", 1); 4130 4131 scb = &ha->scbs[pstatus->fields.command_id]; 4132 scb->basic_status = basic_status = 4133 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK; 4134 scb->extended_status = ext_status = pstatus->fields.extended_status; 4135 4136 sp = &ha->sp; 4137 sp->residue_len = 0; 4138 sp->scb_addr = (void *) scb; 4139 4140 /* Remove the item from the active queue */ 4141 ips_removeq_scb(&ha->scb_activelist, scb); 4142 4143 if (!scb->scsi_cmd) 4144 /* internal commands are handled in do_ipsintr */ 4145 return; 4146 4147 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)", 4148 ips_name, 4149 ha->host_num, 4150 scb->cdb[0], 4151 scb->cmd.basic_io.command_id, 4152 scb->bus, scb->target_id, scb->lun); 4153 4154 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) 4155 /* passthru - just returns the raw result */ 4156 return; 4157 4158 errcode = DID_OK; 4159 4160 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) || 4161 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) { 4162 4163 if (scb->bus == 0) { 4164 if ((basic_status & IPS_GSC_STATUS_MASK) == 4165 IPS_CMD_RECOVERED_ERROR) { 4166 DEBUG_VAR(1, 4167 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", 4168 ips_name, ha->host_num, 4169 scb->cmd.basic_io.op_code, 4170 basic_status, ext_status); 4171 } 4172 4173 switch (scb->scsi_cmd->cmnd[0]) { 4174 case ALLOW_MEDIUM_REMOVAL: 4175 case REZERO_UNIT: 4176 case ERASE: 4177 case WRITE_FILEMARKS: 4178 case SPACE: 4179 errcode = DID_ERROR; 4180 break; 4181 4182 case START_STOP: 4183 break; 4184 4185 case TEST_UNIT_READY: 4186 if (!ips_online(ha, scb)) { 4187 errcode = DID_TIME_OUT; 4188 } 4189 break; 4190 4191 case INQUIRY: 4192 if (ips_online(ha, scb)) { 4193 ips_inquiry(ha, scb); 4194 } else { 4195 errcode = DID_TIME_OUT; 4196 } 4197 break; 4198 4199 case REQUEST_SENSE: 4200 ips_reqsen(ha, scb); 4201 break; 4202 4203 case READ_6: 4204 case WRITE_6: 4205 case READ_10: 4206 case WRITE_10: 4207 case RESERVE: 4208 case RELEASE: 4209 break; 4210 4211 case MODE_SENSE: 4212 if (!ips_online(ha, scb) 4213 || !ips_msense(ha, scb)) { 4214 errcode = DID_ERROR; 4215 } 4216 break; 4217 4218 case READ_CAPACITY: 4219 if (ips_online(ha, scb)) 4220 ips_rdcap(ha, scb); 4221 else { 4222 errcode = DID_TIME_OUT; 4223 } 4224 break; 4225 4226 case SEND_DIAGNOSTIC: 4227 case REASSIGN_BLOCKS: 4228 break; 4229 4230 case FORMAT_UNIT: 4231 errcode = DID_ERROR; 4232 break; 4233 4234 case SEEK_10: 4235 case VERIFY: 4236 case READ_DEFECT_DATA: 4237 case READ_BUFFER: 4238 case WRITE_BUFFER: 4239 break; 4240 4241 default: 4242 errcode = DID_ERROR; 4243 } /* end switch */ 4244 4245 scb->scsi_cmd->result = errcode << 16; 4246 } else { /* bus == 0 */ 4247 /* restrict access to physical drives */ 4248 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 4249 ips_scmd_buf_read(scb->scsi_cmd, 4250 &inquiryData, sizeof (inquiryData)); 4251 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) 4252 scb->scsi_cmd->result = DID_TIME_OUT << 16; 4253 } 4254 } /* else */ 4255 } else { /* recovered error / success */ 4256 if (scb->bus == 0) { 4257 DEBUG_VAR(1, 4258 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", 4259 ips_name, ha->host_num, 4260 scb->cmd.basic_io.op_code, basic_status, 4261 ext_status); 4262 } 4263 4264 ips_map_status(ha, scb, sp); 4265 } /* else */ 4266} 4267 4268/****************************************************************************/ 4269/* */ 4270/* Routine Name: ips_online */ 4271/* */ 4272/* Routine Description: */ 4273/* */ 4274/* Determine if a logical drive is online */ 4275/* */ 4276/****************************************************************************/ 4277static int 4278ips_online(ips_ha_t * ha, ips_scb_t * scb) 4279{ 4280 METHOD_TRACE("ips_online", 1); 4281 4282 if (scb->target_id >= IPS_MAX_LD) 4283 return (0); 4284 4285 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) { 4286 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO)); 4287 return (0); 4288 } 4289 4290 if (ha->logical_drive_info->drive_info[scb->target_id].state != 4291 IPS_LD_OFFLINE 4292 && ha->logical_drive_info->drive_info[scb->target_id].state != 4293 IPS_LD_FREE 4294 && ha->logical_drive_info->drive_info[scb->target_id].state != 4295 IPS_LD_CRS 4296 && ha->logical_drive_info->drive_info[scb->target_id].state != 4297 IPS_LD_SYS) 4298 return (1); 4299 else 4300 return (0); 4301} 4302 4303/****************************************************************************/ 4304/* */ 4305/* Routine Name: ips_inquiry */ 4306/* */ 4307/* Routine Description: */ 4308/* */ 4309/* Simulate an inquiry command to a logical drive */ 4310/* */ 4311/****************************************************************************/ 4312static int 4313ips_inquiry(ips_ha_t * ha, ips_scb_t * scb) 4314{ 4315 IPS_SCSI_INQ_DATA inquiry; 4316 4317 METHOD_TRACE("ips_inquiry", 1); 4318 4319 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA)); 4320 4321 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD; 4322 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED; 4323 inquiry.Version = IPS_SCSI_INQ_REV2; 4324 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2; 4325 inquiry.AdditionalLength = 31; 4326 inquiry.Flags[0] = IPS_SCSI_INQ_Address16; 4327 inquiry.Flags[1] = 4328 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue; 4329 strncpy(inquiry.VendorId, "IBM ", 8); 4330 strncpy(inquiry.ProductId, "SERVERAID ", 16); 4331 strncpy(inquiry.ProductRevisionLevel, "1.00", 4); 4332 4333 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry)); 4334 4335 return (1); 4336} 4337 4338/****************************************************************************/ 4339/* */ 4340/* Routine Name: ips_rdcap */ 4341/* */ 4342/* Routine Description: */ 4343/* */ 4344/* Simulate a read capacity command to a logical drive */ 4345/* */ 4346/****************************************************************************/ 4347static int 4348ips_rdcap(ips_ha_t * ha, ips_scb_t * scb) 4349{ 4350 IPS_SCSI_CAPACITY cap; 4351 4352 METHOD_TRACE("ips_rdcap", 1); 4353 4354 if (scb->scsi_cmd->request_bufflen < 8) 4355 return (0); 4356 4357 cap.lba = 4358 cpu_to_be32(le32_to_cpu 4359 (ha->logical_drive_info-> 4360 drive_info[scb->target_id].sector_count) - 1); 4361 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE); 4362 4363 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap)); 4364 4365 return (1); 4366} 4367 4368/****************************************************************************/ 4369/* */ 4370/* Routine Name: ips_msense */ 4371/* */ 4372/* Routine Description: */ 4373/* */ 4374/* Simulate a mode sense command to a logical drive */ 4375/* */ 4376/****************************************************************************/ 4377static int 4378ips_msense(ips_ha_t * ha, ips_scb_t * scb) 4379{ 4380 uint16_t heads; 4381 uint16_t sectors; 4382 uint32_t cylinders; 4383 IPS_SCSI_MODE_PAGE_DATA mdata; 4384 4385 METHOD_TRACE("ips_msense", 1); 4386 4387 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 && 4388 (ha->enq->ucMiscFlag & 0x8) == 0) { 4389 heads = IPS_NORM_HEADS; 4390 sectors = IPS_NORM_SECTORS; 4391 } else { 4392 heads = IPS_COMP_HEADS; 4393 sectors = IPS_COMP_SECTORS; 4394 } 4395 4396 cylinders = 4397 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) - 4398 1) / (heads * sectors); 4399 4400 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA)); 4401 4402 mdata.hdr.BlockDescLength = 8; 4403 4404 switch (scb->scsi_cmd->cmnd[2] & 0x3f) { 4405 case 0x03: /* page 3 */ 4406 mdata.pdata.pg3.PageCode = 3; 4407 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3); 4408 mdata.hdr.DataLength = 4409 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength; 4410 mdata.pdata.pg3.TracksPerZone = 0; 4411 mdata.pdata.pg3.AltSectorsPerZone = 0; 4412 mdata.pdata.pg3.AltTracksPerZone = 0; 4413 mdata.pdata.pg3.AltTracksPerVolume = 0; 4414 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors); 4415 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE); 4416 mdata.pdata.pg3.Interleave = cpu_to_be16(1); 4417 mdata.pdata.pg3.TrackSkew = 0; 4418 mdata.pdata.pg3.CylinderSkew = 0; 4419 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector; 4420 break; 4421 4422 case 0x4: 4423 mdata.pdata.pg4.PageCode = 4; 4424 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4); 4425 mdata.hdr.DataLength = 4426 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength; 4427 mdata.pdata.pg4.CylindersHigh = 4428 cpu_to_be16((cylinders >> 8) & 0xFFFF); 4429 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF); 4430 mdata.pdata.pg4.Heads = heads; 4431 mdata.pdata.pg4.WritePrecompHigh = 0; 4432 mdata.pdata.pg4.WritePrecompLow = 0; 4433 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0; 4434 mdata.pdata.pg4.ReducedWriteCurrentLow = 0; 4435 mdata.pdata.pg4.StepRate = cpu_to_be16(1); 4436 mdata.pdata.pg4.LandingZoneHigh = 0; 4437 mdata.pdata.pg4.LandingZoneLow = 0; 4438 mdata.pdata.pg4.flags = 0; 4439 mdata.pdata.pg4.RotationalOffset = 0; 4440 mdata.pdata.pg4.MediumRotationRate = 0; 4441 break; 4442 case 0x8: 4443 mdata.pdata.pg8.PageCode = 8; 4444 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8); 4445 mdata.hdr.DataLength = 4446 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength; 4447 /* everything else is left set to 0 */ 4448 break; 4449 4450 default: 4451 return (0); 4452 } /* end switch */ 4453 4454 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata)); 4455 4456 return (1); 4457} 4458 4459/****************************************************************************/ 4460/* */ 4461/* Routine Name: ips_reqsen */ 4462/* */ 4463/* Routine Description: */ 4464/* */ 4465/* Simulate a request sense command to a logical drive */ 4466/* */ 4467/****************************************************************************/ 4468static int 4469ips_reqsen(ips_ha_t * ha, ips_scb_t * scb) 4470{ 4471 IPS_SCSI_REQSEN reqsen; 4472 4473 METHOD_TRACE("ips_reqsen", 1); 4474 4475 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN)); 4476 4477 reqsen.ResponseCode = 4478 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR; 4479 reqsen.AdditionalLength = 10; 4480 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE; 4481 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE; 4482 4483 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen)); 4484 4485 return (1); 4486} 4487 4488/****************************************************************************/ 4489/* */ 4490/* Routine Name: ips_free */ 4491/* */ 4492/* Routine Description: */ 4493/* */ 4494/* Free any allocated space for this controller */ 4495/* */ 4496/****************************************************************************/ 4497static void 4498ips_free(ips_ha_t * ha) 4499{ 4500 4501 METHOD_TRACE("ips_free", 1); 4502 4503 if (ha) { 4504 if (ha->enq) { 4505 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ), 4506 ha->enq, ha->enq_busaddr); 4507 ha->enq = NULL; 4508 } 4509 4510 kfree(ha->conf); 4511 ha->conf = NULL; 4512 4513 if (ha->adapt) { 4514 pci_free_consistent(ha->pcidev, 4515 sizeof (IPS_ADAPTER) + 4516 sizeof (IPS_IO_CMD), ha->adapt, 4517 ha->adapt->hw_status_start); 4518 ha->adapt = NULL; 4519 } 4520 4521 if (ha->logical_drive_info) { 4522 pci_free_consistent(ha->pcidev, 4523 sizeof (IPS_LD_INFO), 4524 ha->logical_drive_info, 4525 ha->logical_drive_info_dma_addr); 4526 ha->logical_drive_info = NULL; 4527 } 4528 4529 kfree(ha->nvram); 4530 ha->nvram = NULL; 4531 4532 kfree(ha->subsys); 4533 ha->subsys = NULL; 4534 4535 if (ha->ioctl_data) { 4536 pci_free_consistent(ha->pcidev, ha->ioctl_len, 4537 ha->ioctl_data, ha->ioctl_busaddr); 4538 ha->ioctl_data = NULL; 4539 ha->ioctl_datasize = 0; 4540 ha->ioctl_len = 0; 4541 } 4542 ips_deallocatescbs(ha, ha->max_cmds); 4543 4544 /* free memory mapped (if applicable) */ 4545 if (ha->mem_ptr) { 4546 iounmap(ha->ioremap_ptr); 4547 ha->ioremap_ptr = NULL; 4548 ha->mem_ptr = NULL; 4549 } 4550 4551 if (ha->mem_addr) 4552 release_mem_region(ha->mem_addr, ha->mem_len); 4553 ha->mem_addr = 0; 4554 4555 } 4556} 4557 4558/****************************************************************************/ 4559/* */ 4560/* Routine Name: ips_deallocatescbs */ 4561/* */ 4562/* Routine Description: */ 4563/* */ 4564/* Free the command blocks */ 4565/* */ 4566/****************************************************************************/ 4567static int 4568ips_deallocatescbs(ips_ha_t * ha, int cmds) 4569{ 4570 if (ha->scbs) { 4571 pci_free_consistent(ha->pcidev, 4572 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds, 4573 ha->scbs->sg_list.list, 4574 ha->scbs->sg_busaddr); 4575 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds, 4576 ha->scbs, ha->scbs->scb_busaddr); 4577 ha->scbs = NULL; 4578 } /* end if */ 4579 return 1; 4580} 4581 4582/****************************************************************************/ 4583/* */ 4584/* Routine Name: ips_allocatescbs */ 4585/* */ 4586/* Routine Description: */ 4587/* */ 4588/* Allocate the command blocks */ 4589/* */ 4590/****************************************************************************/ 4591static int 4592ips_allocatescbs(ips_ha_t * ha) 4593{ 4594 ips_scb_t *scb_p; 4595 IPS_SG_LIST ips_sg; 4596 int i; 4597 dma_addr_t command_dma, sg_dma; 4598 4599 METHOD_TRACE("ips_allocatescbs", 1); 4600 4601 /* Allocate memory for the SCBs */ 4602 ha->scbs = 4603 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t), 4604 &command_dma); 4605 if (ha->scbs == NULL) 4606 return 0; 4607 ips_sg.list = 4608 pci_alloc_consistent(ha->pcidev, 4609 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * 4610 ha->max_cmds, &sg_dma); 4611 if (ips_sg.list == NULL) { 4612 pci_free_consistent(ha->pcidev, 4613 ha->max_cmds * sizeof (ips_scb_t), ha->scbs, 4614 command_dma); 4615 return 0; 4616 } 4617 4618 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t)); 4619 4620 for (i = 0; i < ha->max_cmds; i++) { 4621 scb_p = &ha->scbs[i]; 4622 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i; 4623 /* set up S/G list */ 4624 if (IPS_USE_ENH_SGLIST(ha)) { 4625 scb_p->sg_list.enh_list = 4626 ips_sg.enh_list + i * IPS_MAX_SG; 4627 scb_p->sg_busaddr = 4628 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; 4629 } else { 4630 scb_p->sg_list.std_list = 4631 ips_sg.std_list + i * IPS_MAX_SG; 4632 scb_p->sg_busaddr = 4633 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; 4634 } 4635 4636 /* add to the free list */ 4637 if (i < ha->max_cmds - 1) { 4638 scb_p->q_next = ha->scb_freelist; 4639 ha->scb_freelist = scb_p; 4640 } 4641 } 4642 4643 /* success */ 4644 return (1); 4645} 4646 4647/****************************************************************************/ 4648/* */ 4649/* Routine Name: ips_init_scb */ 4650/* */ 4651/* Routine Description: */ 4652/* */ 4653/* Initialize a CCB to default values */ 4654/* */ 4655/****************************************************************************/ 4656static void 4657ips_init_scb(ips_ha_t * ha, ips_scb_t * scb) 4658{ 4659 IPS_SG_LIST sg_list; 4660 uint32_t cmd_busaddr, sg_busaddr; 4661 METHOD_TRACE("ips_init_scb", 1); 4662 4663 if (scb == NULL) 4664 return; 4665 4666 sg_list.list = scb->sg_list.list; 4667 cmd_busaddr = scb->scb_busaddr; 4668 sg_busaddr = scb->sg_busaddr; 4669 /* zero fill */ 4670 memset(scb, 0, sizeof (ips_scb_t)); 4671 memset(ha->dummy, 0, sizeof (IPS_IO_CMD)); 4672 4673 /* Initialize dummy command bucket */ 4674 ha->dummy->op_code = 0xFF; 4675 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start 4676 + sizeof (IPS_ADAPTER)); 4677 ha->dummy->command_id = IPS_MAX_CMDS; 4678 4679 /* set bus address of scb */ 4680 scb->scb_busaddr = cmd_busaddr; 4681 scb->sg_busaddr = sg_busaddr; 4682 scb->sg_list.list = sg_list.list; 4683 4684 /* Neptune Fix */ 4685 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE); 4686 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start 4687 + sizeof (IPS_ADAPTER)); 4688} 4689 4690/****************************************************************************/ 4691/* */ 4692/* Routine Name: ips_get_scb */ 4693/* */ 4694/* Routine Description: */ 4695/* */ 4696/* Initialize a CCB to default values */ 4697/* */ 4698/* ASSUMED to be callled from within a lock */ 4699/* */ 4700/****************************************************************************/ 4701static ips_scb_t * 4702ips_getscb(ips_ha_t * ha) 4703{ 4704 ips_scb_t *scb; 4705 4706 METHOD_TRACE("ips_getscb", 1); 4707 4708 if ((scb = ha->scb_freelist) == NULL) { 4709 4710 return (NULL); 4711 } 4712 4713 ha->scb_freelist = scb->q_next; 4714 scb->flags = 0; 4715 scb->q_next = NULL; 4716 4717 ips_init_scb(ha, scb); 4718 4719 return (scb); 4720} 4721 4722/****************************************************************************/ 4723/* */ 4724/* Routine Name: ips_free_scb */ 4725/* */ 4726/* Routine Description: */ 4727/* */ 4728/* Return an unused CCB back to the free list */ 4729/* */ 4730/* ASSUMED to be called from within a lock */ 4731/* */ 4732/****************************************************************************/ 4733static void 4734ips_freescb(ips_ha_t * ha, ips_scb_t * scb) 4735{ 4736 4737 METHOD_TRACE("ips_freescb", 1); 4738 if (scb->flags & IPS_SCB_MAP_SG) 4739 pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer, 4740 scb->scsi_cmd->use_sg, IPS_DMA_DIR(scb)); 4741 else if (scb->flags & IPS_SCB_MAP_SINGLE) 4742 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len, 4743 IPS_DMA_DIR(scb)); 4744 4745 /* check to make sure this is not our "special" scb */ 4746 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) { 4747 scb->q_next = ha->scb_freelist; 4748 ha->scb_freelist = scb; 4749 } 4750} 4751 4752/****************************************************************************/ 4753/* */ 4754/* Routine Name: ips_isinit_copperhead */ 4755/* */ 4756/* Routine Description: */ 4757/* */ 4758/* Is controller initialized ? */ 4759/* */ 4760/****************************************************************************/ 4761static int 4762ips_isinit_copperhead(ips_ha_t * ha) 4763{ 4764 uint8_t scpr; 4765 uint8_t isr; 4766 4767 METHOD_TRACE("ips_isinit_copperhead", 1); 4768 4769 isr = inb(ha->io_addr + IPS_REG_HISR); 4770 scpr = inb(ha->io_addr + IPS_REG_SCPR); 4771 4772 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) 4773 return (0); 4774 else 4775 return (1); 4776} 4777 4778/****************************************************************************/ 4779/* */ 4780/* Routine Name: ips_isinit_copperhead_memio */ 4781/* */ 4782/* Routine Description: */ 4783/* */ 4784/* Is controller initialized ? */ 4785/* */ 4786/****************************************************************************/ 4787static int 4788ips_isinit_copperhead_memio(ips_ha_t * ha) 4789{ 4790 uint8_t isr = 0; 4791 uint8_t scpr; 4792 4793 METHOD_TRACE("ips_is_init_copperhead_memio", 1); 4794 4795 isr = readb(ha->mem_ptr + IPS_REG_HISR); 4796 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); 4797 4798 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) 4799 return (0); 4800 else 4801 return (1); 4802} 4803 4804/****************************************************************************/ 4805/* */ 4806/* Routine Name: ips_isinit_morpheus */ 4807/* */ 4808/* Routine Description: */ 4809/* */ 4810/* Is controller initialized ? */ 4811/* */ 4812/****************************************************************************/ 4813static int 4814ips_isinit_morpheus(ips_ha_t * ha) 4815{ 4816 uint32_t post; 4817 uint32_t bits; 4818 4819 METHOD_TRACE("ips_is_init_morpheus", 1); 4820 4821 if (ips_isintr_morpheus(ha)) 4822 ips_flush_and_reset(ha); 4823 4824 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4825 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4826 4827 if (post == 0) 4828 return (0); 4829 else if (bits & 0x3) 4830 return (0); 4831 else 4832 return (1); 4833} 4834 4835/****************************************************************************/ 4836/* */ 4837/* Routine Name: ips_flush_and_reset */ 4838/* */ 4839/* Routine Description: */ 4840/* */ 4841/* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */ 4842/* state ( was trying to INIT and an interrupt was already pending ) ... */ 4843/* */ 4844/****************************************************************************/ 4845static void 4846ips_flush_and_reset(ips_ha_t *ha) 4847{ 4848 ips_scb_t *scb; 4849 int ret; 4850 int time; 4851 int done; 4852 dma_addr_t command_dma; 4853 4854 /* Create a usuable SCB */ 4855 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma); 4856 if (scb) { 4857 memset(scb, 0, sizeof(ips_scb_t)); 4858 ips_init_scb(ha, scb); 4859 scb->scb_busaddr = command_dma; 4860 4861 scb->timeout = ips_cmd_timeout; 4862 scb->cdb[0] = IPS_CMD_FLUSH; 4863 4864 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 4865 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */ 4866 scb->cmd.flush_cache.state = IPS_NORM_STATE; 4867 scb->cmd.flush_cache.reserved = 0; 4868 scb->cmd.flush_cache.reserved2 = 0; 4869 scb->cmd.flush_cache.reserved3 = 0; 4870 scb->cmd.flush_cache.reserved4 = 0; 4871 4872 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */ 4873 4874 if (ret == IPS_SUCCESS) { 4875 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */ 4876 done = 0; 4877 4878 while ((time > 0) && (!done)) { 4879 done = ips_poll_for_flush_complete(ha); 4880 /* This may look evil, but it's only done during extremely rare start-up conditions ! */ 4881 udelay(1000); 4882 time--; 4883 } 4884 } 4885 } 4886 4887 /* Now RESET and INIT the adapter */ 4888 (*ha->func.reset) (ha); 4889 4890 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma); 4891 return; 4892} 4893 4894/****************************************************************************/ 4895/* */ 4896/* Routine Name: ips_poll_for_flush_complete */ 4897/* */ 4898/* Routine Description: */ 4899/* */ 4900/* Poll for the Flush Command issued by ips_flush_and_reset() to complete */ 4901/* All other responses are just taken off the queue and ignored */ 4902/* */ 4903/****************************************************************************/ 4904static int 4905ips_poll_for_flush_complete(ips_ha_t * ha) 4906{ 4907 IPS_STATUS cstatus; 4908 4909 while (TRUE) { 4910 cstatus.value = (*ha->func.statupd) (ha); 4911 4912 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */ 4913 break; 4914 4915 /* Success is when we see the Flush Command ID */ 4916 if (cstatus.fields.command_id == IPS_MAX_CMDS ) 4917 return 1; 4918 } 4919 4920 return 0; 4921} 4922 4923/****************************************************************************/ 4924/* */ 4925/* Routine Name: ips_enable_int_copperhead */ 4926/* */ 4927/* Routine Description: */ 4928/* Turn on interrupts */ 4929/* */ 4930/****************************************************************************/ 4931static void 4932ips_enable_int_copperhead(ips_ha_t * ha) 4933{ 4934 METHOD_TRACE("ips_enable_int_copperhead", 1); 4935 4936 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI); 4937 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ 4938} 4939 4940/****************************************************************************/ 4941/* */ 4942/* Routine Name: ips_enable_int_copperhead_memio */ 4943/* */ 4944/* Routine Description: */ 4945/* Turn on interrupts */ 4946/* */ 4947/****************************************************************************/ 4948static void 4949ips_enable_int_copperhead_memio(ips_ha_t * ha) 4950{ 4951 METHOD_TRACE("ips_enable_int_copperhead_memio", 1); 4952 4953 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); 4954 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ 4955} 4956 4957/****************************************************************************/ 4958/* */ 4959/* Routine Name: ips_enable_int_morpheus */ 4960/* */ 4961/* Routine Description: */ 4962/* Turn on interrupts */ 4963/* */ 4964/****************************************************************************/ 4965static void 4966ips_enable_int_morpheus(ips_ha_t * ha) 4967{ 4968 uint32_t Oimr; 4969 4970 METHOD_TRACE("ips_enable_int_morpheus", 1); 4971 4972 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); 4973 Oimr &= ~0x08; 4974 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); 4975 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ 4976} 4977 4978/****************************************************************************/ 4979/* */ 4980/* Routine Name: ips_init_copperhead */ 4981/* */ 4982/* Routine Description: */ 4983/* */ 4984/* Initialize a copperhead controller */ 4985/* */ 4986/****************************************************************************/ 4987static int 4988ips_init_copperhead(ips_ha_t * ha) 4989{ 4990 uint8_t Isr; 4991 uint8_t Cbsp; 4992 uint8_t PostByte[IPS_MAX_POST_BYTES]; 4993 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES]; 4994 int i, j; 4995 4996 METHOD_TRACE("ips_init_copperhead", 1); 4997 4998 for (i = 0; i < IPS_MAX_POST_BYTES; i++) { 4999 for (j = 0; j < 45; j++) { 5000 Isr = inb(ha->io_addr + IPS_REG_HISR); 5001 if (Isr & IPS_BIT_GHI) 5002 break; 5003 5004 /* Delay for 1 Second */ 5005 MDELAY(IPS_ONE_SEC); 5006 } 5007 5008 if (j >= 45) 5009 /* error occurred */ 5010 return (0); 5011 5012 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR); 5013 outb(Isr, ha->io_addr + IPS_REG_HISR); 5014 } 5015 5016 if (PostByte[0] < IPS_GOOD_POST_STATUS) { 5017 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5018 "reset controller fails (post status %x %x).\n", 5019 PostByte[0], PostByte[1]); 5020 5021 return (0); 5022 } 5023 5024 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { 5025 for (j = 0; j < 240; j++) { 5026 Isr = inb(ha->io_addr + IPS_REG_HISR); 5027 if (Isr & IPS_BIT_GHI) 5028 break; 5029 5030 /* Delay for 1 Second */ 5031 MDELAY(IPS_ONE_SEC); 5032 } 5033 5034 if (j >= 240) 5035 /* error occurred */ 5036 return (0); 5037 5038 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR); 5039 outb(Isr, ha->io_addr + IPS_REG_HISR); 5040 } 5041 5042 for (i = 0; i < 240; i++) { 5043 Cbsp = inb(ha->io_addr + IPS_REG_CBSP); 5044 5045 if ((Cbsp & IPS_BIT_OP) == 0) 5046 break; 5047 5048 /* Delay for 1 Second */ 5049 MDELAY(IPS_ONE_SEC); 5050 } 5051 5052 if (i >= 240) 5053 /* reset failed */ 5054 return (0); 5055 5056 /* setup CCCR */ 5057 outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR); 5058 5059 /* Enable busmastering */ 5060 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR); 5061 5062 if (ha->revision_id == IPS_REVID_TROMBONE64) 5063 /* fix for anaconda64 */ 5064 outl(0, ha->io_addr + IPS_REG_NDAE); 5065 5066 /* Enable interrupts */ 5067 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR); 5068 5069 return (1); 5070} 5071 5072/****************************************************************************/ 5073/* */ 5074/* Routine Name: ips_init_copperhead_memio */ 5075/* */ 5076/* Routine Description: */ 5077/* */ 5078/* Initialize a copperhead controller with memory mapped I/O */ 5079/* */ 5080/****************************************************************************/ 5081static int 5082ips_init_copperhead_memio(ips_ha_t * ha) 5083{ 5084 uint8_t Isr = 0; 5085 uint8_t Cbsp; 5086 uint8_t PostByte[IPS_MAX_POST_BYTES]; 5087 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES]; 5088 int i, j; 5089 5090 METHOD_TRACE("ips_init_copperhead_memio", 1); 5091 5092 for (i = 0; i < IPS_MAX_POST_BYTES; i++) { 5093 for (j = 0; j < 45; j++) { 5094 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 5095 if (Isr & IPS_BIT_GHI) 5096 break; 5097 5098 /* Delay for 1 Second */ 5099 MDELAY(IPS_ONE_SEC); 5100 } 5101 5102 if (j >= 45) 5103 /* error occurred */ 5104 return (0); 5105 5106 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); 5107 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 5108 } 5109 5110 if (PostByte[0] < IPS_GOOD_POST_STATUS) { 5111 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5112 "reset controller fails (post status %x %x).\n", 5113 PostByte[0], PostByte[1]); 5114 5115 return (0); 5116 } 5117 5118 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { 5119 for (j = 0; j < 240; j++) { 5120 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 5121 if (Isr & IPS_BIT_GHI) 5122 break; 5123 5124 /* Delay for 1 Second */ 5125 MDELAY(IPS_ONE_SEC); 5126 } 5127 5128 if (j >= 240) 5129 /* error occurred */ 5130 return (0); 5131 5132 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); 5133 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 5134 } 5135 5136 for (i = 0; i < 240; i++) { 5137 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); 5138 5139 if ((Cbsp & IPS_BIT_OP) == 0) 5140 break; 5141 5142 /* Delay for 1 Second */ 5143 MDELAY(IPS_ONE_SEC); 5144 } 5145 5146 if (i >= 240) 5147 /* error occurred */ 5148 return (0); 5149 5150 /* setup CCCR */ 5151 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); 5152 5153 /* Enable busmastering */ 5154 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); 5155 5156 if (ha->revision_id == IPS_REVID_TROMBONE64) 5157 /* fix for anaconda64 */ 5158 writel(0, ha->mem_ptr + IPS_REG_NDAE); 5159 5160 /* Enable interrupts */ 5161 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); 5162 5163 /* if we get here then everything went OK */ 5164 return (1); 5165} 5166 5167/****************************************************************************/ 5168/* */ 5169/* Routine Name: ips_init_morpheus */ 5170/* */ 5171/* Routine Description: */ 5172/* */ 5173/* Initialize a morpheus controller */ 5174/* */ 5175/****************************************************************************/ 5176static int 5177ips_init_morpheus(ips_ha_t * ha) 5178{ 5179 uint32_t Post; 5180 uint32_t Config; 5181 uint32_t Isr; 5182 uint32_t Oimr; 5183 int i; 5184 5185 METHOD_TRACE("ips_init_morpheus", 1); 5186 5187 /* Wait up to 45 secs for Post */ 5188 for (i = 0; i < 45; i++) { 5189 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 5190 5191 if (Isr & IPS_BIT_I960_MSG0I) 5192 break; 5193 5194 /* Delay for 1 Second */ 5195 MDELAY(IPS_ONE_SEC); 5196 } 5197 5198 if (i >= 45) { 5199 /* error occurred */ 5200 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5201 "timeout waiting for post.\n"); 5202 5203 return (0); 5204 } 5205 5206 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 5207 5208 if (Post == 0x4F00) { /* If Flashing the Battery PIC */ 5209 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5210 "Flashing Battery PIC, Please wait ...\n"); 5211 5212 /* Clear the interrupt bit */ 5213 Isr = (uint32_t) IPS_BIT_I960_MSG0I; 5214 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 5215 5216 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */ 5217 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 5218 if (Post != 0x4F00) 5219 break; 5220 /* Delay for 1 Second */ 5221 MDELAY(IPS_ONE_SEC); 5222 } 5223 5224 if (i >= 120) { 5225 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5226 "timeout waiting for Battery PIC Flash\n"); 5227 return (0); 5228 } 5229 5230 } 5231 5232 /* Clear the interrupt bit */ 5233 Isr = (uint32_t) IPS_BIT_I960_MSG0I; 5234 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 5235 5236 if (Post < (IPS_GOOD_POST_STATUS << 8)) { 5237 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5238 "reset controller fails (post status %x).\n", Post); 5239 5240 return (0); 5241 } 5242 5243 /* Wait up to 240 secs for config bytes */ 5244 for (i = 0; i < 240; i++) { 5245 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 5246 5247 if (Isr & IPS_BIT_I960_MSG1I) 5248 break; 5249 5250 /* Delay for 1 Second */ 5251 MDELAY(IPS_ONE_SEC); 5252 } 5253 5254 if (i >= 240) { 5255 /* error occurred */ 5256 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5257 "timeout waiting for config.\n"); 5258 5259 return (0); 5260 } 5261 5262 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); 5263 5264 /* Clear interrupt bit */ 5265 Isr = (uint32_t) IPS_BIT_I960_MSG1I; 5266 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 5267 5268 /* Turn on the interrupts */ 5269 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); 5270 Oimr &= ~0x8; 5271 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); 5272 5273 /* if we get here then everything went OK */ 5274 5275 /* Since we did a RESET, an EraseStripeLock may be needed */ 5276 if (Post == 0xEF10) { 5277 if ((Config == 0x000F) || (Config == 0x0009)) 5278 ha->requires_esl = 1; 5279 } 5280 5281 return (1); 5282} 5283 5284/****************************************************************************/ 5285/* */ 5286/* Routine Name: ips_reset_copperhead */ 5287/* */ 5288/* Routine Description: */ 5289/* */ 5290/* Reset the controller */ 5291/* */ 5292/****************************************************************************/ 5293static int 5294ips_reset_copperhead(ips_ha_t * ha) 5295{ 5296 int reset_counter; 5297 5298 METHOD_TRACE("ips_reset_copperhead", 1); 5299 5300 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d", 5301 ips_name, ha->host_num, ha->io_addr, ha->irq); 5302 5303 reset_counter = 0; 5304 5305 while (reset_counter < 2) { 5306 reset_counter++; 5307 5308 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR); 5309 5310 /* Delay for 1 Second */ 5311 MDELAY(IPS_ONE_SEC); 5312 5313 outb(0, ha->io_addr + IPS_REG_SCPR); 5314 5315 /* Delay for 1 Second */ 5316 MDELAY(IPS_ONE_SEC); 5317 5318 if ((*ha->func.init) (ha)) 5319 break; 5320 else if (reset_counter >= 2) { 5321 5322 return (0); 5323 } 5324 } 5325 5326 return (1); 5327} 5328 5329/****************************************************************************/ 5330/* */ 5331/* Routine Name: ips_reset_copperhead_memio */ 5332/* */ 5333/* Routine Description: */ 5334/* */ 5335/* Reset the controller */ 5336/* */ 5337/****************************************************************************/ 5338static int 5339ips_reset_copperhead_memio(ips_ha_t * ha) 5340{ 5341 int reset_counter; 5342 5343 METHOD_TRACE("ips_reset_copperhead_memio", 1); 5344 5345 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d", 5346 ips_name, ha->host_num, ha->mem_addr, ha->irq); 5347 5348 reset_counter = 0; 5349 5350 while (reset_counter < 2) { 5351 reset_counter++; 5352 5353 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); 5354 5355 /* Delay for 1 Second */ 5356 MDELAY(IPS_ONE_SEC); 5357 5358 writeb(0, ha->mem_ptr + IPS_REG_SCPR); 5359 5360 /* Delay for 1 Second */ 5361 MDELAY(IPS_ONE_SEC); 5362 5363 if ((*ha->func.init) (ha)) 5364 break; 5365 else if (reset_counter >= 2) { 5366 5367 return (0); 5368 } 5369 } 5370 5371 return (1); 5372} 5373 5374/****************************************************************************/ 5375/* */ 5376/* Routine Name: ips_reset_morpheus */ 5377/* */ 5378/* Routine Description: */ 5379/* */ 5380/* Reset the controller */ 5381/* */ 5382/****************************************************************************/ 5383static int 5384ips_reset_morpheus(ips_ha_t * ha) 5385{ 5386 int reset_counter; 5387 uint8_t junk; 5388 5389 METHOD_TRACE("ips_reset_morpheus", 1); 5390 5391 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d", 5392 ips_name, ha->host_num, ha->mem_addr, ha->irq); 5393 5394 reset_counter = 0; 5395 5396 while (reset_counter < 2) { 5397 reset_counter++; 5398 5399 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); 5400 5401 /* Delay for 5 Seconds */ 5402 MDELAY(5 * IPS_ONE_SEC); 5403 5404 /* Do a PCI config read to wait for adapter */ 5405 pci_read_config_byte(ha->pcidev, 4, &junk); 5406 5407 if ((*ha->func.init) (ha)) 5408 break; 5409 else if (reset_counter >= 2) { 5410 5411 return (0); 5412 } 5413 } 5414 5415 return (1); 5416} 5417 5418/****************************************************************************/ 5419/* */ 5420/* Routine Name: ips_statinit */ 5421/* */ 5422/* Routine Description: */ 5423/* */ 5424/* Initialize the status queues on the controller */ 5425/* */ 5426/****************************************************************************/ 5427static void 5428ips_statinit(ips_ha_t * ha) 5429{ 5430 uint32_t phys_status_start; 5431 5432 METHOD_TRACE("ips_statinit", 1); 5433 5434 ha->adapt->p_status_start = ha->adapt->status; 5435 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; 5436 ha->adapt->p_status_tail = ha->adapt->status; 5437 5438 phys_status_start = ha->adapt->hw_status_start; 5439 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR); 5440 outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE), 5441 ha->io_addr + IPS_REG_SQER); 5442 outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE), 5443 ha->io_addr + IPS_REG_SQHR); 5444 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR); 5445 5446 ha->adapt->hw_status_tail = phys_status_start; 5447} 5448 5449/****************************************************************************/ 5450/* */ 5451/* Routine Name: ips_statinit_memio */ 5452/* */ 5453/* Routine Description: */ 5454/* */ 5455/* Initialize the status queues on the controller */ 5456/* */ 5457/****************************************************************************/ 5458static void 5459ips_statinit_memio(ips_ha_t * ha) 5460{ 5461 uint32_t phys_status_start; 5462 5463 METHOD_TRACE("ips_statinit_memio", 1); 5464 5465 ha->adapt->p_status_start = ha->adapt->status; 5466 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; 5467 ha->adapt->p_status_tail = ha->adapt->status; 5468 5469 phys_status_start = ha->adapt->hw_status_start; 5470 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); 5471 writel(phys_status_start + IPS_STATUS_Q_SIZE, 5472 ha->mem_ptr + IPS_REG_SQER); 5473 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); 5474 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); 5475 5476 ha->adapt->hw_status_tail = phys_status_start; 5477} 5478 5479/****************************************************************************/ 5480/* */ 5481/* Routine Name: ips_statupd_copperhead */ 5482/* */ 5483/* Routine Description: */ 5484/* */ 5485/* Remove an element from the status queue */ 5486/* */ 5487/****************************************************************************/ 5488static uint32_t 5489ips_statupd_copperhead(ips_ha_t * ha) 5490{ 5491 METHOD_TRACE("ips_statupd_copperhead", 1); 5492 5493 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { 5494 ha->adapt->p_status_tail++; 5495 ha->adapt->hw_status_tail += sizeof (IPS_STATUS); 5496 } else { 5497 ha->adapt->p_status_tail = ha->adapt->p_status_start; 5498 ha->adapt->hw_status_tail = ha->adapt->hw_status_start; 5499 } 5500 5501 outl(cpu_to_le32(ha->adapt->hw_status_tail), 5502 ha->io_addr + IPS_REG_SQTR); 5503 5504 return (ha->adapt->p_status_tail->value); 5505} 5506 5507/****************************************************************************/ 5508/* */ 5509/* Routine Name: ips_statupd_copperhead_memio */ 5510/* */ 5511/* Routine Description: */ 5512/* */ 5513/* Remove an element from the status queue */ 5514/* */ 5515/****************************************************************************/ 5516static uint32_t 5517ips_statupd_copperhead_memio(ips_ha_t * ha) 5518{ 5519 METHOD_TRACE("ips_statupd_copperhead_memio", 1); 5520 5521 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { 5522 ha->adapt->p_status_tail++; 5523 ha->adapt->hw_status_tail += sizeof (IPS_STATUS); 5524 } else { 5525 ha->adapt->p_status_tail = ha->adapt->p_status_start; 5526 ha->adapt->hw_status_tail = ha->adapt->hw_status_start; 5527 } 5528 5529 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); 5530 5531 return (ha->adapt->p_status_tail->value); 5532} 5533 5534/****************************************************************************/ 5535/* */ 5536/* Routine Name: ips_statupd_morpheus */ 5537/* */ 5538/* Routine Description: */ 5539/* */ 5540/* Remove an element from the status queue */ 5541/* */ 5542/****************************************************************************/ 5543static uint32_t 5544ips_statupd_morpheus(ips_ha_t * ha) 5545{ 5546 uint32_t val; 5547 5548 METHOD_TRACE("ips_statupd_morpheus", 1); 5549 5550 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); 5551 5552 return (val); 5553} 5554 5555/****************************************************************************/ 5556/* */ 5557/* Routine Name: ips_issue_copperhead */ 5558/* */ 5559/* Routine Description: */ 5560/* */ 5561/* Send a command down to the controller */ 5562/* */ 5563/****************************************************************************/ 5564static int 5565ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb) 5566{ 5567 uint32_t TimeOut; 5568 uint32_t val; 5569 5570 METHOD_TRACE("ips_issue_copperhead", 1); 5571 5572 if (scb->scsi_cmd) { 5573 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5574 ips_name, 5575 ha->host_num, 5576 scb->cdb[0], 5577 scb->cmd.basic_io.command_id, 5578 scb->bus, scb->target_id, scb->lun); 5579 } else { 5580 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d", 5581 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5582 } 5583 5584 TimeOut = 0; 5585 5586 while ((val = 5587 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) { 5588 udelay(1000); 5589 5590 if (++TimeOut >= IPS_SEM_TIMEOUT) { 5591 if (!(val & IPS_BIT_START_STOP)) 5592 break; 5593 5594 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5595 "ips_issue val [0x%x].\n", val); 5596 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5597 "ips_issue semaphore chk timeout.\n"); 5598 5599 return (IPS_FAILURE); 5600 } /* end if */ 5601 } /* end while */ 5602 5603 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR); 5604 outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR); 5605 5606 return (IPS_SUCCESS); 5607} 5608 5609/****************************************************************************/ 5610/* */ 5611/* Routine Name: ips_issue_copperhead_memio */ 5612/* */ 5613/* Routine Description: */ 5614/* */ 5615/* Send a command down to the controller */ 5616/* */ 5617/****************************************************************************/ 5618static int 5619ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb) 5620{ 5621 uint32_t TimeOut; 5622 uint32_t val; 5623 5624 METHOD_TRACE("ips_issue_copperhead_memio", 1); 5625 5626 if (scb->scsi_cmd) { 5627 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5628 ips_name, 5629 ha->host_num, 5630 scb->cdb[0], 5631 scb->cmd.basic_io.command_id, 5632 scb->bus, scb->target_id, scb->lun); 5633 } else { 5634 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5635 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5636 } 5637 5638 TimeOut = 0; 5639 5640 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { 5641 udelay(1000); 5642 5643 if (++TimeOut >= IPS_SEM_TIMEOUT) { 5644 if (!(val & IPS_BIT_START_STOP)) 5645 break; 5646 5647 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5648 "ips_issue val [0x%x].\n", val); 5649 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5650 "ips_issue semaphore chk timeout.\n"); 5651 5652 return (IPS_FAILURE); 5653 } /* end if */ 5654 } /* end while */ 5655 5656 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); 5657 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); 5658 5659 return (IPS_SUCCESS); 5660} 5661 5662/****************************************************************************/ 5663/* */ 5664/* Routine Name: ips_issue_i2o */ 5665/* */ 5666/* Routine Description: */ 5667/* */ 5668/* Send a command down to the controller */ 5669/* */ 5670/****************************************************************************/ 5671static int 5672ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb) 5673{ 5674 5675 METHOD_TRACE("ips_issue_i2o", 1); 5676 5677 if (scb->scsi_cmd) { 5678 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5679 ips_name, 5680 ha->host_num, 5681 scb->cdb[0], 5682 scb->cmd.basic_io.command_id, 5683 scb->bus, scb->target_id, scb->lun); 5684 } else { 5685 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5686 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5687 } 5688 5689 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ); 5690 5691 return (IPS_SUCCESS); 5692} 5693 5694/****************************************************************************/ 5695/* */ 5696/* Routine Name: ips_issue_i2o_memio */ 5697/* */ 5698/* Routine Description: */ 5699/* */ 5700/* Send a command down to the controller */ 5701/* */ 5702/****************************************************************************/ 5703static int 5704ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb) 5705{ 5706 5707 METHOD_TRACE("ips_issue_i2o_memio", 1); 5708 5709 if (scb->scsi_cmd) { 5710 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5711 ips_name, 5712 ha->host_num, 5713 scb->cdb[0], 5714 scb->cmd.basic_io.command_id, 5715 scb->bus, scb->target_id, scb->lun); 5716 } else { 5717 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5718 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5719 } 5720 5721 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); 5722 5723 return (IPS_SUCCESS); 5724} 5725 5726/****************************************************************************/ 5727/* */ 5728/* Routine Name: ips_isintr_copperhead */ 5729/* */ 5730/* Routine Description: */ 5731/* */ 5732/* Test to see if an interrupt is for us */ 5733/* */ 5734/****************************************************************************/ 5735static int 5736ips_isintr_copperhead(ips_ha_t * ha) 5737{ 5738 uint8_t Isr; 5739 5740 METHOD_TRACE("ips_isintr_copperhead", 2); 5741 5742 Isr = inb(ha->io_addr + IPS_REG_HISR); 5743 5744 if (Isr == 0xFF) 5745 /* ?!?! Nothing really there */ 5746 return (0); 5747 5748 if (Isr & IPS_BIT_SCE) 5749 return (1); 5750 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { 5751 /* status queue overflow or GHI */ 5752 /* just clear the interrupt */ 5753 outb(Isr, ha->io_addr + IPS_REG_HISR); 5754 } 5755 5756 return (0); 5757} 5758 5759/****************************************************************************/ 5760/* */ 5761/* Routine Name: ips_isintr_copperhead_memio */ 5762/* */ 5763/* Routine Description: */ 5764/* */ 5765/* Test to see if an interrupt is for us */ 5766/* */ 5767/****************************************************************************/ 5768static int 5769ips_isintr_copperhead_memio(ips_ha_t * ha) 5770{ 5771 uint8_t Isr; 5772 5773 METHOD_TRACE("ips_isintr_memio", 2); 5774 5775 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 5776 5777 if (Isr == 0xFF) 5778 /* ?!?! Nothing really there */ 5779 return (0); 5780 5781 if (Isr & IPS_BIT_SCE) 5782 return (1); 5783 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { 5784 /* status queue overflow or GHI */ 5785 /* just clear the interrupt */ 5786 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 5787 } 5788 5789 return (0); 5790} 5791 5792/****************************************************************************/ 5793/* */ 5794/* Routine Name: ips_isintr_morpheus */ 5795/* */ 5796/* Routine Description: */ 5797/* */ 5798/* Test to see if an interrupt is for us */ 5799/* */ 5800/****************************************************************************/ 5801static int 5802ips_isintr_morpheus(ips_ha_t * ha) 5803{ 5804 uint32_t Isr; 5805 5806 METHOD_TRACE("ips_isintr_morpheus", 2); 5807 5808 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 5809 5810 if (Isr & IPS_BIT_I2O_OPQI) 5811 return (1); 5812 else 5813 return (0); 5814} 5815 5816/****************************************************************************/ 5817/* */ 5818/* Routine Name: ips_wait */ 5819/* */ 5820/* Routine Description: */ 5821/* */ 5822/* Wait for a command to complete */ 5823/* */ 5824/****************************************************************************/ 5825static int 5826ips_wait(ips_ha_t * ha, int time, int intr) 5827{ 5828 int ret; 5829 int done; 5830 5831 METHOD_TRACE("ips_wait", 1); 5832 5833 ret = IPS_FAILURE; 5834 done = FALSE; 5835 5836 time *= IPS_ONE_SEC; /* convert seconds */ 5837 5838 while ((time > 0) && (!done)) { 5839 if (intr == IPS_INTR_ON) { 5840 if (ha->waitflag == FALSE) { 5841 ret = IPS_SUCCESS; 5842 done = TRUE; 5843 break; 5844 } 5845 } else if (intr == IPS_INTR_IORL) { 5846 if (ha->waitflag == FALSE) { 5847 /* 5848 * controller generated an interrupt to 5849 * acknowledge completion of the command 5850 * and ips_intr() has serviced the interrupt. 5851 */ 5852 ret = IPS_SUCCESS; 5853 done = TRUE; 5854 break; 5855 } 5856 5857 /* 5858 * NOTE: we already have the io_request_lock so 5859 * even if we get an interrupt it won't get serviced 5860 * until after we finish. 5861 */ 5862 5863 (*ha->func.intr) (ha); 5864 } 5865 5866 /* This looks like a very evil loop, but it only does this during start-up */ 5867 udelay(1000); 5868 time--; 5869 } 5870 5871 return (ret); 5872} 5873 5874/****************************************************************************/ 5875/* */ 5876/* Routine Name: ips_write_driver_status */ 5877/* */ 5878/* Routine Description: */ 5879/* */ 5880/* Write OS/Driver version to Page 5 of the nvram on the controller */ 5881/* */ 5882/****************************************************************************/ 5883static int 5884ips_write_driver_status(ips_ha_t * ha, int intr) 5885{ 5886 METHOD_TRACE("ips_write_driver_status", 1); 5887 5888 if (!ips_readwrite_page5(ha, FALSE, intr)) { 5889 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5890 "unable to read NVRAM page 5.\n"); 5891 5892 return (0); 5893 } 5894 5895 /* check to make sure the page has a valid */ 5896 /* signature */ 5897 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) { 5898 DEBUG_VAR(1, 5899 "(%s%d) NVRAM page 5 has an invalid signature: %X.", 5900 ips_name, ha->host_num, ha->nvram->signature); 5901 ha->nvram->signature = IPS_NVRAM_P5_SIG; 5902 } 5903 5904 DEBUG_VAR(2, 5905 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.", 5906 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type), 5907 ha->nvram->adapter_slot, ha->nvram->bios_high[0], 5908 ha->nvram->bios_high[1], ha->nvram->bios_high[2], 5909 ha->nvram->bios_high[3], ha->nvram->bios_low[0], 5910 ha->nvram->bios_low[1], ha->nvram->bios_low[2], 5911 ha->nvram->bios_low[3]); 5912 5913 ips_get_bios_version(ha, intr); 5914 5915 /* change values (as needed) */ 5916 ha->nvram->operating_system = IPS_OS_LINUX; 5917 ha->nvram->adapter_type = ha->ad_type; 5918 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4); 5919 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4); 5920 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4); 5921 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4); 5922 5923 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */ 5924 5925 /* now update the page */ 5926 if (!ips_readwrite_page5(ha, TRUE, intr)) { 5927 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5928 "unable to write NVRAM page 5.\n"); 5929 5930 return (0); 5931 } 5932 5933 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */ 5934 ha->slot_num = ha->nvram->adapter_slot; 5935 5936 return (1); 5937} 5938 5939/****************************************************************************/ 5940/* */ 5941/* Routine Name: ips_read_adapter_status */ 5942/* */ 5943/* Routine Description: */ 5944/* */ 5945/* Do an Inquiry command to the adapter */ 5946/* */ 5947/****************************************************************************/ 5948static int 5949ips_read_adapter_status(ips_ha_t * ha, int intr) 5950{ 5951 ips_scb_t *scb; 5952 int ret; 5953 5954 METHOD_TRACE("ips_read_adapter_status", 1); 5955 5956 scb = &ha->scbs[ha->max_cmds - 1]; 5957 5958 ips_init_scb(ha, scb); 5959 5960 scb->timeout = ips_cmd_timeout; 5961 scb->cdb[0] = IPS_CMD_ENQUIRY; 5962 5963 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; 5964 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5965 scb->cmd.basic_io.sg_count = 0; 5966 scb->cmd.basic_io.lba = 0; 5967 scb->cmd.basic_io.sector_count = 0; 5968 scb->cmd.basic_io.log_drv = 0; 5969 scb->data_len = sizeof (*ha->enq); 5970 scb->cmd.basic_io.sg_addr = ha->enq_busaddr; 5971 5972 /* send command */ 5973 if (((ret = 5974 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5975 || (ret == IPS_SUCCESS_IMM) 5976 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5977 return (0); 5978 5979 return (1); 5980} 5981 5982/****************************************************************************/ 5983/* */ 5984/* Routine Name: ips_read_subsystem_parameters */ 5985/* */ 5986/* Routine Description: */ 5987/* */ 5988/* Read subsystem parameters from the adapter */ 5989/* */ 5990/****************************************************************************/ 5991static int 5992ips_read_subsystem_parameters(ips_ha_t * ha, int intr) 5993{ 5994 ips_scb_t *scb; 5995 int ret; 5996 5997 METHOD_TRACE("ips_read_subsystem_parameters", 1); 5998 5999 scb = &ha->scbs[ha->max_cmds - 1]; 6000 6001 ips_init_scb(ha, scb); 6002 6003 scb->timeout = ips_cmd_timeout; 6004 scb->cdb[0] = IPS_CMD_GET_SUBSYS; 6005 6006 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS; 6007 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 6008 scb->cmd.basic_io.sg_count = 0; 6009 scb->cmd.basic_io.lba = 0; 6010 scb->cmd.basic_io.sector_count = 0; 6011 scb->cmd.basic_io.log_drv = 0; 6012 scb->data_len = sizeof (*ha->subsys); 6013 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; 6014 6015 /* send command */ 6016 if (((ret = 6017 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 6018 || (ret == IPS_SUCCESS_IMM) 6019 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 6020 return (0); 6021 6022 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys)); 6023 return (1); 6024} 6025 6026/****************************************************************************/ 6027/* */ 6028/* Routine Name: ips_read_config */ 6029/* */ 6030/* Routine Description: */ 6031/* */ 6032/* Read the configuration on the adapter */ 6033/* */ 6034/****************************************************************************/ 6035static int 6036ips_read_config(ips_ha_t * ha, int intr) 6037{ 6038 ips_scb_t *scb; 6039 int i; 6040 int ret; 6041 6042 METHOD_TRACE("ips_read_config", 1); 6043 6044 /* set defaults for initiator IDs */ 6045 for (i = 0; i < 4; i++) 6046 ha->conf->init_id[i] = 7; 6047 6048 scb = &ha->scbs[ha->max_cmds - 1]; 6049 6050 ips_init_scb(ha, scb); 6051 6052 scb->timeout = ips_cmd_timeout; 6053 scb->cdb[0] = IPS_CMD_READ_CONF; 6054 6055 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF; 6056 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 6057 scb->data_len = sizeof (*ha->conf); 6058 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; 6059 6060 /* send command */ 6061 if (((ret = 6062 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 6063 || (ret == IPS_SUCCESS_IMM) 6064 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 6065 6066 memset(ha->conf, 0, sizeof (IPS_CONF)); 6067 6068 /* reset initiator IDs */ 6069 for (i = 0; i < 4; i++) 6070 ha->conf->init_id[i] = 7; 6071 6072 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */ 6073 if ((scb->basic_status & IPS_GSC_STATUS_MASK) == 6074 IPS_CMD_CMPLT_WERROR) 6075 return (1); 6076 6077 return (0); 6078 } 6079 6080 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf)); 6081 return (1); 6082} 6083 6084/****************************************************************************/ 6085/* */ 6086/* Routine Name: ips_readwrite_page5 */ 6087/* */ 6088/* Routine Description: */ 6089/* */ 6090/* Read nvram page 5 from the adapter */ 6091/* */ 6092/****************************************************************************/ 6093static int 6094ips_readwrite_page5(ips_ha_t * ha, int write, int intr) 6095{ 6096 ips_scb_t *scb; 6097 int ret; 6098 6099 METHOD_TRACE("ips_readwrite_page5", 1); 6100 6101 scb = &ha->scbs[ha->max_cmds - 1]; 6102 6103 ips_init_scb(ha, scb); 6104 6105 scb->timeout = ips_cmd_timeout; 6106 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE; 6107 6108 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE; 6109 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb); 6110 scb->cmd.nvram.page = 5; 6111 scb->cmd.nvram.write = write; 6112 scb->cmd.nvram.reserved = 0; 6113 scb->cmd.nvram.reserved2 = 0; 6114 scb->data_len = sizeof (*ha->nvram); 6115 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr; 6116 if (write) 6117 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram)); 6118 6119 /* issue the command */ 6120 if (((ret = 6121 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 6122 || (ret == IPS_SUCCESS_IMM) 6123 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 6124 6125 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5)); 6126 6127 return (0); 6128 } 6129 if (!write) 6130 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram)); 6131 return (1); 6132} 6133 6134/****************************************************************************/ 6135/* */ 6136/* Routine Name: ips_clear_adapter */ 6137/* */ 6138/* Routine Description: */ 6139/* */ 6140/* Clear the stripe lock tables */ 6141/* */ 6142/****************************************************************************/ 6143static int 6144ips_clear_adapter(ips_ha_t * ha, int intr) 6145{ 6146 ips_scb_t *scb; 6147 int ret; 6148 6149 METHOD_TRACE("ips_clear_adapter", 1); 6150 6151 scb = &ha->scbs[ha->max_cmds - 1]; 6152 6153 ips_init_scb(ha, scb); 6154 6155 scb->timeout = ips_reset_timeout; 6156 scb->cdb[0] = IPS_CMD_CONFIG_SYNC; 6157 6158 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC; 6159 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb); 6160 scb->cmd.config_sync.channel = 0; 6161 scb->cmd.config_sync.source_target = IPS_POCL; 6162 scb->cmd.config_sync.reserved = 0; 6163 scb->cmd.config_sync.reserved2 = 0; 6164 scb->cmd.config_sync.reserved3 = 0; 6165 6166 /* issue command */ 6167 if (((ret = 6168 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE) 6169 || (ret == IPS_SUCCESS_IMM) 6170 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 6171 return (0); 6172 6173 /* send unlock stripe command */ 6174 ips_init_scb(ha, scb); 6175 6176 scb->cdb[0] = IPS_CMD_ERROR_TABLE; 6177 scb->timeout = ips_reset_timeout; 6178 6179 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE; 6180 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb); 6181 scb->cmd.unlock_stripe.log_drv = 0; 6182 scb->cmd.unlock_stripe.control = IPS_CSL; 6183 scb->cmd.unlock_stripe.reserved = 0; 6184 scb->cmd.unlock_stripe.reserved2 = 0; 6185 scb->cmd.unlock_stripe.reserved3 = 0; 6186 6187 /* issue command */ 6188 if (((ret = 6189 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 6190 || (ret == IPS_SUCCESS_IMM) 6191 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 6192 return (0); 6193 6194 return (1); 6195} 6196 6197/****************************************************************************/ 6198/* */ 6199/* Routine Name: ips_ffdc_reset */ 6200/* */ 6201/* Routine Description: */ 6202/* */ 6203/* FFDC: write reset info */ 6204/* */ 6205/****************************************************************************/ 6206static void 6207ips_ffdc_reset(ips_ha_t * ha, int intr) 6208{ 6209 ips_scb_t *scb; 6210 6211 METHOD_TRACE("ips_ffdc_reset", 1); 6212 6213 scb = &ha->scbs[ha->max_cmds - 1]; 6214 6215 ips_init_scb(ha, scb); 6216 6217 scb->timeout = ips_cmd_timeout; 6218 scb->cdb[0] = IPS_CMD_FFDC; 6219 scb->cmd.ffdc.op_code = IPS_CMD_FFDC; 6220 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); 6221 scb->cmd.ffdc.reset_count = ha->reset_count; 6222 scb->cmd.ffdc.reset_type = 0x80; 6223 6224 /* convert time to what the card wants */ 6225 ips_fix_ffdc_time(ha, scb, ha->last_ffdc); 6226 6227 /* issue command */ 6228 ips_send_wait(ha, scb, ips_cmd_timeout, intr); 6229} 6230 6231/****************************************************************************/ 6232/* */ 6233/* Routine Name: ips_ffdc_time */ 6234/* */ 6235/* Routine Description: */ 6236/* */ 6237/* FFDC: write time info */ 6238/* */ 6239/****************************************************************************/ 6240static void 6241ips_ffdc_time(ips_ha_t * ha) 6242{ 6243 ips_scb_t *scb; 6244 6245 METHOD_TRACE("ips_ffdc_time", 1); 6246 6247 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num); 6248 6249 scb = &ha->scbs[ha->max_cmds - 1]; 6250 6251 ips_init_scb(ha, scb); 6252 6253 scb->timeout = ips_cmd_timeout; 6254 scb->cdb[0] = IPS_CMD_FFDC; 6255 scb->cmd.ffdc.op_code = IPS_CMD_FFDC; 6256 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); 6257 scb->cmd.ffdc.reset_count = 0; 6258 scb->cmd.ffdc.reset_type = 0; 6259 6260 /* convert time to what the card wants */ 6261 ips_fix_ffdc_time(ha, scb, ha->last_ffdc); 6262 6263 /* issue command */ 6264 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC); 6265} 6266 6267/****************************************************************************/ 6268/* */ 6269/* Routine Name: ips_fix_ffdc_time */ 6270/* */ 6271/* Routine Description: */ 6272/* Adjust time_t to what the card wants */ 6273/* */ 6274/****************************************************************************/ 6275static void 6276ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time) 6277{ 6278 long days; 6279 long rem; 6280 int i; 6281 int year; 6282 int yleap; 6283 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR }; 6284 int month_lengths[12][2] = { {31, 31}, 6285 {28, 29}, 6286 {31, 31}, 6287 {30, 30}, 6288 {31, 31}, 6289 {30, 30}, 6290 {31, 31}, 6291 {31, 31}, 6292 {30, 30}, 6293 {31, 31}, 6294 {30, 30}, 6295 {31, 31} 6296 }; 6297 6298 METHOD_TRACE("ips_fix_ffdc_time", 1); 6299 6300 days = current_time / IPS_SECS_DAY; 6301 rem = current_time % IPS_SECS_DAY; 6302 6303 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR); 6304 rem = rem % IPS_SECS_HOUR; 6305 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN); 6306 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN); 6307 6308 year = IPS_EPOCH_YEAR; 6309 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) { 6310 int newy; 6311 6312 newy = year + (days / IPS_DAYS_NORMAL_YEAR); 6313 if (days < 0) 6314 --newy; 6315 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR + 6316 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) - 6317 IPS_NUM_LEAP_YEARS_THROUGH(year - 1); 6318 year = newy; 6319 } 6320 6321 scb->cmd.ffdc.yearH = year / 100; 6322 scb->cmd.ffdc.yearL = year % 100; 6323 6324 for (i = 0; days >= month_lengths[i][yleap]; ++i) 6325 days -= month_lengths[i][yleap]; 6326 6327 scb->cmd.ffdc.month = i + 1; 6328 scb->cmd.ffdc.day = days + 1; 6329} 6330 6331/**************************************************************************** 6332 * BIOS Flash Routines * 6333 ****************************************************************************/ 6334 6335/****************************************************************************/ 6336/* */ 6337/* Routine Name: ips_erase_bios */ 6338/* */ 6339/* Routine Description: */ 6340/* Erase the BIOS on the adapter */ 6341/* */ 6342/****************************************************************************/ 6343static int 6344ips_erase_bios(ips_ha_t * ha) 6345{ 6346 int timeout; 6347 uint8_t status = 0; 6348 6349 METHOD_TRACE("ips_erase_bios", 1); 6350 6351 status = 0; 6352 6353 /* Clear the status register */ 6354 outl(0, ha->io_addr + IPS_REG_FLAP); 6355 if (ha->revision_id == IPS_REVID_TROMBONE64) 6356 udelay(25); /* 25 us */ 6357 6358 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6359 if (ha->revision_id == IPS_REVID_TROMBONE64) 6360 udelay(25); /* 25 us */ 6361 6362 /* Erase Setup */ 6363 outb(0x20, ha->io_addr + IPS_REG_FLDP); 6364 if (ha->revision_id == IPS_REVID_TROMBONE64) 6365 udelay(25); /* 25 us */ 6366 6367 /* Erase Confirm */ 6368 outb(0xD0, ha->io_addr + IPS_REG_FLDP); 6369 if (ha->revision_id == IPS_REVID_TROMBONE64) 6370 udelay(25); /* 25 us */ 6371 6372 /* Erase Status */ 6373 outb(0x70, ha->io_addr + IPS_REG_FLDP); 6374 if (ha->revision_id == IPS_REVID_TROMBONE64) 6375 udelay(25); /* 25 us */ 6376 6377 timeout = 80000; /* 80 seconds */ 6378 6379 while (timeout > 0) { 6380 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6381 outl(0, ha->io_addr + IPS_REG_FLAP); 6382 udelay(25); /* 25 us */ 6383 } 6384 6385 status = inb(ha->io_addr + IPS_REG_FLDP); 6386 6387 if (status & 0x80) 6388 break; 6389 6390 MDELAY(1); 6391 timeout--; 6392 } 6393 6394 /* check for timeout */ 6395 if (timeout <= 0) { 6396 /* timeout */ 6397 6398 /* try to suspend the erase */ 6399 outb(0xB0, ha->io_addr + IPS_REG_FLDP); 6400 if (ha->revision_id == IPS_REVID_TROMBONE64) 6401 udelay(25); /* 25 us */ 6402 6403 /* wait for 10 seconds */ 6404 timeout = 10000; 6405 while (timeout > 0) { 6406 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6407 outl(0, ha->io_addr + IPS_REG_FLAP); 6408 udelay(25); /* 25 us */ 6409 } 6410 6411 status = inb(ha->io_addr + IPS_REG_FLDP); 6412 6413 if (status & 0xC0) 6414 break; 6415 6416 MDELAY(1); 6417 timeout--; 6418 } 6419 6420 return (1); 6421 } 6422 6423 /* check for valid VPP */ 6424 if (status & 0x08) 6425 /* VPP failure */ 6426 return (1); 6427 6428 /* check for successful flash */ 6429 if (status & 0x30) 6430 /* sequence error */ 6431 return (1); 6432 6433 /* Otherwise, we were successful */ 6434 /* clear status */ 6435 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6436 if (ha->revision_id == IPS_REVID_TROMBONE64) 6437 udelay(25); /* 25 us */ 6438 6439 /* enable reads */ 6440 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6441 if (ha->revision_id == IPS_REVID_TROMBONE64) 6442 udelay(25); /* 25 us */ 6443 6444 return (0); 6445} 6446 6447/****************************************************************************/ 6448/* */ 6449/* Routine Name: ips_erase_bios_memio */ 6450/* */ 6451/* Routine Description: */ 6452/* Erase the BIOS on the adapter */ 6453/* */ 6454/****************************************************************************/ 6455static int 6456ips_erase_bios_memio(ips_ha_t * ha) 6457{ 6458 int timeout; 6459 uint8_t status; 6460 6461 METHOD_TRACE("ips_erase_bios_memio", 1); 6462 6463 status = 0; 6464 6465 /* Clear the status register */ 6466 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6467 if (ha->revision_id == IPS_REVID_TROMBONE64) 6468 udelay(25); /* 25 us */ 6469 6470 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6471 if (ha->revision_id == IPS_REVID_TROMBONE64) 6472 udelay(25); /* 25 us */ 6473 6474 /* Erase Setup */ 6475 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); 6476 if (ha->revision_id == IPS_REVID_TROMBONE64) 6477 udelay(25); /* 25 us */ 6478 6479 /* Erase Confirm */ 6480 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); 6481 if (ha->revision_id == IPS_REVID_TROMBONE64) 6482 udelay(25); /* 25 us */ 6483 6484 /* Erase Status */ 6485 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); 6486 if (ha->revision_id == IPS_REVID_TROMBONE64) 6487 udelay(25); /* 25 us */ 6488 6489 timeout = 80000; /* 80 seconds */ 6490 6491 while (timeout > 0) { 6492 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6493 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6494 udelay(25); /* 25 us */ 6495 } 6496 6497 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6498 6499 if (status & 0x80) 6500 break; 6501 6502 MDELAY(1); 6503 timeout--; 6504 } 6505 6506 /* check for timeout */ 6507 if (timeout <= 0) { 6508 /* timeout */ 6509 6510 /* try to suspend the erase */ 6511 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); 6512 if (ha->revision_id == IPS_REVID_TROMBONE64) 6513 udelay(25); /* 25 us */ 6514 6515 /* wait for 10 seconds */ 6516 timeout = 10000; 6517 while (timeout > 0) { 6518 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6519 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6520 udelay(25); /* 25 us */ 6521 } 6522 6523 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6524 6525 if (status & 0xC0) 6526 break; 6527 6528 MDELAY(1); 6529 timeout--; 6530 } 6531 6532 return (1); 6533 } 6534 6535 /* check for valid VPP */ 6536 if (status & 0x08) 6537 /* VPP failure */ 6538 return (1); 6539 6540 /* check for successful flash */ 6541 if (status & 0x30) 6542 /* sequence error */ 6543 return (1); 6544 6545 /* Otherwise, we were successful */ 6546 /* clear status */ 6547 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6548 if (ha->revision_id == IPS_REVID_TROMBONE64) 6549 udelay(25); /* 25 us */ 6550 6551 /* enable reads */ 6552 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6553 if (ha->revision_id == IPS_REVID_TROMBONE64) 6554 udelay(25); /* 25 us */ 6555 6556 return (0); 6557} 6558 6559/****************************************************************************/ 6560/* */ 6561/* Routine Name: ips_program_bios */ 6562/* */ 6563/* Routine Description: */ 6564/* Program the BIOS on the adapter */ 6565/* */ 6566/****************************************************************************/ 6567static int 6568ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6569 uint32_t offset) 6570{ 6571 int i; 6572 int timeout; 6573 uint8_t status = 0; 6574 6575 METHOD_TRACE("ips_program_bios", 1); 6576 6577 status = 0; 6578 6579 for (i = 0; i < buffersize; i++) { 6580 /* write a byte */ 6581 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); 6582 if (ha->revision_id == IPS_REVID_TROMBONE64) 6583 udelay(25); /* 25 us */ 6584 6585 outb(0x40, ha->io_addr + IPS_REG_FLDP); 6586 if (ha->revision_id == IPS_REVID_TROMBONE64) 6587 udelay(25); /* 25 us */ 6588 6589 outb(buffer[i], ha->io_addr + IPS_REG_FLDP); 6590 if (ha->revision_id == IPS_REVID_TROMBONE64) 6591 udelay(25); /* 25 us */ 6592 6593 /* wait up to one second */ 6594 timeout = 1000; 6595 while (timeout > 0) { 6596 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6597 outl(0, ha->io_addr + IPS_REG_FLAP); 6598 udelay(25); /* 25 us */ 6599 } 6600 6601 status = inb(ha->io_addr + IPS_REG_FLDP); 6602 6603 if (status & 0x80) 6604 break; 6605 6606 MDELAY(1); 6607 timeout--; 6608 } 6609 6610 if (timeout == 0) { 6611 /* timeout error */ 6612 outl(0, ha->io_addr + IPS_REG_FLAP); 6613 if (ha->revision_id == IPS_REVID_TROMBONE64) 6614 udelay(25); /* 25 us */ 6615 6616 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6617 if (ha->revision_id == IPS_REVID_TROMBONE64) 6618 udelay(25); /* 25 us */ 6619 6620 return (1); 6621 } 6622 6623 /* check the status */ 6624 if (status & 0x18) { 6625 /* programming error */ 6626 outl(0, ha->io_addr + IPS_REG_FLAP); 6627 if (ha->revision_id == IPS_REVID_TROMBONE64) 6628 udelay(25); /* 25 us */ 6629 6630 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6631 if (ha->revision_id == IPS_REVID_TROMBONE64) 6632 udelay(25); /* 25 us */ 6633 6634 return (1); 6635 } 6636 } /* end for */ 6637 6638 /* Enable reading */ 6639 outl(0, ha->io_addr + IPS_REG_FLAP); 6640 if (ha->revision_id == IPS_REVID_TROMBONE64) 6641 udelay(25); /* 25 us */ 6642 6643 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6644 if (ha->revision_id == IPS_REVID_TROMBONE64) 6645 udelay(25); /* 25 us */ 6646 6647 return (0); 6648} 6649 6650/****************************************************************************/ 6651/* */ 6652/* Routine Name: ips_program_bios_memio */ 6653/* */ 6654/* Routine Description: */ 6655/* Program the BIOS on the adapter */ 6656/* */ 6657/****************************************************************************/ 6658static int 6659ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6660 uint32_t offset) 6661{ 6662 int i; 6663 int timeout; 6664 uint8_t status = 0; 6665 6666 METHOD_TRACE("ips_program_bios_memio", 1); 6667 6668 status = 0; 6669 6670 for (i = 0; i < buffersize; i++) { 6671 /* write a byte */ 6672 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6673 if (ha->revision_id == IPS_REVID_TROMBONE64) 6674 udelay(25); /* 25 us */ 6675 6676 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); 6677 if (ha->revision_id == IPS_REVID_TROMBONE64) 6678 udelay(25); /* 25 us */ 6679 6680 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); 6681 if (ha->revision_id == IPS_REVID_TROMBONE64) 6682 udelay(25); /* 25 us */ 6683 6684 /* wait up to one second */ 6685 timeout = 1000; 6686 while (timeout > 0) { 6687 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6688 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6689 udelay(25); /* 25 us */ 6690 } 6691 6692 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6693 6694 if (status & 0x80) 6695 break; 6696 6697 MDELAY(1); 6698 timeout--; 6699 } 6700 6701 if (timeout == 0) { 6702 /* timeout error */ 6703 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6704 if (ha->revision_id == IPS_REVID_TROMBONE64) 6705 udelay(25); /* 25 us */ 6706 6707 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6708 if (ha->revision_id == IPS_REVID_TROMBONE64) 6709 udelay(25); /* 25 us */ 6710 6711 return (1); 6712 } 6713 6714 /* check the status */ 6715 if (status & 0x18) { 6716 /* programming error */ 6717 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6718 if (ha->revision_id == IPS_REVID_TROMBONE64) 6719 udelay(25); /* 25 us */ 6720 6721 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6722 if (ha->revision_id == IPS_REVID_TROMBONE64) 6723 udelay(25); /* 25 us */ 6724 6725 return (1); 6726 } 6727 } /* end for */ 6728 6729 /* Enable reading */ 6730 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6731 if (ha->revision_id == IPS_REVID_TROMBONE64) 6732 udelay(25); /* 25 us */ 6733 6734 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6735 if (ha->revision_id == IPS_REVID_TROMBONE64) 6736 udelay(25); /* 25 us */ 6737 6738 return (0); 6739} 6740 6741/****************************************************************************/ 6742/* */ 6743/* Routine Name: ips_verify_bios */ 6744/* */ 6745/* Routine Description: */ 6746/* Verify the BIOS on the adapter */ 6747/* */ 6748/****************************************************************************/ 6749static int 6750ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6751 uint32_t offset) 6752{ 6753 uint8_t checksum; 6754 int i; 6755 6756 METHOD_TRACE("ips_verify_bios", 1); 6757 6758 /* test 1st byte */ 6759 outl(0, ha->io_addr + IPS_REG_FLAP); 6760 if (ha->revision_id == IPS_REVID_TROMBONE64) 6761 udelay(25); /* 25 us */ 6762 6763 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 6764 return (1); 6765 6766 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); 6767 if (ha->revision_id == IPS_REVID_TROMBONE64) 6768 udelay(25); /* 25 us */ 6769 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 6770 return (1); 6771 6772 checksum = 0xff; 6773 for (i = 2; i < buffersize; i++) { 6774 6775 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); 6776 if (ha->revision_id == IPS_REVID_TROMBONE64) 6777 udelay(25); /* 25 us */ 6778 6779 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP); 6780 } 6781 6782 if (checksum != 0) 6783 /* failure */ 6784 return (1); 6785 else 6786 /* success */ 6787 return (0); 6788} 6789 6790/****************************************************************************/ 6791/* */ 6792/* Routine Name: ips_verify_bios_memio */ 6793/* */ 6794/* Routine Description: */ 6795/* Verify the BIOS on the adapter */ 6796/* */ 6797/****************************************************************************/ 6798static int 6799ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6800 uint32_t offset) 6801{ 6802 uint8_t checksum; 6803 int i; 6804 6805 METHOD_TRACE("ips_verify_bios_memio", 1); 6806 6807 /* test 1st byte */ 6808 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6809 if (ha->revision_id == IPS_REVID_TROMBONE64) 6810 udelay(25); /* 25 us */ 6811 6812 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 6813 return (1); 6814 6815 writel(1, ha->mem_ptr + IPS_REG_FLAP); 6816 if (ha->revision_id == IPS_REVID_TROMBONE64) 6817 udelay(25); /* 25 us */ 6818 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 6819 return (1); 6820 6821 checksum = 0xff; 6822 for (i = 2; i < buffersize; i++) { 6823 6824 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6825 if (ha->revision_id == IPS_REVID_TROMBONE64) 6826 udelay(25); /* 25 us */ 6827 6828 checksum = 6829 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); 6830 } 6831 6832 if (checksum != 0) 6833 /* failure */ 6834 return (1); 6835 else 6836 /* success */ 6837 return (0); 6838} 6839 6840/****************************************************************************/ 6841/* */ 6842/* Routine Name: ips_abort_init */ 6843/* */ 6844/* Routine Description: */ 6845/* cleanup routine for a failed adapter initialization */ 6846/****************************************************************************/ 6847static int 6848ips_abort_init(ips_ha_t * ha, int index) 6849{ 6850 ha->active = 0; 6851 ips_free(ha); 6852 ips_ha[index] = NULL; 6853 ips_sh[index] = NULL; 6854 return -1; 6855} 6856 6857/****************************************************************************/ 6858/* */ 6859/* Routine Name: ips_shift_controllers */ 6860/* */ 6861/* Routine Description: */ 6862/* helper function for ordering adapters */ 6863/****************************************************************************/ 6864static void 6865ips_shift_controllers(int lowindex, int highindex) 6866{ 6867 ips_ha_t *ha_sav = ips_ha[highindex]; 6868 struct Scsi_Host *sh_sav = ips_sh[highindex]; 6869 int i; 6870 6871 for (i = highindex; i > lowindex; i--) { 6872 ips_ha[i] = ips_ha[i - 1]; 6873 ips_sh[i] = ips_sh[i - 1]; 6874 ips_ha[i]->host_num = i; 6875 } 6876 ha_sav->host_num = lowindex; 6877 ips_ha[lowindex] = ha_sav; 6878 ips_sh[lowindex] = sh_sav; 6879} 6880 6881/****************************************************************************/ 6882/* */ 6883/* Routine Name: ips_order_controllers */ 6884/* */ 6885/* Routine Description: */ 6886/* place controllers is the "proper" boot order */ 6887/****************************************************************************/ 6888static void 6889ips_order_controllers(void) 6890{ 6891 int i, j, tmp, position = 0; 6892 IPS_NVRAM_P5 *nvram; 6893 if (!ips_ha[0]) 6894 return; 6895 nvram = ips_ha[0]->nvram; 6896 6897 if (nvram->adapter_order[0]) { 6898 for (i = 1; i <= nvram->adapter_order[0]; i++) { 6899 for (j = position; j < ips_num_controllers; j++) { 6900 switch (ips_ha[j]->ad_type) { 6901 case IPS_ADTYPE_SERVERAID6M: 6902 case IPS_ADTYPE_SERVERAID7M: 6903 if (nvram->adapter_order[i] == 'M') { 6904 ips_shift_controllers(position, 6905 j); 6906 position++; 6907 } 6908 break; 6909 case IPS_ADTYPE_SERVERAID4L: 6910 case IPS_ADTYPE_SERVERAID4M: 6911 case IPS_ADTYPE_SERVERAID4MX: 6912 case IPS_ADTYPE_SERVERAID4LX: 6913 if (nvram->adapter_order[i] == 'N') { 6914 ips_shift_controllers(position, 6915 j); 6916 position++; 6917 } 6918 break; 6919 case IPS_ADTYPE_SERVERAID6I: 6920 case IPS_ADTYPE_SERVERAID5I2: 6921 case IPS_ADTYPE_SERVERAID5I1: 6922 case IPS_ADTYPE_SERVERAID7k: 6923 if (nvram->adapter_order[i] == 'S') { 6924 ips_shift_controllers(position, 6925 j); 6926 position++; 6927 } 6928 break; 6929 case IPS_ADTYPE_SERVERAID: 6930 case IPS_ADTYPE_SERVERAID2: 6931 case IPS_ADTYPE_NAVAJO: 6932 case IPS_ADTYPE_KIOWA: 6933 case IPS_ADTYPE_SERVERAID3L: 6934 case IPS_ADTYPE_SERVERAID3: 6935 case IPS_ADTYPE_SERVERAID4H: 6936 if (nvram->adapter_order[i] == 'A') { 6937 ips_shift_controllers(position, 6938 j); 6939 position++; 6940 } 6941 break; 6942 default: 6943 break; 6944 } 6945 } 6946 } 6947 /* if adapter_order[0], then ordering is complete */ 6948 return; 6949 } 6950 /* old bios, use older ordering */ 6951 tmp = 0; 6952 for (i = position; i < ips_num_controllers; i++) { 6953 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 || 6954 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) { 6955 ips_shift_controllers(position, i); 6956 position++; 6957 tmp = 1; 6958 } 6959 } 6960 /* if there were no 5I cards, then don't do any extra ordering */ 6961 if (!tmp) 6962 return; 6963 for (i = position; i < ips_num_controllers; i++) { 6964 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L || 6965 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M || 6966 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX || 6967 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) { 6968 ips_shift_controllers(position, i); 6969 position++; 6970 } 6971 } 6972 6973 return; 6974} 6975 6976/****************************************************************************/ 6977/* */ 6978/* Routine Name: ips_register_scsi */ 6979/* */ 6980/* Routine Description: */ 6981/* perform any registration and setup with the scsi layer */ 6982/****************************************************************************/ 6983static int 6984ips_register_scsi(int index) 6985{ 6986 struct Scsi_Host *sh; 6987 ips_ha_t *ha, *oldha = ips_ha[index]; 6988 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t)); 6989 if (!sh) { 6990 IPS_PRINTK(KERN_WARNING, oldha->pcidev, 6991 "Unable to register controller with SCSI subsystem\n"); 6992 return -1; 6993 } 6994 ha = IPS_HA(sh); 6995 memcpy(ha, oldha, sizeof (ips_ha_t)); 6996 free_irq(oldha->irq, oldha); 6997 /* Install the interrupt handler with the new ha */ 6998 if (request_irq(ha->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 6999 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7000 "Unable to install interrupt handler\n"); 7001 scsi_host_put(sh); 7002 return -1; 7003 } 7004 7005 kfree(oldha); 7006 ips_sh[index] = sh; 7007 ips_ha[index] = ha; 7008 IPS_SCSI_SET_DEVICE(sh, ha); 7009 7010 /* Store away needed values for later use */ 7011 sh->io_port = ha->io_addr; 7012 sh->n_io_port = ha->io_addr ? 255 : 0; 7013 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; 7014 sh->irq = ha->irq; 7015 sh->sg_tablesize = sh->hostt->sg_tablesize; 7016 sh->can_queue = sh->hostt->can_queue; 7017 sh->cmd_per_lun = sh->hostt->cmd_per_lun; 7018 sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma; 7019 sh->use_clustering = sh->hostt->use_clustering; 7020 7021#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,7) 7022 sh->max_sectors = 128; 7023#endif 7024 7025 sh->max_id = ha->ntargets; 7026 sh->max_lun = ha->nlun; 7027 sh->max_channel = ha->nbus - 1; 7028 sh->can_queue = ha->max_cmds - 1; 7029 7030 IPS_ADD_HOST(sh, NULL); 7031 return 0; 7032} 7033 7034/*---------------------------------------------------------------------------*/ 7035/* Routine Name: ips_remove_device */ 7036/* */ 7037/* Routine Description: */ 7038/* Remove one Adapter ( Hot Plugging ) */ 7039/*---------------------------------------------------------------------------*/ 7040static void __devexit 7041ips_remove_device(struct pci_dev *pci_dev) 7042{ 7043 int i; 7044 struct Scsi_Host *sh; 7045 ips_ha_t *ha; 7046 7047 for (i = 0; i < IPS_MAX_ADAPTERS; i++) { 7048 ha = ips_ha[i]; 7049 if (ha) { 7050 if ((pci_dev->bus->number == ha->pcidev->bus->number) && 7051 (pci_dev->devfn == ha->pcidev->devfn)) { 7052 sh = ips_sh[i]; 7053 ips_release(sh); 7054 } 7055 } 7056 } 7057} 7058 7059/****************************************************************************/ 7060/* */ 7061/* Routine Name: ips_module_init */ 7062/* */ 7063/* Routine Description: */ 7064/* function called on module load */ 7065/****************************************************************************/ 7066static int __init 7067ips_module_init(void) 7068{ 7069 if (pci_register_driver(&ips_pci_driver) < 0) 7070 return -ENODEV; 7071 ips_driver_template.module = THIS_MODULE; 7072 ips_order_controllers(); 7073 if (IPS_REGISTER_HOSTS(&ips_driver_template)) { 7074 pci_unregister_driver(&ips_pci_driver); 7075 return -ENODEV; 7076 } 7077 register_reboot_notifier(&ips_notifier); 7078 return 0; 7079} 7080 7081/****************************************************************************/ 7082/* */ 7083/* Routine Name: ips_module_exit */ 7084/* */ 7085/* Routine Description: */ 7086/* function called on module unload */ 7087/****************************************************************************/ 7088static void __exit 7089ips_module_exit(void) 7090{ 7091 IPS_UNREGISTER_HOSTS(&ips_driver_template); 7092 pci_unregister_driver(&ips_pci_driver); 7093 unregister_reboot_notifier(&ips_notifier); 7094} 7095 7096module_init(ips_module_init); 7097module_exit(ips_module_exit); 7098 7099/*---------------------------------------------------------------------------*/ 7100/* Routine Name: ips_insert_device */ 7101/* */ 7102/* Routine Description: */ 7103/* Add One Adapter ( Hot Plug ) */ 7104/* */ 7105/* Return Value: */ 7106/* 0 if Successful, else non-zero */ 7107/*---------------------------------------------------------------------------*/ 7108static int __devinit 7109ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent) 7110{ 7111 int index; 7112 int rc; 7113 7114 METHOD_TRACE("ips_insert_device", 1); 7115 if (pci_enable_device(pci_dev)) 7116 return -1; 7117 7118 rc = ips_init_phase1(pci_dev, &index); 7119 if (rc == SUCCESS) 7120 rc = ips_init_phase2(index); 7121 7122 if (ips_hotplug) 7123 if (ips_register_scsi(index)) { 7124 ips_free(ips_ha[index]); 7125 rc = -1; 7126 } 7127 7128 if (rc == SUCCESS) 7129 ips_num_controllers++; 7130 7131 ips_next_controller = ips_num_controllers; 7132 return rc; 7133} 7134 7135/*---------------------------------------------------------------------------*/ 7136/* Routine Name: ips_init_phase1 */ 7137/* */ 7138/* Routine Description: */ 7139/* Adapter Initialization */ 7140/* */ 7141/* Return Value: */ 7142/* 0 if Successful, else non-zero */ 7143/*---------------------------------------------------------------------------*/ 7144static int 7145ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) 7146{ 7147 ips_ha_t *ha; 7148 uint32_t io_addr; 7149 uint32_t mem_addr; 7150 uint32_t io_len; 7151 uint32_t mem_len; 7152 uint8_t revision_id; 7153 uint8_t bus; 7154 uint8_t func; 7155 uint8_t irq; 7156 uint16_t subdevice_id; 7157 int j; 7158 int index; 7159 dma_addr_t dma_address; 7160 char __iomem *ioremap_ptr; 7161 char __iomem *mem_ptr; 7162 uint32_t IsDead; 7163 7164 METHOD_TRACE("ips_init_phase1", 1); 7165 index = IPS_MAX_ADAPTERS; 7166 for (j = 0; j < IPS_MAX_ADAPTERS; j++) { 7167 if (ips_ha[j] == 0) { 7168 index = j; 7169 break; 7170 } 7171 } 7172 7173 if (index >= IPS_MAX_ADAPTERS) 7174 return -1; 7175 7176 /* stuff that we get in dev */ 7177 irq = pci_dev->irq; 7178 bus = pci_dev->bus->number; 7179 func = pci_dev->devfn; 7180 7181 /* Init MEM/IO addresses to 0 */ 7182 mem_addr = 0; 7183 io_addr = 0; 7184 mem_len = 0; 7185 io_len = 0; 7186 7187 for (j = 0; j < 2; j++) { 7188 if (!pci_resource_start(pci_dev, j)) 7189 break; 7190 7191 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) { 7192 io_addr = pci_resource_start(pci_dev, j); 7193 io_len = pci_resource_len(pci_dev, j); 7194 } else { 7195 mem_addr = pci_resource_start(pci_dev, j); 7196 mem_len = pci_resource_len(pci_dev, j); 7197 } 7198 } 7199 7200 /* setup memory mapped area (if applicable) */ 7201 if (mem_addr) { 7202 uint32_t base; 7203 uint32_t offs; 7204 7205 if (!request_mem_region(mem_addr, mem_len, "ips")) { 7206 IPS_PRINTK(KERN_WARNING, pci_dev, 7207 "Couldn't allocate IO Memory space %x len %d.\n", 7208 mem_addr, mem_len); 7209 return -1; 7210 } 7211 7212 base = mem_addr & PAGE_MASK; 7213 offs = mem_addr - base; 7214 ioremap_ptr = ioremap(base, PAGE_SIZE); 7215 mem_ptr = ioremap_ptr + offs; 7216 } else { 7217 ioremap_ptr = NULL; 7218 mem_ptr = NULL; 7219 } 7220 7221 /* setup I/O mapped area (if applicable) */ 7222 if (io_addr) { 7223 if (!request_region(io_addr, io_len, "ips")) { 7224 IPS_PRINTK(KERN_WARNING, pci_dev, 7225 "Couldn't allocate IO space %x len %d.\n", 7226 io_addr, io_len); 7227 return -1; 7228 } 7229 } 7230 7231 /* get the revision ID */ 7232 if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) { 7233 IPS_PRINTK(KERN_WARNING, pci_dev, "Can't get revision id.\n"); 7234 return -1; 7235 } 7236 7237 subdevice_id = pci_dev->subsystem_device; 7238 7239 /* found a controller */ 7240 ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL); 7241 if (ha == NULL) { 7242 IPS_PRINTK(KERN_WARNING, pci_dev, 7243 "Unable to allocate temporary ha struct\n"); 7244 return -1; 7245 } 7246 7247 memset(ha, 0, sizeof (ips_ha_t)); 7248 7249 ips_sh[index] = NULL; 7250 ips_ha[index] = ha; 7251 ha->active = 1; 7252 7253 /* Store info in HA structure */ 7254 ha->irq = irq; 7255 ha->io_addr = io_addr; 7256 ha->io_len = io_len; 7257 ha->mem_addr = mem_addr; 7258 ha->mem_len = mem_len; 7259 ha->mem_ptr = mem_ptr; 7260 ha->ioremap_ptr = ioremap_ptr; 7261 ha->host_num = (uint32_t) index; 7262 ha->revision_id = revision_id; 7263 ha->slot_num = PCI_SLOT(pci_dev->devfn); 7264 ha->device_id = pci_dev->device; 7265 ha->subdevice_id = subdevice_id; 7266 ha->pcidev = pci_dev; 7267 7268 /* 7269 * Set the pci_dev's dma_mask. Not all adapters support 64bit 7270 * addressing so don't enable it if the adapter can't support 7271 * it! Also, don't use 64bit addressing if dma addresses 7272 * are guaranteed to be < 4G. 7273 */ 7274 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) && 7275 !pci_set_dma_mask(ha->pcidev, DMA_64BIT_MASK)) { 7276 (ha)->flags |= IPS_HA_ENH_SG; 7277 } else { 7278 if (pci_set_dma_mask(ha->pcidev, DMA_32BIT_MASK) != 0) { 7279 printk(KERN_WARNING "Unable to set DMA Mask\n"); 7280 return ips_abort_init(ha, index); 7281 } 7282 } 7283 if(ips_cd_boot && !ips_FlashData){ 7284 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7, 7285 &ips_flashbusaddr); 7286 } 7287 7288 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ), 7289 &ha->enq_busaddr); 7290 if (!ha->enq) { 7291 IPS_PRINTK(KERN_WARNING, pci_dev, 7292 "Unable to allocate host inquiry structure\n"); 7293 return ips_abort_init(ha, index); 7294 } 7295 7296 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) + 7297 sizeof (IPS_IO_CMD), &dma_address); 7298 if (!ha->adapt) { 7299 IPS_PRINTK(KERN_WARNING, pci_dev, 7300 "Unable to allocate host adapt & dummy structures\n"); 7301 return ips_abort_init(ha, index); 7302 } 7303 ha->adapt->hw_status_start = dma_address; 7304 ha->dummy = (void *) (ha->adapt + 1); 7305 7306 7307 7308 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address); 7309 if (!ha->logical_drive_info) { 7310 IPS_PRINTK(KERN_WARNING, pci_dev, 7311 "Unable to allocate logical drive info structure\n"); 7312 return ips_abort_init(ha, index); 7313 } 7314 ha->logical_drive_info_dma_addr = dma_address; 7315 7316 7317 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL); 7318 7319 if (!ha->conf) { 7320 IPS_PRINTK(KERN_WARNING, pci_dev, 7321 "Unable to allocate host conf structure\n"); 7322 return ips_abort_init(ha, index); 7323 } 7324 7325 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL); 7326 7327 if (!ha->nvram) { 7328 IPS_PRINTK(KERN_WARNING, pci_dev, 7329 "Unable to allocate host NVRAM structure\n"); 7330 return ips_abort_init(ha, index); 7331 } 7332 7333 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL); 7334 7335 if (!ha->subsys) { 7336 IPS_PRINTK(KERN_WARNING, pci_dev, 7337 "Unable to allocate host subsystem structure\n"); 7338 return ips_abort_init(ha, index); 7339 } 7340 7341 /* the ioctl buffer is now used during adapter initialization, so its 7342 * successful allocation is now required */ 7343 if (ips_ioctlsize < PAGE_SIZE) 7344 ips_ioctlsize = PAGE_SIZE; 7345 7346 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize, 7347 &ha->ioctl_busaddr); 7348 ha->ioctl_len = ips_ioctlsize; 7349 if (!ha->ioctl_data) { 7350 IPS_PRINTK(KERN_WARNING, pci_dev, 7351 "Unable to allocate IOCTL data\n"); 7352 return ips_abort_init(ha, index); 7353 } 7354 7355 /* 7356 * Setup Functions 7357 */ 7358 ips_setup_funclist(ha); 7359 7360 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) { 7361 /* If Morpheus appears dead, reset it */ 7362 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); 7363 if (IsDead == 0xDEADBEEF) { 7364 ips_reset_morpheus(ha); 7365 } 7366 } 7367 7368 /* 7369 * Initialize the card if it isn't already 7370 */ 7371 7372 if (!(*ha->func.isinit) (ha)) { 7373 if (!(*ha->func.init) (ha)) { 7374 /* 7375 * Initialization failed 7376 */ 7377 IPS_PRINTK(KERN_WARNING, pci_dev, 7378 "Unable to initialize controller\n"); 7379 return ips_abort_init(ha, index); 7380 } 7381 } 7382 7383 *indexPtr = index; 7384 return SUCCESS; 7385} 7386 7387/*---------------------------------------------------------------------------*/ 7388/* Routine Name: ips_init_phase2 */ 7389/* */ 7390/* Routine Description: */ 7391/* Adapter Initialization Phase 2 */ 7392/* */ 7393/* Return Value: */ 7394/* 0 if Successful, else non-zero */ 7395/*---------------------------------------------------------------------------*/ 7396static int 7397ips_init_phase2(int index) 7398{ 7399 ips_ha_t *ha; 7400 7401 ha = ips_ha[index]; 7402 7403 METHOD_TRACE("ips_init_phase2", 1); 7404 if (!ha->active) { 7405 ips_ha[index] = NULL; 7406 return -1; 7407 } 7408 7409 /* Install the interrupt handler */ 7410 if (request_irq(ha->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 7411 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7412 "Unable to install interrupt handler\n"); 7413 return ips_abort_init(ha, index); 7414 } 7415 7416 /* 7417 * Allocate a temporary SCB for initialization 7418 */ 7419 ha->max_cmds = 1; 7420 if (!ips_allocatescbs(ha)) { 7421 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7422 "Unable to allocate a CCB\n"); 7423 free_irq(ha->irq, ha); 7424 return ips_abort_init(ha, index); 7425 } 7426 7427 if (!ips_hainit(ha)) { 7428 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7429 "Unable to initialize controller\n"); 7430 free_irq(ha->irq, ha); 7431 return ips_abort_init(ha, index); 7432 } 7433 /* Free the temporary SCB */ 7434 ips_deallocatescbs(ha, 1); 7435 7436 /* allocate CCBs */ 7437 if (!ips_allocatescbs(ha)) { 7438 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7439 "Unable to allocate CCBs\n"); 7440 free_irq(ha->irq, ha); 7441 return ips_abort_init(ha, index); 7442 } 7443 7444 return SUCCESS; 7445} 7446 7447#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,9) 7448MODULE_LICENSE("GPL"); 7449#endif 7450 7451MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING); 7452 7453#ifdef MODULE_VERSION 7454MODULE_VERSION(IPS_VER_STRING); 7455#endif 7456 7457 7458/* 7459 * Overrides for Emacs so that we almost follow Linus's tabbing style. 7460 * Emacs will notice this stuff at the end of the file and automatically 7461 * adjust the settings for this buffer only. This must remain at the end 7462 * of the file. 7463 * --------------------------------------------------------------------------- 7464 * Local variables: 7465 * c-indent-level: 2 7466 * c-brace-imaginary-offset: 0 7467 * c-brace-offset: -2 7468 * c-argdecl-indent: 2 7469 * c-label-offset: -2 7470 * c-continued-statement-offset: 2 7471 * c-continued-brace-offset: 0 7472 * indent-tabs-mode: nil 7473 * tab-width: 8 7474 * End: 7475 */ 7476