1/* $Id: uctrl.c,v 1.1.1.1 2007/08/03 18:52:55 Exp $
2 * uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3
3 *
4 * Copyright 1999 Derrick J Brashear (shadow@dementia.org)
5 */
6
7#include <linux/module.h>
8#include <linux/errno.h>
9#include <linux/delay.h>
10#include <linux/interrupt.h>
11#include <linux/slab.h>
12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/miscdevice.h>
15#include <linux/mm.h>
16
17#include <asm/openprom.h>
18#include <asm/oplib.h>
19#include <asm/system.h>
20#include <asm/irq.h>
21#include <asm/io.h>
22#include <asm/pgtable.h>
23#include <asm/sbus.h>
24
25#define UCTRL_MINOR	174
26
27#define DEBUG 1
28#ifdef DEBUG
29#define dprintk(x) printk x
30#else
31#define dprintk(x)
32#endif
33
34struct uctrl_regs {
35	volatile u32 uctrl_intr;
36	volatile u32 uctrl_data;
37	volatile u32 uctrl_stat;
38	volatile u32 uctrl_xxx[5];
39};
40
41struct ts102_regs {
42	volatile u32 card_a_intr;
43	volatile u32 card_a_stat;
44	volatile u32 card_a_ctrl;
45	volatile u32 card_a_xxx;
46	volatile u32 card_b_intr;
47	volatile u32 card_b_stat;
48	volatile u32 card_b_ctrl;
49	volatile u32 card_b_xxx;
50	volatile u32 uctrl_intr;
51	volatile u32 uctrl_data;
52	volatile u32 uctrl_stat;
53	volatile u32 uctrl_xxx;
54	volatile u32 ts102_xxx[4];
55};
56
57/* Bits for uctrl_intr register */
58#define UCTRL_INTR_TXE_REQ         0x01    /* transmit FIFO empty int req */
59#define UCTRL_INTR_TXNF_REQ        0x02    /* transmit FIFO not full int req */
60#define UCTRL_INTR_RXNE_REQ        0x04    /* receive FIFO not empty int req */
61#define UCTRL_INTR_RXO_REQ         0x08    /* receive FIFO overflow int req */
62#define UCTRL_INTR_TXE_MSK         0x10    /* transmit FIFO empty mask */
63#define UCTRL_INTR_TXNF_MSK        0x20    /* transmit FIFO not full mask */
64#define UCTRL_INTR_RXNE_MSK        0x40    /* receive FIFO not empty mask */
65#define UCTRL_INTR_RXO_MSK         0x80    /* receive FIFO overflow mask */
66
67/* Bits for uctrl_stat register */
68#define UCTRL_STAT_TXE_STA         0x01    /* transmit FIFO empty status */
69#define UCTRL_STAT_TXNF_STA        0x02    /* transmit FIFO not full status */
70#define UCTRL_STAT_RXNE_STA        0x04    /* receive FIFO not empty status */
71#define UCTRL_STAT_RXO_STA         0x08    /* receive FIFO overflow status */
72
73static const char *uctrl_extstatus[16] = {
74        "main power available",
75        "internal battery attached",
76        "external battery attached",
77        "external VGA attached",
78        "external keyboard attached",
79        "external mouse attached",
80        "lid down",
81        "internal battery currently charging",
82        "external battery currently charging",
83        "internal battery currently discharging",
84        "external battery currently discharging",
85};
86
87/* Everything required for one transaction with the uctrl */
88struct uctrl_txn {
89	u8 opcode;
90	u8 inbits;
91	u8 outbits;
92	u8 *inbuf;
93	u8 *outbuf;
94};
95
96struct uctrl_status {
97	u8 current_temp; /* 0x07 */
98	u8 reset_status; /* 0x0b */
99	u16 event_status; /* 0x0c */
100	u16 error_status; /* 0x10 */
101	u16 external_status; /* 0x11, 0x1b */
102	u8 internal_charge; /* 0x18 */
103	u8 external_charge; /* 0x19 */
104	u16 control_lcd; /* 0x20 */
105	u8 control_bitport; /* 0x21 */
106	u8 speaker_volume; /* 0x23 */
107	u8 control_tft_brightness; /* 0x24 */
108	u8 control_kbd_repeat_delay; /* 0x28 */
109	u8 control_kbd_repeat_period; /* 0x29 */
110	u8 control_screen_contrast; /* 0x2F */
111};
112
113enum uctrl_opcode {
114  READ_SERIAL_NUMBER=0x1,
115  READ_ETHERNET_ADDRESS=0x2,
116  READ_HARDWARE_VERSION=0x3,
117  READ_MICROCONTROLLER_VERSION=0x4,
118  READ_MAX_TEMPERATURE=0x5,
119  READ_MIN_TEMPERATURE=0x6,
120  READ_CURRENT_TEMPERATURE=0x7,
121  READ_SYSTEM_VARIANT=0x8,
122  READ_POWERON_CYCLES=0x9,
123  READ_POWERON_SECONDS=0xA,
124  READ_RESET_STATUS=0xB,
125  READ_EVENT_STATUS=0xC,
126  READ_REAL_TIME_CLOCK=0xD,
127  READ_EXTERNAL_VGA_PORT=0xE,
128  READ_MICROCONTROLLER_ROM_CHECKSUM=0xF,
129  READ_ERROR_STATUS=0x10,
130  READ_EXTERNAL_STATUS=0x11,
131  READ_USER_CONFIGURATION_AREA=0x12,
132  READ_MICROCONTROLLER_VOLTAGE=0x13,
133  READ_INTERNAL_BATTERY_VOLTAGE=0x14,
134  READ_DCIN_VOLTAGE=0x15,
135  READ_HORIZONTAL_POINTER_VOLTAGE=0x16,
136  READ_VERTICAL_POINTER_VOLTAGE=0x17,
137  READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18,
138  READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19,
139  READ_REAL_TIME_CLOCK_ALARM=0x1A,
140  READ_EVENT_STATUS_NO_RESET=0x1B,
141  READ_INTERNAL_KEYBOARD_LAYOUT=0x1C,
142  READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D,
143  READ_EEPROM_STATUS=0x1E,
144  CONTROL_LCD=0x20,
145  CONTROL_BITPORT=0x21,
146  SPEAKER_VOLUME=0x23,
147  CONTROL_TFT_BRIGHTNESS=0x24,
148  CONTROL_WATCHDOG=0x25,
149  CONTROL_FACTORY_EEPROM_AREA=0x26,
150  CONTROL_KBD_TIME_UNTIL_REPEAT=0x28,
151  CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29,
152  CONTROL_TIMEZONE=0x2A,
153  CONTROL_MARK_SPACE_RATIO=0x2B,
154  CONTROL_DIAGNOSTIC_MODE=0x2E,
155  CONTROL_SCREEN_CONTRAST=0x2F,
156  RING_BELL=0x30,
157  SET_DIAGNOSTIC_STATUS=0x32,
158  CLEAR_KEY_COMBINATION_TABLE=0x33,
159  PERFORM_SOFTWARE_RESET=0x34,
160  SET_REAL_TIME_CLOCK=0x35,
161  RECALIBRATE_POINTING_STICK=0x36,
162  SET_BELL_FREQUENCY=0x37,
163  SET_INTERNAL_BATTERY_CHARGE_RATE=0x39,
164  SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A,
165  SET_REAL_TIME_CLOCK_ALARM=0x3B,
166  READ_EEPROM=0x40,
167  WRITE_EEPROM=0x41,
168  WRITE_TO_STATUS_DISPLAY=0x42,
169  DEFINE_SPECIAL_CHARACTER=0x43,
170  DEFINE_KEY_COMBINATION_ENTRY=0x50,
171  DEFINE_STRING_TABLE_ENTRY=0x51,
172  DEFINE_STATUS_SCREEN_DISPLAY=0x52,
173  PERFORM_EMU_COMMANDS=0x64,
174  READ_EMU_REGISTER=0x65,
175  WRITE_EMU_REGISTER=0x66,
176  READ_EMU_RAM=0x67,
177  WRITE_EMU_RAM=0x68,
178  READ_BQ_REGISTER=0x69,
179  WRITE_BQ_REGISTER=0x6A,
180  SET_USER_PASSWORD=0x70,
181  VERIFY_USER_PASSWORD=0x71,
182  GET_SYSTEM_PASSWORD_KEY=0x72,
183  VERIFY_SYSTEM_PASSWORD=0x73,
184  POWER_OFF=0x82,
185  POWER_RESTART=0x83,
186};
187
188struct uctrl_driver {
189	struct uctrl_regs *regs;
190	int irq;
191	int pending;
192	struct uctrl_status status;
193};
194
195static struct uctrl_driver drv;
196
197void uctrl_get_event_status(void);
198void uctrl_get_external_status(void);
199
200static int
201uctrl_ioctl(struct inode *inode, struct file *file,
202	      unsigned int cmd, unsigned long arg)
203{
204	switch (cmd) {
205		default:
206			return -EINVAL;
207	}
208	return 0;
209}
210
211static int
212uctrl_open(struct inode *inode, struct file *file)
213{
214	uctrl_get_event_status();
215	uctrl_get_external_status();
216	return 0;
217}
218
219static irqreturn_t uctrl_interrupt(int irq, void *dev_id)
220{
221	struct uctrl_driver *driver = (struct uctrl_driver *)dev_id;
222	printk("in uctrl_interrupt\n");
223	return IRQ_HANDLED;
224}
225
226static const struct file_operations uctrl_fops = {
227	.owner =	THIS_MODULE,
228	.llseek =	no_llseek,
229	.ioctl =	uctrl_ioctl,
230	.open =		uctrl_open,
231};
232
233static struct miscdevice uctrl_dev = {
234	UCTRL_MINOR,
235	"uctrl",
236	&uctrl_fops
237};
238
239/* Wait for space to write, then write to it */
240#define WRITEUCTLDATA(value) \
241{ \
242  unsigned int i; \
243  for (i = 0; i < 10000; i++) { \
244    if (UCTRL_STAT_TXNF_STA & driver->regs->uctrl_stat) \
245      break; \
246  } \
247  dprintk(("write data 0x%02x\n", value)); \
248  driver->regs->uctrl_data = value; \
249}
250
251/* Wait for something to read, read it, then clear the bit */
252#define READUCTLDATA(value) \
253{ \
254  unsigned int i; \
255  value = 0; \
256  for (i = 0; i < 10000; i++) { \
257    if ((UCTRL_STAT_RXNE_STA & driver->regs->uctrl_stat) == 0) \
258      break; \
259    udelay(1); \
260  } \
261  value = driver->regs->uctrl_data; \
262  dprintk(("read data 0x%02x\n", value)); \
263  driver->regs->uctrl_stat = UCTRL_STAT_RXNE_STA; \
264}
265
266void uctrl_set_video(int status)
267{
268	struct uctrl_driver *driver = &drv;
269
270}
271
272static void uctrl_do_txn(struct uctrl_txn *txn)
273{
274	struct uctrl_driver *driver = &drv;
275	int stat, incnt, outcnt, bytecnt, intr;
276	u32 byte;
277
278	stat = driver->regs->uctrl_stat;
279	intr = driver->regs->uctrl_intr;
280	driver->regs->uctrl_stat = stat;
281
282	dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr));
283
284	incnt = txn->inbits;
285	outcnt = txn->outbits;
286	byte = (txn->opcode << 8);
287	WRITEUCTLDATA(byte);
288
289	bytecnt = 0;
290	while (incnt > 0) {
291		byte = (txn->inbuf[bytecnt] << 8);
292		WRITEUCTLDATA(byte);
293		incnt--;
294		bytecnt++;
295	}
296
297	/* Get the ack */
298	READUCTLDATA(byte);
299	dprintk(("ack was %x\n", (byte >> 8)));
300
301	bytecnt = 0;
302	while (outcnt > 0) {
303		READUCTLDATA(byte);
304		txn->outbuf[bytecnt] = (byte >> 8);
305		dprintk(("set byte to %02x\n", byte));
306		outcnt--;
307		bytecnt++;
308	}
309}
310
311void uctrl_get_event_status(void)
312{
313	struct uctrl_driver *driver = &drv;
314	struct uctrl_txn txn;
315	u8 outbits[2];
316
317	txn.opcode = READ_EVENT_STATUS;
318	txn.inbits = 0;
319	txn.outbits = 2;
320	txn.inbuf = NULL;
321	txn.outbuf = outbits;
322
323	uctrl_do_txn(&txn);
324
325	dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
326	driver->status.event_status =
327		((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff);
328	dprintk(("ev is %x\n", driver->status.event_status));
329}
330
331void uctrl_get_external_status(void)
332{
333	struct uctrl_driver *driver = &drv;
334	struct uctrl_txn txn;
335	u8 outbits[2];
336	int i, v;
337
338	txn.opcode = READ_EXTERNAL_STATUS;
339	txn.inbits = 0;
340	txn.outbits = 2;
341	txn.inbuf = NULL;
342	txn.outbuf = outbits;
343
344	uctrl_do_txn(&txn);
345
346	dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
347	driver->status.external_status =
348		((outbits[0] * 256) + (outbits[1]));
349	dprintk(("ex is %x\n", driver->status.external_status));
350	v = driver->status.external_status;
351	for (i = 0; v != 0; i++, v >>= 1) {
352		if (v & 1) {
353			dprintk(("%s%s", " ", uctrl_extstatus[i]));
354		}
355	}
356	dprintk(("\n"));
357
358}
359
360static int __init ts102_uctrl_init(void)
361{
362	struct uctrl_driver *driver = &drv;
363	int len, i;
364	struct linux_prom_irqs tmp_irq[2];
365        unsigned int vaddr[2] = { 0, 0 };
366	int tmpnode, uctrlnode = prom_getchild(prom_root_node);
367	int err;
368
369	tmpnode = prom_searchsiblings(uctrlnode, "obio");
370
371	if (tmpnode)
372	  uctrlnode = prom_getchild(tmpnode);
373
374	uctrlnode = prom_searchsiblings(uctrlnode, "uctrl");
375
376	if (!uctrlnode)
377		return -ENODEV;
378
379	/* the prom mapped it for us */
380	len = prom_getproperty(uctrlnode, "address", (void *) vaddr,
381			       sizeof(vaddr));
382	driver->regs = (struct uctrl_regs *)vaddr[0];
383
384	len = prom_getproperty(uctrlnode, "intr", (char *) tmp_irq,
385			       sizeof(tmp_irq));
386
387	/* Flush device */
388	READUCTLDATA(len);
389
390	if(!driver->irq)
391		driver->irq = tmp_irq[0].pri;
392
393	err = request_irq(driver->irq, uctrl_interrupt, 0, "uctrl", driver);
394	if (err) {
395		printk("%s: unable to register irq %d\n",
396		       __FUNCTION__, driver->irq);
397		return err;
398	}
399
400	if (misc_register(&uctrl_dev)) {
401		printk("%s: unable to get misc minor %d\n",
402		       __FUNCTION__, uctrl_dev.minor);
403		free_irq(driver->irq, driver);
404		return -ENODEV;
405	}
406
407	driver->regs->uctrl_intr = UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK;
408	printk("uctrl: 0x%p (irq %d)\n", driver->regs, driver->irq);
409	uctrl_get_event_status();
410	uctrl_get_external_status();
411        return 0;
412}
413
414static void __exit ts102_uctrl_cleanup(void)
415{
416	struct uctrl_driver *driver = &drv;
417
418	misc_deregister(&uctrl_dev);
419	if (driver->irq)
420		free_irq(driver->irq, driver);
421	if (driver->regs)
422		driver->regs = NULL;
423}
424
425module_init(ts102_uctrl_init);
426module_exit(ts102_uctrl_cleanup);
427MODULE_LICENSE("GPL");
428