1/* 2 * IBM Hot Plug Controller Driver 3 * 4 * Written By: Jyoti Shah, IBM Corporation 5 * 6 * Copyright (C) 2001-2003 IBM Corp. 7 * 8 * All rights reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 18 * NON INFRINGEMENT. See the GNU General Public License for more 19 * details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * Send feedback to <gregkh@us.ibm.com> 26 * <jshah@us.ibm.com> 27 * 28 */ 29 30#include <linux/wait.h> 31#include <linux/time.h> 32#include <linux/delay.h> 33#include <linux/module.h> 34#include <linux/pci.h> 35#include <linux/init.h> 36#include <linux/mutex.h> 37#include <linux/sched.h> 38 39#include "ibmphp.h" 40 41static int to_debug = 0; 42#define debug_polling(fmt, arg...) do { if (to_debug) debug (fmt, arg); } while (0) 43 44//---------------------------------------------------------------------------- 45// timeout values 46//---------------------------------------------------------------------------- 47#define CMD_COMPLETE_TOUT_SEC 60 // give HPC 60 sec to finish cmd 48#define HPC_CTLR_WORKING_TOUT 60 // give HPC 60 sec to finish cmd 49#define HPC_GETACCESS_TIMEOUT 60 // seconds 50#define POLL_INTERVAL_SEC 2 // poll HPC every 2 seconds 51#define POLL_LATCH_CNT 5 // poll latch 5 times, then poll slots 52 53//---------------------------------------------------------------------------- 54// Winnipeg Architected Register Offsets 55//---------------------------------------------------------------------------- 56#define WPG_I2CMBUFL_OFFSET 0x08 // I2C Message Buffer Low 57#define WPG_I2CMOSUP_OFFSET 0x10 // I2C Master Operation Setup Reg 58#define WPG_I2CMCNTL_OFFSET 0x20 // I2C Master Control Register 59#define WPG_I2CPARM_OFFSET 0x40 // I2C Parameter Register 60#define WPG_I2CSTAT_OFFSET 0x70 // I2C Status Register 61 62//---------------------------------------------------------------------------- 63// Winnipeg Store Type commands (Add this commands to the register offset) 64//---------------------------------------------------------------------------- 65#define WPG_I2C_AND 0x1000 // I2C AND operation 66#define WPG_I2C_OR 0x2000 // I2C OR operation 67 68//---------------------------------------------------------------------------- 69// Command set for I2C Master Operation Setup Register 70//---------------------------------------------------------------------------- 71#define WPG_READATADDR_MASK 0x00010000 // read,bytes,I2C shifted,index 72#define WPG_WRITEATADDR_MASK 0x40010000 // write,bytes,I2C shifted,index 73#define WPG_READDIRECT_MASK 0x10010000 74#define WPG_WRITEDIRECT_MASK 0x60010000 75 76 77//---------------------------------------------------------------------------- 78// bit masks for I2C Master Control Register 79//---------------------------------------------------------------------------- 80#define WPG_I2CMCNTL_STARTOP_MASK 0x00000002 // Start the Operation 81 82//---------------------------------------------------------------------------- 83// 84//---------------------------------------------------------------------------- 85#define WPG_I2C_IOREMAP_SIZE 0x2044 // size of linear address interval 86 87//---------------------------------------------------------------------------- 88// command index 89//---------------------------------------------------------------------------- 90#define WPG_1ST_SLOT_INDEX 0x01 // index - 1st slot for ctlr 91#define WPG_CTLR_INDEX 0x0F // index - ctlr 92#define WPG_1ST_EXTSLOT_INDEX 0x10 // index - 1st ext slot for ctlr 93#define WPG_1ST_BUS_INDEX 0x1F // index - 1st bus for ctlr 94 95//---------------------------------------------------------------------------- 96// macro utilities 97//---------------------------------------------------------------------------- 98// if bits 20,22,25,26,27,29,30 are OFF return 1 99#define HPC_I2CSTATUS_CHECK(s) ((u8)((s & 0x00000A76) ? 0 : 1)) 100 101//---------------------------------------------------------------------------- 102// global variables 103//---------------------------------------------------------------------------- 104static int ibmphp_shutdown; 105static int tid_poll; 106static struct mutex sem_hpcaccess; // lock access to HPC 107static struct semaphore semOperations; // lock all operations and 108 // access to data structures 109static struct semaphore sem_exit; // make sure polling thread goes away 110//---------------------------------------------------------------------------- 111// local function prototypes 112//---------------------------------------------------------------------------- 113static u8 i2c_ctrl_read (struct controller *, void __iomem *, u8); 114static u8 i2c_ctrl_write (struct controller *, void __iomem *, u8, u8); 115static u8 hpc_writecmdtoindex (u8, u8); 116static u8 hpc_readcmdtoindex (u8, u8); 117static void get_hpc_access (void); 118static void free_hpc_access (void); 119static void poll_hpc (void); 120static int process_changeinstatus (struct slot *, struct slot *); 121static int process_changeinlatch (u8, u8, struct controller *); 122static int hpc_poll_thread (void *); 123static int hpc_wait_ctlr_notworking (int, struct controller *, void __iomem *, u8 *); 124//---------------------------------------------------------------------------- 125 126 127/*---------------------------------------------------------------------- 128* Name: ibmphp_hpc_initvars 129* 130* Action: initialize semaphores and variables 131*---------------------------------------------------------------------*/ 132void __init ibmphp_hpc_initvars (void) 133{ 134 debug ("%s - Entry\n", __FUNCTION__); 135 136 mutex_init(&sem_hpcaccess); 137 init_MUTEX (&semOperations); 138 init_MUTEX_LOCKED (&sem_exit); 139 to_debug = 0; 140 ibmphp_shutdown = 0; 141 tid_poll = 0; 142 143 debug ("%s - Exit\n", __FUNCTION__); 144} 145 146/*---------------------------------------------------------------------- 147* Name: i2c_ctrl_read 148* 149* Action: read from HPC over I2C 150* 151*---------------------------------------------------------------------*/ 152static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index) 153{ 154 u8 status; 155 int i; 156 void __iomem *wpg_addr; // base addr + offset 157 unsigned long wpg_data; // data to/from WPG LOHI format 158 unsigned long ultemp; 159 unsigned long data; // actual data HILO format 160 161 debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __FUNCTION__, WPGBbar, index); 162 163 //-------------------------------------------------------------------- 164 // READ - step 1 165 // read at address, byte length, I2C address (shifted), index 166 // or read direct, byte length, index 167 if (ctlr_ptr->ctlr_type == 0x02) { 168 data = WPG_READATADDR_MASK; 169 // fill in I2C address 170 ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr; 171 ultemp = ultemp >> 1; 172 data |= (ultemp << 8); 173 174 // fill in index 175 data |= (unsigned long)index; 176 } else if (ctlr_ptr->ctlr_type == 0x04) { 177 data = WPG_READDIRECT_MASK; 178 179 // fill in index 180 ultemp = (unsigned long)index; 181 ultemp = ultemp << 8; 182 data |= ultemp; 183 } else { 184 err ("this controller type is not supported \n"); 185 return HPC_ERROR; 186 } 187 188 wpg_data = swab32 (data); // swap data before writing 189 wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; 190 writel (wpg_data, wpg_addr); 191 192 //-------------------------------------------------------------------- 193 // READ - step 2 : clear the message buffer 194 data = 0x00000000; 195 wpg_data = swab32 (data); 196 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; 197 writel (wpg_data, wpg_addr); 198 199 //-------------------------------------------------------------------- 200 // READ - step 3 : issue start operation, I2C master control bit 30:ON 201 // 2020 : [20] OR operation at [20] offset 0x20 202 data = WPG_I2CMCNTL_STARTOP_MASK; 203 wpg_data = swab32 (data); 204 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; 205 writel (wpg_data, wpg_addr); 206 207 //-------------------------------------------------------------------- 208 // READ - step 4 : wait until start operation bit clears 209 i = CMD_COMPLETE_TOUT_SEC; 210 while (i) { 211 msleep(10); 212 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; 213 wpg_data = readl (wpg_addr); 214 data = swab32 (wpg_data); 215 if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) 216 break; 217 i--; 218 } 219 if (i == 0) { 220 debug ("%s - Error : WPG timeout\n", __FUNCTION__); 221 return HPC_ERROR; 222 } 223 //-------------------------------------------------------------------- 224 // READ - step 5 : read I2C status register 225 i = CMD_COMPLETE_TOUT_SEC; 226 while (i) { 227 msleep(10); 228 wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; 229 wpg_data = readl (wpg_addr); 230 data = swab32 (wpg_data); 231 if (HPC_I2CSTATUS_CHECK (data)) 232 break; 233 i--; 234 } 235 if (i == 0) { 236 debug ("ctrl_read - Exit Error:I2C timeout\n"); 237 return HPC_ERROR; 238 } 239 240 //-------------------------------------------------------------------- 241 // READ - step 6 : get DATA 242 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; 243 wpg_data = readl (wpg_addr); 244 data = swab32 (wpg_data); 245 246 status = (u8) data; 247 248 debug_polling ("%s - Exit index[%x] status[%x]\n", __FUNCTION__, index, status); 249 250 return (status); 251} 252 253/*---------------------------------------------------------------------- 254* Name: i2c_ctrl_write 255* 256* Action: write to HPC over I2C 257* 258* Return 0 or error codes 259*---------------------------------------------------------------------*/ 260static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index, u8 cmd) 261{ 262 u8 rc; 263 void __iomem *wpg_addr; // base addr + offset 264 unsigned long wpg_data; // data to/from WPG LOHI format 265 unsigned long ultemp; 266 unsigned long data; // actual data HILO format 267 int i; 268 269 debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __FUNCTION__, WPGBbar, index, cmd); 270 271 rc = 0; 272 //-------------------------------------------------------------------- 273 // WRITE - step 1 274 // write at address, byte length, I2C address (shifted), index 275 // or write direct, byte length, index 276 data = 0x00000000; 277 278 if (ctlr_ptr->ctlr_type == 0x02) { 279 data = WPG_WRITEATADDR_MASK; 280 // fill in I2C address 281 ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr; 282 ultemp = ultemp >> 1; 283 data |= (ultemp << 8); 284 285 // fill in index 286 data |= (unsigned long)index; 287 } else if (ctlr_ptr->ctlr_type == 0x04) { 288 data = WPG_WRITEDIRECT_MASK; 289 290 // fill in index 291 ultemp = (unsigned long)index; 292 ultemp = ultemp << 8; 293 data |= ultemp; 294 } else { 295 err ("this controller type is not supported \n"); 296 return HPC_ERROR; 297 } 298 299 wpg_data = swab32 (data); // swap data before writing 300 wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; 301 writel (wpg_data, wpg_addr); 302 303 //-------------------------------------------------------------------- 304 // WRITE - step 2 : clear the message buffer 305 data = 0x00000000 | (unsigned long)cmd; 306 wpg_data = swab32 (data); 307 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; 308 writel (wpg_data, wpg_addr); 309 310 //-------------------------------------------------------------------- 311 // WRITE - step 3 : issue start operation,I2C master control bit 30:ON 312 // 2020 : [20] OR operation at [20] offset 0x20 313 data = WPG_I2CMCNTL_STARTOP_MASK; 314 wpg_data = swab32 (data); 315 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; 316 writel (wpg_data, wpg_addr); 317 318 //-------------------------------------------------------------------- 319 // WRITE - step 4 : wait until start operation bit clears 320 i = CMD_COMPLETE_TOUT_SEC; 321 while (i) { 322 msleep(10); 323 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; 324 wpg_data = readl (wpg_addr); 325 data = swab32 (wpg_data); 326 if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) 327 break; 328 i--; 329 } 330 if (i == 0) { 331 debug ("%s - Exit Error:WPG timeout\n", __FUNCTION__); 332 rc = HPC_ERROR; 333 } 334 335 //-------------------------------------------------------------------- 336 // WRITE - step 5 : read I2C status register 337 i = CMD_COMPLETE_TOUT_SEC; 338 while (i) { 339 msleep(10); 340 wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; 341 wpg_data = readl (wpg_addr); 342 data = swab32 (wpg_data); 343 if (HPC_I2CSTATUS_CHECK (data)) 344 break; 345 i--; 346 } 347 if (i == 0) { 348 debug ("ctrl_read - Error : I2C timeout\n"); 349 rc = HPC_ERROR; 350 } 351 352 debug_polling ("%s Exit rc[%x]\n", __FUNCTION__, rc); 353 return (rc); 354} 355 356//------------------------------------------------------------ 357// Read from ISA type HPC 358//------------------------------------------------------------ 359static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset) 360{ 361 u16 start_address; 362 u16 end_address; 363 u8 data; 364 365 start_address = ctlr_ptr->u.isa_ctlr.io_start; 366 end_address = ctlr_ptr->u.isa_ctlr.io_end; 367 data = inb (start_address + offset); 368 return data; 369} 370 371//-------------------------------------------------------------- 372// Write to ISA type HPC 373//-------------------------------------------------------------- 374static void isa_ctrl_write (struct controller *ctlr_ptr, u8 offset, u8 data) 375{ 376 u16 start_address; 377 u16 port_address; 378 379 start_address = ctlr_ptr->u.isa_ctlr.io_start; 380 port_address = start_address + (u16) offset; 381 outb (data, port_address); 382} 383 384static u8 pci_ctrl_read (struct controller *ctrl, u8 offset) 385{ 386 u8 data = 0x00; 387 debug ("inside pci_ctrl_read\n"); 388 if (ctrl->ctrl_dev) 389 pci_read_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data); 390 return data; 391} 392 393static u8 pci_ctrl_write (struct controller *ctrl, u8 offset, u8 data) 394{ 395 u8 rc = -ENODEV; 396 debug ("inside pci_ctrl_write\n"); 397 if (ctrl->ctrl_dev) { 398 pci_write_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data); 399 rc = 0; 400 } 401 return rc; 402} 403 404static u8 ctrl_read (struct controller *ctlr, void __iomem *base, u8 offset) 405{ 406 u8 rc; 407 switch (ctlr->ctlr_type) { 408 case 0: 409 rc = isa_ctrl_read (ctlr, offset); 410 break; 411 case 1: 412 rc = pci_ctrl_read (ctlr, offset); 413 break; 414 case 2: 415 case 4: 416 rc = i2c_ctrl_read (ctlr, base, offset); 417 break; 418 default: 419 return -ENODEV; 420 } 421 return rc; 422} 423 424static u8 ctrl_write (struct controller *ctlr, void __iomem *base, u8 offset, u8 data) 425{ 426 u8 rc = 0; 427 switch (ctlr->ctlr_type) { 428 case 0: 429 isa_ctrl_write(ctlr, offset, data); 430 break; 431 case 1: 432 rc = pci_ctrl_write (ctlr, offset, data); 433 break; 434 case 2: 435 case 4: 436 rc = i2c_ctrl_write(ctlr, base, offset, data); 437 break; 438 default: 439 return -ENODEV; 440 } 441 return rc; 442} 443/*---------------------------------------------------------------------- 444* Name: hpc_writecmdtoindex() 445* 446* Action: convert a write command to proper index within a controller 447* 448* Return index, HPC_ERROR 449*---------------------------------------------------------------------*/ 450static u8 hpc_writecmdtoindex (u8 cmd, u8 index) 451{ 452 u8 rc; 453 454 switch (cmd) { 455 case HPC_CTLR_ENABLEIRQ: // 0x00.N.15 456 case HPC_CTLR_CLEARIRQ: // 0x06.N.15 457 case HPC_CTLR_RESET: // 0x07.N.15 458 case HPC_CTLR_IRQSTEER: // 0x08.N.15 459 case HPC_CTLR_DISABLEIRQ: // 0x01.N.15 460 case HPC_ALLSLOT_ON: // 0x11.N.15 461 case HPC_ALLSLOT_OFF: // 0x12.N.15 462 rc = 0x0F; 463 break; 464 465 case HPC_SLOT_OFF: // 0x02.Y.0-14 466 case HPC_SLOT_ON: // 0x03.Y.0-14 467 case HPC_SLOT_ATTNOFF: // 0x04.N.0-14 468 case HPC_SLOT_ATTNON: // 0x05.N.0-14 469 case HPC_SLOT_BLINKLED: // 0x13.N.0-14 470 rc = index; 471 break; 472 473 case HPC_BUS_33CONVMODE: 474 case HPC_BUS_66CONVMODE: 475 case HPC_BUS_66PCIXMODE: 476 case HPC_BUS_100PCIXMODE: 477 case HPC_BUS_133PCIXMODE: 478 rc = index + WPG_1ST_BUS_INDEX - 1; 479 break; 480 481 default: 482 err ("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd); 483 rc = HPC_ERROR; 484 } 485 486 return rc; 487} 488 489/*---------------------------------------------------------------------- 490* Name: hpc_readcmdtoindex() 491* 492* Action: convert a read command to proper index within a controller 493* 494* Return index, HPC_ERROR 495*---------------------------------------------------------------------*/ 496static u8 hpc_readcmdtoindex (u8 cmd, u8 index) 497{ 498 u8 rc; 499 500 switch (cmd) { 501 case READ_CTLRSTATUS: 502 rc = 0x0F; 503 break; 504 case READ_SLOTSTATUS: 505 case READ_ALLSTAT: 506 rc = index; 507 break; 508 case READ_EXTSLOTSTATUS: 509 rc = index + WPG_1ST_EXTSLOT_INDEX; 510 break; 511 case READ_BUSSTATUS: 512 rc = index + WPG_1ST_BUS_INDEX - 1; 513 break; 514 case READ_SLOTLATCHLOWREG: 515 rc = 0x28; 516 break; 517 case READ_REVLEVEL: 518 rc = 0x25; 519 break; 520 case READ_HPCOPTIONS: 521 rc = 0x27; 522 break; 523 default: 524 rc = HPC_ERROR; 525 } 526 return rc; 527} 528 529/*---------------------------------------------------------------------- 530* Name: HPCreadslot() 531* 532* Action: issue a READ command to HPC 533* 534* Input: pslot - cannot be NULL for READ_ALLSTAT 535* pstatus - can be NULL for READ_ALLSTAT 536* 537* Return 0 or error codes 538*---------------------------------------------------------------------*/ 539int ibmphp_hpc_readslot (struct slot * pslot, u8 cmd, u8 * pstatus) 540{ 541 void __iomem *wpg_bbar = NULL; 542 struct controller *ctlr_ptr; 543 struct list_head *pslotlist; 544 u8 index, status; 545 int rc = 0; 546 int busindex; 547 548 debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __FUNCTION__, pslot, cmd, pstatus); 549 550 if ((pslot == NULL) 551 || ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) { 552 rc = -EINVAL; 553 err ("%s - Error invalid pointer, rc[%d]\n", __FUNCTION__, rc); 554 return rc; 555 } 556 557 if (cmd == READ_BUSSTATUS) { 558 busindex = ibmphp_get_bus_index (pslot->bus); 559 if (busindex < 0) { 560 rc = -EINVAL; 561 err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__, rc); 562 return rc; 563 } else 564 index = (u8) busindex; 565 } else 566 index = pslot->ctlr_index; 567 568 index = hpc_readcmdtoindex (cmd, index); 569 570 if (index == HPC_ERROR) { 571 rc = -EINVAL; 572 err ("%s - Exit Error:invalid index, rc[%d]\n", __FUNCTION__, rc); 573 return rc; 574 } 575 576 ctlr_ptr = pslot->ctrl; 577 578 get_hpc_access (); 579 580 //-------------------------------------------------------------------- 581 // map physical address to logical address 582 //-------------------------------------------------------------------- 583 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) 584 wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE); 585 586 //-------------------------------------------------------------------- 587 // check controller status before reading 588 //-------------------------------------------------------------------- 589 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status); 590 if (!rc) { 591 switch (cmd) { 592 case READ_ALLSTAT: 593 // update the slot structure 594 pslot->ctrl->status = status; 595 pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index); 596 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, 597 &status); 598 if (!rc) 599 pslot->ext_status = ctrl_read (ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX); 600 601 break; 602 603 case READ_SLOTSTATUS: 604 // DO NOT update the slot structure 605 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 606 break; 607 608 case READ_EXTSLOTSTATUS: 609 // DO NOT update the slot structure 610 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 611 break; 612 613 case READ_CTLRSTATUS: 614 // DO NOT update the slot structure 615 *pstatus = status; 616 break; 617 618 case READ_BUSSTATUS: 619 pslot->busstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 620 break; 621 case READ_REVLEVEL: 622 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 623 break; 624 case READ_HPCOPTIONS: 625 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 626 break; 627 case READ_SLOTLATCHLOWREG: 628 // DO NOT update the slot structure 629 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 630 break; 631 632 // Not used 633 case READ_ALLSLOT: 634 list_for_each (pslotlist, &ibmphp_slot_head) { 635 pslot = list_entry (pslotlist, struct slot, ibm_slot_list); 636 index = pslot->ctlr_index; 637 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, 638 wpg_bbar, &status); 639 if (!rc) { 640 pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index); 641 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, 642 ctlr_ptr, wpg_bbar, &status); 643 if (!rc) 644 pslot->ext_status = 645 ctrl_read (ctlr_ptr, wpg_bbar, 646 index + WPG_1ST_EXTSLOT_INDEX); 647 } else { 648 err ("%s - Error ctrl_read failed\n", __FUNCTION__); 649 rc = -EINVAL; 650 break; 651 } 652 } 653 break; 654 default: 655 rc = -EINVAL; 656 break; 657 } 658 } 659 //-------------------------------------------------------------------- 660 // cleanup 661 //-------------------------------------------------------------------- 662 663 // remove physical to logical address mapping 664 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) 665 iounmap (wpg_bbar); 666 667 free_hpc_access (); 668 669 debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__, rc); 670 return rc; 671} 672 673/*---------------------------------------------------------------------- 674* Name: ibmphp_hpc_writeslot() 675* 676* Action: issue a WRITE command to HPC 677*---------------------------------------------------------------------*/ 678int ibmphp_hpc_writeslot (struct slot * pslot, u8 cmd) 679{ 680 void __iomem *wpg_bbar = NULL; 681 struct controller *ctlr_ptr; 682 u8 index, status; 683 int busindex; 684 u8 done; 685 int rc = 0; 686 int timeout; 687 688 debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __FUNCTION__, pslot, cmd); 689 if (pslot == NULL) { 690 rc = -EINVAL; 691 err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc); 692 return rc; 693 } 694 695 if ((cmd == HPC_BUS_33CONVMODE) || (cmd == HPC_BUS_66CONVMODE) || 696 (cmd == HPC_BUS_66PCIXMODE) || (cmd == HPC_BUS_100PCIXMODE) || 697 (cmd == HPC_BUS_133PCIXMODE)) { 698 busindex = ibmphp_get_bus_index (pslot->bus); 699 if (busindex < 0) { 700 rc = -EINVAL; 701 err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__, rc); 702 return rc; 703 } else 704 index = (u8) busindex; 705 } else 706 index = pslot->ctlr_index; 707 708 index = hpc_writecmdtoindex (cmd, index); 709 710 if (index == HPC_ERROR) { 711 rc = -EINVAL; 712 err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc); 713 return rc; 714 } 715 716 ctlr_ptr = pslot->ctrl; 717 718 get_hpc_access (); 719 720 //-------------------------------------------------------------------- 721 // map physical address to logical address 722 //-------------------------------------------------------------------- 723 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) { 724 wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE); 725 726 debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __FUNCTION__, 727 ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar, 728 ctlr_ptr->u.wpeg_ctlr.i2c_addr); 729 } 730 //-------------------------------------------------------------------- 731 // check controller status before writing 732 //-------------------------------------------------------------------- 733 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status); 734 if (!rc) { 735 736 ctrl_write (ctlr_ptr, wpg_bbar, index, cmd); 737 738 //-------------------------------------------------------------------- 739 // check controller is still not working on the command 740 //-------------------------------------------------------------------- 741 timeout = CMD_COMPLETE_TOUT_SEC; 742 done = 0; 743 while (!done) { 744 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, 745 &status); 746 if (!rc) { 747 if (NEEDTOCHECK_CMDSTATUS (cmd)) { 748 if (CTLR_FINISHED (status) == HPC_CTLR_FINISHED_YES) 749 done = 1; 750 } else 751 done = 1; 752 } 753 if (!done) { 754 msleep(1000); 755 if (timeout < 1) { 756 done = 1; 757 err ("%s - Error command complete timeout\n", __FUNCTION__); 758 rc = -EFAULT; 759 } else 760 timeout--; 761 } 762 } 763 ctlr_ptr->status = status; 764 } 765 // cleanup 766 767 // remove physical to logical address mapping 768 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) 769 iounmap (wpg_bbar); 770 free_hpc_access (); 771 772 debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__, rc); 773 return rc; 774} 775 776/*---------------------------------------------------------------------- 777* Name: get_hpc_access() 778* 779* Action: make sure only one process can access HPC at one time 780*---------------------------------------------------------------------*/ 781static void get_hpc_access (void) 782{ 783 mutex_lock(&sem_hpcaccess); 784} 785 786/*---------------------------------------------------------------------- 787* Name: free_hpc_access() 788*---------------------------------------------------------------------*/ 789void free_hpc_access (void) 790{ 791 mutex_unlock(&sem_hpcaccess); 792} 793 794/*---------------------------------------------------------------------- 795* Name: ibmphp_lock_operations() 796* 797* Action: make sure only one process can change the data structure 798*---------------------------------------------------------------------*/ 799void ibmphp_lock_operations (void) 800{ 801 down (&semOperations); 802 to_debug = 1; 803} 804 805/*---------------------------------------------------------------------- 806* Name: ibmphp_unlock_operations() 807*---------------------------------------------------------------------*/ 808void ibmphp_unlock_operations (void) 809{ 810 debug ("%s - Entry\n", __FUNCTION__); 811 up (&semOperations); 812 to_debug = 0; 813 debug ("%s - Exit\n", __FUNCTION__); 814} 815 816/*---------------------------------------------------------------------- 817* Name: poll_hpc() 818*---------------------------------------------------------------------*/ 819#define POLL_LATCH_REGISTER 0 820#define POLL_SLOTS 1 821#define POLL_SLEEP 2 822static void poll_hpc (void) 823{ 824 struct slot myslot; 825 struct slot *pslot = NULL; 826 struct list_head *pslotlist; 827 int rc; 828 int poll_state = POLL_LATCH_REGISTER; 829 u8 oldlatchlow = 0x00; 830 u8 curlatchlow = 0x00; 831 int poll_count = 0; 832 u8 ctrl_count = 0x00; 833 834 debug ("%s - Entry\n", __FUNCTION__); 835 836 while (!ibmphp_shutdown) { 837 if (ibmphp_shutdown) 838 break; 839 840 /* try to get the lock to do some kind of hardware access */ 841 down (&semOperations); 842 843 switch (poll_state) { 844 case POLL_LATCH_REGISTER: 845 oldlatchlow = curlatchlow; 846 ctrl_count = 0x00; 847 list_for_each (pslotlist, &ibmphp_slot_head) { 848 if (ctrl_count >= ibmphp_get_total_controllers()) 849 break; 850 pslot = list_entry (pslotlist, struct slot, ibm_slot_list); 851 if (pslot->ctrl->ctlr_relative_id == ctrl_count) { 852 ctrl_count++; 853 if (READ_SLOT_LATCH (pslot->ctrl)) { 854 rc = ibmphp_hpc_readslot (pslot, 855 READ_SLOTLATCHLOWREG, 856 &curlatchlow); 857 if (oldlatchlow != curlatchlow) 858 process_changeinlatch (oldlatchlow, 859 curlatchlow, 860 pslot->ctrl); 861 } 862 } 863 } 864 ++poll_count; 865 poll_state = POLL_SLEEP; 866 break; 867 case POLL_SLOTS: 868 list_for_each (pslotlist, &ibmphp_slot_head) { 869 pslot = list_entry (pslotlist, struct slot, ibm_slot_list); 870 // make a copy of the old status 871 memcpy ((void *) &myslot, (void *) pslot, 872 sizeof (struct slot)); 873 rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL); 874 if ((myslot.status != pslot->status) 875 || (myslot.ext_status != pslot->ext_status)) 876 process_changeinstatus (pslot, &myslot); 877 } 878 ctrl_count = 0x00; 879 list_for_each (pslotlist, &ibmphp_slot_head) { 880 if (ctrl_count >= ibmphp_get_total_controllers()) 881 break; 882 pslot = list_entry (pslotlist, struct slot, ibm_slot_list); 883 if (pslot->ctrl->ctlr_relative_id == ctrl_count) { 884 ctrl_count++; 885 if (READ_SLOT_LATCH (pslot->ctrl)) 886 rc = ibmphp_hpc_readslot (pslot, 887 READ_SLOTLATCHLOWREG, 888 &curlatchlow); 889 } 890 } 891 ++poll_count; 892 poll_state = POLL_SLEEP; 893 break; 894 case POLL_SLEEP: 895 /* don't sleep with a lock on the hardware */ 896 up (&semOperations); 897 msleep(POLL_INTERVAL_SEC * 1000); 898 899 if (ibmphp_shutdown) 900 break; 901 902 down (&semOperations); 903 904 if (poll_count >= POLL_LATCH_CNT) { 905 poll_count = 0; 906 poll_state = POLL_SLOTS; 907 } else 908 poll_state = POLL_LATCH_REGISTER; 909 break; 910 } 911 /* give up the hardware semaphore */ 912 up (&semOperations); 913 /* sleep for a short time just for good measure */ 914 msleep(100); 915 } 916 up (&sem_exit); 917 debug ("%s - Exit\n", __FUNCTION__); 918} 919 920 921/*---------------------------------------------------------------------- 922* Name: process_changeinstatus 923* 924* Action: compare old and new slot status, process the change in status 925* 926* Input: pointer to slot struct, old slot struct 927* 928* Return 0 or error codes 929* Value: 930* 931* Side 932* Effects: None. 933* 934* Notes: 935*---------------------------------------------------------------------*/ 936static int process_changeinstatus (struct slot *pslot, struct slot *poldslot) 937{ 938 u8 status; 939 int rc = 0; 940 u8 disable = 0; 941 u8 update = 0; 942 943 debug ("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot); 944 945 // bit 0 - HPC_SLOT_POWER 946 if ((pslot->status & 0x01) != (poldslot->status & 0x01)) 947 update = 1; 948 949 // bit 1 - HPC_SLOT_CONNECT 950 // ignore 951 952 // bit 2 - HPC_SLOT_ATTN 953 if ((pslot->status & 0x04) != (poldslot->status & 0x04)) 954 update = 1; 955 956 // bit 3 - HPC_SLOT_PRSNT2 957 // bit 4 - HPC_SLOT_PRSNT1 958 if (((pslot->status & 0x08) != (poldslot->status & 0x08)) 959 || ((pslot->status & 0x10) != (poldslot->status & 0x10))) 960 update = 1; 961 962 // bit 5 - HPC_SLOT_PWRGD 963 if ((pslot->status & 0x20) != (poldslot->status & 0x20)) 964 // OFF -> ON: ignore, ON -> OFF: disable slot 965 if ((poldslot->status & 0x20) && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) 966 disable = 1; 967 968 // bit 6 - HPC_SLOT_BUS_SPEED 969 // ignore 970 971 // bit 7 - HPC_SLOT_LATCH 972 if ((pslot->status & 0x80) != (poldslot->status & 0x80)) { 973 update = 1; 974 // OPEN -> CLOSE 975 if (pslot->status & 0x80) { 976 if (SLOT_PWRGD (pslot->status)) { 977 // power goes on and off after closing latch 978 // check again to make sure power is still ON 979 msleep(1000); 980 rc = ibmphp_hpc_readslot (pslot, READ_SLOTSTATUS, &status); 981 if (SLOT_PWRGD (status)) 982 update = 1; 983 else // overwrite power in pslot to OFF 984 pslot->status &= ~HPC_SLOT_POWER; 985 } 986 } 987 // CLOSE -> OPEN 988 else if ((SLOT_PWRGD (poldslot->status) == HPC_SLOT_PWRGD_GOOD) 989 && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) { 990 disable = 1; 991 } 992 // else - ignore 993 } 994 // bit 4 - HPC_SLOT_BLINK_ATTN 995 if ((pslot->ext_status & 0x08) != (poldslot->ext_status & 0x08)) 996 update = 1; 997 998 if (disable) { 999 debug ("process_changeinstatus - disable slot\n"); 1000 pslot->flag = 0; 1001 rc = ibmphp_do_disable_slot (pslot); 1002 } 1003 1004 if (update || disable) { 1005 ibmphp_update_slot_info (pslot); 1006 } 1007 1008 debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __FUNCTION__, rc, disable, update); 1009 1010 return rc; 1011} 1012 1013/*---------------------------------------------------------------------- 1014* Name: process_changeinlatch 1015* 1016* Action: compare old and new latch reg status, process the change 1017* 1018* Input: old and current latch register status 1019* 1020* Return 0 or error codes 1021* Value: 1022*---------------------------------------------------------------------*/ 1023static int process_changeinlatch (u8 old, u8 new, struct controller *ctrl) 1024{ 1025 struct slot myslot, *pslot; 1026 u8 i; 1027 u8 mask; 1028 int rc = 0; 1029 1030 debug ("%s - Entry old[%x], new[%x]\n", __FUNCTION__, old, new); 1031 // bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots 1032 1033 for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) { 1034 mask = 0x01 << i; 1035 if ((mask & old) != (mask & new)) { 1036 pslot = ibmphp_get_slot_from_physical_num (i); 1037 if (pslot) { 1038 memcpy ((void *) &myslot, (void *) pslot, sizeof (struct slot)); 1039 rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL); 1040 debug ("%s - call process_changeinstatus for slot[%d]\n", __FUNCTION__, i); 1041 process_changeinstatus (pslot, &myslot); 1042 } else { 1043 rc = -EINVAL; 1044 err ("%s - Error bad pointer for slot[%d]\n", __FUNCTION__, i); 1045 } 1046 } 1047 } 1048 debug ("%s - Exit rc[%d]\n", __FUNCTION__, rc); 1049 return rc; 1050} 1051 1052/*---------------------------------------------------------------------- 1053* Name: hpc_poll_thread 1054* 1055* Action: polling 1056* 1057* Return 0 1058* Value: 1059*---------------------------------------------------------------------*/ 1060static int hpc_poll_thread (void *data) 1061{ 1062 debug ("%s - Entry\n", __FUNCTION__); 1063 1064 daemonize("hpc_poll"); 1065 allow_signal(SIGKILL); 1066 1067 poll_hpc (); 1068 1069 tid_poll = 0; 1070 debug ("%s - Exit\n", __FUNCTION__); 1071 return 0; 1072} 1073 1074 1075/*---------------------------------------------------------------------- 1076* Name: ibmphp_hpc_start_poll_thread 1077* 1078* Action: start polling thread 1079*---------------------------------------------------------------------*/ 1080int __init ibmphp_hpc_start_poll_thread (void) 1081{ 1082 int rc = 0; 1083 1084 debug ("%s - Entry\n", __FUNCTION__); 1085 1086 tid_poll = kernel_thread (hpc_poll_thread, NULL, 0); 1087 if (tid_poll < 0) { 1088 err ("%s - Error, thread not started\n", __FUNCTION__); 1089 rc = -1; 1090 } 1091 1092 debug ("%s - Exit tid_poll[%d] rc[%d]\n", __FUNCTION__, tid_poll, rc); 1093 return rc; 1094} 1095 1096/*---------------------------------------------------------------------- 1097* Name: ibmphp_hpc_stop_poll_thread 1098* 1099* Action: stop polling thread and cleanup 1100*---------------------------------------------------------------------*/ 1101void __exit ibmphp_hpc_stop_poll_thread (void) 1102{ 1103 debug ("%s - Entry\n", __FUNCTION__); 1104 1105 ibmphp_shutdown = 1; 1106 debug ("before locking operations \n"); 1107 ibmphp_lock_operations (); 1108 debug ("after locking operations \n"); 1109 1110 // wait for poll thread to exit 1111 debug ("before sem_exit down \n"); 1112 down (&sem_exit); 1113 debug ("after sem_exit down \n"); 1114 1115 // cleanup 1116 debug ("before free_hpc_access \n"); 1117 free_hpc_access (); 1118 debug ("after free_hpc_access \n"); 1119 ibmphp_unlock_operations (); 1120 debug ("after unlock operations \n"); 1121 up (&sem_exit); 1122 debug ("after sem exit up\n"); 1123 1124 debug ("%s - Exit\n", __FUNCTION__); 1125} 1126 1127/*---------------------------------------------------------------------- 1128* Name: hpc_wait_ctlr_notworking 1129* 1130* Action: wait until the controller is in a not working state 1131* 1132* Return 0, HPC_ERROR 1133* Value: 1134*---------------------------------------------------------------------*/ 1135static int hpc_wait_ctlr_notworking (int timeout, struct controller *ctlr_ptr, void __iomem *wpg_bbar, 1136 u8 * pstatus) 1137{ 1138 int rc = 0; 1139 u8 done = 0; 1140 1141 debug_polling ("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout); 1142 1143 while (!done) { 1144 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX); 1145 if (*pstatus == HPC_ERROR) { 1146 rc = HPC_ERROR; 1147 done = 1; 1148 } 1149 if (CTLR_WORKING (*pstatus) == HPC_CTLR_WORKING_NO) 1150 done = 1; 1151 if (!done) { 1152 msleep(1000); 1153 if (timeout < 1) { 1154 done = 1; 1155 err ("HPCreadslot - Error ctlr timeout\n"); 1156 rc = HPC_ERROR; 1157 } else 1158 timeout--; 1159 } 1160 } 1161 debug_polling ("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus); 1162 return rc; 1163} 1164