1/* 2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * 6 * Description: 7 * Internal header file for UCC Gigabit Ethernet unit routines. 8 * 9 * Changelog: 10 * Jun 28, 2006 Li Yang <LeoLi@freescale.com> 11 * - Rearrange code and style fixes 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18#ifndef __UCC_GETH_H__ 19#define __UCC_GETH_H__ 20 21#include <linux/kernel.h> 22#include <linux/list.h> 23#include <linux/fsl_devices.h> 24 25#include <asm/immap_qe.h> 26#include <asm/qe.h> 27 28#include <asm/ucc.h> 29#include <asm/ucc_fast.h> 30 31#include "ucc_geth_mii.h" 32 33#define NUM_TX_QUEUES 8 34#define NUM_RX_QUEUES 8 35#define NUM_BDS_IN_PREFETCHED_BDS 4 36#define TX_IP_OFFSET_ENTRY_MAX 8 37#define NUM_OF_PADDRS 4 38#define ENET_INIT_PARAM_MAX_ENTRIES_RX 9 39#define ENET_INIT_PARAM_MAX_ENTRIES_TX 8 40 41struct ucc_geth { 42 struct ucc_fast uccf; 43 44 u32 maccfg1; /* mac configuration reg. 1 */ 45 u32 maccfg2; /* mac configuration reg. 2 */ 46 u32 ipgifg; /* interframe gap reg. */ 47 u32 hafdup; /* half-duplex reg. */ 48 u8 res1[0x10]; 49 u8 miimng[0x18]; /* MII management structure moved to _mii.h */ 50 u32 ifctl; /* interface control reg */ 51 u32 ifstat; /* interface statux reg */ 52 u32 macstnaddr1; /* mac station address part 1 reg */ 53 u32 macstnaddr2; /* mac station address part 2 reg */ 54 u8 res2[0x8]; 55 u32 uempr; /* UCC Ethernet Mac parameter reg */ 56 u32 utbipar; /* UCC tbi address reg */ 57 u16 uescr; /* UCC Ethernet statistics control reg */ 58 u8 res3[0x180 - 0x15A]; 59 u32 tx64; /* Total number of frames (including bad 60 frames) transmitted that were exactly of the 61 minimal length (64 for un tagged, 68 for 62 tagged, or with length exactly equal to the 63 parameter MINLength */ 64 u32 tx127; /* Total number of frames (including bad 65 frames) transmitted that were between 66 MINLength (Including FCS length==4) and 127 67 octets */ 68 u32 tx255; /* Total number of frames (including bad 69 frames) transmitted that were between 128 70 (Including FCS length==4) and 255 octets */ 71 u32 rx64; /* Total number of frames received including 72 bad frames that were exactly of the mninimal 73 length (64 bytes) */ 74 u32 rx127; /* Total number of frames (including bad 75 frames) received that were between MINLength 76 (Including FCS length==4) and 127 octets */ 77 u32 rx255; /* Total number of frames (including bad 78 frames) received that were between 128 79 (Including FCS length==4) and 255 octets */ 80 u32 txok; /* Total number of octets residing in frames 81 that where involved in succesfull 82 transmission */ 83 u16 txcf; /* Total number of PAUSE control frames 84 transmitted by this MAC */ 85 u8 res4[0x2]; 86 u32 tmca; /* Total number of frames that were transmitted 87 succesfully with the group address bit set 88 that are not broadcast frames */ 89 u32 tbca; /* Total number of frames transmitted 90 succesfully that had destination address 91 field equal to the broadcast address */ 92 u32 rxfok; /* Total number of frames received OK */ 93 u32 rxbok; /* Total number of octets received OK */ 94 u32 rbyt; /* Total number of octets received including 95 octets in bad frames. Must be implemented in 96 HW because it includes octets in frames that 97 never even reach the UCC */ 98 u32 rmca; /* Total number of frames that were received 99 succesfully with the group address bit set 100 that are not broadcast frames */ 101 u32 rbca; /* Total number of frames received succesfully 102 that had destination address equal to the 103 broadcast address */ 104 u32 scar; /* Statistics carry register */ 105 u32 scam; /* Statistics caryy mask register */ 106 u8 res5[0x200 - 0x1c4]; 107} __attribute__ ((packed)); 108 109/* UCC GETH TEMODR Register */ 110#define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics 111 */ 112#define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */ 113#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4 114 checksums */ 115#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance 116 optimization 117 enhancement (mode1) */ 118#define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics 119 */ 120#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues << 121 shift */ 122 123/* UCC GETH TEMODR Register */ 124#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx 125 statistics */ 126#define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable 127 extended 128 features */ 129#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation 130 tagged << shift */ 131#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non 132 tagged << shift */ 133#define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift 134 */ 135#define REMODER_RMON_STATISTICS 0x00001000 /* enable rx 136 statistics */ 137#define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended 138 filtering 139 vs. 140 mpc82xx-like 141 filtering */ 142#define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues << 143 shift */ 144#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable 145 dynamic max 146 frame length 147 */ 148#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable 149 dynamic min 150 frame length 151 */ 152#define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4 153 checksums */ 154#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip 155 address to 156 4-byte 157 boundary */ 158 159/* UCC GETH Event Register */ 160#define UCCE_MPD 0x80000000 /* Magic packet 161 detection */ 162#define UCCE_SCAR 0x40000000 163#define UCCE_GRA 0x20000000 /* Tx graceful 164 stop 165 complete */ 166#define UCCE_CBPR 0x10000000 167#define UCCE_BSY 0x08000000 168#define UCCE_RXC 0x04000000 169#define UCCE_TXC 0x02000000 170#define UCCE_TXE 0x01000000 171#define UCCE_TXB7 0x00800000 172#define UCCE_TXB6 0x00400000 173#define UCCE_TXB5 0x00200000 174#define UCCE_TXB4 0x00100000 175#define UCCE_TXB3 0x00080000 176#define UCCE_TXB2 0x00040000 177#define UCCE_TXB1 0x00020000 178#define UCCE_TXB0 0x00010000 179#define UCCE_RXB7 0x00008000 180#define UCCE_RXB6 0x00004000 181#define UCCE_RXB5 0x00002000 182#define UCCE_RXB4 0x00001000 183#define UCCE_RXB3 0x00000800 184#define UCCE_RXB2 0x00000400 185#define UCCE_RXB1 0x00000200 186#define UCCE_RXB0 0x00000100 187#define UCCE_RXF7 0x00000080 188#define UCCE_RXF6 0x00000040 189#define UCCE_RXF5 0x00000020 190#define UCCE_RXF4 0x00000010 191#define UCCE_RXF3 0x00000008 192#define UCCE_RXF2 0x00000004 193#define UCCE_RXF1 0x00000002 194#define UCCE_RXF0 0x00000001 195 196#define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0) 197#define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0) 198 199#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\ 200 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) 201#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\ 202 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) 203#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\ 204 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) 205#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\ 206 UCCE_RXC | UCCE_TXC | UCCE_TXE) 207 208#define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY) 209#define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE) 210 211/* UCC GETH UPSMR (Protocol Specific Mode Register) */ 212#define UPSMR_ECM 0x04000000 /* Enable CAM 213 Miss or 214 Enable 215 Filtering 216 Miss */ 217#define UPSMR_HSE 0x02000000 /* Hardware 218 Statistics 219 Enable */ 220#define UPSMR_PRO 0x00400000 /* Promiscuous*/ 221#define UPSMR_CAP 0x00200000 /* CAM polarity 222 */ 223#define UPSMR_RSH 0x00100000 /* Receive 224 Short Frames 225 */ 226#define UPSMR_RPM 0x00080000 /* Reduced Pin 227 Mode 228 interfaces */ 229#define UPSMR_R10M 0x00040000 /* RGMII/RMII 230 10 Mode */ 231#define UPSMR_RLPB 0x00020000 /* RMII 232 Loopback 233 Mode */ 234#define UPSMR_TBIM 0x00010000 /* Ten-bit 235 Interface 236 Mode */ 237#define UPSMR_RMM 0x00001000 /* RMII/RGMII 238 Mode */ 239#define UPSMR_CAM 0x00000400 /* CAM Address 240 Matching */ 241#define UPSMR_BRO 0x00000200 /* Broadcast 242 Address */ 243#define UPSMR_RES1 0x00002000 /* Reserved 244 feild - must 245 be 1 */ 246 247/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ 248#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control 249 Rx */ 250#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control 251 Tx */ 252#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable 253 synchronized 254 to Rx stream 255 */ 256#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ 257#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable 258 synchronized 259 to Tx stream 260 */ 261#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ 262 263/* UCC GETH MACCFG2 (MAC Configuration 2 Register) */ 264#define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble 265 Length << 266 shift */ 267#define MACCFG2_PREL_MASK 0x0000f000 /* Preamble 268 Length mask */ 269#define MACCFG2_SRP 0x00000080 /* Soft Receive 270 Preamble */ 271#define MACCFG2_STP 0x00000040 /* Soft 272 Transmit 273 Preamble */ 274#define MACCFG2_RESERVED_1 0x00000020 /* Reserved - 275 must be set 276 to 1 */ 277#define MACCFG2_LC 0x00000010 /* Length Check 278 */ 279#define MACCFG2_MPE 0x00000008 /* Magic packet 280 detect */ 281#define MACCFG2_FDX 0x00000001 /* Full Duplex */ 282#define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex 283 mask */ 284#define MACCFG2_PAD_CRC 0x00000004 285#define MACCFG2_CRC_EN 0x00000002 286#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither 287 Padding 288 short frames 289 nor CRC */ 290#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC 291 only */ 292#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 293#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode 294 (MII/RMII/RGMII 295 10/100bps) */ 296#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode 297 (GMII/TBI/RTB/RGMII 298 1000bps ) */ 299#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask 300 covering all 301 relevant 302 bits */ 303 304/* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */ 305#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non 306 back-to-back 307 inter frame 308 gap part 1. 309 << shift */ 310#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non 311 back-to-back 312 inter frame 313 gap part 2. 314 << shift */ 315#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG 316 Enforcement 317 << shift */ 318#define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back 319 inter frame 320 gap << shift 321 */ 322#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back 323 inter frame gap part 324 1. max val */ 325#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back 326 inter frame gap part 327 2. max val */ 328#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG 329 Enforcement max val */ 330#define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter 331 frame gap max val */ 332#define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000 333#define IPGIFG_NBTB_IPG_MASK 0x007F0000 334#define IPGIFG_MIN_IFG_MASK 0x0000FF00 335#define IPGIFG_BTB_IPG_MASK 0x0000007F 336 337/* UCC GETH HAFDUP (Half Duplex Register) */ 338#define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate 339 Binary 340 Exponential 341 Backoff 342 Truncation 343 << shift */ 344#define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary 345 Exponential Backoff 346 Truncation max val */ 347#define HALFDUP_ALT_BEB 0x00080000 /* Alternate 348 Binary 349 Exponential 350 Backoff */ 351#define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back 352 pressure no 353 backoff */ 354#define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */ 355#define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive 356 Defer */ 357#define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum 358 Retransmission 359 << shift */ 360#define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum 361 Retransmission max 362 val */ 363#define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision 364 Window << 365 shift */ 366#define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max 367 val */ 368#define HALFDUP_ALT_BEB_TR_MASK 0x00F00000 369#define HALFDUP_RETRANS_MASK 0x0000F000 370#define HALFDUP_COL_WINDOW_MASK 0x0000003F 371 372/* UCC GETH UCCS (Ethernet Status Register) */ 373#define UCCS_BPR 0x02 /* Back pressure (in 374 half duplex mode) */ 375#define UCCS_PAU 0x02 /* Pause state (in full 376 duplex mode) */ 377#define UCCS_MPD 0x01 /* Magic Packet 378 Detected */ 379 380/* UCC GETH IFSTAT (Interface Status Register) */ 381#define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive 382 transmission 383 defer */ 384 385/* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */ 386#define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station 387 address 6th 388 octet << 389 shift */ 390#define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station 391 address 5th 392 octet << 393 shift */ 394#define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station 395 address 4th 396 octet << 397 shift */ 398#define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station 399 address 3rd 400 octet << 401 shift */ 402 403/* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */ 404#define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station 405 address 2nd 406 octet << 407 shift */ 408#define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station 409 address 1st 410 octet << 411 shift */ 412 413/* UCC GETH UEMPR (Ethernet Mac Parameter Register) */ 414#define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time 415 value << 416 shift */ 417#define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended 418 pause time 419 value << 420 shift */ 421 422/* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */ 423#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address 424 << shift */ 425#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address 426 mask */ 427 428/* UCC GETH UESCR (Ethernet Statistics Control Register) */ 429#define UESCR_AUTOZ 0x8000 /* Automatically zero 430 addressed 431 statistical counter 432 values */ 433#define UESCR_CLRCNT 0x4000 /* Clear all statistics 434 counters */ 435#define UESCR_MAXCOV_SHIFT (15 - 7) /* Max 436 Coalescing 437 Value << 438 shift */ 439#define UESCR_SCOV_SHIFT (15 - 15) /* Status 440 Coalescing 441 Value << 442 shift */ 443 444/* UCC GETH UDSR (Data Synchronization Register) */ 445#define UDSR_MAGIC 0x067E 446 447struct ucc_geth_thread_data_tx { 448 u8 res0[104]; 449} __attribute__ ((packed)); 450 451struct ucc_geth_thread_data_rx { 452 u8 res0[40]; 453} __attribute__ ((packed)); 454 455/* Send Queue Queue-Descriptor */ 456struct ucc_geth_send_queue_qd { 457 u32 bd_ring_base; /* pointer to BD ring base address */ 458 u8 res0[0x8]; 459 u32 last_bd_completed_address;/* initialize to last entry in BD ring */ 460 u8 res1[0x30]; 461} __attribute__ ((packed)); 462 463struct ucc_geth_send_queue_mem_region { 464 struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES]; 465} __attribute__ ((packed)); 466 467struct ucc_geth_thread_tx_pram { 468 u8 res0[64]; 469} __attribute__ ((packed)); 470 471struct ucc_geth_thread_rx_pram { 472 u8 res0[128]; 473} __attribute__ ((packed)); 474 475#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64 476#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64 477#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96 478 479struct ucc_geth_scheduler { 480 u16 cpucount0; /* CPU packet counter */ 481 u16 cpucount1; /* CPU packet counter */ 482 u16 cecount0; /* QE packet counter */ 483 u16 cecount1; /* QE packet counter */ 484 u16 cpucount2; /* CPU packet counter */ 485 u16 cpucount3; /* CPU packet counter */ 486 u16 cecount2; /* QE packet counter */ 487 u16 cecount3; /* QE packet counter */ 488 u16 cpucount4; /* CPU packet counter */ 489 u16 cpucount5; /* CPU packet counter */ 490 u16 cecount4; /* QE packet counter */ 491 u16 cecount5; /* QE packet counter */ 492 u16 cpucount6; /* CPU packet counter */ 493 u16 cpucount7; /* CPU packet counter */ 494 u16 cecount6; /* QE packet counter */ 495 u16 cecount7; /* QE packet counter */ 496 u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */ 497 u32 rtsrshadow; /* temporary variable handled by QE */ 498 u32 time; /* temporary variable handled by QE */ 499 u32 ttl; /* temporary variable handled by QE */ 500 u32 mblinterval; /* max burst length interval */ 501 u16 nortsrbytetime; /* normalized value of byte time in tsr units */ 502 u8 fracsiz; /* radix 2 log value of denom. of 503 NorTSRByteTime */ 504 u8 res0[1]; 505 u8 strictpriorityq; /* Strict Priority Mask register */ 506 u8 txasap; /* Transmit ASAP register */ 507 u8 extrabw; /* Extra BandWidth register */ 508 u8 oldwfqmask; /* temporary variable handled by QE */ 509 u8 weightfactor[NUM_TX_QUEUES]; 510 /**< weight factor for queues */ 511 u32 minw; /* temporary variable handled by QE */ 512 u8 res1[0x70 - 0x64]; 513} __attribute__ ((packed)); 514 515struct ucc_geth_tx_firmware_statistics_pram { 516 u32 sicoltx; /* single collision */ 517 u32 mulcoltx; /* multiple collision */ 518 u32 latecoltxfr; /* late collision */ 519 u32 frabortduecol; /* frames aborted due to transmit collision */ 520 u32 frlostinmactxer; /* frames lost due to internal MAC error 521 transmission that are not counted on any 522 other counter */ 523 u32 carriersenseertx; /* carrier sense error */ 524 u32 frtxok; /* frames transmitted OK */ 525 u32 txfrexcessivedefer; /* frames with defferal time greater than 526 specified threshold */ 527 u32 txpkts256; /* total packets (including bad) between 256 528 and 511 octets */ 529 u32 txpkts512; /* total packets (including bad) between 512 530 and 1023 octets */ 531 u32 txpkts1024; /* total packets (including bad) between 1024 532 and 1518 octets */ 533 u32 txpktsjumbo; /* total packets (including bad) between 1024 534 and MAXLength octets */ 535} __attribute__ ((packed)); 536 537struct ucc_geth_rx_firmware_statistics_pram { 538 u32 frrxfcser; /* frames with crc error */ 539 u32 fraligner; /* frames with alignment error */ 540 u32 inrangelenrxer; /* in range length error */ 541 u32 outrangelenrxer; /* out of range length error */ 542 u32 frtoolong; /* frame too long */ 543 u32 runt; /* runt */ 544 u32 verylongevent; /* very long event */ 545 u32 symbolerror; /* symbol error */ 546 u32 dropbsy; /* drop because of BD not ready */ 547 u8 res0[0x8]; 548 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address 549 or type mismatch) */ 550 u32 underpkts; /* total frames less than 64 octets */ 551 u32 pkts256; /* total frames (including bad) between 256 and 552 511 octets */ 553 u32 pkts512; /* total frames (including bad) between 512 and 554 1023 octets */ 555 u32 pkts1024; /* total frames (including bad) between 1024 556 and 1518 octets */ 557 u32 pktsjumbo; /* total frames (including bad) between 1024 558 and MAXLength octets */ 559 u32 frlossinmacer; /* frames lost because of internal MAC error 560 that is not counted in any other counter */ 561 u32 pausefr; /* pause frames */ 562 u8 res1[0x4]; 563 u32 removevlan; /* total frames that had their VLAN tag removed 564 */ 565 u32 replacevlan; /* total frames that had their VLAN tag 566 replaced */ 567 u32 insertvlan; /* total frames that had their VLAN tag 568 inserted */ 569} __attribute__ ((packed)); 570 571struct ucc_geth_rx_interrupt_coalescing_entry { 572 u32 interruptcoalescingmaxvalue; /* interrupt coalescing max 573 value */ 574 u32 interruptcoalescingcounter; /* interrupt coalescing counter, 575 initialize to 576 interruptcoalescingmaxvalue */ 577} __attribute__ ((packed)); 578 579struct ucc_geth_rx_interrupt_coalescing_table { 580 struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES]; 581 /**< interrupt coalescing entry */ 582} __attribute__ ((packed)); 583 584struct ucc_geth_rx_prefetched_bds { 585 struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */ 586} __attribute__ ((packed)); 587 588struct ucc_geth_rx_bd_queues_entry { 589 u32 bdbaseptr; /* BD base pointer */ 590 u32 bdptr; /* BD pointer */ 591 u32 externalbdbaseptr; /* external BD base pointer */ 592 u32 externalbdptr; /* external BD pointer */ 593} __attribute__ ((packed)); 594 595struct ucc_geth_tx_global_pram { 596 u16 temoder; 597 u8 res0[0x38 - 0x02]; 598 u32 sqptr; /* a base pointer to send queue memory region */ 599 u32 schedulerbasepointer; /* a base pointer to scheduler memory 600 region */ 601 u32 txrmonbaseptr; /* base pointer to Tx RMON statistics counter */ 602 u32 tstate; /* tx internal state. High byte contains 603 function code */ 604 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX]; 605 u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */ 606 u32 tqptr; /* a base pointer to the Tx Queues Memory 607 Region */ 608 u8 res2[0x80 - 0x74]; 609} __attribute__ ((packed)); 610 611/* structure representing Extended Filtering Global Parameters in PRAM */ 612struct ucc_geth_exf_global_pram { 613 u32 l2pcdptr; /* individual address filter, high */ 614 u8 res0[0x10 - 0x04]; 615} __attribute__ ((packed)); 616 617struct ucc_geth_rx_global_pram { 618 u32 remoder; /* ethernet mode reg. */ 619 u32 rqptr; /* base pointer to the Rx Queues Memory Region*/ 620 u32 res0[0x1]; 621 u8 res1[0x20 - 0xC]; 622 u16 typeorlen; /* cutoff point less than which, type/len field 623 is considered length */ 624 u8 res2[0x1]; 625 u8 rxgstpack; /* acknowledgement on GRACEFUL STOP RX command*/ 626 u32 rxrmonbaseptr; /* base pointer to Rx RMON statistics counter */ 627 u8 res3[0x30 - 0x28]; 628 u32 intcoalescingptr; /* Interrupt coalescing table pointer */ 629 u8 res4[0x36 - 0x34]; 630 u8 rstate; /* rx internal state. High byte contains 631 function code */ 632 u8 res5[0x46 - 0x37]; 633 u16 mrblr; /* max receive buffer length reg. */ 634 u32 rbdqptr; /* base pointer to RxBD parameter table 635 description */ 636 u16 mflr; /* max frame length reg. */ 637 u16 minflr; /* min frame length reg. */ 638 u16 maxd1; /* max dma1 length reg. */ 639 u16 maxd2; /* max dma2 length reg. */ 640 u32 ecamptr; /* external CAM address */ 641 u32 l2qt; /* VLAN priority mapping table. */ 642 u32 l3qt[0x8]; /* IP priority mapping table. */ 643 u16 vlantype; /* vlan type */ 644 u16 vlantci; /* default vlan tci */ 645 u8 addressfiltering[64]; /* address filtering data structure */ 646 u32 exfGlobalParam; /* base address for extended filtering global 647 parameters */ 648 u8 res6[0x100 - 0xC4]; /* Initialize to zero */ 649} __attribute__ ((packed)); 650 651#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 652 653/* structure representing InitEnet command */ 654struct ucc_geth_init_pram { 655 u8 resinit1; 656 u8 resinit2; 657 u8 resinit3; 658 u8 resinit4; 659 u16 resinit5; 660 u8 res1[0x1]; 661 u8 largestexternallookupkeysize; 662 u32 rgftgfrxglobal; 663 u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX]; /* rx threads */ 664 u8 res2[0x38 - 0x30]; 665 u32 txglobal; /* tx global */ 666 u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */ 667 u8 res3[0x1]; 668} __attribute__ ((packed)); 669 670#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) 671#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) 672 673#define ENET_INIT_PARAM_RISC_MASK 0x0000003f 674#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 675#define ENET_INIT_PARAM_SNUM_MASK 0xff000000 676#define ENET_INIT_PARAM_SNUM_SHIFT 24 677 678#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06 679#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30 680#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff 681#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00 682#define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400 683 684/* structure representing 82xx Address Filtering Enet Address in PRAM */ 685struct ucc_geth_82xx_enet_address { 686 u8 res1[0x2]; 687 u16 h; /* address (MSB) */ 688 u16 m; /* address */ 689 u16 l; /* address (LSB) */ 690} __attribute__ ((packed)); 691 692/* structure representing 82xx Address Filtering PRAM */ 693struct ucc_geth_82xx_address_filtering_pram { 694 u32 iaddr_h; /* individual address filter, high */ 695 u32 iaddr_l; /* individual address filter, low */ 696 u32 gaddr_h; /* group address filter, high */ 697 u32 gaddr_l; /* group address filter, low */ 698 struct ucc_geth_82xx_enet_address taddr; 699 struct ucc_geth_82xx_enet_address paddr[NUM_OF_PADDRS]; 700 u8 res0[0x40 - 0x38]; 701} __attribute__ ((packed)); 702 703/* GETH Tx firmware statistics structure, used when calling 704 UCC_GETH_GetStatistics. */ 705struct ucc_geth_tx_firmware_statistics { 706 u32 sicoltx; /* single collision */ 707 u32 mulcoltx; /* multiple collision */ 708 u32 latecoltxfr; /* late collision */ 709 u32 frabortduecol; /* frames aborted due to transmit collision */ 710 u32 frlostinmactxer; /* frames lost due to internal MAC error 711 transmission that are not counted on any 712 other counter */ 713 u32 carriersenseertx; /* carrier sense error */ 714 u32 frtxok; /* frames transmitted OK */ 715 u32 txfrexcessivedefer; /* frames with defferal time greater than 716 specified threshold */ 717 u32 txpkts256; /* total packets (including bad) between 256 718 and 511 octets */ 719 u32 txpkts512; /* total packets (including bad) between 512 720 and 1023 octets */ 721 u32 txpkts1024; /* total packets (including bad) between 1024 722 and 1518 octets */ 723 u32 txpktsjumbo; /* total packets (including bad) between 1024 724 and MAXLength octets */ 725} __attribute__ ((packed)); 726 727/* GETH Rx firmware statistics structure, used when calling 728 UCC_GETH_GetStatistics. */ 729struct ucc_geth_rx_firmware_statistics { 730 u32 frrxfcser; /* frames with crc error */ 731 u32 fraligner; /* frames with alignment error */ 732 u32 inrangelenrxer; /* in range length error */ 733 u32 outrangelenrxer; /* out of range length error */ 734 u32 frtoolong; /* frame too long */ 735 u32 runt; /* runt */ 736 u32 verylongevent; /* very long event */ 737 u32 symbolerror; /* symbol error */ 738 u32 dropbsy; /* drop because of BD not ready */ 739 u8 res0[0x8]; 740 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address 741 or type mismatch) */ 742 u32 underpkts; /* total frames less than 64 octets */ 743 u32 pkts256; /* total frames (including bad) between 256 and 744 511 octets */ 745 u32 pkts512; /* total frames (including bad) between 512 and 746 1023 octets */ 747 u32 pkts1024; /* total frames (including bad) between 1024 748 and 1518 octets */ 749 u32 pktsjumbo; /* total frames (including bad) between 1024 750 and MAXLength octets */ 751 u32 frlossinmacer; /* frames lost because of internal MAC error 752 that is not counted in any other counter */ 753 u32 pausefr; /* pause frames */ 754 u8 res1[0x4]; 755 u32 removevlan; /* total frames that had their VLAN tag removed 756 */ 757 u32 replacevlan; /* total frames that had their VLAN tag 758 replaced */ 759 u32 insertvlan; /* total frames that had their VLAN tag 760 inserted */ 761} __attribute__ ((packed)); 762 763/* GETH hardware statistics structure, used when calling 764 UCC_GETH_GetStatistics. */ 765struct ucc_geth_hardware_statistics { 766 u32 tx64; /* Total number of frames (including bad 767 frames) transmitted that were exactly of the 768 minimal length (64 for un tagged, 68 for 769 tagged, or with length exactly equal to the 770 parameter MINLength */ 771 u32 tx127; /* Total number of frames (including bad 772 frames) transmitted that were between 773 MINLength (Including FCS length==4) and 127 774 octets */ 775 u32 tx255; /* Total number of frames (including bad 776 frames) transmitted that were between 128 777 (Including FCS length==4) and 255 octets */ 778 u32 rx64; /* Total number of frames received including 779 bad frames that were exactly of the mninimal 780 length (64 bytes) */ 781 u32 rx127; /* Total number of frames (including bad 782 frames) received that were between MINLength 783 (Including FCS length==4) and 127 octets */ 784 u32 rx255; /* Total number of frames (including bad 785 frames) received that were between 128 786 (Including FCS length==4) and 255 octets */ 787 u32 txok; /* Total number of octets residing in frames 788 that where involved in succesfull 789 transmission */ 790 u16 txcf; /* Total number of PAUSE control frames 791 transmitted by this MAC */ 792 u32 tmca; /* Total number of frames that were transmitted 793 succesfully with the group address bit set 794 that are not broadcast frames */ 795 u32 tbca; /* Total number of frames transmitted 796 succesfully that had destination address 797 field equal to the broadcast address */ 798 u32 rxfok; /* Total number of frames received OK */ 799 u32 rxbok; /* Total number of octets received OK */ 800 u32 rbyt; /* Total number of octets received including 801 octets in bad frames. Must be implemented in 802 HW because it includes octets in frames that 803 never even reach the UCC */ 804 u32 rmca; /* Total number of frames that were received 805 succesfully with the group address bit set 806 that are not broadcast frames */ 807 u32 rbca; /* Total number of frames received succesfully 808 that had destination address equal to the 809 broadcast address */ 810} __attribute__ ((packed)); 811 812/* UCC GETH Tx errors returned via TxConf callback */ 813#define TX_ERRORS_DEF 0x0200 814#define TX_ERRORS_EXDEF 0x0100 815#define TX_ERRORS_LC 0x0080 816#define TX_ERRORS_RL 0x0040 817#define TX_ERRORS_RC_MASK 0x003C 818#define TX_ERRORS_RC_SHIFT 2 819#define TX_ERRORS_UN 0x0002 820#define TX_ERRORS_CSL 0x0001 821 822/* UCC GETH Rx errors returned via RxStore callback */ 823#define RX_ERRORS_CMR 0x0200 824#define RX_ERRORS_M 0x0100 825#define RX_ERRORS_BC 0x0080 826#define RX_ERRORS_MC 0x0040 827 828/* Transmit BD. These are in addition to values defined in uccf. */ 829#define T_VID 0x003c0000 /* insert VLAN id index mask. */ 830#define T_DEF (((u32) TX_ERRORS_DEF ) << 16) 831#define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16) 832#define T_LC (((u32) TX_ERRORS_LC ) << 16) 833#define T_RL (((u32) TX_ERRORS_RL ) << 16) 834#define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16) 835#define T_UN (((u32) TX_ERRORS_UN ) << 16) 836#define T_CSL (((u32) TX_ERRORS_CSL ) << 16) 837#define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \ 838 | T_UN | T_CSL) /* transmit errors to report */ 839 840/* Receive BD. These are in addition to values defined in uccf. */ 841#define R_LG 0x00200000 /* Frame length violation. */ 842#define R_NO 0x00100000 /* Non-octet aligned frame. */ 843#define R_SH 0x00080000 /* Short frame. */ 844#define R_CR 0x00040000 /* CRC error. */ 845#define R_OV 0x00020000 /* Overrun. */ 846#define R_IPCH 0x00010000 /* IP checksum check failed. */ 847#define R_CMR (((u32) RX_ERRORS_CMR ) << 16) 848#define R_M (((u32) RX_ERRORS_M ) << 16) 849#define R_BC (((u32) RX_ERRORS_BC ) << 16) 850#define R_MC (((u32) RX_ERRORS_MC ) << 16) 851#define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to 852 report */ 853#define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \ 854 R_OV | R_IPCH) /* receive errors to discard */ 855 856/* Alignments */ 857#define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256 858#define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128 859#define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128 860#define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64 861#define UCC_GETH_THREAD_DATA_ALIGNMENT 256 /* spec gives values 862 based on num of 863 threads, but always 864 using the maximum is 865 easier */ 866#define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 867#define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */ 868#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */ 869#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */ 870#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64 871#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */ 872#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */ 873#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This 874 is a 875 guess 876 */ 877#define UCC_GETH_RX_BD_RING_ALIGNMENT 32 878#define UCC_GETH_TX_BD_RING_ALIGNMENT 32 879#define UCC_GETH_MRBLR_ALIGNMENT 128 880#define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4 881#define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 882#define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64 883 884#define UCC_GETH_TAD_EF 0x80 885#define UCC_GETH_TAD_V 0x40 886#define UCC_GETH_TAD_REJ 0x20 887#define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2 888#define UCC_GETH_TAD_VTAG_OP_SHIFT 6 889#define UCC_GETH_TAD_V_NON_VTAG_OP 0x20 890#define UCC_GETH_TAD_RQOS_SHIFT 0 891#define UCC_GETH_TAD_V_PRIORITY_SHIFT 5 892#define UCC_GETH_TAD_CFI 0x10 893 894#define UCC_GETH_VLAN_PRIORITY_MAX 8 895#define UCC_GETH_IP_PRIORITY_MAX 64 896#define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8 897#define UCC_GETH_RX_BD_RING_SIZE_MIN 8 898#define UCC_GETH_TX_BD_RING_SIZE_MIN 2 899 900#define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD 901 902/* Driver definitions */ 903#define TX_BD_RING_LEN 0x10 904#define RX_BD_RING_LEN 0x10 905#define UCC_GETH_DEV_WEIGHT TX_BD_RING_LEN 906 907#define TX_RING_MOD_MASK(size) (size-1) 908#define RX_RING_MOD_MASK(size) (size-1) 909 910#define ENET_NUM_OCTETS_PER_ADDRESS 6 911#define ENET_GROUP_ADDR 0x01 /* Group address mask 912 for ethernet 913 addresses */ 914 915#define TX_TIMEOUT (1*HZ) 916#define SKB_ALLOC_TIMEOUT 100000 917#define PHY_INIT_TIMEOUT 100000 918#define PHY_CHANGE_TIME 2 919 920/* Fast Ethernet (10/100 Mbps) */ 921#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size 922 */ 923#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ 924#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ 925#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size 926 */ 927#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ 928#define UCC_GETH_UTFTT_INIT 128 929/* Gigabit Ethernet (1000 Mbps) */ 930#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual 931 FIFO size */ 932#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ 933#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ 934#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual 935 FIFO size */ 936#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ 937#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ 938 939#define UCC_GETH_REMODER_INIT 0 /* bits that must be 940 set */ 941#define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */ 942#define UCC_GETH_UPSMR_INIT (UPSMR_RES1) /* Start value 943 for this 944 register */ 945#define UCC_GETH_MACCFG1_INIT 0 946#define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) 947 948/* Ethernet Address Type. */ 949enum enet_addr_type { 950 ENET_ADDR_TYPE_INDIVIDUAL, 951 ENET_ADDR_TYPE_GROUP, 952 ENET_ADDR_TYPE_BROADCAST 953}; 954 955/* UCC GETH 82xx Ethernet Address Recognition Location */ 956enum ucc_geth_enet_address_recognition_location { 957 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station 958 address */ 959 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional 960 station 961 address 962 paddr1 */ 963 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2, /* additional 964 station 965 address 966 paddr2 */ 967 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3, /* additional 968 station 969 address 970 paddr3 */ 971 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST, /* additional 972 station 973 address 974 paddr4 */ 975 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */ 976 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual 977 hash */ 978}; 979 980/* UCC GETH vlan operation tagged */ 981enum ucc_geth_vlan_operation_tagged { 982 UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */ 983 UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG 984 = 0x1, /* Tagged - replace vid portion of q tag */ 985 UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE 986 = 0x2, /* Tagged - if vid0 replace vid with default value */ 987 UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME 988 = 0x3 /* Tagged - extract q tag from frame */ 989}; 990 991/* UCC GETH vlan operation non-tagged */ 992enum ucc_geth_vlan_operation_non_tagged { 993 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */ 994 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged - 995 q tag insert 996 */ 997}; 998 999/* UCC GETH Rx Quality of Service Mode */ 1000enum ucc_geth_qos_mode { 1001 UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */ 1002 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue 1003 determined 1004 by L2 1005 criteria */ 1006 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2 /* queue 1007 determined 1008 by L3 1009 criteria */ 1010}; 1011 1012/* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together 1013 for combined functionality */ 1014enum ucc_geth_statistics_gathering_mode { 1015 UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No 1016 statistics 1017 gathering */ 1018 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable 1019 hardware 1020 statistics 1021 gathering 1022 */ 1023 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable 1024 firmware 1025 tx 1026 statistics 1027 gathering 1028 */ 1029 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable 1030 firmware 1031 rx 1032 statistics 1033 gathering 1034 */ 1035}; 1036 1037/* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */ 1038enum ucc_geth_maccfg2_pad_and_crc_mode { 1039 UCC_GETH_PAD_AND_CRC_MODE_NONE 1040 = MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding 1041 short frames 1042 nor CRC */ 1043 UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY 1044 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY, /* Append 1045 CRC only */ 1046 UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC = 1047 MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 1048}; 1049 1050/* UCC GETH upsmr Flow Control Mode */ 1051enum ucc_geth_flow_control_mode { 1052 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic 1053 flow control 1054 */ 1055 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY 1056 = 0x00004000 /* Send pause frame when RxFIFO reaches its 1057 emergency threshold */ 1058}; 1059 1060/* UCC GETH number of threads */ 1061enum ucc_geth_num_of_threads { 1062 UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */ 1063 UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */ 1064 UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */ 1065 UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */ 1066 UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */ 1067}; 1068 1069/* UCC GETH number of station addresses */ 1070enum ucc_geth_num_of_station_addresses { 1071 UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */ 1072 UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */ 1073}; 1074 1075/* UCC GETH 82xx Ethernet Address Container */ 1076struct enet_addr_container { 1077 u8 address[ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */ 1078 enum ucc_geth_enet_address_recognition_location location; /* location in 1079 82xx address 1080 recognition 1081 hardware */ 1082 struct list_head node; 1083}; 1084 1085#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node) 1086 1087/* UCC GETH Termination Action Descriptor (TAD) structure. */ 1088struct ucc_geth_tad_params { 1089 int rx_non_dynamic_extended_features_mode; 1090 int reject_frame; 1091 enum ucc_geth_vlan_operation_tagged vtag_op; 1092 enum ucc_geth_vlan_operation_non_tagged vnontag_op; 1093 enum ucc_geth_qos_mode rqos; 1094 u8 vpri; 1095 u16 vid; 1096}; 1097 1098/* GETH protocol initialization structure */ 1099struct ucc_geth_info { 1100 struct ucc_fast_info uf_info; 1101 u8 numQueuesTx; 1102 u8 numQueuesRx; 1103 int ipCheckSumCheck; 1104 int ipCheckSumGenerate; 1105 int rxExtendedFiltering; 1106 u32 extendedFilteringChainPointer; 1107 u16 typeorlen; 1108 int dynamicMaxFrameLength; 1109 int dynamicMinFrameLength; 1110 u8 nonBackToBackIfgPart1; 1111 u8 nonBackToBackIfgPart2; 1112 u8 miminumInterFrameGapEnforcement; 1113 u8 backToBackInterFrameGap; 1114 int ipAddressAlignment; 1115 int lengthCheckRx; 1116 u32 mblinterval; 1117 u16 nortsrbytetime; 1118 u8 fracsiz; 1119 u8 strictpriorityq; 1120 u8 txasap; 1121 u8 extrabw; 1122 int miiPreambleSupress; 1123 u8 altBebTruncation; 1124 int altBeb; 1125 int backPressureNoBackoff; 1126 int noBackoff; 1127 int excessDefer; 1128 u8 maxRetransmission; 1129 u8 collisionWindow; 1130 int pro; 1131 int cap; 1132 int rsh; 1133 int rlpb; 1134 int cam; 1135 int bro; 1136 int ecm; 1137 int receiveFlowControl; 1138 u8 maxGroupAddrInHash; 1139 u8 maxIndAddrInHash; 1140 u8 prel; 1141 u16 maxFrameLength; 1142 u16 minFrameLength; 1143 u16 maxD1Length; 1144 u16 maxD2Length; 1145 u16 vlantype; 1146 u16 vlantci; 1147 u32 ecamptr; 1148 u32 eventRegMask; 1149 u16 pausePeriod; 1150 u16 extensionField; 1151 u8 phy_address; 1152 u32 mdio_bus; 1153 u8 weightfactor[NUM_TX_QUEUES]; 1154 u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; 1155 u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; 1156 u8 l3qt[UCC_GETH_IP_PRIORITY_MAX]; 1157 u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX]; 1158 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX]; 1159 u16 bdRingLenTx[NUM_TX_QUEUES]; 1160 u16 bdRingLenRx[NUM_RX_QUEUES]; 1161 enum ucc_geth_num_of_station_addresses numStationAddresses; 1162 enum qe_fltr_largest_external_tbl_lookup_key_size 1163 largestexternallookupkeysize; 1164 enum ucc_geth_statistics_gathering_mode statisticsMode; 1165 enum ucc_geth_vlan_operation_tagged vlanOperationTagged; 1166 enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged; 1167 enum ucc_geth_qos_mode rxQoSMode; 1168 enum ucc_geth_flow_control_mode aufc; 1169 enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; 1170 enum ucc_geth_num_of_threads numThreadsTx; 1171 enum ucc_geth_num_of_threads numThreadsRx; 1172 enum qe_risc_allocation riscTx; 1173 enum qe_risc_allocation riscRx; 1174}; 1175 1176/* structure representing UCC GETH */ 1177struct ucc_geth_private { 1178 struct ucc_geth_info *ug_info; 1179 struct ucc_fast_private *uccf; 1180 struct net_device *dev; 1181 struct net_device_stats stats; /* linux network statistics */ 1182 struct ucc_geth *ug_regs; 1183 struct ucc_geth_init_pram *p_init_enet_param_shadow; 1184 struct ucc_geth_exf_global_pram *p_exf_glbl_param; 1185 u32 exf_glbl_param_offset; 1186 struct ucc_geth_rx_global_pram *p_rx_glbl_pram; 1187 u32 rx_glbl_pram_offset; 1188 struct ucc_geth_tx_global_pram *p_tx_glbl_pram; 1189 u32 tx_glbl_pram_offset; 1190 struct ucc_geth_send_queue_mem_region *p_send_q_mem_reg; 1191 u32 send_q_mem_reg_offset; 1192 struct ucc_geth_thread_data_tx *p_thread_data_tx; 1193 u32 thread_dat_tx_offset; 1194 struct ucc_geth_thread_data_rx *p_thread_data_rx; 1195 u32 thread_dat_rx_offset; 1196 struct ucc_geth_scheduler *p_scheduler; 1197 u32 scheduler_offset; 1198 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; 1199 u32 tx_fw_statistics_pram_offset; 1200 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; 1201 u32 rx_fw_statistics_pram_offset; 1202 struct ucc_geth_rx_interrupt_coalescing_table *p_rx_irq_coalescing_tbl; 1203 u32 rx_irq_coalescing_tbl_offset; 1204 struct ucc_geth_rx_bd_queues_entry *p_rx_bd_qs_tbl; 1205 u32 rx_bd_qs_tbl_offset; 1206 u8 *p_tx_bd_ring[NUM_TX_QUEUES]; 1207 u32 tx_bd_ring_offset[NUM_TX_QUEUES]; 1208 u8 *p_rx_bd_ring[NUM_RX_QUEUES]; 1209 u32 rx_bd_ring_offset[NUM_RX_QUEUES]; 1210 u8 *confBd[NUM_TX_QUEUES]; 1211 u8 *txBd[NUM_TX_QUEUES]; 1212 u8 *rxBd[NUM_RX_QUEUES]; 1213 int badFrame[NUM_RX_QUEUES]; 1214 u16 cpucount[NUM_TX_QUEUES]; 1215 volatile u16 *p_cpucount[NUM_TX_QUEUES]; 1216 int indAddrRegUsed[NUM_OF_PADDRS]; 1217 u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */ 1218 u8 numGroupAddrInHash; 1219 u8 numIndAddrInHash; 1220 u8 numIndAddrInReg; 1221 int rx_extended_features; 1222 int rx_non_dynamic_extended_features; 1223 struct list_head conf_skbs; 1224 struct list_head group_hash_q; 1225 struct list_head ind_hash_q; 1226 u32 saved_uccm; 1227 spinlock_t lock; 1228 /* pointers to arrays of skbuffs for tx and rx */ 1229 struct sk_buff **tx_skbuff[NUM_TX_QUEUES]; 1230 struct sk_buff **rx_skbuff[NUM_RX_QUEUES]; 1231 /* indices pointing to the next free sbk in skb arrays */ 1232 u16 skb_curtx[NUM_TX_QUEUES]; 1233 u16 skb_currx[NUM_RX_QUEUES]; 1234 /* index of the first skb which hasn't been transmitted yet. */ 1235 u16 skb_dirtytx[NUM_TX_QUEUES]; 1236 1237 struct ugeth_mii_info *mii_info; 1238 struct phy_device *phydev; 1239 phy_interface_t phy_interface; 1240 int max_speed; 1241 uint32_t msg_enable; 1242 int oldspeed; 1243 int oldduplex; 1244 int oldlink; 1245}; 1246 1247#endif /* __UCC_GETH_H__ */ 1248