1#ifndef _TITAN_GE_H_ 2#define _TITAN_GE_H_ 3 4#include <linux/module.h> 5#include <linux/kernel.h> 6#include <linux/spinlock.h> 7#include <asm/byteorder.h> 8 9/* 10 * These functions should be later moved to a more generic location since there 11 * will be others accessing it also 12 */ 13 14/* 15 * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in 16 * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5 17 * register. 18 */ 19 20#define TITAN_GE_BASE 0xfe000000UL 21#define TITAN_GE_SIZE 0x10000UL 22 23extern unsigned long titan_ge_base; 24 25#define TITAN_GE_WRITE(offset, data) \ 26 *(volatile u32 *)(titan_ge_base + (offset)) = (data) 27 28#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset)) 29 30#ifndef msec_delay 31#define msec_delay(x) do { if(in_interrupt()) { \ 32 /* Don't mdelay in interrupt context! */ \ 33 BUG(); \ 34 } else { \ 35 set_current_state(TASK_UNINTERRUPTIBLE); \ 36 schedule_timeout((x * HZ)/1000); \ 37 } } while(0) 38#endif 39 40#define TITAN_GE_PORT_0 41 42#define TITAN_SRAM_BASE ((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4) 43#define TITAN_SRAM_SIZE 0x2000UL 44 45/* 46 * We may need these constants 47 */ 48#define TITAN_BIT0 0x00000001 49#define TITAN_BIT1 0x00000002 50#define TITAN_BIT2 0x00000004 51#define TITAN_BIT3 0x00000008 52#define TITAN_BIT4 0x00000010 53#define TITAN_BIT5 0x00000020 54#define TITAN_BIT6 0x00000040 55#define TITAN_BIT7 0x00000080 56#define TITAN_BIT8 0x00000100 57#define TITAN_BIT9 0x00000200 58#define TITAN_BIT10 0x00000400 59#define TITAN_BIT11 0x00000800 60#define TITAN_BIT12 0x00001000 61#define TITAN_BIT13 0x00002000 62#define TITAN_BIT14 0x00004000 63#define TITAN_BIT15 0x00008000 64#define TITAN_BIT16 0x00010000 65#define TITAN_BIT17 0x00020000 66#define TITAN_BIT18 0x00040000 67#define TITAN_BIT19 0x00080000 68#define TITAN_BIT20 0x00100000 69#define TITAN_BIT21 0x00200000 70#define TITAN_BIT22 0x00400000 71#define TITAN_BIT23 0x00800000 72#define TITAN_BIT24 0x01000000 73#define TITAN_BIT25 0x02000000 74#define TITAN_BIT26 0x04000000 75#define TITAN_BIT27 0x08000000 76#define TITAN_BIT28 0x10000000 77#define TITAN_BIT29 0x20000000 78#define TITAN_BIT30 0x40000000 79#define TITAN_BIT31 0x80000000 80 81/* Flow Control */ 82#define TITAN_GE_FC_NONE 0x0 83#define TITAN_GE_FC_FULL 0x1 84#define TITAN_GE_FC_TX_PAUSE 0x2 85#define TITAN_GE_FC_RX_PAUSE 0x3 86 87/* Duplex Settings */ 88#define TITAN_GE_FULL_DUPLEX 0x1 89#define TITAN_GE_HALF_DUPLEX 0x2 90 91/* Speed settings */ 92#define TITAN_GE_SPEED_1000 0x1 93#define TITAN_GE_SPEED_100 0x2 94#define TITAN_GE_SPEED_10 0x3 95 96/* Debugging info only */ 97#undef TITAN_DEBUG 98 99/* Keep the rings in the Titan's SSRAM */ 100#define TITAN_RX_RING_IN_SRAM 101 102#ifdef CONFIG_64BIT 103#define TITAN_GE_IE_MASK 0xfffffffffb001b64 104#define TITAN_GE_IE_STATUS 0xfffffffffb001b60 105#else 106#define TITAN_GE_IE_MASK 0xfb001b64 107#define TITAN_GE_IE_STATUS 0xfb001b60 108#endif 109 110/* Support for Jumbo Frames */ 111#undef TITAN_GE_JUMBO_FRAMES 112 113/* Rx buffer size */ 114#ifdef TITAN_GE_JUMBO_FRAMES 115#define TITAN_GE_JUMBO_BUFSIZE 9080 116#else 117#define TITAN_GE_STD_BUFSIZE 1580 118#endif 119 120/* 121 * Tx and Rx Interrupt Coalescing parameter. These values are 122 * for 1 Ghz processor. Rx coalescing can be taken care of 123 * by NAPI. NAPI is adaptive and hence useful. Tx coalescing 124 * is not adaptive. Hence, these values need to be adjusted 125 * based on load, CPU speed etc. 126 */ 127#define TITAN_GE_RX_COAL 150 128#define TITAN_GE_TX_COAL 300 129 130#if defined(__BIG_ENDIAN) 131 132/* Define the Rx descriptor */ 133typedef struct eth_rx_desc { 134 u32 reserved; /* Unused */ 135 u32 buffer_addr; /* CPU buffer address */ 136 u32 cmd_sts; /* Command and Status */ 137 u32 buffer; /* XDMA buffer address */ 138} titan_ge_rx_desc; 139 140/* Define the Tx descriptor */ 141typedef struct eth_tx_desc { 142 u16 cmd_sts; /* Command, Status and Buffer count */ 143 u16 buffer_len; /* Length of the buffer */ 144 u32 buffer_addr; /* Physical address of the buffer */ 145} titan_ge_tx_desc; 146 147#elif defined(__LITTLE_ENDIAN) 148 149/* Define the Rx descriptor */ 150typedef struct eth_rx_desc { 151 u32 buffer_addr; /* CPU buffer address */ 152 u32 reserved; /* Unused */ 153 u32 buffer; /* XDMA buffer address */ 154 u32 cmd_sts; /* Command and Status */ 155} titan_ge_rx_desc; 156 157/* Define the Tx descriptor */ 158typedef struct eth_tx_desc { 159 u32 buffer_addr; /* Physical address of the buffer */ 160 u16 buffer_len; /* Length of the buffer */ 161 u16 cmd_sts; /* Command, Status and Buffer count */ 162} titan_ge_tx_desc; 163#endif 164 165/* Default Tx Queue Size */ 166#define TITAN_GE_TX_QUEUE 128 167#define TITAN_TX_RING_BYTES (TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc)) 168 169/* Default Rx Queue Size */ 170#define TITAN_GE_RX_QUEUE 64 171#define TITAN_RX_RING_BYTES (TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc)) 172 173/* Packet Structure */ 174typedef struct _pkt_info { 175 unsigned int len; 176 unsigned int cmd_sts; 177 unsigned int buffer; 178 struct sk_buff *skb; 179 unsigned int checksum; 180} titan_ge_packet; 181 182 183#define PHYS_CNT 3 184 185/* Titan Port specific data structure */ 186typedef struct _eth_port_ctrl { 187 unsigned int port_num; 188 u8 port_mac_addr[6]; 189 190 /* Rx descriptor pointers */ 191 int rx_curr_desc_q, rx_used_desc_q; 192 193 /* Tx descriptor pointers */ 194 int tx_curr_desc_q, tx_used_desc_q; 195 196 /* Rx descriptor area */ 197 volatile titan_ge_rx_desc *rx_desc_area; 198 unsigned int rx_desc_area_size; 199 struct sk_buff* rx_skb[TITAN_GE_RX_QUEUE]; 200 201 /* Tx Descriptor area */ 202 volatile titan_ge_tx_desc *tx_desc_area; 203 unsigned int tx_desc_area_size; 204 struct sk_buff* tx_skb[TITAN_GE_TX_QUEUE]; 205 206 /* Timeout task */ 207 struct work_struct tx_timeout_task; 208 209 /* DMA structures and handles */ 210 dma_addr_t tx_dma; 211 dma_addr_t rx_dma; 212 dma_addr_t tx_dma_array[TITAN_GE_TX_QUEUE]; 213 214 /* Device lock */ 215 spinlock_t lock; 216 217 unsigned int tx_ring_skbs; 218 unsigned int rx_ring_size; 219 unsigned int tx_ring_size; 220 unsigned int rx_ring_skbs; 221 222 struct net_device_stats stats; 223 224 /* Tx and Rx coalescing */ 225 unsigned long rx_int_coal; 226 unsigned long tx_int_coal; 227 228 /* Threshold for replenishing the Rx and Tx rings */ 229 unsigned int tx_threshold; 230 unsigned int rx_threshold; 231 232 /* NAPI work limit */ 233 unsigned int rx_work_limit; 234} titan_ge_port_info; 235 236/* Titan specific constants */ 237#define TITAN_ETH_PORT_IRQ 3 238 239/* Max Rx buffer */ 240#define TITAN_GE_MAX_RX_BUFFER 65536 241 242/* Tx and Rx Error */ 243#define TITAN_GE_ERROR 244 245/* Rx Descriptor Command and Status */ 246 247#define TITAN_GE_RX_CRC_ERROR TITAN_BIT27 /* crc error */ 248#define TITAN_GE_RX_OVERFLOW_ERROR TITAN_BIT15 /* overflow */ 249#define TITAN_GE_RX_BUFFER_OWNED TITAN_BIT21 /* buffer ownership */ 250#define TITAN_GE_RX_STP TITAN_BIT31 /* start of packet */ 251#define TITAN_GE_RX_BAM TITAN_BIT30 /* broadcast address match */ 252#define TITAN_GE_RX_PAM TITAN_BIT28 /* physical address match */ 253#define TITAN_GE_RX_LAFM TITAN_BIT29 /* logical address filter match */ 254#define TITAN_GE_RX_VLAN TITAN_BIT26 /* virtual lans */ 255#define TITAN_GE_RX_PERR TITAN_BIT19 /* packet error */ 256#define TITAN_GE_RX_TRUNC TITAN_BIT20 /* packet size greater than 32 buffers */ 257 258/* Tx Descriptor Command */ 259#define TITAN_GE_TX_BUFFER_OWNED TITAN_BIT5 /* buffer ownership */ 260#define TITAN_GE_TX_ENABLE_INTERRUPT TITAN_BIT15 /* Interrupt Enable */ 261 262/* Return Status */ 263#define TITAN_OK 0x1 /* Good Status */ 264#define TITAN_ERROR 0x2 /* Error Status */ 265 266/* MIB specific register offset */ 267#define TITAN_GE_MSTATX_STATS_BASE_LOW 0x0800 /* MSTATX COUNTL[15:0] */ 268#define TITAN_GE_MSTATX_STATS_BASE_MID 0x0804 /* MSTATX COUNTM[15:0] */ 269#define TITAN_GE_MSTATX_STATS_BASE_HI 0x0808 /* MSTATX COUNTH[7:0] */ 270#define TITAN_GE_MSTATX_CONTROL 0x0828 /* MSTATX Control */ 271#define TITAN_GE_MSTATX_VARIABLE_SELECT 0x082C /* MSTATX Variable Select */ 272 273/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */ 274#define TITAN_GE_MSTATX_RXFRAMESOK 0x0040 275#define TITAN_GE_MSTATX_RXOCTETSOK 0x0050 276#define TITAN_GE_MSTATX_RXFRAMES 0x0060 277#define TITAN_GE_MSTATX_RXOCTETS 0x0070 278#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK 0x0080 279#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK 0x0090 280#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK 0x00A0 281#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK 0x00B0 282#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK 0x00C0 283#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK 0x00D0 284#define TITAN_GE_MSTATX_RXFCSERROR 0x00E0 285#define TITAN_GE_MSTATX_RXALIGNMENTERROR 0x00F0 286#define TITAN_GE_MSTATX_RXSYMBOLERROR 0x0100 287#define TITAN_GE_MSTATX_RXLAYER1ERROR 0x0110 288#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR 0x0120 289#define TITAN_GE_MSTATX_RXLONGLENGTHERROR 0x0130 290#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR 0x0140 291#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR 0x0150 292#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR 0x0160 293#define TITAN_GE_MSTATX_RXFRAMES64OCTETS 0x0170 294#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS 0x0180 295#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS 0x0190 296#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS 0x01A0 297#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS 0x01B0 298#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS 0x01C0 299#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE 0x01D0 300#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED 0x01E0 301#define TITAN_GE_MSTATX_RXVARIABLE 0x01F0 302#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED 0x0200 303#define TITAN_GE_MSTATX_UNICASTFILTERED 0x0210 304#define TITAN_GE_MSTATX_MULTICASTFILTERED 0x0220 305#define TITAN_GE_MSTATX_BROADCASTFILTERED 0x0230 306#define TITAN_GE_MSTATX_HASHFILTERED 0x0240 307#define TITAN_GE_MSTATX_TXFRAMESOK 0x0250 308#define TITAN_GE_MSTATX_TXOCTETSOK 0x0260 309#define TITAN_GE_MSTATX_TXOCTETS 0x0270 310#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK 0x0280 311#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK 0x0290 312#define TITAN_GE_MSTATX_TXFCSERROR 0x02A0 313#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR 0x02B0 314#define TITAN_GE_MSTATX_TXLONGLENGTHERROR 0x02C0 315#define TITAN_GE_MSTATX_TXSYSTEMERROR 0x02D0 316#define TITAN_GE_MSTATX_TXMACERROR 0x02E0 317#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR 0x02F0 318#define TITAN_GE_MSTATX_TXSQETESTERROR 0x0300 319#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK 0x0310 320#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK 0x0320 321#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK 0x0330 322#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED 0x0340 323#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED 0x0350 324#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED 0x0360 325#define TITAN_GE_MSTATX_TXFRAMES64OCTETS 0x0370 326#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS 0x0380 327#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS 0x0390 328#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS 0x03A0 329#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS 0x03B0 330#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS 0x03C0 331#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE 0x03D0 332#define TITAN_GE_MSTATX_TXVARIABLE 0x03E0 333#define TITAN_GE_MSTATX_RXSYSTEMERROR 0x03F0 334#define TITAN_GE_MSTATX_SINGLECOLLISION 0x0400 335#define TITAN_GE_MSTATX_MULTIPLECOLLISION 0x0410 336#define TITAN_GE_MSTATX_DEFERREDXMISSIONS 0x0420 337#define TITAN_GE_MSTATX_LATECOLLISIONS 0x0430 338#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS 0x0440 339 340/* Interrupt specific defines */ 341#define TITAN_GE_DEVICE_ID 0x0000 /* Device ID */ 342#define TITAN_GE_RESET 0x0004 /* Reset reg */ 343#define TITAN_GE_TSB_CTRL_0 0x000C /* TSB Control reg 0 */ 344#define TITAN_GE_TSB_CTRL_1 0x0010 /* TSB Control reg 1 */ 345#define TITAN_GE_INTR_GRP0_STATUS 0x0040 /* General Interrupt Group 0 Status */ 346#define TITAN_GE_INTR_XDMA_CORE_A 0x0048 /* XDMA Channel Interrupt Status, Core A*/ 347#define TITAN_GE_INTR_XDMA_CORE_B 0x004C /* XDMA Channel Interrupt Status, Core B*/ 348#define TITAN_GE_INTR_XDMA_IE 0x0058 /* XDMA Channel Interrupt Enable */ 349#define TITAN_GE_SDQPF_ECC_INTR 0x480C /* SDQPF ECC Interrupt Status */ 350#define TITAN_GE_SDQPF_RXFIFO_CTL 0x4828 /* SDQPF RxFifo Control and Interrupt Enb*/ 351#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C /* SDQPF RxFifo Interrupt Status */ 352#define TITAN_GE_SDQPF_TXFIFO_CTL 0x4928 /* SDQPF TxFifo Control and Interrupt Enb*/ 353#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C /* SDQPF TxFifo Interrupt Status */ 354#define TITAN_GE_SDQPF_RXFIFO_0 0x4840 /* SDQPF RxFIFO Enable */ 355#define TITAN_GE_SDQPF_TXFIFO_0 0x4940 /* SDQPF TxFIFO Enable */ 356#define TITAN_GE_XDMA_CONFIG 0x5000 /* XDMA Global Configuration */ 357#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010 /* XDMA Interrupt Summary */ 358#define TITAN_GE_XDMA_BUFADDRPRE 0x5018 /* XDMA Buffer Address Prefix */ 359#define TITAN_GE_XDMA_DESCADDRPRE 0x501C /* XDMA Descriptor Address Prefix */ 360#define TITAN_GE_XDMA_PORTWEIGHT 0x502C /* XDMA Port Weight Configuration */ 361 362/* Rx MAC defines */ 363#define TITAN_GE_RMAC_CONFIG_1 0x1200 /* RMAC Configuration 1 */ 364#define TITAN_GE_RMAC_CONFIG_2 0x1204 /* RMAC Configuration 2 */ 365#define TITAN_GE_RMAC_MAX_FRAME_LEN 0x1208 /* RMAC Max Frame Length */ 366#define TITAN_GE_RMAC_STATION_HI 0x120C /* Rx Station Address High */ 367#define TITAN_GE_RMAC_STATION_MID 0x1210 /* Rx Station Address Middle */ 368#define TITAN_GE_RMAC_STATION_LOW 0x1214 /* Rx Station Address Low */ 369#define TITAN_GE_RMAC_LINK_CONFIG 0x1218 /* RMAC Link Configuration */ 370 371/* Tx MAC defines */ 372#define TITAN_GE_TMAC_CONFIG_1 0x1240 /* TMAC Configuration 1 */ 373#define TITAN_GE_TMAC_CONFIG_2 0x1244 /* TMAC Configuration 2 */ 374#define TITAN_GE_TMAC_IPG 0x1248 /* TMAC Inter-Packet Gap */ 375#define TITAN_GE_TMAC_STATION_HI 0x124C /* Tx Station Address High */ 376#define TITAN_GE_TMAC_STATION_MID 0x1250 /* Tx Station Address Middle */ 377#define TITAN_GE_TMAC_STATION_LOW 0x1254 /* Tx Station Address Low */ 378#define TITAN_GE_TMAC_MAX_FRAME_LEN 0x1258 /* TMAC Max Frame Length */ 379#define TITAN_GE_TMAC_MIN_FRAME_LEN 0x125C /* TMAC Min Frame Length */ 380#define TITAN_GE_TMAC_PAUSE_FRAME_TIME 0x1260 /* TMAC Pause Frame Time */ 381#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL 0x1264 /* TMAC Pause Frame Interval */ 382 383/* GMII register */ 384#define TITAN_GE_GMII_INTERRUPT_STATUS 0x1348 /* GMII Interrupt Status */ 385#define TITAN_GE_GMII_CONFIG_GENERAL 0x134C /* GMII Configuration General */ 386#define TITAN_GE_GMII_CONFIG_MODE 0x1350 /* GMII Configuration Mode */ 387 388/* Tx and Rx XDMA defines */ 389#define TITAN_GE_INT_COALESCING 0x5030 /* Interrupt Coalescing */ 390#define TITAN_GE_CHANNEL0_CONFIG 0x5040 /* Channel 0 XDMA config */ 391#define TITAN_GE_CHANNEL0_INTERRUPT 0x504c /* Channel 0 Interrupt Status */ 392#define TITAN_GE_GDI_INTERRUPT_ENABLE 0x5050 /* IE for the GDI Errors */ 393#define TITAN_GE_CHANNEL0_PACKET 0x5060 /* Channel 0 Packet count */ 394#define TITAN_GE_CHANNEL0_BYTE 0x5064 /* Channel 0 Byte count */ 395#define TITAN_GE_CHANNEL0_TX_DESC 0x5054 /* Channel 0 Tx first desc */ 396#define TITAN_GE_CHANNEL0_RX_DESC 0x5058 /* Channel 0 Rx first desc */ 397 398/* AFX (Address Filter Exact) register offsets for Slice 0 */ 399#define TITAN_GE_AFX_EXACT_MATCH_LOW 0x1100 /* AFX Exact Match Address Low*/ 400#define TITAN_GE_AFX_EXACT_MATCH_MID 0x1104 /* AFX Exact Match Address Mid*/ 401#define TITAN_GE_AFX_EXACT_MATCH_HIGH 0x1108 /* AFX Exact Match Address Hi */ 402#define TITAN_GE_AFX_EXACT_MATCH_VID 0x110C /* AFX Exact Match VID */ 403#define TITAN_GE_AFX_MULTICAST_HASH_LOW 0x1110 /* AFX Multicast HASH Low */ 404#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW 0x1114 /* AFX Multicast HASH MidLow */ 405#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI 0x1118 /* AFX Multicast HASH MidHi */ 406#define TITAN_GE_AFX_MULTICAST_HASH_HI 0x111C /* AFX Multicast HASH Hi */ 407#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 0x1120 /* AFX Address Filter Ctrl 0 */ 408#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 0x1124 /* AFX Address Filter Ctrl 1 */ 409#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 0x1128 /* AFX Address Filter Ctrl 2 */ 410 411/* Traffic Groomer block */ 412#define TITAN_GE_TRTG_CONFIG 0x1000 /* TRTG Config */ 413 414#endif /* _TITAN_GE_H_ */ 415