1/* $Id: tg3.h,v 1.1.1.1 2007/08/03 18:52:45 Exp $ 2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 3 * 4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) 6 * Copyright (C) 2004 Sun Microsystems Inc. 7 */ 8 9#ifndef _T3_H 10#define _T3_H 11 12#define TG3_64BIT_REG_HIGH 0x00UL 13#define TG3_64BIT_REG_LOW 0x04UL 14 15/* Descriptor block info. */ 16#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 17#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 18#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 19#define BDINFO_FLAGS_DISABLED 0x00000002 20#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 21#define BDINFO_FLAGS_MAXLEN_SHIFT 16 22#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 23#define TG3_BDINFO_SIZE 0x10UL 24 25#define RX_COPY_THRESHOLD 256 26 27#define TG3_RX_INTERNAL_RING_SZ_5906 32 28 29#define RX_STD_MAX_SIZE 1536 30#define RX_STD_MAX_SIZE_5705 512 31#define RX_JUMBO_MAX_SIZE 0xdeadbeef 32 33/* First 256 bytes are a mirror of PCI config space. */ 34#define TG3PCI_VENDOR 0x00000000 35#define TG3PCI_VENDOR_BROADCOM 0x14e4 36#define TG3PCI_DEVICE 0x00000002 37#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 38#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 39#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 40#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 41#define TG3PCI_COMMAND 0x00000004 42#define TG3PCI_STATUS 0x00000006 43#define TG3PCI_CCREVID 0x00000008 44#define TG3PCI_CACHELINESZ 0x0000000c 45#define TG3PCI_LATTIMER 0x0000000d 46#define TG3PCI_HEADERTYPE 0x0000000e 47#define TG3PCI_BIST 0x0000000f 48#define TG3PCI_BASE0_LOW 0x00000010 49#define TG3PCI_BASE0_HIGH 0x00000014 50/* 0x18 --> 0x2c unused */ 51#define TG3PCI_SUBSYSVENID 0x0000002c 52#define TG3PCI_SUBSYSID 0x0000002e 53#define TG3PCI_ROMADDR 0x00000030 54#define TG3PCI_CAPLIST 0x00000034 55/* 0x35 --> 0x3c unused */ 56#define TG3PCI_IRQ_LINE 0x0000003c 57#define TG3PCI_IRQ_PIN 0x0000003d 58#define TG3PCI_MIN_GNT 0x0000003e 59#define TG3PCI_MAX_LAT 0x0000003f 60#define TG3PCI_X_CAPS 0x00000040 61#define PCIX_CAPS_RELAXED_ORDERING 0x00020000 62#define PCIX_CAPS_SPLIT_MASK 0x00700000 63#define PCIX_CAPS_SPLIT_SHIFT 20 64#define PCIX_CAPS_BURST_MASK 0x000c0000 65#define PCIX_CAPS_BURST_SHIFT 18 66#define PCIX_CAPS_MAX_BURST_CPIOB 2 67#define TG3PCI_PM_CAP_PTR 0x00000041 68#define TG3PCI_X_COMMAND 0x00000042 69#define TG3PCI_X_STATUS 0x00000044 70#define TG3PCI_PM_CAP_ID 0x00000048 71#define TG3PCI_VPD_CAP_PTR 0x00000049 72#define TG3PCI_PM_CAPS 0x0000004a 73#define TG3PCI_PM_CTRL_STAT 0x0000004c 74#define TG3PCI_BR_SUPP_EXT 0x0000004e 75#define TG3PCI_PM_DATA 0x0000004f 76#define TG3PCI_VPD_CAP_ID 0x00000050 77#define TG3PCI_MSI_CAP_PTR 0x00000051 78#define TG3PCI_VPD_ADDR_FLAG 0x00000052 79#define VPD_ADDR_FLAG_WRITE 0x00008000 80#define TG3PCI_VPD_DATA 0x00000054 81#define TG3PCI_MSI_CAP_ID 0x00000058 82#define TG3PCI_NXT_CAP_PTR 0x00000059 83#define TG3PCI_MSI_CTRL 0x0000005a 84#define TG3PCI_MSI_ADDR_LOW 0x0000005c 85#define TG3PCI_MSI_ADDR_HIGH 0x00000060 86#define TG3PCI_MSI_DATA 0x00000064 87/* 0x66 --> 0x68 unused */ 88#define TG3PCI_MISC_HOST_CTRL 0x00000068 89#define MISC_HOST_CTRL_CLEAR_INT 0x00000001 90#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 91#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 92#define MISC_HOST_CTRL_WORD_SWAP 0x00000008 93#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 94#define MISC_HOST_CTRL_CLKREG_RW 0x00000020 95#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 96#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 97#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 98#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 99#define MISC_HOST_CTRL_CHIPREV 0xffff0000 100#define MISC_HOST_CTRL_CHIPREV_SHIFT 16 101#define GET_CHIP_REV_ID(MISC_HOST_CTRL) \ 102 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \ 103 MISC_HOST_CTRL_CHIPREV_SHIFT) 104#define CHIPREV_ID_5700_A0 0x7000 105#define CHIPREV_ID_5700_A1 0x7001 106#define CHIPREV_ID_5700_B0 0x7100 107#define CHIPREV_ID_5700_B1 0x7101 108#define CHIPREV_ID_5700_B3 0x7102 109#define CHIPREV_ID_5700_ALTIMA 0x7104 110#define CHIPREV_ID_5700_C0 0x7200 111#define CHIPREV_ID_5701_A0 0x0000 112#define CHIPREV_ID_5701_B0 0x0100 113#define CHIPREV_ID_5701_B2 0x0102 114#define CHIPREV_ID_5701_B5 0x0105 115#define CHIPREV_ID_5703_A0 0x1000 116#define CHIPREV_ID_5703_A1 0x1001 117#define CHIPREV_ID_5703_A2 0x1002 118#define CHIPREV_ID_5703_A3 0x1003 119#define CHIPREV_ID_5704_A0 0x2000 120#define CHIPREV_ID_5704_A1 0x2001 121#define CHIPREV_ID_5704_A2 0x2002 122#define CHIPREV_ID_5704_A3 0x2003 123#define CHIPREV_ID_5705_A0 0x3000 124#define CHIPREV_ID_5705_A1 0x3001 125#define CHIPREV_ID_5705_A2 0x3002 126#define CHIPREV_ID_5705_A3 0x3003 127#define CHIPREV_ID_5750_A0 0x4000 128#define CHIPREV_ID_5750_A1 0x4001 129#define CHIPREV_ID_5750_A3 0x4003 130#define CHIPREV_ID_5750_C2 0x4202 131#define CHIPREV_ID_5752_A0_HW 0x5000 132#define CHIPREV_ID_5752_A0 0x6000 133#define CHIPREV_ID_5752_A1 0x6001 134#define CHIPREV_ID_5714_A2 0x9002 135#define CHIPREV_ID_5906_A1 0xc001 136#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) 137#define ASIC_REV_5700 0x07 138#define ASIC_REV_5701 0x00 139#define ASIC_REV_5703 0x01 140#define ASIC_REV_5704 0x02 141#define ASIC_REV_5705 0x03 142#define ASIC_REV_5750 0x04 143#define ASIC_REV_5752 0x06 144#define ASIC_REV_5780 0x08 145#define ASIC_REV_5714 0x09 146#define ASIC_REV_5755 0x0a 147#define ASIC_REV_5787 0x0b 148#define ASIC_REV_5906 0x0c 149#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 150#define CHIPREV_5700_AX 0x70 151#define CHIPREV_5700_BX 0x71 152#define CHIPREV_5700_CX 0x72 153#define CHIPREV_5701_AX 0x00 154#define CHIPREV_5703_AX 0x10 155#define CHIPREV_5704_AX 0x20 156#define CHIPREV_5704_BX 0x21 157#define CHIPREV_5750_AX 0x40 158#define CHIPREV_5750_BX 0x41 159#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) 160#define METAL_REV_A0 0x00 161#define METAL_REV_A1 0x01 162#define METAL_REV_B0 0x00 163#define METAL_REV_B1 0x01 164#define METAL_REV_B2 0x02 165#define TG3PCI_DMA_RW_CTRL 0x0000006c 166#define DMA_RWCTRL_MIN_DMA 0x000000ff 167#define DMA_RWCTRL_MIN_DMA_SHIFT 0 168#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 169#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 170#define DMA_RWCTRL_READ_BNDRY_16 0x00000100 171#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 172#define DMA_RWCTRL_READ_BNDRY_32 0x00000200 173#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 174#define DMA_RWCTRL_READ_BNDRY_64 0x00000300 175#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 176#define DMA_RWCTRL_READ_BNDRY_128 0x00000400 177#define DMA_RWCTRL_READ_BNDRY_256 0x00000500 178#define DMA_RWCTRL_READ_BNDRY_512 0x00000600 179#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 180#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 181#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 182#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 183#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 184#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 185#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 186#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 187#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 188#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 189#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 190#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 191#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 192#define DMA_RWCTRL_ONE_DMA 0x00004000 193#define DMA_RWCTRL_READ_WATER 0x00070000 194#define DMA_RWCTRL_READ_WATER_SHIFT 16 195#define DMA_RWCTRL_WRITE_WATER 0x00380000 196#define DMA_RWCTRL_WRITE_WATER_SHIFT 19 197#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 198#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 199#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 200#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 201#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 202#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 203#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 204#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 205#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 206#define TG3PCI_PCISTATE 0x00000070 207#define PCISTATE_FORCE_RESET 0x00000001 208#define PCISTATE_INT_NOT_ACTIVE 0x00000002 209#define PCISTATE_CONV_PCI_MODE 0x00000004 210#define PCISTATE_BUS_SPEED_HIGH 0x00000008 211#define PCISTATE_BUS_32BIT 0x00000010 212#define PCISTATE_ROM_ENABLE 0x00000020 213#define PCISTATE_ROM_RETRY_ENABLE 0x00000040 214#define PCISTATE_FLAT_VIEW 0x00000100 215#define PCISTATE_RETRY_SAME_DMA 0x00002000 216#define TG3PCI_CLOCK_CTRL 0x00000074 217#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 218#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 219#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 220#define CLOCK_CTRL_ALTCLK 0x00001000 221#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 222#define CLOCK_CTRL_44MHZ_CORE 0x00040000 223#define CLOCK_CTRL_625_CORE 0x00100000 224#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 225#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 226#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 227#define TG3PCI_REG_BASE_ADDR 0x00000078 228#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 229#define TG3PCI_REG_DATA 0x00000080 230#define TG3PCI_MEM_WIN_DATA 0x00000084 231#define TG3PCI_MODE_CTRL 0x00000088 232#define TG3PCI_MISC_CFG 0x0000008c 233#define TG3PCI_MISC_LOCAL_CTRL 0x00000090 234/* 0x94 --> 0x98 unused */ 235#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 236#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 237#define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */ 238/* 0xb0 --> 0xb8 unused */ 239#define TG3PCI_DUAL_MAC_CTRL 0x000000b8 240#define DUAL_MAC_CTRL_CH_MASK 0x00000003 241#define DUAL_MAC_CTRL_ID 0x00000004 242/* 0xbc --> 0x100 unused */ 243 244/* 0x100 --> 0x200 unused */ 245 246/* Mailbox registers */ 247#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 248#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 249#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 250#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 251#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 252#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 253#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 254#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 255#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 256#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 257#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 258#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 259#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 260#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 261#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 262#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 263#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 264#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 265#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 266#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 267#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 268#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 269#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 270#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 271#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 272#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 273#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 274#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 275#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 276#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 277#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 278#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 279#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 280#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 281#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 282#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 283#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 284#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 285#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 286#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 287#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 288#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 289#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 290#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 291#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 292#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 293#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 294#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 295#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 296#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 297#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 298#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 299#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 300#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 301#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 302#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 303#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 304#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 305#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 306#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 307#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 308#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 309#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 310#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 311 312/* MAC control registers */ 313#define MAC_MODE 0x00000400 314#define MAC_MODE_RESET 0x00000001 315#define MAC_MODE_HALF_DUPLEX 0x00000002 316#define MAC_MODE_PORT_MODE_MASK 0x0000000c 317#define MAC_MODE_PORT_MODE_TBI 0x0000000c 318#define MAC_MODE_PORT_MODE_GMII 0x00000008 319#define MAC_MODE_PORT_MODE_MII 0x00000004 320#define MAC_MODE_PORT_MODE_NONE 0x00000000 321#define MAC_MODE_PORT_INT_LPBACK 0x00000010 322#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 323#define MAC_MODE_TX_BURSTING 0x00000100 324#define MAC_MODE_MAX_DEFER 0x00000200 325#define MAC_MODE_LINK_POLARITY 0x00000400 326#define MAC_MODE_RXSTAT_ENABLE 0x00000800 327#define MAC_MODE_RXSTAT_CLEAR 0x00001000 328#define MAC_MODE_RXSTAT_FLUSH 0x00002000 329#define MAC_MODE_TXSTAT_ENABLE 0x00004000 330#define MAC_MODE_TXSTAT_CLEAR 0x00008000 331#define MAC_MODE_TXSTAT_FLUSH 0x00010000 332#define MAC_MODE_SEND_CONFIGS 0x00020000 333#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 334#define MAC_MODE_ACPI_ENABLE 0x00080000 335#define MAC_MODE_MIP_ENABLE 0x00100000 336#define MAC_MODE_TDE_ENABLE 0x00200000 337#define MAC_MODE_RDE_ENABLE 0x00400000 338#define MAC_MODE_FHDE_ENABLE 0x00800000 339#define MAC_STATUS 0x00000404 340#define MAC_STATUS_PCS_SYNCED 0x00000001 341#define MAC_STATUS_SIGNAL_DET 0x00000002 342#define MAC_STATUS_RCVD_CFG 0x00000004 343#define MAC_STATUS_CFG_CHANGED 0x00000008 344#define MAC_STATUS_SYNC_CHANGED 0x00000010 345#define MAC_STATUS_PORT_DEC_ERR 0x00000400 346#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 347#define MAC_STATUS_MI_COMPLETION 0x00400000 348#define MAC_STATUS_MI_INTERRUPT 0x00800000 349#define MAC_STATUS_AP_ERROR 0x01000000 350#define MAC_STATUS_ODI_ERROR 0x02000000 351#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 352#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 353#define MAC_EVENT 0x00000408 354#define MAC_EVENT_PORT_DECODE_ERR 0x00000400 355#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 356#define MAC_EVENT_MI_COMPLETION 0x00400000 357#define MAC_EVENT_MI_INTERRUPT 0x00800000 358#define MAC_EVENT_AP_ERROR 0x01000000 359#define MAC_EVENT_ODI_ERROR 0x02000000 360#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 361#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 362#define MAC_LED_CTRL 0x0000040c 363#define LED_CTRL_LNKLED_OVERRIDE 0x00000001 364#define LED_CTRL_1000MBPS_ON 0x00000002 365#define LED_CTRL_100MBPS_ON 0x00000004 366#define LED_CTRL_10MBPS_ON 0x00000008 367#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 368#define LED_CTRL_TRAFFIC_BLINK 0x00000020 369#define LED_CTRL_TRAFFIC_LED 0x00000040 370#define LED_CTRL_1000MBPS_STATUS 0x00000080 371#define LED_CTRL_100MBPS_STATUS 0x00000100 372#define LED_CTRL_10MBPS_STATUS 0x00000200 373#define LED_CTRL_TRAFFIC_STATUS 0x00000400 374#define LED_CTRL_MODE_MAC 0x00000000 375#define LED_CTRL_MODE_PHY_1 0x00000800 376#define LED_CTRL_MODE_PHY_2 0x00001000 377#define LED_CTRL_MODE_SHASTA_MAC 0x00002000 378#define LED_CTRL_MODE_SHARED 0x00004000 379#define LED_CTRL_MODE_COMBO 0x00008000 380#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 381#define LED_CTRL_BLINK_RATE_SHIFT 19 382#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 383#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 384#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 385#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 386#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 387#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 388#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 389#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 390#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 391#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 392#define MAC_ACPI_MBUF_PTR 0x00000430 393#define MAC_ACPI_LEN_OFFSET 0x00000434 394#define ACPI_LENOFF_LEN_MASK 0x0000ffff 395#define ACPI_LENOFF_LEN_SHIFT 0 396#define ACPI_LENOFF_OFF_MASK 0x0fff0000 397#define ACPI_LENOFF_OFF_SHIFT 16 398#define MAC_TX_BACKOFF_SEED 0x00000438 399#define TX_BACKOFF_SEED_MASK 0x000003ff 400#define MAC_RX_MTU_SIZE 0x0000043c 401#define RX_MTU_SIZE_MASK 0x0000ffff 402#define MAC_PCS_TEST 0x00000440 403#define PCS_TEST_PATTERN_MASK 0x000fffff 404#define PCS_TEST_PATTERN_SHIFT 0 405#define PCS_TEST_ENABLE 0x00100000 406#define MAC_TX_AUTO_NEG 0x00000444 407#define TX_AUTO_NEG_MASK 0x0000ffff 408#define TX_AUTO_NEG_SHIFT 0 409#define MAC_RX_AUTO_NEG 0x00000448 410#define RX_AUTO_NEG_MASK 0x0000ffff 411#define RX_AUTO_NEG_SHIFT 0 412#define MAC_MI_COM 0x0000044c 413#define MI_COM_CMD_MASK 0x0c000000 414#define MI_COM_CMD_WRITE 0x04000000 415#define MI_COM_CMD_READ 0x08000000 416#define MI_COM_READ_FAILED 0x10000000 417#define MI_COM_START 0x20000000 418#define MI_COM_BUSY 0x20000000 419#define MI_COM_PHY_ADDR_MASK 0x03e00000 420#define MI_COM_PHY_ADDR_SHIFT 21 421#define MI_COM_REG_ADDR_MASK 0x001f0000 422#define MI_COM_REG_ADDR_SHIFT 16 423#define MI_COM_DATA_MASK 0x0000ffff 424#define MAC_MI_STAT 0x00000450 425#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 426#define MAC_MI_MODE 0x00000454 427#define MAC_MI_MODE_CLK_10MHZ 0x00000001 428#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 429#define MAC_MI_MODE_AUTO_POLL 0x00000010 430#define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000 431#define MAC_MI_MODE_BASE 0x000c0000 432#define MAC_AUTO_POLL_STATUS 0x00000458 433#define MAC_AUTO_POLL_ERROR 0x00000001 434#define MAC_TX_MODE 0x0000045c 435#define TX_MODE_RESET 0x00000001 436#define TX_MODE_ENABLE 0x00000002 437#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 438#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 439#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 440#define MAC_TX_STATUS 0x00000460 441#define TX_STATUS_XOFFED 0x00000001 442#define TX_STATUS_SENT_XOFF 0x00000002 443#define TX_STATUS_SENT_XON 0x00000004 444#define TX_STATUS_LINK_UP 0x00000008 445#define TX_STATUS_ODI_UNDERRUN 0x00000010 446#define TX_STATUS_ODI_OVERRUN 0x00000020 447#define MAC_TX_LENGTHS 0x00000464 448#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 449#define TX_LENGTHS_SLOT_TIME_SHIFT 0 450#define TX_LENGTHS_IPG_MASK 0x00000f00 451#define TX_LENGTHS_IPG_SHIFT 8 452#define TX_LENGTHS_IPG_CRS_MASK 0x00003000 453#define TX_LENGTHS_IPG_CRS_SHIFT 12 454#define MAC_RX_MODE 0x00000468 455#define RX_MODE_RESET 0x00000001 456#define RX_MODE_ENABLE 0x00000002 457#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 458#define RX_MODE_KEEP_MAC_CTRL 0x00000008 459#define RX_MODE_KEEP_PAUSE 0x00000010 460#define RX_MODE_ACCEPT_OVERSIZED 0x00000020 461#define RX_MODE_ACCEPT_RUNTS 0x00000040 462#define RX_MODE_LEN_CHECK 0x00000080 463#define RX_MODE_PROMISC 0x00000100 464#define RX_MODE_NO_CRC_CHECK 0x00000200 465#define RX_MODE_KEEP_VLAN_TAG 0x00000400 466#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 467#define MAC_RX_STATUS 0x0000046c 468#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 469#define RX_STATUS_XOFF_RCVD 0x00000002 470#define RX_STATUS_XON_RCVD 0x00000004 471#define MAC_HASH_REG_0 0x00000470 472#define MAC_HASH_REG_1 0x00000474 473#define MAC_HASH_REG_2 0x00000478 474#define MAC_HASH_REG_3 0x0000047c 475#define MAC_RCV_RULE_0 0x00000480 476#define MAC_RCV_VALUE_0 0x00000484 477#define MAC_RCV_RULE_1 0x00000488 478#define MAC_RCV_VALUE_1 0x0000048c 479#define MAC_RCV_RULE_2 0x00000490 480#define MAC_RCV_VALUE_2 0x00000494 481#define MAC_RCV_RULE_3 0x00000498 482#define MAC_RCV_VALUE_3 0x0000049c 483#define MAC_RCV_RULE_4 0x000004a0 484#define MAC_RCV_VALUE_4 0x000004a4 485#define MAC_RCV_RULE_5 0x000004a8 486#define MAC_RCV_VALUE_5 0x000004ac 487#define MAC_RCV_RULE_6 0x000004b0 488#define MAC_RCV_VALUE_6 0x000004b4 489#define MAC_RCV_RULE_7 0x000004b8 490#define MAC_RCV_VALUE_7 0x000004bc 491#define MAC_RCV_RULE_8 0x000004c0 492#define MAC_RCV_VALUE_8 0x000004c4 493#define MAC_RCV_RULE_9 0x000004c8 494#define MAC_RCV_VALUE_9 0x000004cc 495#define MAC_RCV_RULE_10 0x000004d0 496#define MAC_RCV_VALUE_10 0x000004d4 497#define MAC_RCV_RULE_11 0x000004d8 498#define MAC_RCV_VALUE_11 0x000004dc 499#define MAC_RCV_RULE_12 0x000004e0 500#define MAC_RCV_VALUE_12 0x000004e4 501#define MAC_RCV_RULE_13 0x000004e8 502#define MAC_RCV_VALUE_13 0x000004ec 503#define MAC_RCV_RULE_14 0x000004f0 504#define MAC_RCV_VALUE_14 0x000004f4 505#define MAC_RCV_RULE_15 0x000004f8 506#define MAC_RCV_VALUE_15 0x000004fc 507#define RCV_RULE_DISABLE_MASK 0x7fffffff 508#define MAC_RCV_RULE_CFG 0x00000500 509#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 510#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 511/* 0x508 --> 0x520 unused */ 512#define MAC_HASHREGU_0 0x00000520 513#define MAC_HASHREGU_1 0x00000524 514#define MAC_HASHREGU_2 0x00000528 515#define MAC_HASHREGU_3 0x0000052c 516#define MAC_EXTADDR_0_HIGH 0x00000530 517#define MAC_EXTADDR_0_LOW 0x00000534 518#define MAC_EXTADDR_1_HIGH 0x00000538 519#define MAC_EXTADDR_1_LOW 0x0000053c 520#define MAC_EXTADDR_2_HIGH 0x00000540 521#define MAC_EXTADDR_2_LOW 0x00000544 522#define MAC_EXTADDR_3_HIGH 0x00000548 523#define MAC_EXTADDR_3_LOW 0x0000054c 524#define MAC_EXTADDR_4_HIGH 0x00000550 525#define MAC_EXTADDR_4_LOW 0x00000554 526#define MAC_EXTADDR_5_HIGH 0x00000558 527#define MAC_EXTADDR_5_LOW 0x0000055c 528#define MAC_EXTADDR_6_HIGH 0x00000560 529#define MAC_EXTADDR_6_LOW 0x00000564 530#define MAC_EXTADDR_7_HIGH 0x00000568 531#define MAC_EXTADDR_7_LOW 0x0000056c 532#define MAC_EXTADDR_8_HIGH 0x00000570 533#define MAC_EXTADDR_8_LOW 0x00000574 534#define MAC_EXTADDR_9_HIGH 0x00000578 535#define MAC_EXTADDR_9_LOW 0x0000057c 536#define MAC_EXTADDR_10_HIGH 0x00000580 537#define MAC_EXTADDR_10_LOW 0x00000584 538#define MAC_EXTADDR_11_HIGH 0x00000588 539#define MAC_EXTADDR_11_LOW 0x0000058c 540#define MAC_SERDES_CFG 0x00000590 541#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 542#define MAC_SERDES_STAT 0x00000594 543/* 0x598 --> 0x5b0 unused */ 544#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 545#define SERDES_RX_SIG_DETECT 0x00000400 546#define SG_DIG_CTRL 0x000005b0 547#define SG_DIG_USING_HW_AUTONEG 0x80000000 548#define SG_DIG_SOFT_RESET 0x40000000 549#define SG_DIG_DISABLE_LINKRDY 0x20000000 550#define SG_DIG_CRC16_CLEAR_N 0x01000000 551#define SG_DIG_EN10B 0x00800000 552#define SG_DIG_CLEAR_STATUS 0x00400000 553#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 554#define SG_DIG_LOCAL_LINK_STATUS 0x00100000 555#define SG_DIG_SPEED_STATUS_MASK 0x000c0000 556#define SG_DIG_SPEED_STATUS_SHIFT 18 557#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 558#define SG_DIG_RESTART_AUTONEG 0x00010000 559#define SG_DIG_FIBER_MODE 0x00008000 560#define SG_DIG_REMOTE_FAULT_MASK 0x00006000 561#define SG_DIG_PAUSE_MASK 0x00001800 562#define SG_DIG_GBIC_ENABLE 0x00000400 563#define SG_DIG_CHECK_END_ENABLE 0x00000200 564#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 565#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 566#define SG_DIG_GMII_INPUT_SELECT 0x00000040 567#define SG_DIG_MRADV_CRC16_SELECT 0x00000020 568#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 569#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 570#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 571#define SG_DIG_REMOTE_LOOPBACK 0x00000002 572#define SG_DIG_LOOPBACK 0x00000001 573#define SG_DIG_STATUS 0x000005b4 574#define SG_DIG_CRC16_BUS_MASK 0xffff0000 575#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ 576#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ 577#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ 578#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ 579#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ 580#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ 581#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 582#define SG_DIG_COMMA_DETECTOR 0x00000008 583#define SG_DIG_MAC_ACK_STATUS 0x00000004 584#define SG_DIG_AUTONEG_COMPLETE 0x00000002 585#define SG_DIG_AUTONEG_ERROR 0x00000001 586/* 0x5b8 --> 0x600 unused */ 587#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 588#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 589/* 0x624 --> 0x800 unused */ 590#define MAC_TX_STATS_OCTETS 0x00000800 591#define MAC_TX_STATS_RESV1 0x00000804 592#define MAC_TX_STATS_COLLISIONS 0x00000808 593#define MAC_TX_STATS_XON_SENT 0x0000080c 594#define MAC_TX_STATS_XOFF_SENT 0x00000810 595#define MAC_TX_STATS_RESV2 0x00000814 596#define MAC_TX_STATS_MAC_ERRORS 0x00000818 597#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 598#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 599#define MAC_TX_STATS_DEFERRED 0x00000824 600#define MAC_TX_STATS_RESV3 0x00000828 601#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 602#define MAC_TX_STATS_LATE_COL 0x00000830 603#define MAC_TX_STATS_RESV4_1 0x00000834 604#define MAC_TX_STATS_RESV4_2 0x00000838 605#define MAC_TX_STATS_RESV4_3 0x0000083c 606#define MAC_TX_STATS_RESV4_4 0x00000840 607#define MAC_TX_STATS_RESV4_5 0x00000844 608#define MAC_TX_STATS_RESV4_6 0x00000848 609#define MAC_TX_STATS_RESV4_7 0x0000084c 610#define MAC_TX_STATS_RESV4_8 0x00000850 611#define MAC_TX_STATS_RESV4_9 0x00000854 612#define MAC_TX_STATS_RESV4_10 0x00000858 613#define MAC_TX_STATS_RESV4_11 0x0000085c 614#define MAC_TX_STATS_RESV4_12 0x00000860 615#define MAC_TX_STATS_RESV4_13 0x00000864 616#define MAC_TX_STATS_RESV4_14 0x00000868 617#define MAC_TX_STATS_UCAST 0x0000086c 618#define MAC_TX_STATS_MCAST 0x00000870 619#define MAC_TX_STATS_BCAST 0x00000874 620#define MAC_TX_STATS_RESV5_1 0x00000878 621#define MAC_TX_STATS_RESV5_2 0x0000087c 622#define MAC_RX_STATS_OCTETS 0x00000880 623#define MAC_RX_STATS_RESV1 0x00000884 624#define MAC_RX_STATS_FRAGMENTS 0x00000888 625#define MAC_RX_STATS_UCAST 0x0000088c 626#define MAC_RX_STATS_MCAST 0x00000890 627#define MAC_RX_STATS_BCAST 0x00000894 628#define MAC_RX_STATS_FCS_ERRORS 0x00000898 629#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 630#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 631#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 632#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 633#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 634#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 635#define MAC_RX_STATS_JABBERS 0x000008b4 636#define MAC_RX_STATS_UNDERSIZE 0x000008b8 637/* 0x8bc --> 0xc00 unused */ 638 639/* Send data initiator control registers */ 640#define SNDDATAI_MODE 0x00000c00 641#define SNDDATAI_MODE_RESET 0x00000001 642#define SNDDATAI_MODE_ENABLE 0x00000002 643#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 644#define SNDDATAI_STATUS 0x00000c04 645#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 646#define SNDDATAI_STATSCTRL 0x00000c08 647#define SNDDATAI_SCTRL_ENABLE 0x00000001 648#define SNDDATAI_SCTRL_FASTUPD 0x00000002 649#define SNDDATAI_SCTRL_CLEAR 0x00000004 650#define SNDDATAI_SCTRL_FLUSH 0x00000008 651#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 652#define SNDDATAI_STATSENAB 0x00000c0c 653#define SNDDATAI_STATSINCMASK 0x00000c10 654#define ISO_PKT_TX 0x00000c20 655/* 0xc24 --> 0xc80 unused */ 656#define SNDDATAI_COS_CNT_0 0x00000c80 657#define SNDDATAI_COS_CNT_1 0x00000c84 658#define SNDDATAI_COS_CNT_2 0x00000c88 659#define SNDDATAI_COS_CNT_3 0x00000c8c 660#define SNDDATAI_COS_CNT_4 0x00000c90 661#define SNDDATAI_COS_CNT_5 0x00000c94 662#define SNDDATAI_COS_CNT_6 0x00000c98 663#define SNDDATAI_COS_CNT_7 0x00000c9c 664#define SNDDATAI_COS_CNT_8 0x00000ca0 665#define SNDDATAI_COS_CNT_9 0x00000ca4 666#define SNDDATAI_COS_CNT_10 0x00000ca8 667#define SNDDATAI_COS_CNT_11 0x00000cac 668#define SNDDATAI_COS_CNT_12 0x00000cb0 669#define SNDDATAI_COS_CNT_13 0x00000cb4 670#define SNDDATAI_COS_CNT_14 0x00000cb8 671#define SNDDATAI_COS_CNT_15 0x00000cbc 672#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 673#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 674#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 675#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 676#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 677#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 678#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 679#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 680/* 0xce0 --> 0x1000 unused */ 681 682/* Send data completion control registers */ 683#define SNDDATAC_MODE 0x00001000 684#define SNDDATAC_MODE_RESET 0x00000001 685#define SNDDATAC_MODE_ENABLE 0x00000002 686/* 0x1004 --> 0x1400 unused */ 687 688/* Send BD ring selector */ 689#define SNDBDS_MODE 0x00001400 690#define SNDBDS_MODE_RESET 0x00000001 691#define SNDBDS_MODE_ENABLE 0x00000002 692#define SNDBDS_MODE_ATTN_ENABLE 0x00000004 693#define SNDBDS_STATUS 0x00001404 694#define SNDBDS_STATUS_ERROR_ATTN 0x00000004 695#define SNDBDS_HWDIAG 0x00001408 696/* 0x140c --> 0x1440 */ 697#define SNDBDS_SEL_CON_IDX_0 0x00001440 698#define SNDBDS_SEL_CON_IDX_1 0x00001444 699#define SNDBDS_SEL_CON_IDX_2 0x00001448 700#define SNDBDS_SEL_CON_IDX_3 0x0000144c 701#define SNDBDS_SEL_CON_IDX_4 0x00001450 702#define SNDBDS_SEL_CON_IDX_5 0x00001454 703#define SNDBDS_SEL_CON_IDX_6 0x00001458 704#define SNDBDS_SEL_CON_IDX_7 0x0000145c 705#define SNDBDS_SEL_CON_IDX_8 0x00001460 706#define SNDBDS_SEL_CON_IDX_9 0x00001464 707#define SNDBDS_SEL_CON_IDX_10 0x00001468 708#define SNDBDS_SEL_CON_IDX_11 0x0000146c 709#define SNDBDS_SEL_CON_IDX_12 0x00001470 710#define SNDBDS_SEL_CON_IDX_13 0x00001474 711#define SNDBDS_SEL_CON_IDX_14 0x00001478 712#define SNDBDS_SEL_CON_IDX_15 0x0000147c 713/* 0x1480 --> 0x1800 unused */ 714 715/* Send BD initiator control registers */ 716#define SNDBDI_MODE 0x00001800 717#define SNDBDI_MODE_RESET 0x00000001 718#define SNDBDI_MODE_ENABLE 0x00000002 719#define SNDBDI_MODE_ATTN_ENABLE 0x00000004 720#define SNDBDI_STATUS 0x00001804 721#define SNDBDI_STATUS_ERROR_ATTN 0x00000004 722#define SNDBDI_IN_PROD_IDX_0 0x00001808 723#define SNDBDI_IN_PROD_IDX_1 0x0000180c 724#define SNDBDI_IN_PROD_IDX_2 0x00001810 725#define SNDBDI_IN_PROD_IDX_3 0x00001814 726#define SNDBDI_IN_PROD_IDX_4 0x00001818 727#define SNDBDI_IN_PROD_IDX_5 0x0000181c 728#define SNDBDI_IN_PROD_IDX_6 0x00001820 729#define SNDBDI_IN_PROD_IDX_7 0x00001824 730#define SNDBDI_IN_PROD_IDX_8 0x00001828 731#define SNDBDI_IN_PROD_IDX_9 0x0000182c 732#define SNDBDI_IN_PROD_IDX_10 0x00001830 733#define SNDBDI_IN_PROD_IDX_11 0x00001834 734#define SNDBDI_IN_PROD_IDX_12 0x00001838 735#define SNDBDI_IN_PROD_IDX_13 0x0000183c 736#define SNDBDI_IN_PROD_IDX_14 0x00001840 737#define SNDBDI_IN_PROD_IDX_15 0x00001844 738/* 0x1848 --> 0x1c00 unused */ 739 740/* Send BD completion control registers */ 741#define SNDBDC_MODE 0x00001c00 742#define SNDBDC_MODE_RESET 0x00000001 743#define SNDBDC_MODE_ENABLE 0x00000002 744#define SNDBDC_MODE_ATTN_ENABLE 0x00000004 745/* 0x1c04 --> 0x2000 unused */ 746 747/* Receive list placement control registers */ 748#define RCVLPC_MODE 0x00002000 749#define RCVLPC_MODE_RESET 0x00000001 750#define RCVLPC_MODE_ENABLE 0x00000002 751#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 752#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 753#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 754#define RCVLPC_STATUS 0x00002004 755#define RCVLPC_STATUS_CLASS0 0x00000004 756#define RCVLPC_STATUS_MAPOOR 0x00000008 757#define RCVLPC_STATUS_STAT_OFLOW 0x00000010 758#define RCVLPC_LOCK 0x00002008 759#define RCVLPC_LOCK_REQ_MASK 0x0000ffff 760#define RCVLPC_LOCK_REQ_SHIFT 0 761#define RCVLPC_LOCK_GRANT_MASK 0xffff0000 762#define RCVLPC_LOCK_GRANT_SHIFT 16 763#define RCVLPC_NON_EMPTY_BITS 0x0000200c 764#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 765#define RCVLPC_CONFIG 0x00002010 766#define RCVLPC_STATSCTRL 0x00002014 767#define RCVLPC_STATSCTRL_ENABLE 0x00000001 768#define RCVLPC_STATSCTRL_FASTUPD 0x00000002 769#define RCVLPC_STATS_ENABLE 0x00002018 770#define RCVLPC_STATSENAB_DACK_FIX 0x00040000 771#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 772#define RCVLPC_STATS_INCMASK 0x0000201c 773/* 0x2020 --> 0x2100 unused */ 774#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 775#define SELLST_TAIL 0x00000004 776#define SELLST_CONT 0x00000008 777#define SELLST_UNUSED 0x0000000c 778#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 779#define RCVLPC_DROP_FILTER_CNT 0x00002240 780#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 781#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 782#define RCVLPC_NO_RCV_BD_CNT 0x0000224c 783#define RCVLPC_IN_DISCARDS_CNT 0x00002250 784#define RCVLPC_IN_ERRORS_CNT 0x00002254 785#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 786/* 0x225c --> 0x2400 unused */ 787 788/* Receive Data and Receive BD Initiator Control */ 789#define RCVDBDI_MODE 0x00002400 790#define RCVDBDI_MODE_RESET 0x00000001 791#define RCVDBDI_MODE_ENABLE 0x00000002 792#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 793#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 794#define RCVDBDI_MODE_INV_RING_SZ 0x00000010 795#define RCVDBDI_STATUS 0x00002404 796#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 797#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 798#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 799#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 800/* 0x240c --> 0x2440 unused */ 801#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 802#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 803#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 804#define RCVDBDI_JUMBO_CON_IDX 0x00002470 805#define RCVDBDI_STD_CON_IDX 0x00002474 806#define RCVDBDI_MINI_CON_IDX 0x00002478 807/* 0x247c --> 0x2480 unused */ 808#define RCVDBDI_BD_PROD_IDX_0 0x00002480 809#define RCVDBDI_BD_PROD_IDX_1 0x00002484 810#define RCVDBDI_BD_PROD_IDX_2 0x00002488 811#define RCVDBDI_BD_PROD_IDX_3 0x0000248c 812#define RCVDBDI_BD_PROD_IDX_4 0x00002490 813#define RCVDBDI_BD_PROD_IDX_5 0x00002494 814#define RCVDBDI_BD_PROD_IDX_6 0x00002498 815#define RCVDBDI_BD_PROD_IDX_7 0x0000249c 816#define RCVDBDI_BD_PROD_IDX_8 0x000024a0 817#define RCVDBDI_BD_PROD_IDX_9 0x000024a4 818#define RCVDBDI_BD_PROD_IDX_10 0x000024a8 819#define RCVDBDI_BD_PROD_IDX_11 0x000024ac 820#define RCVDBDI_BD_PROD_IDX_12 0x000024b0 821#define RCVDBDI_BD_PROD_IDX_13 0x000024b4 822#define RCVDBDI_BD_PROD_IDX_14 0x000024b8 823#define RCVDBDI_BD_PROD_IDX_15 0x000024bc 824#define RCVDBDI_HWDIAG 0x000024c0 825/* 0x24c4 --> 0x2800 unused */ 826 827/* Receive Data Completion Control */ 828#define RCVDCC_MODE 0x00002800 829#define RCVDCC_MODE_RESET 0x00000001 830#define RCVDCC_MODE_ENABLE 0x00000002 831#define RCVDCC_MODE_ATTN_ENABLE 0x00000004 832/* 0x2804 --> 0x2c00 unused */ 833 834/* Receive BD Initiator Control Registers */ 835#define RCVBDI_MODE 0x00002c00 836#define RCVBDI_MODE_RESET 0x00000001 837#define RCVBDI_MODE_ENABLE 0x00000002 838#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 839#define RCVBDI_STATUS 0x00002c04 840#define RCVBDI_STATUS_RCB_ATTN 0x00000004 841#define RCVBDI_JUMBO_PROD_IDX 0x00002c08 842#define RCVBDI_STD_PROD_IDX 0x00002c0c 843#define RCVBDI_MINI_PROD_IDX 0x00002c10 844#define RCVBDI_MINI_THRESH 0x00002c14 845#define RCVBDI_STD_THRESH 0x00002c18 846#define RCVBDI_JUMBO_THRESH 0x00002c1c 847/* 0x2c20 --> 0x3000 unused */ 848 849/* Receive BD Completion Control Registers */ 850#define RCVCC_MODE 0x00003000 851#define RCVCC_MODE_RESET 0x00000001 852#define RCVCC_MODE_ENABLE 0x00000002 853#define RCVCC_MODE_ATTN_ENABLE 0x00000004 854#define RCVCC_STATUS 0x00003004 855#define RCVCC_STATUS_ERROR_ATTN 0x00000004 856#define RCVCC_JUMP_PROD_IDX 0x00003008 857#define RCVCC_STD_PROD_IDX 0x0000300c 858#define RCVCC_MINI_PROD_IDX 0x00003010 859/* 0x3014 --> 0x3400 unused */ 860 861/* Receive list selector control registers */ 862#define RCVLSC_MODE 0x00003400 863#define RCVLSC_MODE_RESET 0x00000001 864#define RCVLSC_MODE_ENABLE 0x00000002 865#define RCVLSC_MODE_ATTN_ENABLE 0x00000004 866#define RCVLSC_STATUS 0x00003404 867#define RCVLSC_STATUS_ERROR_ATTN 0x00000004 868/* 0x3408 --> 0x3800 unused */ 869 870/* Mbuf cluster free registers */ 871#define MBFREE_MODE 0x00003800 872#define MBFREE_MODE_RESET 0x00000001 873#define MBFREE_MODE_ENABLE 0x00000002 874#define MBFREE_STATUS 0x00003804 875/* 0x3808 --> 0x3c00 unused */ 876 877/* Host coalescing control registers */ 878#define HOSTCC_MODE 0x00003c00 879#define HOSTCC_MODE_RESET 0x00000001 880#define HOSTCC_MODE_ENABLE 0x00000002 881#define HOSTCC_MODE_ATTN 0x00000004 882#define HOSTCC_MODE_NOW 0x00000008 883#define HOSTCC_MODE_FULL_STATUS 0x00000000 884#define HOSTCC_MODE_64BYTE 0x00000080 885#define HOSTCC_MODE_32BYTE 0x00000100 886#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 887#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 888#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 889#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 890#define HOSTCC_STATUS 0x00003c04 891#define HOSTCC_STATUS_ERROR_ATTN 0x00000004 892#define HOSTCC_RXCOL_TICKS 0x00003c08 893#define LOW_RXCOL_TICKS 0x00000032 894#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 895#define DEFAULT_RXCOL_TICKS 0x00000048 896#define HIGH_RXCOL_TICKS 0x00000096 897#define MAX_RXCOL_TICKS 0x000003ff 898#define HOSTCC_TXCOL_TICKS 0x00003c0c 899#define LOW_TXCOL_TICKS 0x00000096 900#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 901#define DEFAULT_TXCOL_TICKS 0x0000012c 902#define HIGH_TXCOL_TICKS 0x00000145 903#define MAX_TXCOL_TICKS 0x000003ff 904#define HOSTCC_RXMAX_FRAMES 0x00003c10 905#define LOW_RXMAX_FRAMES 0x00000005 906#define DEFAULT_RXMAX_FRAMES 0x00000008 907#define HIGH_RXMAX_FRAMES 0x00000012 908#define MAX_RXMAX_FRAMES 0x000000ff 909#define HOSTCC_TXMAX_FRAMES 0x00003c14 910#define LOW_TXMAX_FRAMES 0x00000035 911#define DEFAULT_TXMAX_FRAMES 0x0000004b 912#define HIGH_TXMAX_FRAMES 0x00000052 913#define MAX_TXMAX_FRAMES 0x000000ff 914#define HOSTCC_RXCOAL_TICK_INT 0x00003c18 915#define DEFAULT_RXCOAL_TICK_INT 0x00000019 916#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 917#define MAX_RXCOAL_TICK_INT 0x000003ff 918#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 919#define DEFAULT_TXCOAL_TICK_INT 0x00000019 920#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 921#define MAX_TXCOAL_TICK_INT 0x000003ff 922#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 923#define DEFAULT_RXCOAL_MAXF_INT 0x00000005 924#define MAX_RXCOAL_MAXF_INT 0x000000ff 925#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 926#define DEFAULT_TXCOAL_MAXF_INT 0x00000005 927#define MAX_TXCOAL_MAXF_INT 0x000000ff 928#define HOSTCC_STAT_COAL_TICKS 0x00003c28 929#define DEFAULT_STAT_COAL_TICKS 0x000f4240 930#define MAX_STAT_COAL_TICKS 0xd693d400 931#define MIN_STAT_COAL_TICKS 0x00000064 932/* 0x3c2c --> 0x3c30 unused */ 933#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 934#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 935#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 936#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 937#define HOSTCC_FLOW_ATTN 0x00003c48 938/* 0x3c4c --> 0x3c50 unused */ 939#define HOSTCC_JUMBO_CON_IDX 0x00003c50 940#define HOSTCC_STD_CON_IDX 0x00003c54 941#define HOSTCC_MINI_CON_IDX 0x00003c58 942/* 0x3c5c --> 0x3c80 unused */ 943#define HOSTCC_RET_PROD_IDX_0 0x00003c80 944#define HOSTCC_RET_PROD_IDX_1 0x00003c84 945#define HOSTCC_RET_PROD_IDX_2 0x00003c88 946#define HOSTCC_RET_PROD_IDX_3 0x00003c8c 947#define HOSTCC_RET_PROD_IDX_4 0x00003c90 948#define HOSTCC_RET_PROD_IDX_5 0x00003c94 949#define HOSTCC_RET_PROD_IDX_6 0x00003c98 950#define HOSTCC_RET_PROD_IDX_7 0x00003c9c 951#define HOSTCC_RET_PROD_IDX_8 0x00003ca0 952#define HOSTCC_RET_PROD_IDX_9 0x00003ca4 953#define HOSTCC_RET_PROD_IDX_10 0x00003ca8 954#define HOSTCC_RET_PROD_IDX_11 0x00003cac 955#define HOSTCC_RET_PROD_IDX_12 0x00003cb0 956#define HOSTCC_RET_PROD_IDX_13 0x00003cb4 957#define HOSTCC_RET_PROD_IDX_14 0x00003cb8 958#define HOSTCC_RET_PROD_IDX_15 0x00003cbc 959#define HOSTCC_SND_CON_IDX_0 0x00003cc0 960#define HOSTCC_SND_CON_IDX_1 0x00003cc4 961#define HOSTCC_SND_CON_IDX_2 0x00003cc8 962#define HOSTCC_SND_CON_IDX_3 0x00003ccc 963#define HOSTCC_SND_CON_IDX_4 0x00003cd0 964#define HOSTCC_SND_CON_IDX_5 0x00003cd4 965#define HOSTCC_SND_CON_IDX_6 0x00003cd8 966#define HOSTCC_SND_CON_IDX_7 0x00003cdc 967#define HOSTCC_SND_CON_IDX_8 0x00003ce0 968#define HOSTCC_SND_CON_IDX_9 0x00003ce4 969#define HOSTCC_SND_CON_IDX_10 0x00003ce8 970#define HOSTCC_SND_CON_IDX_11 0x00003cec 971#define HOSTCC_SND_CON_IDX_12 0x00003cf0 972#define HOSTCC_SND_CON_IDX_13 0x00003cf4 973#define HOSTCC_SND_CON_IDX_14 0x00003cf8 974#define HOSTCC_SND_CON_IDX_15 0x00003cfc 975/* 0x3d00 --> 0x4000 unused */ 976 977/* Memory arbiter control registers */ 978#define MEMARB_MODE 0x00004000 979#define MEMARB_MODE_RESET 0x00000001 980#define MEMARB_MODE_ENABLE 0x00000002 981#define MEMARB_STATUS 0x00004004 982#define MEMARB_TRAP_ADDR_LOW 0x00004008 983#define MEMARB_TRAP_ADDR_HIGH 0x0000400c 984/* 0x4010 --> 0x4400 unused */ 985 986/* Buffer manager control registers */ 987#define BUFMGR_MODE 0x00004400 988#define BUFMGR_MODE_RESET 0x00000001 989#define BUFMGR_MODE_ENABLE 0x00000002 990#define BUFMGR_MODE_ATTN_ENABLE 0x00000004 991#define BUFMGR_MODE_BM_TEST 0x00000008 992#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 993#define BUFMGR_STATUS 0x00004404 994#define BUFMGR_STATUS_ERROR 0x00000004 995#define BUFMGR_STATUS_MBLOW 0x00000010 996#define BUFMGR_MB_POOL_ADDR 0x00004408 997#define BUFMGR_MB_POOL_SIZE 0x0000440c 998#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 999#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 1000#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 1001#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 1002#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 1003#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 1004#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 1005#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 1006#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 1007#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 1008#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b 1009#define BUFMGR_MB_HIGH_WATER 0x00004418 1010#define DEFAULT_MB_HIGH_WATER 0x00000060 1011#define DEFAULT_MB_HIGH_WATER_5705 0x00000060 1012#define DEFAULT_MB_HIGH_WATER_5906 0x00000010 1013#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 1014#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 1015#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 1016#define BUFMGR_MB_ALLOC_BIT 0x10000000 1017#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1018#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 1019#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 1020#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 1021#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 1022#define BUFMGR_DMA_LOW_WATER 0x00004434 1023#define DEFAULT_DMA_LOW_WATER 0x00000005 1024#define BUFMGR_DMA_HIGH_WATER 0x00004438 1025#define DEFAULT_DMA_HIGH_WATER 0x0000000a 1026#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 1027#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 1028#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 1029#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 1030#define BUFMGR_HWDIAG_0 0x0000444c 1031#define BUFMGR_HWDIAG_1 0x00004450 1032#define BUFMGR_HWDIAG_2 0x00004454 1033/* 0x4458 --> 0x4800 unused */ 1034 1035/* Read DMA control registers */ 1036#define RDMAC_MODE 0x00004800 1037#define RDMAC_MODE_RESET 0x00000001 1038#define RDMAC_MODE_ENABLE 0x00000002 1039#define RDMAC_MODE_TGTABORT_ENAB 0x00000004 1040#define RDMAC_MODE_MSTABORT_ENAB 0x00000008 1041#define RDMAC_MODE_PARITYERR_ENAB 0x00000010 1042#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1043#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1044#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 1045#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1046#define RDMAC_MODE_LNGREAD_ENAB 0x00000200 1047#define RDMAC_MODE_SPLIT_ENABLE 0x00000800 1048#define RDMAC_MODE_SPLIT_RESET 0x00001000 1049#define RDMAC_MODE_FIFO_SIZE_128 0x00020000 1050#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 1051#define RDMAC_STATUS 0x00004804 1052#define RDMAC_STATUS_TGTABORT 0x00000004 1053#define RDMAC_STATUS_MSTABORT 0x00000008 1054#define RDMAC_STATUS_PARITYERR 0x00000010 1055#define RDMAC_STATUS_ADDROFLOW 0x00000020 1056#define RDMAC_STATUS_FIFOOFLOW 0x00000040 1057#define RDMAC_STATUS_FIFOURUN 0x00000080 1058#define RDMAC_STATUS_FIFOOREAD 0x00000100 1059#define RDMAC_STATUS_LNGREAD 0x00000200 1060/* 0x4808 --> 0x4c00 unused */ 1061 1062/* Write DMA control registers */ 1063#define WDMAC_MODE 0x00004c00 1064#define WDMAC_MODE_RESET 0x00000001 1065#define WDMAC_MODE_ENABLE 0x00000002 1066#define WDMAC_MODE_TGTABORT_ENAB 0x00000004 1067#define WDMAC_MODE_MSTABORT_ENAB 0x00000008 1068#define WDMAC_MODE_PARITYERR_ENAB 0x00000010 1069#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1070#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1071#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 1072#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1073#define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1074#define WDMAC_MODE_RX_ACCEL 0x00000400 1075#define WDMAC_STATUS 0x00004c04 1076#define WDMAC_STATUS_TGTABORT 0x00000004 1077#define WDMAC_STATUS_MSTABORT 0x00000008 1078#define WDMAC_STATUS_PARITYERR 0x00000010 1079#define WDMAC_STATUS_ADDROFLOW 0x00000020 1080#define WDMAC_STATUS_FIFOOFLOW 0x00000040 1081#define WDMAC_STATUS_FIFOURUN 0x00000080 1082#define WDMAC_STATUS_FIFOOREAD 0x00000100 1083#define WDMAC_STATUS_LNGREAD 0x00000200 1084/* 0x4c08 --> 0x5000 unused */ 1085 1086/* Per-cpu register offsets (arm9) */ 1087#define CPU_MODE 0x00000000 1088#define CPU_MODE_RESET 0x00000001 1089#define CPU_MODE_HALT 0x00000400 1090#define CPU_STATE 0x00000004 1091#define CPU_EVTMASK 0x00000008 1092/* 0xc --> 0x1c reserved */ 1093#define CPU_PC 0x0000001c 1094#define CPU_INSN 0x00000020 1095#define CPU_SPAD_UFLOW 0x00000024 1096#define CPU_WDOG_CLEAR 0x00000028 1097#define CPU_WDOG_VECTOR 0x0000002c 1098#define CPU_WDOG_PC 0x00000030 1099#define CPU_HW_BP 0x00000034 1100/* 0x38 --> 0x44 unused */ 1101#define CPU_WDOG_SAVED_STATE 0x00000044 1102#define CPU_LAST_BRANCH_ADDR 0x00000048 1103#define CPU_SPAD_UFLOW_SET 0x0000004c 1104/* 0x50 --> 0x200 unused */ 1105#define CPU_R0 0x00000200 1106#define CPU_R1 0x00000204 1107#define CPU_R2 0x00000208 1108#define CPU_R3 0x0000020c 1109#define CPU_R4 0x00000210 1110#define CPU_R5 0x00000214 1111#define CPU_R6 0x00000218 1112#define CPU_R7 0x0000021c 1113#define CPU_R8 0x00000220 1114#define CPU_R9 0x00000224 1115#define CPU_R10 0x00000228 1116#define CPU_R11 0x0000022c 1117#define CPU_R12 0x00000230 1118#define CPU_R13 0x00000234 1119#define CPU_R14 0x00000238 1120#define CPU_R15 0x0000023c 1121#define CPU_R16 0x00000240 1122#define CPU_R17 0x00000244 1123#define CPU_R18 0x00000248 1124#define CPU_R19 0x0000024c 1125#define CPU_R20 0x00000250 1126#define CPU_R21 0x00000254 1127#define CPU_R22 0x00000258 1128#define CPU_R23 0x0000025c 1129#define CPU_R24 0x00000260 1130#define CPU_R25 0x00000264 1131#define CPU_R26 0x00000268 1132#define CPU_R27 0x0000026c 1133#define CPU_R28 0x00000270 1134#define CPU_R29 0x00000274 1135#define CPU_R30 0x00000278 1136#define CPU_R31 0x0000027c 1137/* 0x280 --> 0x400 unused */ 1138 1139#define RX_CPU_BASE 0x00005000 1140#define RX_CPU_MODE 0x00005000 1141#define RX_CPU_STATE 0x00005004 1142#define RX_CPU_PGMCTR 0x0000501c 1143#define RX_CPU_HWBKPT 0x00005034 1144#define TX_CPU_BASE 0x00005400 1145#define TX_CPU_MODE 0x00005400 1146#define TX_CPU_STATE 0x00005404 1147#define TX_CPU_PGMCTR 0x0000541c 1148 1149#define VCPU_STATUS 0x00005100 1150#define VCPU_STATUS_INIT_DONE 0x04000000 1151#define VCPU_STATUS_DRV_RESET 0x08000000 1152 1153#define VCPU_CFGSHDW 0x00005104 1154#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 1155 1156/* Mailboxes */ 1157#define GRCMBOX_BASE 0x00005600 1158#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1159#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 1160#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 1161#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 1162#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 1163#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 1164#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 1165#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 1166#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 1167#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 1168#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 1169#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 1170#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 1171#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 1172#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 1173#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 1174#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 1175#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 1176#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 1177#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 1178#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 1179#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 1180#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 1181#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 1182#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 1183#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 1184#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 1185#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 1186#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 1187#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 1188#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 1189#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 1190#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 1191#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 1192#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 1193#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 1194#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 1195#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 1196#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 1197#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 1198#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 1199#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 1200#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 1201#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 1202#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 1203#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 1204#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 1205#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 1206#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 1207#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 1208#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 1209#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 1210#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 1211#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 1212#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 1213#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 1214#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 1215#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 1216#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 1217#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 1218#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 1219#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 1220#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 1221#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 1222#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 1223#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 1224#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 1225#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 1226/* 0x5a10 --> 0x5c00 */ 1227 1228/* Flow Through queues */ 1229#define FTQ_RESET 0x00005c00 1230/* 0x5c04 --> 0x5c10 unused */ 1231#define FTQ_DMA_NORM_READ_CTL 0x00005c10 1232#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 1233#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 1234#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 1235#define FTQ_DMA_HIGH_READ_CTL 0x00005c20 1236#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 1237#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 1238#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 1239#define FTQ_DMA_COMP_DISC_CTL 0x00005c30 1240#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 1241#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 1242#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 1243#define FTQ_SEND_BD_COMP_CTL 0x00005c40 1244#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 1245#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 1246#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 1247#define FTQ_SEND_DATA_INIT_CTL 0x00005c50 1248#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 1249#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 1250#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 1251#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 1252#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 1253#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 1254#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 1255#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 1256#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 1257#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 1258#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 1259#define FTQ_SWTYPE1_CTL 0x00005c80 1260#define FTQ_SWTYPE1_FULL_CNT 0x00005c84 1261#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 1262#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 1263#define FTQ_SEND_DATA_COMP_CTL 0x00005c90 1264#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 1265#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 1266#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 1267#define FTQ_HOST_COAL_CTL 0x00005ca0 1268#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 1269#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 1270#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 1271#define FTQ_MAC_TX_CTL 0x00005cb0 1272#define FTQ_MAC_TX_FULL_CNT 0x00005cb4 1273#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 1274#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 1275#define FTQ_MB_FREE_CTL 0x00005cc0 1276#define FTQ_MB_FREE_FULL_CNT 0x00005cc4 1277#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 1278#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 1279#define FTQ_RCVBD_COMP_CTL 0x00005cd0 1280#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 1281#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 1282#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 1283#define FTQ_RCVLST_PLMT_CTL 0x00005ce0 1284#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 1285#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 1286#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 1287#define FTQ_RCVDATA_INI_CTL 0x00005cf0 1288#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 1289#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 1290#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 1291#define FTQ_RCVDATA_COMP_CTL 0x00005d00 1292#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 1293#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 1294#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 1295#define FTQ_SWTYPE2_CTL 0x00005d10 1296#define FTQ_SWTYPE2_FULL_CNT 0x00005d14 1297#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 1298#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 1299/* 0x5d20 --> 0x6000 unused */ 1300 1301/* Message signaled interrupt registers */ 1302#define MSGINT_MODE 0x00006000 1303#define MSGINT_MODE_RESET 0x00000001 1304#define MSGINT_MODE_ENABLE 0x00000002 1305#define MSGINT_STATUS 0x00006004 1306#define MSGINT_FIFO 0x00006008 1307/* 0x600c --> 0x6400 unused */ 1308 1309/* DMA completion registers */ 1310#define DMAC_MODE 0x00006400 1311#define DMAC_MODE_RESET 0x00000001 1312#define DMAC_MODE_ENABLE 0x00000002 1313/* 0x6404 --> 0x6800 unused */ 1314 1315/* GRC registers */ 1316#define GRC_MODE 0x00006800 1317#define GRC_MODE_UPD_ON_COAL 0x00000001 1318#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 1319#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 1320#define GRC_MODE_BSWAP_DATA 0x00000010 1321#define GRC_MODE_WSWAP_DATA 0x00000020 1322#define GRC_MODE_SPLITHDR 0x00000100 1323#define GRC_MODE_NOFRM_CRACKING 0x00000200 1324#define GRC_MODE_INCL_CRC 0x00000400 1325#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 1326#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 1327#define GRC_MODE_NOIRQ_ON_RCV 0x00004000 1328#define GRC_MODE_FORCE_PCI32BIT 0x00008000 1329#define GRC_MODE_HOST_STACKUP 0x00010000 1330#define GRC_MODE_HOST_SENDBDS 0x00020000 1331#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1332#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 1333#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1334#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1335#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1336#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 1337#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1338#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1339#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1340#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1341#define GRC_MISC_CFG 0x00006804 1342#define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1343#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1344#define GRC_MISC_CFG_PRESCALAR_SHIFT 1 1345#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 1346#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 1347#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 1348#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 1349#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 1350#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 1351#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 1352#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 1353#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 1354#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1355#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1356#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1357#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 1358#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1359#define GRC_LOCAL_CTRL 0x00006808 1360#define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1361#define GRC_LCLCTRL_CLEARINT 0x00000002 1362#define GRC_LCLCTRL_SETINT 0x00000004 1363#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1364#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1365#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1366#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1367#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 1368#define GRC_LCLCTRL_GPIO_OE3 0x00000040 1369#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 1370#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1371#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1372#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1373#define GRC_LCLCTRL_GPIO_OE0 0x00000800 1374#define GRC_LCLCTRL_GPIO_OE1 0x00001000 1375#define GRC_LCLCTRL_GPIO_OE2 0x00002000 1376#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 1377#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 1378#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 1379#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 1380#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 1381#define GRC_LCLCTRL_MEMSZ_256K 0x00000000 1382#define GRC_LCLCTRL_MEMSZ_512K 0x00040000 1383#define GRC_LCLCTRL_MEMSZ_1M 0x00080000 1384#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 1385#define GRC_LCLCTRL_MEMSZ_4M 0x00100000 1386#define GRC_LCLCTRL_MEMSZ_8M 0x00140000 1387#define GRC_LCLCTRL_MEMSZ_16M 0x00180000 1388#define GRC_LCLCTRL_BANK_SELECT 0x00200000 1389#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 1390#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1391#define GRC_TIMER 0x0000680c 1392#define GRC_RX_CPU_EVENT 0x00006810 1393#define GRC_RX_TIMER_REF 0x00006814 1394#define GRC_RX_CPU_SEM 0x00006818 1395#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1396#define GRC_TX_CPU_EVENT 0x00006820 1397#define GRC_TX_TIMER_REF 0x00006824 1398#define GRC_TX_CPU_SEM 0x00006828 1399#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 1400#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 1401#define GRC_EEPROM_ADDR 0x00006838 1402#define EEPROM_ADDR_WRITE 0x00000000 1403#define EEPROM_ADDR_READ 0x80000000 1404#define EEPROM_ADDR_COMPLETE 0x40000000 1405#define EEPROM_ADDR_FSM_RESET 0x20000000 1406#define EEPROM_ADDR_DEVID_MASK 0x1c000000 1407#define EEPROM_ADDR_DEVID_SHIFT 26 1408#define EEPROM_ADDR_START 0x02000000 1409#define EEPROM_ADDR_CLKPERD_SHIFT 16 1410#define EEPROM_ADDR_ADDR_MASK 0x0000ffff 1411#define EEPROM_ADDR_ADDR_SHIFT 0 1412#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 1413#define EEPROM_CHIP_SIZE (64 * 1024) 1414#define GRC_EEPROM_DATA 0x0000683c 1415#define GRC_EEPROM_CTRL 0x00006840 1416#define GRC_MDI_CTRL 0x00006844 1417#define GRC_SEEPROM_DELAY 0x00006848 1418/* 0x684c --> 0x6890 unused */ 1419#define GRC_VCPU_EXT_CTRL 0x00006890 1420#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1421#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1422#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ 1423 1424/* 0x6c00 --> 0x7000 unused */ 1425 1426/* NVRAM Control registers */ 1427#define NVRAM_CMD 0x00007000 1428#define NVRAM_CMD_RESET 0x00000001 1429#define NVRAM_CMD_DONE 0x00000008 1430#define NVRAM_CMD_GO 0x00000010 1431#define NVRAM_CMD_WR 0x00000020 1432#define NVRAM_CMD_RD 0x00000000 1433#define NVRAM_CMD_ERASE 0x00000040 1434#define NVRAM_CMD_FIRST 0x00000080 1435#define NVRAM_CMD_LAST 0x00000100 1436#define NVRAM_CMD_WREN 0x00010000 1437#define NVRAM_CMD_WRDI 0x00020000 1438#define NVRAM_STAT 0x00007004 1439#define NVRAM_WRDATA 0x00007008 1440#define NVRAM_ADDR 0x0000700c 1441#define NVRAM_ADDR_MSK 0x00ffffff 1442#define NVRAM_RDDATA 0x00007010 1443#define NVRAM_CFG1 0x00007014 1444#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 1445#define NVRAM_CFG1_BUFFERED_MODE 0x00000002 1446#define NVRAM_CFG1_PASS_THRU 0x00000004 1447#define NVRAM_CFG1_STATUS_BITS 0x00000070 1448#define NVRAM_CFG1_BIT_BANG 0x00000008 1449#define NVRAM_CFG1_FLASH_SIZE 0x02000000 1450#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 1451#define NVRAM_CFG1_VENDOR_MASK 0x03000003 1452#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 1453#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1454#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 1455#define FLASH_VENDOR_ST 0x03000001 1456#define FLASH_VENDOR_SAIFUN 0x01000003 1457#define FLASH_VENDOR_SST_SMALL 0x00000001 1458#define FLASH_VENDOR_SST_LARGE 0x02000001 1459#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 1460#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 1461#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 1462#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1463#define FLASH_5752VENDOR_ST_M45PE10 0x02400000 1464#define FLASH_5752VENDOR_ST_M45PE20 0x02400002 1465#define FLASH_5752VENDOR_ST_M45PE40 0x02400001 1466#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 1467#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 1468#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 1469#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 1470#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 1471#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 1472#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 1473#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 1474#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 1475#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 1476#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1477#define FLASH_5752PAGE_SIZE_256 0x00000000 1478#define FLASH_5752PAGE_SIZE_512 0x10000000 1479#define FLASH_5752PAGE_SIZE_1K 0x20000000 1480#define FLASH_5752PAGE_SIZE_2K 0x30000000 1481#define FLASH_5752PAGE_SIZE_4K 0x40000000 1482#define FLASH_5752PAGE_SIZE_264 0x50000000 1483#define NVRAM_CFG2 0x00007018 1484#define NVRAM_CFG3 0x0000701c 1485#define NVRAM_SWARB 0x00007020 1486#define SWARB_REQ_SET0 0x00000001 1487#define SWARB_REQ_SET1 0x00000002 1488#define SWARB_REQ_SET2 0x00000004 1489#define SWARB_REQ_SET3 0x00000008 1490#define SWARB_REQ_CLR0 0x00000010 1491#define SWARB_REQ_CLR1 0x00000020 1492#define SWARB_REQ_CLR2 0x00000040 1493#define SWARB_REQ_CLR3 0x00000080 1494#define SWARB_GNT0 0x00000100 1495#define SWARB_GNT1 0x00000200 1496#define SWARB_GNT2 0x00000400 1497#define SWARB_GNT3 0x00000800 1498#define SWARB_REQ0 0x00001000 1499#define SWARB_REQ1 0x00002000 1500#define SWARB_REQ2 0x00004000 1501#define SWARB_REQ3 0x00008000 1502#define NVRAM_ACCESS 0x00007024 1503#define ACCESS_ENABLE 0x00000001 1504#define ACCESS_WR_ENABLE 0x00000002 1505#define NVRAM_WRITE1 0x00007028 1506/* 0x702c --> 0x7400 unused */ 1507 1508/* 0x7400 --> 0x7c00 unused */ 1509#define PCIE_TRANSACTION_CFG 0x00007c04 1510#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 1511#define PCIE_TRANS_CFG_LOM 0x00000020 1512 1513#define PCIE_PWR_MGMT_THRESH 0x00007d28 1514#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 1515 1516#define TG3_EEPROM_MAGIC 0x669955aa 1517#define TG3_EEPROM_MAGIC_FW 0xa5000000 1518#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 1519#define TG3_EEPROM_MAGIC_HW 0xabcd 1520#define TG3_EEPROM_MAGIC_HW_MSK 0xffff 1521 1522/* 32K Window into NIC internal memory */ 1523#define NIC_SRAM_WIN_BASE 0x00008000 1524 1525/* Offsets into first 32k of NIC internal memory. */ 1526#define NIC_SRAM_PAGE_ZERO 0x00000000 1527#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 1528#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 1529#define NIC_SRAM_STATS_BLK 0x00000300 1530#define NIC_SRAM_STATUS_BLK 0x00000b00 1531 1532#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 1533#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 1534#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 1535 1536#define NIC_SRAM_DATA_SIG 0x00000b54 1537#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 1538 1539#define NIC_SRAM_DATA_CFG 0x00000b58 1540#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 1541#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 1542#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 1543#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 1544#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 1545#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 1546#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 1547#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 1548#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 1549#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 1550#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 1551#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 1552#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 1553#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 1554 1555#define NIC_SRAM_DATA_VER 0x00000b5c 1556#define NIC_SRAM_DATA_VER_SHIFT 16 1557 1558#define NIC_SRAM_DATA_PHY_ID 0x00000b74 1559#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 1560#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 1561 1562#define NIC_SRAM_FW_CMD_MBOX 0x00000b78 1563#define FWCMD_NICDRV_ALIVE 0x00000001 1564#define FWCMD_NICDRV_PAUSE_FW 0x00000002 1565#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 1566#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 1567#define FWCMD_NICDRV_FIX_DMAR 0x00000005 1568#define FWCMD_NICDRV_FIX_DMAW 0x00000006 1569#define FWCMD_NICDRV_ALIVE2 0x0000000d 1570#define FWCMD_NICDRV_ALIVE3 0x0000000e 1571#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 1572#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 1573#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 1574#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 1575#define DRV_STATE_START 0x00000001 1576#define DRV_STATE_START_DONE 0x80000001 1577#define DRV_STATE_UNLOAD 0x00000002 1578#define DRV_STATE_UNLOAD_DONE 0x80000002 1579#define DRV_STATE_WOL 0x00000003 1580#define DRV_STATE_SUSPEND 0x00000004 1581 1582#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 1583 1584#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 1585#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 1586 1587#define NIC_SRAM_WOL_MBOX 0x00000d30 1588#define WOL_SIGNATURE 0x474c0000 1589#define WOL_DRV_STATE_SHUTDOWN 0x00000001 1590#define WOL_DRV_WOL 0x00000002 1591#define WOL_SET_MAGIC_PKT 0x00000004 1592 1593#define NIC_SRAM_DATA_CFG_2 0x00000d38 1594 1595#define SHASTA_EXT_LED_MODE_MASK 0x00018000 1596#define SHASTA_EXT_LED_LEGACY 0x00000000 1597#define SHASTA_EXT_LED_SHARED 0x00008000 1598#define SHASTA_EXT_LED_MAC 0x00010000 1599#define SHASTA_EXT_LED_COMBO 0x00018000 1600 1601#define NIC_SRAM_DATA_CFG_3 0x00000d3c 1602#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 1603 1604#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 1605 1606#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 1607#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 1608#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 1609#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 1610#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 1611#define NIC_SRAM_MBUF_POOL_BASE 0x00008000 1612#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 1613#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 1614#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 1615#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 1616 1617/* Currently this is fixed. */ 1618#define PHY_ADDR 0x01 1619 1620/* Tigon3 specific PHY MII registers. */ 1621#define TG3_BMCR_SPEED1000 0x0040 1622 1623#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ 1624#define MII_TG3_CTRL_ADV_1000_HALF 0x0100 1625#define MII_TG3_CTRL_ADV_1000_FULL 0x0200 1626#define MII_TG3_CTRL_AS_MASTER 0x0800 1627#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 1628 1629#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 1630#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 1631#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 1632#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 1633#define MII_TG3_EXT_CTRL_TBI 0x8000 1634 1635#define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 1636#define MII_TG3_EXT_STAT_LPASS 0x0100 1637 1638#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 1639 1640#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 1641#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */ 1642 1643#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ 1644 1645#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ 1646#define MII_TG3_AUX_STAT_LPASS 0x0004 1647#define MII_TG3_AUX_STAT_SPDMASK 0x0700 1648#define MII_TG3_AUX_STAT_10HALF 0x0100 1649#define MII_TG3_AUX_STAT_10FULL 0x0200 1650#define MII_TG3_AUX_STAT_100HALF 0x0300 1651#define MII_TG3_AUX_STAT_100_4 0x0400 1652#define MII_TG3_AUX_STAT_100FULL 0x0500 1653#define MII_TG3_AUX_STAT_1000HALF 0x0600 1654#define MII_TG3_AUX_STAT_1000FULL 0x0700 1655#define MII_TG3_AUX_STAT_100 0x0008 1656#define MII_TG3_AUX_STAT_FULL 0x0001 1657 1658#define MII_TG3_ISTAT 0x1a /* IRQ status register */ 1659#define MII_TG3_IMASK 0x1b /* IRQ mask register */ 1660 1661/* ISTAT/IMASK event bits */ 1662#define MII_TG3_INT_LINKCHG 0x0002 1663#define MII_TG3_INT_SPEEDCHG 0x0004 1664#define MII_TG3_INT_DUPLEXCHG 0x0008 1665#define MII_TG3_INT_ANEG_PAGE_RX 0x0400 1666 1667#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ 1668#define MII_TG3_EPHY_SHADOW_EN 0x80 1669 1670#define MII_TG3_TEST1 0x1e 1671#define MII_TG3_TEST1_TRIM_EN 0x0010 1672#define MII_TG3_TEST1_CRC_EN 0x8000 1673 1674/* There are two ways to manage the TX descriptors on the tigon3. 1675 * Either the descriptors are in host DMA'able memory, or they 1676 * exist only in the cards on-chip SRAM. All 16 send bds are under 1677 * the same mode, they may not be configured individually. 1678 * 1679 * This driver always uses host memory TX descriptors. 1680 * 1681 * To use host memory TX descriptors: 1682 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 1683 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 1684 * 2) Allocate DMA'able memory. 1685 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 1686 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 1687 * obtained in step 2 1688 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 1689 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 1690 * of TX descriptors. Leave flags field clear. 1691 * 4) Access TX descriptors via host memory. The chip 1692 * will refetch into local SRAM as needed when producer 1693 * index mailboxes are updated. 1694 * 1695 * To use on-chip TX descriptors: 1696 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 1697 * Make sure GRC_MODE_HOST_SENDBDS is clear. 1698 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 1699 * a) Set TG3_BDINFO_HOST_ADDR to zero. 1700 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 1701 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 1702 * 3) Access TX descriptors directly in on-chip SRAM 1703 * using normal {read,write}l(). (and not using 1704 * pointer dereferencing of ioremap()'d memory like 1705 * the broken Broadcom driver does) 1706 * 1707 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 1708 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 1709 */ 1710struct tg3_tx_buffer_desc { 1711 u32 addr_hi; 1712 u32 addr_lo; 1713 1714 u32 len_flags; 1715#define TXD_FLAG_TCPUDP_CSUM 0x0001 1716#define TXD_FLAG_IP_CSUM 0x0002 1717#define TXD_FLAG_END 0x0004 1718#define TXD_FLAG_IP_FRAG 0x0008 1719#define TXD_FLAG_IP_FRAG_END 0x0010 1720#define TXD_FLAG_VLAN 0x0040 1721#define TXD_FLAG_COAL_NOW 0x0080 1722#define TXD_FLAG_CPU_PRE_DMA 0x0100 1723#define TXD_FLAG_CPU_POST_DMA 0x0200 1724#define TXD_FLAG_ADD_SRC_ADDR 0x1000 1725#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 1726#define TXD_FLAG_NO_CRC 0x8000 1727#define TXD_LEN_SHIFT 16 1728 1729 u32 vlan_tag; 1730#define TXD_VLAN_TAG_SHIFT 0 1731#define TXD_MSS_SHIFT 16 1732}; 1733 1734#define TXD_ADDR 0x00UL /* 64-bit */ 1735#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 1736#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 1737#define TXD_SIZE 0x10UL 1738 1739struct tg3_rx_buffer_desc { 1740 u32 addr_hi; 1741 u32 addr_lo; 1742 1743 u32 idx_len; 1744#define RXD_IDX_MASK 0xffff0000 1745#define RXD_IDX_SHIFT 16 1746#define RXD_LEN_MASK 0x0000ffff 1747#define RXD_LEN_SHIFT 0 1748 1749 u32 type_flags; 1750#define RXD_TYPE_SHIFT 16 1751#define RXD_FLAGS_SHIFT 0 1752 1753#define RXD_FLAG_END 0x0004 1754#define RXD_FLAG_MINI 0x0800 1755#define RXD_FLAG_JUMBO 0x0020 1756#define RXD_FLAG_VLAN 0x0040 1757#define RXD_FLAG_ERROR 0x0400 1758#define RXD_FLAG_IP_CSUM 0x1000 1759#define RXD_FLAG_TCPUDP_CSUM 0x2000 1760#define RXD_FLAG_IS_TCP 0x4000 1761 1762 u32 ip_tcp_csum; 1763#define RXD_IPCSUM_MASK 0xffff0000 1764#define RXD_IPCSUM_SHIFT 16 1765#define RXD_TCPCSUM_MASK 0x0000ffff 1766#define RXD_TCPCSUM_SHIFT 0 1767 1768 u32 err_vlan; 1769 1770#define RXD_VLAN_MASK 0x0000ffff 1771 1772#define RXD_ERR_BAD_CRC 0x00010000 1773#define RXD_ERR_COLLISION 0x00020000 1774#define RXD_ERR_LINK_LOST 0x00040000 1775#define RXD_ERR_PHY_DECODE 0x00080000 1776#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 1777#define RXD_ERR_MAC_ABRT 0x00200000 1778#define RXD_ERR_TOO_SMALL 0x00400000 1779#define RXD_ERR_NO_RESOURCES 0x00800000 1780#define RXD_ERR_HUGE_FRAME 0x01000000 1781#define RXD_ERR_MASK 0xffff0000 1782 1783 u32 reserved; 1784 u32 opaque; 1785#define RXD_OPAQUE_INDEX_MASK 0x0000ffff 1786#define RXD_OPAQUE_INDEX_SHIFT 0 1787#define RXD_OPAQUE_RING_STD 0x00010000 1788#define RXD_OPAQUE_RING_JUMBO 0x00020000 1789#define RXD_OPAQUE_RING_MINI 0x00040000 1790#define RXD_OPAQUE_RING_MASK 0x00070000 1791}; 1792 1793struct tg3_ext_rx_buffer_desc { 1794 struct { 1795 u32 addr_hi; 1796 u32 addr_lo; 1797 } addrlist[3]; 1798 u32 len2_len1; 1799 u32 resv_len3; 1800 struct tg3_rx_buffer_desc std; 1801}; 1802 1803/* We only use this when testing out the DMA engine 1804 * at probe time. This is the internal format of buffer 1805 * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 1806 */ 1807struct tg3_internal_buffer_desc { 1808 u32 addr_hi; 1809 u32 addr_lo; 1810 u32 nic_mbuf; 1811#ifdef __BIG_ENDIAN 1812 u16 cqid_sqid; 1813 u16 len; 1814#else 1815 u16 len; 1816 u16 cqid_sqid; 1817#endif 1818 u32 flags; 1819 u32 __cookie1; 1820 u32 __cookie2; 1821 u32 __cookie3; 1822}; 1823 1824#define TG3_HW_STATUS_SIZE 0x50 1825struct tg3_hw_status { 1826 u32 status; 1827#define SD_STATUS_UPDATED 0x00000001 1828#define SD_STATUS_LINK_CHG 0x00000002 1829#define SD_STATUS_ERROR 0x00000004 1830 1831 u32 status_tag; 1832 1833#ifdef __BIG_ENDIAN 1834 u16 rx_consumer; 1835 u16 rx_jumbo_consumer; 1836#else 1837 u16 rx_jumbo_consumer; 1838 u16 rx_consumer; 1839#endif 1840 1841#ifdef __BIG_ENDIAN 1842 u16 reserved; 1843 u16 rx_mini_consumer; 1844#else 1845 u16 rx_mini_consumer; 1846 u16 reserved; 1847#endif 1848 struct { 1849#ifdef __BIG_ENDIAN 1850 u16 tx_consumer; 1851 u16 rx_producer; 1852#else 1853 u16 rx_producer; 1854 u16 tx_consumer; 1855#endif 1856 } idx[16]; 1857}; 1858 1859typedef struct { 1860 u32 high, low; 1861} tg3_stat64_t; 1862 1863struct tg3_hw_stats { 1864 u8 __reserved0[0x400-0x300]; 1865 1866 /* Statistics maintained by Receive MAC. */ 1867 tg3_stat64_t rx_octets; 1868 u64 __reserved1; 1869 tg3_stat64_t rx_fragments; 1870 tg3_stat64_t rx_ucast_packets; 1871 tg3_stat64_t rx_mcast_packets; 1872 tg3_stat64_t rx_bcast_packets; 1873 tg3_stat64_t rx_fcs_errors; 1874 tg3_stat64_t rx_align_errors; 1875 tg3_stat64_t rx_xon_pause_rcvd; 1876 tg3_stat64_t rx_xoff_pause_rcvd; 1877 tg3_stat64_t rx_mac_ctrl_rcvd; 1878 tg3_stat64_t rx_xoff_entered; 1879 tg3_stat64_t rx_frame_too_long_errors; 1880 tg3_stat64_t rx_jabbers; 1881 tg3_stat64_t rx_undersize_packets; 1882 tg3_stat64_t rx_in_length_errors; 1883 tg3_stat64_t rx_out_length_errors; 1884 tg3_stat64_t rx_64_or_less_octet_packets; 1885 tg3_stat64_t rx_65_to_127_octet_packets; 1886 tg3_stat64_t rx_128_to_255_octet_packets; 1887 tg3_stat64_t rx_256_to_511_octet_packets; 1888 tg3_stat64_t rx_512_to_1023_octet_packets; 1889 tg3_stat64_t rx_1024_to_1522_octet_packets; 1890 tg3_stat64_t rx_1523_to_2047_octet_packets; 1891 tg3_stat64_t rx_2048_to_4095_octet_packets; 1892 tg3_stat64_t rx_4096_to_8191_octet_packets; 1893 tg3_stat64_t rx_8192_to_9022_octet_packets; 1894 1895 u64 __unused0[37]; 1896 1897 /* Statistics maintained by Transmit MAC. */ 1898 tg3_stat64_t tx_octets; 1899 u64 __reserved2; 1900 tg3_stat64_t tx_collisions; 1901 tg3_stat64_t tx_xon_sent; 1902 tg3_stat64_t tx_xoff_sent; 1903 tg3_stat64_t tx_flow_control; 1904 tg3_stat64_t tx_mac_errors; 1905 tg3_stat64_t tx_single_collisions; 1906 tg3_stat64_t tx_mult_collisions; 1907 tg3_stat64_t tx_deferred; 1908 u64 __reserved3; 1909 tg3_stat64_t tx_excessive_collisions; 1910 tg3_stat64_t tx_late_collisions; 1911 tg3_stat64_t tx_collide_2times; 1912 tg3_stat64_t tx_collide_3times; 1913 tg3_stat64_t tx_collide_4times; 1914 tg3_stat64_t tx_collide_5times; 1915 tg3_stat64_t tx_collide_6times; 1916 tg3_stat64_t tx_collide_7times; 1917 tg3_stat64_t tx_collide_8times; 1918 tg3_stat64_t tx_collide_9times; 1919 tg3_stat64_t tx_collide_10times; 1920 tg3_stat64_t tx_collide_11times; 1921 tg3_stat64_t tx_collide_12times; 1922 tg3_stat64_t tx_collide_13times; 1923 tg3_stat64_t tx_collide_14times; 1924 tg3_stat64_t tx_collide_15times; 1925 tg3_stat64_t tx_ucast_packets; 1926 tg3_stat64_t tx_mcast_packets; 1927 tg3_stat64_t tx_bcast_packets; 1928 tg3_stat64_t tx_carrier_sense_errors; 1929 tg3_stat64_t tx_discards; 1930 tg3_stat64_t tx_errors; 1931 1932 u64 __unused1[31]; 1933 1934 /* Statistics maintained by Receive List Placement. */ 1935 tg3_stat64_t COS_rx_packets[16]; 1936 tg3_stat64_t COS_rx_filter_dropped; 1937 tg3_stat64_t dma_writeq_full; 1938 tg3_stat64_t dma_write_prioq_full; 1939 tg3_stat64_t rxbds_empty; 1940 tg3_stat64_t rx_discards; 1941 tg3_stat64_t rx_errors; 1942 tg3_stat64_t rx_threshold_hit; 1943 1944 u64 __unused2[9]; 1945 1946 /* Statistics maintained by Send Data Initiator. */ 1947 tg3_stat64_t COS_out_packets[16]; 1948 tg3_stat64_t dma_readq_full; 1949 tg3_stat64_t dma_read_prioq_full; 1950 tg3_stat64_t tx_comp_queue_full; 1951 1952 /* Statistics maintained by Host Coalescing. */ 1953 tg3_stat64_t ring_set_send_prod_index; 1954 tg3_stat64_t ring_status_update; 1955 tg3_stat64_t nic_irqs; 1956 tg3_stat64_t nic_avoided_irqs; 1957 tg3_stat64_t nic_tx_threshold_hit; 1958 1959 u8 __reserved4[0xb00-0x9c0]; 1960}; 1961 1962/* 'mapping' is superfluous as the chip does not write into 1963 * the tx/rx post rings so we could just fetch it from there. 1964 * But the cache behavior is better how we are doing it now. 1965 */ 1966struct ring_info { 1967 struct sk_buff *skb; 1968 DECLARE_PCI_UNMAP_ADDR(mapping) 1969}; 1970 1971struct tx_ring_info { 1972 struct sk_buff *skb; 1973 DECLARE_PCI_UNMAP_ADDR(mapping) 1974 u32 prev_vlan_tag; 1975}; 1976 1977struct tg3_config_info { 1978 u32 flags; 1979}; 1980 1981struct tg3_link_config { 1982 /* Describes what we're trying to get. */ 1983 u32 advertising; 1984 u16 speed; 1985 u8 duplex; 1986 u8 autoneg; 1987 1988 /* Describes what we actually have. */ 1989 u16 active_speed; 1990 u8 active_duplex; 1991#define SPEED_INVALID 0xffff 1992#define DUPLEX_INVALID 0xff 1993#define AUTONEG_INVALID 0xff 1994 1995 /* When we go in and out of low power mode we need 1996 * to swap with this state. 1997 */ 1998 int phy_is_low_power; 1999 u16 orig_speed; 2000 u8 orig_duplex; 2001 u8 orig_autoneg; 2002}; 2003 2004struct tg3_bufmgr_config { 2005 u32 mbuf_read_dma_low_water; 2006 u32 mbuf_mac_rx_low_water; 2007 u32 mbuf_high_water; 2008 2009 u32 mbuf_read_dma_low_water_jumbo; 2010 u32 mbuf_mac_rx_low_water_jumbo; 2011 u32 mbuf_high_water_jumbo; 2012 2013 u32 dma_low_water; 2014 u32 dma_high_water; 2015}; 2016 2017struct tg3_ethtool_stats { 2018 /* Statistics maintained by Receive MAC. */ 2019 u64 rx_octets; 2020 u64 rx_fragments; 2021 u64 rx_ucast_packets; 2022 u64 rx_mcast_packets; 2023 u64 rx_bcast_packets; 2024 u64 rx_fcs_errors; 2025 u64 rx_align_errors; 2026 u64 rx_xon_pause_rcvd; 2027 u64 rx_xoff_pause_rcvd; 2028 u64 rx_mac_ctrl_rcvd; 2029 u64 rx_xoff_entered; 2030 u64 rx_frame_too_long_errors; 2031 u64 rx_jabbers; 2032 u64 rx_undersize_packets; 2033 u64 rx_in_length_errors; 2034 u64 rx_out_length_errors; 2035 u64 rx_64_or_less_octet_packets; 2036 u64 rx_65_to_127_octet_packets; 2037 u64 rx_128_to_255_octet_packets; 2038 u64 rx_256_to_511_octet_packets; 2039 u64 rx_512_to_1023_octet_packets; 2040 u64 rx_1024_to_1522_octet_packets; 2041 u64 rx_1523_to_2047_octet_packets; 2042 u64 rx_2048_to_4095_octet_packets; 2043 u64 rx_4096_to_8191_octet_packets; 2044 u64 rx_8192_to_9022_octet_packets; 2045 2046 /* Statistics maintained by Transmit MAC. */ 2047 u64 tx_octets; 2048 u64 tx_collisions; 2049 u64 tx_xon_sent; 2050 u64 tx_xoff_sent; 2051 u64 tx_flow_control; 2052 u64 tx_mac_errors; 2053 u64 tx_single_collisions; 2054 u64 tx_mult_collisions; 2055 u64 tx_deferred; 2056 u64 tx_excessive_collisions; 2057 u64 tx_late_collisions; 2058 u64 tx_collide_2times; 2059 u64 tx_collide_3times; 2060 u64 tx_collide_4times; 2061 u64 tx_collide_5times; 2062 u64 tx_collide_6times; 2063 u64 tx_collide_7times; 2064 u64 tx_collide_8times; 2065 u64 tx_collide_9times; 2066 u64 tx_collide_10times; 2067 u64 tx_collide_11times; 2068 u64 tx_collide_12times; 2069 u64 tx_collide_13times; 2070 u64 tx_collide_14times; 2071 u64 tx_collide_15times; 2072 u64 tx_ucast_packets; 2073 u64 tx_mcast_packets; 2074 u64 tx_bcast_packets; 2075 u64 tx_carrier_sense_errors; 2076 u64 tx_discards; 2077 u64 tx_errors; 2078 2079 /* Statistics maintained by Receive List Placement. */ 2080 u64 dma_writeq_full; 2081 u64 dma_write_prioq_full; 2082 u64 rxbds_empty; 2083 u64 rx_discards; 2084 u64 rx_errors; 2085 u64 rx_threshold_hit; 2086 2087 /* Statistics maintained by Send Data Initiator. */ 2088 u64 dma_readq_full; 2089 u64 dma_read_prioq_full; 2090 u64 tx_comp_queue_full; 2091 2092 /* Statistics maintained by Host Coalescing. */ 2093 u64 ring_set_send_prod_index; 2094 u64 ring_status_update; 2095 u64 nic_irqs; 2096 u64 nic_avoided_irqs; 2097 u64 nic_tx_threshold_hit; 2098}; 2099 2100struct tg3 { 2101 /* begin "general, frequently-used members" cacheline section */ 2102 2103 /* If the IRQ handler (which runs lockless) needs to be 2104 * quiesced, the following bitmask state is used. The 2105 * SYNC flag is set by non-IRQ context code to initiate 2106 * the quiescence. 2107 * 2108 * When the IRQ handler notices that SYNC is set, it 2109 * disables interrupts and returns. 2110 * 2111 * When all outstanding IRQ handlers have returned after 2112 * the SYNC flag has been set, the setter can be assured 2113 * that interrupts will no longer get run. 2114 * 2115 * In this way all SMP driver locks are never acquired 2116 * in hw IRQ context, only sw IRQ context or lower. 2117 */ 2118 unsigned int irq_sync; 2119 2120 /* SMP locking strategy: 2121 * 2122 * lock: Held during reset, PHY access, timer, and when 2123 * updating tg3_flags and tg3_flags2. 2124 * 2125 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds 2126 * netif_tx_lock when it needs to call 2127 * netif_wake_queue. 2128 * 2129 * Both of these locks are to be held with BH safety. 2130 * 2131 * Because the IRQ handler, tg3_poll, and tg3_start_xmit 2132 * are running lockless, it is necessary to completely 2133 * quiesce the chip with tg3_netif_stop and tg3_full_lock 2134 * before reconfiguring the device. 2135 * 2136 * indirect_lock: Held when accessing registers indirectly 2137 * with IRQ disabling. 2138 */ 2139 spinlock_t lock; 2140 spinlock_t indirect_lock; 2141 2142 u32 (*read32) (struct tg3 *, u32); 2143 void (*write32) (struct tg3 *, u32, u32); 2144 u32 (*read32_mbox) (struct tg3 *, u32); 2145 void (*write32_mbox) (struct tg3 *, u32, 2146 u32); 2147 void __iomem *regs; 2148 struct net_device *dev; 2149 struct pci_dev *pdev; 2150 2151 struct tg3_hw_status *hw_status; 2152 dma_addr_t status_mapping; 2153 u32 last_tag; 2154 2155 u32 msg_enable; 2156 2157 /* begin "tx thread" cacheline section */ 2158 void (*write32_tx_mbox) (struct tg3 *, u32, 2159 u32); 2160 u32 tx_prod; 2161 u32 tx_cons; 2162 u32 tx_pending; 2163 2164 struct tg3_tx_buffer_desc *tx_ring; 2165 struct tx_ring_info *tx_buffers; 2166 dma_addr_t tx_desc_mapping; 2167 2168 /* begin "rx thread" cacheline section */ 2169 void (*write32_rx_mbox) (struct tg3 *, u32, 2170 u32); 2171 u32 rx_rcb_ptr; 2172 u32 rx_std_ptr; 2173 u32 rx_jumbo_ptr; 2174 u32 rx_pending; 2175 u32 rx_jumbo_pending; 2176#if TG3_VLAN_TAG_USED 2177 struct vlan_group *vlgrp; 2178#endif 2179 2180 struct tg3_rx_buffer_desc *rx_std; 2181 struct ring_info *rx_std_buffers; 2182 dma_addr_t rx_std_mapping; 2183 u32 rx_std_max_post; 2184 2185 struct tg3_rx_buffer_desc *rx_jumbo; 2186 struct ring_info *rx_jumbo_buffers; 2187 dma_addr_t rx_jumbo_mapping; 2188 2189 struct tg3_rx_buffer_desc *rx_rcb; 2190 dma_addr_t rx_rcb_mapping; 2191 2192 u32 rx_pkt_buf_sz; 2193 2194 /* begin "everything else" cacheline(s) section */ 2195 struct net_device_stats net_stats; 2196 struct net_device_stats net_stats_prev; 2197 struct tg3_ethtool_stats estats; 2198 struct tg3_ethtool_stats estats_prev; 2199 2200 unsigned long phy_crc_errors; 2201 2202 u32 rx_offset; 2203 u32 tg3_flags; 2204#define TG3_FLAG_TAGGED_STATUS 0x00000001 2205#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 2206#define TG3_FLAG_RX_CHECKSUMS 0x00000004 2207#define TG3_FLAG_USE_LINKCHG_REG 0x00000008 2208#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 2209#define TG3_FLAG_ENABLE_ASF 0x00000020 2210#define TG3_FLAG_ASPM_WORKAROUND 0x00000040 2211#define TG3_FLAG_POLL_SERDES 0x00000080 2212#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 2213#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 2214#define TG3_FLAG_WOL_SPEED_100MB 0x00000400 2215#define TG3_FLAG_WOL_ENABLE 0x00000800 2216#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000 2217#define TG3_FLAG_NVRAM 0x00002000 2218#define TG3_FLAG_NVRAM_BUFFERED 0x00004000 2219#define TG3_FLAG_RX_PAUSE 0x00008000 2220#define TG3_FLAG_TX_PAUSE 0x00010000 2221#define TG3_FLAG_PCIX_MODE 0x00020000 2222#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 2223#define TG3_FLAG_PCI_32BIT 0x00080000 2224#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 2225#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000 2226#define TG3_FLAG_WOL_CAP 0x00400000 2227#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 2228#define TG3_FLAG_10_100_ONLY 0x01000000 2229#define TG3_FLAG_PAUSE_AUTONEG 0x02000000 2230 2231#define TG3_FLAG_40BIT_DMA_BUG 0x08000000 2232#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 2233#define TG3_FLAG_SUPPORT_MSI 0x20000000 2234#define TG3_FLAG_CHIP_RESETTING 0x40000000 2235#define TG3_FLAG_INIT_COMPLETE 0x80000000 2236 u32 tg3_flags2; 2237#define TG3_FLG2_RESTART_TIMER 0x00000001 2238#define TG3_FLG2_TSO_BUG 0x00000002 2239#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 2240#define TG3_FLG2_IS_5788 0x00000008 2241#define TG3_FLG2_MAX_RXPEND_64 0x00000010 2242#define TG3_FLG2_TSO_CAPABLE 0x00000020 2243#define TG3_FLG2_PHY_ADC_BUG 0x00000040 2244#define TG3_FLG2_PHY_5704_A0_BUG 0x00000080 2245#define TG3_FLG2_PHY_BER_BUG 0x00000100 2246#define TG3_FLG2_PCI_EXPRESS 0x00000200 2247#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400 2248#define TG3_FLG2_HW_AUTONEG 0x00000800 2249#define TG3_FLG2_IS_NIC 0x00001000 2250#define TG3_FLG2_PHY_SERDES 0x00002000 2251#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000 2252#define TG3_FLG2_FLASH 0x00008000 2253#define TG3_FLG2_HW_TSO_1 0x00010000 2254#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000 2255#define TG3_FLG2_5705_PLUS 0x00040000 2256#define TG3_FLG2_5750_PLUS 0x00080000 2257#define TG3_FLG2_PROTECTED_NVRAM 0x00100000 2258#define TG3_FLG2_USING_MSI 0x00200000 2259#define TG3_FLG2_JUMBO_CAPABLE 0x00400000 2260#define TG3_FLG2_MII_SERDES 0x00800000 2261#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \ 2262 TG3_FLG2_MII_SERDES) 2263#define TG3_FLG2_PARALLEL_DETECT 0x01000000 2264#define TG3_FLG2_ICH_WORKAROUND 0x02000000 2265#define TG3_FLG2_5780_CLASS 0x04000000 2266#define TG3_FLG2_HW_TSO_2 0x08000000 2267#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2) 2268#define TG3_FLG2_1SHOT_MSI 0x10000000 2269#define TG3_FLG2_PHY_JITTER_BUG 0x20000000 2270#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 2271#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000 2272 2273 struct timer_list timer; 2274 u16 timer_counter; 2275 u16 timer_multiplier; 2276 u32 timer_offset; 2277 u16 asf_counter; 2278 u16 asf_multiplier; 2279 2280 /* 1 second counter for transient serdes link events */ 2281 u32 serdes_counter; 2282#define SERDES_AN_TIMEOUT_5704S 2 2283#define SERDES_PARALLEL_DET_TIMEOUT 1 2284#define SERDES_AN_TIMEOUT_5714S 1 2285 2286 struct tg3_link_config link_config; 2287 struct tg3_bufmgr_config bufmgr_config; 2288 2289 /* cache h/w values, often passed straight to h/w */ 2290 u32 rx_mode; 2291 u32 tx_mode; 2292 u32 mac_mode; 2293 u32 mi_mode; 2294 u32 misc_host_ctrl; 2295 u32 grc_mode; 2296 u32 grc_local_ctrl; 2297 u32 dma_rwctrl; 2298 u32 coalesce_mode; 2299 u32 pwrmgmt_thresh; 2300 2301 /* PCI block */ 2302 u16 pci_chip_rev_id; 2303 u8 pci_cacheline_sz; 2304 u8 pci_lat_timer; 2305 u8 pci_hdr_type; 2306 u8 pci_bist; 2307 2308 int pm_cap; 2309 int msi_cap; 2310 2311 /* PHY info */ 2312 u32 phy_id; 2313#define PHY_ID_MASK 0xfffffff0 2314#define PHY_ID_BCM5400 0x60008040 2315#define PHY_ID_BCM5401 0x60008050 2316#define PHY_ID_BCM5411 0x60008070 2317#define PHY_ID_BCM5701 0x60008110 2318#define PHY_ID_BCM5703 0x60008160 2319#define PHY_ID_BCM5704 0x60008190 2320#define PHY_ID_BCM5705 0x600081a0 2321#define PHY_ID_BCM5750 0x60008180 2322#define PHY_ID_BCM5752 0x60008100 2323#define PHY_ID_BCM5714 0x60008340 2324#define PHY_ID_BCM5780 0x60008350 2325#define PHY_ID_BCM5755 0xbc050cc0 2326#define PHY_ID_BCM5787 0xbc050ce0 2327#define PHY_ID_BCM5756 0xbc050ed0 2328#define PHY_ID_BCM5906 0xdc00ac40 2329#define PHY_ID_BCM8002 0x60010140 2330#define PHY_ID_INVALID 0xffffffff 2331#define PHY_ID_REV_MASK 0x0000000f 2332#define PHY_REV_BCM5401_B0 0x1 2333#define PHY_REV_BCM5401_B2 0x3 2334#define PHY_REV_BCM5401_C0 0x6 2335#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */ 2336 2337 u32 led_ctrl; 2338 2339 char board_part_number[24]; 2340 char fw_ver[16]; 2341 u32 nic_sram_data_cfg; 2342 u32 pci_clock_ctrl; 2343 struct pci_dev *pdev_peer; 2344 2345 /* This macro assumes the passed PHY ID is already masked 2346 * with PHY_ID_MASK. 2347 */ 2348#define KNOWN_PHY_ID(X) \ 2349 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \ 2350 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \ 2351 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \ 2352 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \ 2353 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \ 2354 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \ 2355 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \ 2356 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002) 2357 2358 struct tg3_hw_stats *hw_stats; 2359 dma_addr_t stats_mapping; 2360 struct work_struct reset_task; 2361 2362 int nvram_lock_cnt; 2363 u32 nvram_size; 2364 u32 nvram_pagesize; 2365 u32 nvram_jedecnum; 2366 2367#define JEDEC_ATMEL 0x1f 2368#define JEDEC_ST 0x20 2369#define JEDEC_SAIFUN 0x4f 2370#define JEDEC_SST 0xbf 2371 2372#define ATMEL_AT24C64_CHIP_SIZE (64 * 1024) 2373#define ATMEL_AT24C64_PAGE_SIZE (32) 2374 2375#define ATMEL_AT24C512_CHIP_SIZE (512 * 1024) 2376#define ATMEL_AT24C512_PAGE_SIZE (128) 2377 2378#define ATMEL_AT45DB0X1B_PAGE_POS 9 2379#define ATMEL_AT45DB0X1B_PAGE_SIZE 264 2380 2381#define ATMEL_AT25F512_PAGE_SIZE 256 2382 2383#define ST_M45PEX0_PAGE_SIZE 256 2384 2385#define SAIFUN_SA25F0XX_PAGE_SIZE 256 2386 2387#define SST_25VF0X0_PAGE_SIZE 4098 2388 2389 struct ethtool_coalesce coal; 2390}; 2391 2392#endif /* !(_T3_H) */ 2393