1/* sun3lance.c: Ethernet driver for SUN3 Lance chip */ 2/* 3 4 Sun3 Lance ethernet driver, by Sam Creasey (sammy@users.qual.net). 5 This driver is a part of the linux kernel, and is thus distributed 6 under the GNU General Public License. 7 8 The values used in LANCE_OBIO and LANCE_IRQ seem to be empirically 9 true for the correct IRQ and address of the lance registers. They 10 have not been widely tested, however. What we probably need is a 11 "proper" way to search for a device in the sun3's prom, but, alas, 12 linux has no such thing. 13 14 This driver is largely based on atarilance.c, by Roman Hodek. Other 15 sources of inspiration were the NetBSD sun3 am7990 driver, and the 16 linux sparc lance driver (sunlance.c). 17 18 There are more assumptions made throughout this driver, it almost 19 certainly still needs work, but it does work at least for RARP/BOOTP and 20 mounting the root NFS filesystem. 21 22*/ 23 24static char *version = "sun3lance.c: v1.2 1/12/2001 Sam Creasey (sammy@sammy.net)\n"; 25 26#include <linux/module.h> 27#include <linux/stddef.h> 28#include <linux/kernel.h> 29#include <linux/string.h> 30#include <linux/errno.h> 31#include <linux/slab.h> 32#include <linux/interrupt.h> 33#include <linux/init.h> 34#include <linux/ioport.h> 35#include <linux/delay.h> 36#include <linux/netdevice.h> 37#include <linux/etherdevice.h> 38#include <linux/skbuff.h> 39#include <linux/bitops.h> 40 41#include <asm/cacheflush.h> 42#include <asm/setup.h> 43#include <asm/irq.h> 44#include <asm/io.h> 45#include <asm/pgtable.h> 46#include <asm/dvma.h> 47#include <asm/idprom.h> 48#include <asm/machines.h> 49 50#ifdef CONFIG_SUN3 51#include <asm/sun3mmu.h> 52#else 53#include <asm/sun3xprom.h> 54#endif 55 56/* sun3/60 addr/irq for the lance chip. If your sun is different, 57 change this. */ 58#define LANCE_OBIO 0x120000 59#define LANCE_IRQ IRQ_AUTO_3 60 61/* Debug level: 62 * 0 = silent, print only serious errors 63 * 1 = normal, print error messages 64 * 2 = debug, print debug infos 65 * 3 = debug, print even more debug infos (packet data) 66 */ 67 68#define LANCE_DEBUG 0 69 70#ifdef LANCE_DEBUG 71static int lance_debug = LANCE_DEBUG; 72#else 73static int lance_debug = 1; 74#endif 75module_param(lance_debug, int, 0); 76MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)"); 77MODULE_LICENSE("GPL"); 78 79#define DPRINTK(n,a) \ 80 do { \ 81 if (lance_debug >= n) \ 82 printk a; \ 83 } while( 0 ) 84 85 86/* we're only using 32k of memory, so we use 4 TX 87 buffers and 16 RX buffers. These values are expressed as log2. */ 88 89#define TX_LOG_RING_SIZE 3 90#define RX_LOG_RING_SIZE 5 91 92/* These are the derived values */ 93 94#define TX_RING_SIZE (1 << TX_LOG_RING_SIZE) 95#define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5) 96#define TX_RING_MOD_MASK (TX_RING_SIZE - 1) 97 98#define RX_RING_SIZE (1 << RX_LOG_RING_SIZE) 99#define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5) 100#define RX_RING_MOD_MASK (RX_RING_SIZE - 1) 101 102/* Definitions for packet buffer access: */ 103#define PKT_BUF_SZ 1544 104 105/* Get the address of a packet buffer corresponding to a given buffer head */ 106#define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base) 107 108 109/* The LANCE Rx and Tx ring descriptors. */ 110struct lance_rx_head { 111 unsigned short base; /* Low word of base addr */ 112 volatile unsigned char flag; 113 unsigned char base_hi; /* High word of base addr (unused) */ 114 short buf_length; /* This length is 2s complement! */ 115 volatile short msg_length; /* This length is "normal". */ 116}; 117 118struct lance_tx_head { 119 unsigned short base; /* Low word of base addr */ 120 volatile unsigned char flag; 121 unsigned char base_hi; /* High word of base addr (unused) */ 122 short length; /* Length is 2s complement! */ 123 volatile short misc; 124}; 125 126/* The LANCE initialization block, described in databook. */ 127struct lance_init_block { 128 unsigned short mode; /* Pre-set mode */ 129 unsigned char hwaddr[6]; /* Physical ethernet address */ 130 unsigned int filter[2]; /* Multicast filter (unused). */ 131 /* Receive and transmit ring base, along with length bits. */ 132 unsigned short rdra; 133 unsigned short rlen; 134 unsigned short tdra; 135 unsigned short tlen; 136 unsigned short pad[4]; /* is thie needed? */ 137}; 138 139/* The whole layout of the Lance shared memory */ 140struct lance_memory { 141 struct lance_init_block init; 142 struct lance_tx_head tx_head[TX_RING_SIZE]; 143 struct lance_rx_head rx_head[RX_RING_SIZE]; 144 char rx_data[RX_RING_SIZE][PKT_BUF_SZ]; 145 char tx_data[TX_RING_SIZE][PKT_BUF_SZ]; 146}; 147 148/* The driver's private device structure */ 149 150struct lance_private { 151 volatile unsigned short *iobase; 152 struct lance_memory *mem; 153 int new_rx, new_tx; /* The next free ring entry */ 154 int old_tx, old_rx; /* ring entry to be processed */ 155 struct net_device_stats stats; 156/* These two must be longs for set_bit() */ 157 long tx_full; 158 long lock; 159}; 160 161/* I/O register access macros */ 162 163#define MEM lp->mem 164#define DREG lp->iobase[0] 165#define AREG lp->iobase[1] 166#define REGA(a) (*( AREG = (a), &DREG )) 167 168/* Definitions for the Lance */ 169 170/* tx_head flags */ 171#define TMD1_ENP 0x01 /* end of packet */ 172#define TMD1_STP 0x02 /* start of packet */ 173#define TMD1_DEF 0x04 /* deferred */ 174#define TMD1_ONE 0x08 /* one retry needed */ 175#define TMD1_MORE 0x10 /* more than one retry needed */ 176#define TMD1_ERR 0x40 /* error summary */ 177#define TMD1_OWN 0x80 /* ownership (set: chip owns) */ 178 179#define TMD1_OWN_CHIP TMD1_OWN 180#define TMD1_OWN_HOST 0 181 182/* tx_head misc field */ 183#define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */ 184#define TMD3_RTRY 0x0400 /* failed after 16 retries */ 185#define TMD3_LCAR 0x0800 /* carrier lost */ 186#define TMD3_LCOL 0x1000 /* late collision */ 187#define TMD3_UFLO 0x4000 /* underflow (late memory) */ 188#define TMD3_BUFF 0x8000 /* buffering error (no ENP) */ 189 190/* rx_head flags */ 191#define RMD1_ENP 0x01 /* end of packet */ 192#define RMD1_STP 0x02 /* start of packet */ 193#define RMD1_BUFF 0x04 /* buffer error */ 194#define RMD1_CRC 0x08 /* CRC error */ 195#define RMD1_OFLO 0x10 /* overflow */ 196#define RMD1_FRAM 0x20 /* framing error */ 197#define RMD1_ERR 0x40 /* error summary */ 198#define RMD1_OWN 0x80 /* ownership (set: ship owns) */ 199 200#define RMD1_OWN_CHIP RMD1_OWN 201#define RMD1_OWN_HOST 0 202 203/* register names */ 204#define CSR0 0 /* mode/status */ 205#define CSR1 1 /* init block addr (low) */ 206#define CSR2 2 /* init block addr (high) */ 207#define CSR3 3 /* misc */ 208#define CSR8 8 /* address filter */ 209#define CSR15 15 /* promiscuous mode */ 210 211/* CSR0 */ 212/* (R=readable, W=writeable, S=set on write, C=clear on write) */ 213#define CSR0_INIT 0x0001 /* initialize (RS) */ 214#define CSR0_STRT 0x0002 /* start (RS) */ 215#define CSR0_STOP 0x0004 /* stop (RS) */ 216#define CSR0_TDMD 0x0008 /* transmit demand (RS) */ 217#define CSR0_TXON 0x0010 /* transmitter on (R) */ 218#define CSR0_RXON 0x0020 /* receiver on (R) */ 219#define CSR0_INEA 0x0040 /* interrupt enable (RW) */ 220#define CSR0_INTR 0x0080 /* interrupt active (R) */ 221#define CSR0_IDON 0x0100 /* initialization done (RC) */ 222#define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */ 223#define CSR0_RINT 0x0400 /* receiver interrupt (RC) */ 224#define CSR0_MERR 0x0800 /* memory error (RC) */ 225#define CSR0_MISS 0x1000 /* missed frame (RC) */ 226#define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */ 227#define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */ 228#define CSR0_ERR 0x8000 /* error (RC) */ 229 230/* CSR3 */ 231#define CSR3_BCON 0x0001 /* byte control */ 232#define CSR3_ACON 0x0002 /* ALE control */ 233#define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */ 234 235/***************************** Prototypes *****************************/ 236 237static int lance_probe( struct net_device *dev); 238static int lance_open( struct net_device *dev ); 239static void lance_init_ring( struct net_device *dev ); 240static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev ); 241static irqreturn_t lance_interrupt( int irq, void *dev_id); 242static int lance_rx( struct net_device *dev ); 243static int lance_close( struct net_device *dev ); 244static struct net_device_stats *lance_get_stats( struct net_device *dev ); 245static void set_multicast_list( struct net_device *dev ); 246 247/************************* End of Prototypes **************************/ 248 249struct net_device * __init sun3lance_probe(int unit) 250{ 251 struct net_device *dev; 252 static int found; 253 int err = -ENODEV; 254 255 /* check that this machine has an onboard lance */ 256 switch(idprom->id_machtype) { 257 case SM_SUN3|SM_3_50: 258 case SM_SUN3|SM_3_60: 259 case SM_SUN3X|SM_3_80: 260 /* these machines have lance */ 261 break; 262 263 default: 264 return ERR_PTR(-ENODEV); 265 } 266 267 if (found) 268 return ERR_PTR(-ENODEV); 269 270 dev = alloc_etherdev(sizeof(struct lance_private)); 271 if (!dev) 272 return ERR_PTR(-ENOMEM); 273 if (unit >= 0) { 274 sprintf(dev->name, "eth%d", unit); 275 netdev_boot_setup_check(dev); 276 } 277 SET_MODULE_OWNER(dev); 278 279 if (!lance_probe(dev)) 280 goto out; 281 282 err = register_netdev(dev); 283 if (err) 284 goto out1; 285 found = 1; 286 return dev; 287 288out1: 289#ifdef CONFIG_SUN3 290 iounmap((void __iomem *)dev->base_addr); 291#endif 292out: 293 free_netdev(dev); 294 return ERR_PTR(err); 295} 296 297static int __init lance_probe( struct net_device *dev) 298{ 299 unsigned long ioaddr; 300 301 struct lance_private *lp; 302 int i; 303 static int did_version; 304 volatile unsigned short *ioaddr_probe; 305 unsigned short tmp1, tmp2; 306 307#ifdef CONFIG_SUN3 308 ioaddr = (unsigned long)ioremap(LANCE_OBIO, PAGE_SIZE); 309 if (!ioaddr) 310 return 0; 311#else 312 ioaddr = SUN3X_LANCE; 313#endif 314 315 /* test to see if there's really a lance here */ 316 /* (CSRO_INIT shouldn't be readable) */ 317 318 ioaddr_probe = (volatile unsigned short *)ioaddr; 319 tmp1 = ioaddr_probe[0]; 320 tmp2 = ioaddr_probe[1]; 321 322 ioaddr_probe[1] = CSR0; 323 ioaddr_probe[0] = CSR0_INIT | CSR0_STOP; 324 325 if(ioaddr_probe[0] != CSR0_STOP) { 326 ioaddr_probe[0] = tmp1; 327 ioaddr_probe[1] = tmp2; 328 329#ifdef CONFIG_SUN3 330 iounmap((void __iomem *)ioaddr); 331#endif 332 return 0; 333 } 334 335 lp = netdev_priv(dev); 336 337 MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000); 338 if (MEM == NULL) { 339#ifdef CONFIG_SUN3 340 iounmap((void __iomem *)ioaddr); 341#endif 342 printk(KERN_WARNING "SUN3 Lance couldn't allocate DVMA memory\n"); 343 return 0; 344 } 345 346 lp->iobase = (volatile unsigned short *)ioaddr; 347 dev->base_addr = (unsigned long)ioaddr; /* informational only */ 348 349 REGA(CSR0) = CSR0_STOP; 350 351 if (request_irq(LANCE_IRQ, lance_interrupt, IRQF_DISABLED, "SUN3 Lance", dev) < 0) { 352#ifdef CONFIG_SUN3 353 iounmap((void __iomem *)ioaddr); 354#endif 355 dvma_free((void *)MEM); 356 printk(KERN_WARNING "SUN3 Lance unable to allocate IRQ\n"); 357 return 0; 358 } 359 dev->irq = (unsigned short)LANCE_IRQ; 360 361 362 printk("%s: SUN3 Lance at io %#lx, mem %#lx, irq %d, hwaddr ", 363 dev->name, 364 (unsigned long)ioaddr, 365 (unsigned long)MEM, 366 dev->irq); 367 368 /* copy in the ethernet address from the prom */ 369 for(i = 0; i < 6 ; i++) 370 dev->dev_addr[i] = idprom->id_ethaddr[i]; 371 372 /* tell the card it's ether address, bytes swapped */ 373 MEM->init.hwaddr[0] = dev->dev_addr[1]; 374 MEM->init.hwaddr[1] = dev->dev_addr[0]; 375 MEM->init.hwaddr[2] = dev->dev_addr[3]; 376 MEM->init.hwaddr[3] = dev->dev_addr[2]; 377 MEM->init.hwaddr[4] = dev->dev_addr[5]; 378 MEM->init.hwaddr[5] = dev->dev_addr[4]; 379 380 for( i = 0; i < 6; ++i ) 381 printk( "%02x%s", dev->dev_addr[i], (i < 5) ? ":" : "\n" ); 382 383 MEM->init.mode = 0x0000; 384 MEM->init.filter[0] = 0x00000000; 385 MEM->init.filter[1] = 0x00000000; 386 MEM->init.rdra = dvma_vtob(MEM->rx_head); 387 MEM->init.rlen = (RX_LOG_RING_SIZE << 13) | 388 (dvma_vtob(MEM->rx_head) >> 16); 389 MEM->init.tdra = dvma_vtob(MEM->tx_head); 390 MEM->init.tlen = (TX_LOG_RING_SIZE << 13) | 391 (dvma_vtob(MEM->tx_head) >> 16); 392 393 DPRINTK(2, ("initaddr: %08lx rx_ring: %08lx tx_ring: %08lx\n", 394 dvma_vtob(&(MEM->init)), dvma_vtob(MEM->rx_head), 395 (dvma_vtob(MEM->tx_head)))); 396 397 if (did_version++ == 0) 398 printk( version ); 399 400 /* The LANCE-specific entries in the device structure. */ 401 dev->open = &lance_open; 402 dev->hard_start_xmit = &lance_start_xmit; 403 dev->stop = &lance_close; 404 dev->get_stats = &lance_get_stats; 405 dev->set_multicast_list = &set_multicast_list; 406 dev->set_mac_address = NULL; 407// KLUDGE -- REMOVE ME 408 set_bit(__LINK_STATE_PRESENT, &dev->state); 409 410 411 memset( &lp->stats, 0, sizeof(lp->stats) ); 412 413 return 1; 414} 415 416static int lance_open( struct net_device *dev ) 417{ 418 struct lance_private *lp = netdev_priv(dev); 419 int i; 420 421 DPRINTK( 2, ( "%s: lance_open()\n", dev->name )); 422 423 REGA(CSR0) = CSR0_STOP; 424 425 lance_init_ring(dev); 426 427 /* From now on, AREG is kept to point to CSR0 */ 428 REGA(CSR0) = CSR0_INIT; 429 430 i = 1000000; 431 while (--i > 0) 432 if (DREG & CSR0_IDON) 433 break; 434 if (i < 0 || (DREG & CSR0_ERR)) { 435 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n", 436 dev->name, i, DREG )); 437 DREG = CSR0_STOP; 438 return( -EIO ); 439 } 440 441 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA; 442 443 netif_start_queue(dev); 444 445 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG )); 446 447 return( 0 ); 448} 449 450 451/* Initialize the LANCE Rx and Tx rings. */ 452 453static void lance_init_ring( struct net_device *dev ) 454{ 455 struct lance_private *lp = netdev_priv(dev); 456 int i; 457 458 lp->lock = 0; 459 lp->tx_full = 0; 460 lp->new_rx = lp->new_tx = 0; 461 lp->old_rx = lp->old_tx = 0; 462 463 for( i = 0; i < TX_RING_SIZE; i++ ) { 464 MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]); 465 MEM->tx_head[i].flag = 0; 466 MEM->tx_head[i].base_hi = 467 (dvma_vtob(MEM->tx_data[i])) >>16; 468 MEM->tx_head[i].length = 0; 469 MEM->tx_head[i].misc = 0; 470 } 471 472 for( i = 0; i < RX_RING_SIZE; i++ ) { 473 MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]); 474 MEM->rx_head[i].flag = RMD1_OWN_CHIP; 475 MEM->rx_head[i].base_hi = 476 (dvma_vtob(MEM->rx_data[i])) >> 16; 477 MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000; 478 MEM->rx_head[i].msg_length = 0; 479 } 480 481 /* tell the card it's ether address, bytes swapped */ 482 MEM->init.hwaddr[0] = dev->dev_addr[1]; 483 MEM->init.hwaddr[1] = dev->dev_addr[0]; 484 MEM->init.hwaddr[2] = dev->dev_addr[3]; 485 MEM->init.hwaddr[3] = dev->dev_addr[2]; 486 MEM->init.hwaddr[4] = dev->dev_addr[5]; 487 MEM->init.hwaddr[5] = dev->dev_addr[4]; 488 489 MEM->init.mode = 0x0000; 490 MEM->init.filter[0] = 0x00000000; 491 MEM->init.filter[1] = 0x00000000; 492 MEM->init.rdra = dvma_vtob(MEM->rx_head); 493 MEM->init.rlen = (RX_LOG_RING_SIZE << 13) | 494 (dvma_vtob(MEM->rx_head) >> 16); 495 MEM->init.tdra = dvma_vtob(MEM->tx_head); 496 MEM->init.tlen = (TX_LOG_RING_SIZE << 13) | 497 (dvma_vtob(MEM->tx_head) >> 16); 498 499 500 /* tell the lance the address of its init block */ 501 REGA(CSR1) = dvma_vtob(&(MEM->init)); 502 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16; 503 504#ifdef CONFIG_SUN3X 505 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON; 506#else 507 REGA(CSR3) = CSR3_BSWP; 508#endif 509 510} 511 512 513static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev ) 514{ 515 struct lance_private *lp = netdev_priv(dev); 516 int entry, len; 517 struct lance_tx_head *head; 518 unsigned long flags; 519 520 DPRINTK( 1, ( "%s: transmit start.\n", 521 dev->name)); 522 523 /* Transmitter timeout, serious problems. */ 524 if (netif_queue_stopped(dev)) { 525 int tickssofar = jiffies - dev->trans_start; 526 if (tickssofar < 20) 527 return( 1 ); 528 529 DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n", 530 dev->name, DREG )); 531 DREG = CSR0_STOP; 532 /* 533 * Always set BSWP after a STOP as STOP puts it back into 534 * little endian mode. 535 */ 536 REGA(CSR3) = CSR3_BSWP; 537 lp->stats.tx_errors++; 538 539 if(lance_debug >= 2) { 540 int i; 541 printk("Ring data: old_tx %d new_tx %d%s new_rx %d\n", 542 lp->old_tx, lp->new_tx, 543 lp->tx_full ? " (full)" : "", 544 lp->new_rx ); 545 for( i = 0 ; i < RX_RING_SIZE; i++ ) 546 printk( "rx #%d: base=%04x blen=%04x mlen=%04x\n", 547 i, MEM->rx_head[i].base, 548 -MEM->rx_head[i].buf_length, 549 MEM->rx_head[i].msg_length); 550 for( i = 0 ; i < TX_RING_SIZE; i++ ) 551 printk("tx #%d: base=%04x len=%04x misc=%04x\n", 552 i, MEM->tx_head[i].base, 553 -MEM->tx_head[i].length, 554 MEM->tx_head[i].misc ); 555 } 556 557 lance_init_ring(dev); 558 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; 559 560 netif_start_queue(dev); 561 dev->trans_start = jiffies; 562 563 return 0; 564 } 565 566 567 /* Block a timer-based transmit from overlapping. This could better be 568 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */ 569 570 /* Block a timer-based transmit from overlapping with us by 571 stopping the queue for a bit... */ 572 573 netif_stop_queue(dev); 574 575 if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) { 576 printk( "%s: tx queue lock!.\n", dev->name); 577 /* don't clear dev->tbusy flag. */ 578 return 1; 579 } 580 581 AREG = CSR0; 582 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n", 583 dev->name, DREG )); 584 585#ifdef CONFIG_SUN3X 586 /* this weirdness doesn't appear on sun3... */ 587 if(!(DREG & CSR0_INIT)) { 588 DPRINTK( 1, ("INIT not set, reinitializing...\n")); 589 REGA( CSR0 ) = CSR0_STOP; 590 lance_init_ring(dev); 591 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT; 592 } 593#endif 594 595 /* Fill in a Tx ring entry */ 596 /* We're not prepared for the int until the last flags are set/reset. 597 * And the int may happen already after setting the OWN_CHIP... */ 598 local_irq_save(flags); 599 600 /* Mask to ring buffer boundary. */ 601 entry = lp->new_tx; 602 head = &(MEM->tx_head[entry]); 603 604 /* Caution: the write order is important here, set the "ownership" bits 605 * last. 606 */ 607 608 /* the sun3's lance needs it's buffer padded to the minimum 609 size */ 610 len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN; 611 612// head->length = -len; 613 head->length = (-len) | 0xf000; 614 head->misc = 0; 615 616 skb_copy_from_linear_data(skb, PKTBUF_ADDR(head), skb->len); 617 if (len != skb->len) 618 memset(PKTBUF_ADDR(head) + skb->len, 0, len-skb->len); 619 620 head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP; 621 lp->new_tx = (lp->new_tx + 1) & TX_RING_MOD_MASK; 622 lp->stats.tx_bytes += skb->len; 623 624 /* Trigger an immediate send poll. */ 625 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT; 626 AREG = CSR0; 627 DPRINTK( 2, ( "%s: lance_start_xmit() exiting, csr0 %4.4x.\n", 628 dev->name, DREG )); 629 dev->trans_start = jiffies; 630 dev_kfree_skb( skb ); 631 632 lp->lock = 0; 633 if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) == 634 TMD1_OWN_HOST) 635 netif_start_queue(dev); 636 637 local_irq_restore(flags); 638 639 return 0; 640} 641 642/* The LANCE interrupt handler. */ 643 644static irqreturn_t lance_interrupt( int irq, void *dev_id) 645{ 646 struct net_device *dev = dev_id; 647 struct lance_private *lp = netdev_priv(dev); 648 int csr0; 649 static int in_interrupt; 650 651 if (dev == NULL) { 652 DPRINTK( 1, ( "lance_interrupt(): invalid dev_id\n" )); 653 return IRQ_NONE; 654 } 655 656 if (in_interrupt) 657 DPRINTK( 2, ( "%s: Re-entering the interrupt handler.\n", dev->name )); 658 in_interrupt = 1; 659 660 still_more: 661 flush_cache_all(); 662 663 AREG = CSR0; 664 csr0 = DREG; 665 666 /* ack interrupts */ 667 DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON); 668 669 /* clear errors */ 670 if(csr0 & CSR0_ERR) 671 DREG = CSR0_BABL | CSR0_MERR | CSR0_CERR | CSR0_MISS; 672 673 674 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n", 675 dev->name, csr0, DREG )); 676 677 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ 678 int old_tx = lp->old_tx; 679 680// if(lance_debug >= 3) { 681// int i; 682// 683// printk("%s: tx int\n", dev->name); 684// 685// for(i = 0; i < TX_RING_SIZE; i++) 686// printk("ring %d flag=%04x\n", i, 687// MEM->tx_head[i].flag); 688// } 689 690 while( old_tx != lp->new_tx) { 691 struct lance_tx_head *head = &(MEM->tx_head[old_tx]); 692 693 DPRINTK(3, ("on tx_ring %d\n", old_tx)); 694 695 if (head->flag & TMD1_OWN_CHIP) 696 break; /* It still hasn't been Txed */ 697 698 if (head->flag & TMD1_ERR) { 699 int status = head->misc; 700 lp->stats.tx_errors++; 701 if (status & TMD3_RTRY) lp->stats.tx_aborted_errors++; 702 if (status & TMD3_LCAR) lp->stats.tx_carrier_errors++; 703 if (status & TMD3_LCOL) lp->stats.tx_window_errors++; 704 if (status & (TMD3_UFLO | TMD3_BUFF)) { 705 lp->stats.tx_fifo_errors++; 706 printk("%s: Tx FIFO error\n", 707 dev->name); 708 REGA(CSR0) = CSR0_STOP; 709 REGA(CSR3) = CSR3_BSWP; 710 lance_init_ring(dev); 711 REGA(CSR0) = CSR0_STRT | CSR0_INEA; 712 return IRQ_HANDLED; 713 } 714 } else if(head->flag & (TMD1_ENP | TMD1_STP)) { 715 716 head->flag &= ~(TMD1_ENP | TMD1_STP); 717 if(head->flag & (TMD1_ONE | TMD1_MORE)) 718 lp->stats.collisions++; 719 720 lp->stats.tx_packets++; 721 DPRINTK(3, ("cleared tx ring %d\n", old_tx)); 722 } 723 old_tx = (old_tx +1) & TX_RING_MOD_MASK; 724 } 725 726 lp->old_tx = old_tx; 727 } 728 729 730 if (netif_queue_stopped(dev)) { 731 /* The ring is no longer full, clear tbusy. */ 732 netif_start_queue(dev); 733 netif_wake_queue(dev); 734 } 735 736 if (csr0 & CSR0_RINT) /* Rx interrupt */ 737 lance_rx( dev ); 738 739 /* Log misc errors. */ 740 if (csr0 & CSR0_BABL) lp->stats.tx_errors++; /* Tx babble. */ 741 if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */ 742 if (csr0 & CSR0_MERR) { 743 DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), " 744 "status %04x.\n", dev->name, csr0 )); 745 /* Restart the chip. */ 746 REGA(CSR0) = CSR0_STOP; 747 REGA(CSR3) = CSR3_BSWP; 748 lance_init_ring(dev); 749 REGA(CSR0) = CSR0_STRT | CSR0_INEA; 750 } 751 752 753 /* Clear any other interrupt, and set interrupt enable. */ 754// DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR | 755// CSR0_IDON | CSR0_INEA; 756 757 REGA(CSR0) = CSR0_INEA; 758 759 if(DREG & (CSR0_RINT | CSR0_TINT)) { 760 DPRINTK(2, ("restarting interrupt, csr0=%#04x\n", DREG)); 761 goto still_more; 762 } 763 764 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n", 765 dev->name, DREG )); 766 in_interrupt = 0; 767 return IRQ_HANDLED; 768} 769 770/* get packet, toss into skbuff */ 771static int lance_rx( struct net_device *dev ) 772{ 773 struct lance_private *lp = netdev_priv(dev); 774 int entry = lp->new_rx; 775 776 /* If we own the next entry, it's a new packet. Send it up. */ 777 while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) { 778 struct lance_rx_head *head = &(MEM->rx_head[entry]); 779 int status = head->flag; 780 781 if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */ 782 /* There is a tricky error noted by John Murphy, 783 <murf@perftech.com> to Russ Nelson: Even with 784 full-sized buffers it's possible for a jabber packet to use two 785 buffers, with only the last correctly noting the error. */ 786 if (status & RMD1_ENP) /* Only count a general error at the */ 787 lp->stats.rx_errors++; /* end of a packet.*/ 788 if (status & RMD1_FRAM) lp->stats.rx_frame_errors++; 789 if (status & RMD1_OFLO) lp->stats.rx_over_errors++; 790 if (status & RMD1_CRC) lp->stats.rx_crc_errors++; 791 if (status & RMD1_BUFF) lp->stats.rx_fifo_errors++; 792 head->flag &= (RMD1_ENP|RMD1_STP); 793 } else { 794 /* Malloc up new buffer, compatible with net-3. */ 795// short pkt_len = head->msg_length;// & 0xfff; 796 short pkt_len = (head->msg_length & 0xfff) - 4; 797 struct sk_buff *skb; 798 799 if (pkt_len < 60) { 800 printk( "%s: Runt packet!\n", dev->name ); 801 lp->stats.rx_errors++; 802 } 803 else { 804 skb = dev_alloc_skb( pkt_len+2 ); 805 if (skb == NULL) { 806 DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n", 807 dev->name )); 808 809 lp->stats.rx_dropped++; 810 head->msg_length = 0; 811 head->flag |= RMD1_OWN_CHIP; 812 lp->new_rx = (lp->new_rx+1) & 813 RX_RING_MOD_MASK; 814 } 815 816 if (lance_debug >= 3) { 817 u_char *data = PKTBUF_ADDR(head); 818 printk( "%s: RX pkt %d type 0x%04x len %d\n ", dev->name, entry, ((u_short *)data)[6], pkt_len); 819 } 820 821 822 skb_reserve( skb, 2 ); /* 16 byte align */ 823 skb_put( skb, pkt_len ); /* Make room */ 824// skb_copy_to_linear_data(skb, PKTBUF_ADDR(head), pkt_len); 825 eth_copy_and_sum(skb, 826 PKTBUF_ADDR(head), 827 pkt_len, 0); 828 829 skb->protocol = eth_type_trans( skb, dev ); 830 netif_rx( skb ); 831 dev->last_rx = jiffies; 832 lp->stats.rx_packets++; 833 lp->stats.rx_bytes += pkt_len; 834 } 835 } 836 837// head->buf_length = -PKT_BUF_SZ | 0xf000; 838 head->msg_length = 0; 839 head->flag = RMD1_OWN_CHIP; 840 841 entry = lp->new_rx = (lp->new_rx +1) & RX_RING_MOD_MASK; 842 } 843 844 /* From lance.c (Donald Becker): */ 845 /* We should check that at least two ring entries are free. 846 If not, we should free one and mark stats->rx_dropped++. */ 847 848 return 0; 849} 850 851 852static int lance_close( struct net_device *dev ) 853{ 854 struct lance_private *lp = netdev_priv(dev); 855 856 netif_stop_queue(dev); 857 858 AREG = CSR0; 859 860 DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n", 861 dev->name, DREG )); 862 863 /* We stop the LANCE here -- it occasionally polls 864 memory if we don't. */ 865 DREG = CSR0_STOP; 866 return 0; 867} 868 869 870static struct net_device_stats *lance_get_stats( struct net_device *dev ) 871{ 872 struct lance_private *lp = netdev_priv(dev); 873 874 return &lp->stats; 875} 876 877 878/* Set or clear the multicast filter for this adaptor. 879 num_addrs == -1 Promiscuous mode, receive all packets 880 num_addrs == 0 Normal mode, clear multicast list 881 num_addrs > 0 Multicast mode, receive normal and MC packets, and do 882 best-effort filtering. 883 */ 884 885/* completely untested on a sun3 */ 886static void set_multicast_list( struct net_device *dev ) 887{ 888 struct lance_private *lp = netdev_priv(dev); 889 890 if(netif_queue_stopped(dev)) 891 /* Only possible if board is already started */ 892 return; 893 894 /* We take the simple way out and always enable promiscuous mode. */ 895 DREG = CSR0_STOP; /* Temporarily stop the lance. */ 896 897 if (dev->flags & IFF_PROMISC) { 898 /* Log any net taps. */ 899 DPRINTK( 3, ( "%s: Promiscuous mode enabled.\n", dev->name )); 900 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */ 901 } else { 902 short multicast_table[4]; 903 int num_addrs = dev->mc_count; 904 int i; 905 /* We don't use the multicast table, but rely on upper-layer 906 * filtering. */ 907 memset( multicast_table, (num_addrs == 0) ? 0 : -1, 908 sizeof(multicast_table) ); 909 for( i = 0; i < 4; i++ ) 910 REGA( CSR8+i ) = multicast_table[i]; 911 REGA( CSR15 ) = 0; /* Unset promiscuous mode */ 912 } 913 914 /* 915 * Always set BSWP after a STOP as STOP puts it back into 916 * little endian mode. 917 */ 918 REGA( CSR3 ) = CSR3_BSWP; 919 920 /* Resume normal operation and reset AREG to CSR0 */ 921 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; 922} 923 924 925#ifdef MODULE 926 927static struct net_device *sun3lance_dev; 928 929int __init init_module(void) 930{ 931 sun3lance_dev = sun3lance_probe(-1); 932 if (IS_ERR(sun3lance_dev)) 933 return PTR_ERR(sun3lance_dev); 934 return 0; 935} 936 937void __exit cleanup_module(void) 938{ 939 unregister_netdev(sun3lance_dev); 940#ifdef CONFIG_SUN3 941 iounmap((void __iomem *)sun3lance_dev->base_addr); 942#endif 943 free_netdev(sun3lance_dev); 944} 945 946#endif /* MODULE */ 947