1/* 2 * New driver for Marvell Yukon 2 chipset. 3 * Based on earlier sk98lin, and skge driver. 4 * 5 * This driver intentionally does not support all the features 6 * of the original driver such as link fail-over and link management because 7 * those should be done at higher levels. 8 * 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25#include <linux/crc32.h> 26#include <linux/kernel.h> 27#include <linux/version.h> 28#include <linux/module.h> 29#include <linux/netdevice.h> 30#include <linux/dma-mapping.h> 31#include <linux/etherdevice.h> 32#include <linux/ethtool.h> 33#include <linux/pci.h> 34#include <linux/ip.h> 35#include <net/ip.h> 36#include <linux/tcp.h> 37#include <linux/in.h> 38#include <linux/delay.h> 39#include <linux/workqueue.h> 40#include <linux/if_vlan.h> 41#include <linux/prefetch.h> 42#include <linux/mii.h> 43 44#include <asm/irq.h> 45 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 47#define SKY2_VLAN_TAG_USED 1 48#endif 49 50#include "sky2.h" 51 52#define DRV_NAME "sky2" 53#define DRV_VERSION "1.14" 54#define PFX DRV_NAME " " 55 56/* 57 * The Yukon II chipset takes 64 bit command blocks (called list elements) 58 * that are organized into three (receive, transmit, status) different rings 59 * similar to Tigon3. 60 */ 61 62#define RX_LE_SIZE 1024 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 65#define RX_DEF_PENDING RX_MAX_PENDING 66#define RX_SKB_ALIGN 8 67#define RX_BUF_WRITE 16 68 69#define TX_RING_SIZE 512 70#define TX_DEF_PENDING (TX_RING_SIZE - 1) 71#define TX_MIN_PENDING 64 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS) 73 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) 76#define TX_WATCHDOG (5 * HZ) 77#define NAPI_WEIGHT 64 78#define PHY_RETRIES 1000 79 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1)) 81 82static const u32 default_msg = 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 86 87static int debug = -1; /* defaults above */ 88module_param(debug, int, 0); 89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 90 91static int copybreak __read_mostly = 128; 92module_param(copybreak, int, 0); 93MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 94 95static int disable_msi = 0; 96module_param(disable_msi, int, 0); 97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 98 99static int idle_timeout = 0; 100module_param(idle_timeout, int, 0); 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)"); 102 103static const struct pci_device_id sky2_id_table[] = { 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 133// { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 134 { 0 } 135}; 136 137MODULE_DEVICE_TABLE(pci, sky2_id_table); 138 139/* Avoid conditionals by using array */ 140static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 141static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 142static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 143 144/* This driver supports yukon2 chipset only */ 145static const char *yukon2_name[] = { 146 "XL", /* 0xb3 */ 147 "EC Ultra", /* 0xb4 */ 148 "Extreme", /* 0xb5 */ 149 "EC", /* 0xb6 */ 150 "FE", /* 0xb7 */ 151}; 152 153/* Access to external PHY */ 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 155{ 156 int i; 157 158 gma_write16(hw, port, GM_SMI_DATA, val); 159 gma_write16(hw, port, GM_SMI_CTRL, 160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 161 162 for (i = 0; i < PHY_RETRIES; i++) { 163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) 164 return 0; 165 udelay(1); 166 } 167 168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); 169 return -ETIMEDOUT; 170} 171 172static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 173{ 174 int i; 175 176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 178 179 for (i = 0; i < PHY_RETRIES; i++) { 180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { 181 *val = gma_read16(hw, port, GM_SMI_DATA); 182 return 0; 183 } 184 185 udelay(1); 186 } 187 188 return -ETIMEDOUT; 189} 190 191static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 192{ 193 u16 v; 194 195 if (__gm_phy_read(hw, port, reg, &v) != 0) 196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); 197 return v; 198} 199 200 201static void sky2_power_on(struct sky2_hw *hw) 202{ 203 /* switch power to VCC (WA for VAUX problem) */ 204 sky2_write8(hw, B0_POWER_CTRL, 205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 206 207 /* disable Core Clock Division, */ 208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 209 210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 211 /* enable bits are inverted */ 212 sky2_write8(hw, B2_Y2_CLK_GATE, 213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 216 else 217 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 218 219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) { 220 u32 reg1; 221 222 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 223 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); 224 reg1 &= P_ASPM_CONTROL_MSK; 225 sky2_pci_write32(hw, PCI_DEV_REG4, reg1); 226 sky2_pci_write32(hw, PCI_DEV_REG5, 0); 227 } 228} 229 230static void sky2_power_aux(struct sky2_hw *hw) 231{ 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 233 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 234 else 235 /* enable bits are inverted */ 236 sky2_write8(hw, B2_Y2_CLK_GATE, 237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 240 241 /* switch power to VAUX */ 242 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) 243 sky2_write8(hw, B0_POWER_CTRL, 244 (PC_VAUX_ENA | PC_VCC_ENA | 245 PC_VAUX_ON | PC_VCC_OFF)); 246} 247 248static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 249{ 250 u16 reg; 251 252 /* disable all GMAC IRQ's */ 253 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 254 /* disable PHY IRQs */ 255 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 256 257 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 258 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 259 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 260 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 261 262 reg = gma_read16(hw, port, GM_RX_CTRL); 263 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 264 gma_write16(hw, port, GM_RX_CTRL, reg); 265} 266 267/* flow control to advertise bits */ 268static const u16 copper_fc_adv[] = { 269 [FC_NONE] = 0, 270 [FC_TX] = PHY_M_AN_ASP, 271 [FC_RX] = PHY_M_AN_PC, 272 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 273}; 274 275/* flow control to advertise bits when using 1000BaseX */ 276static const u16 fiber_fc_adv[] = { 277 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 278 [FC_TX] = PHY_M_P_ASYM_MD_X, 279 [FC_RX] = PHY_M_P_SYM_MD_X, 280 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 281}; 282 283/* flow control to GMA disable bits */ 284static const u16 gm_fc_disable[] = { 285 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 286 [FC_TX] = GM_GPCR_FC_RX_DIS, 287 [FC_RX] = GM_GPCR_FC_TX_DIS, 288 [FC_BOTH] = 0, 289}; 290 291 292static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 293{ 294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 296 297 if (sky2->autoneg == AUTONEG_ENABLE 298 && !(hw->chip_id == CHIP_ID_YUKON_XL 299 || hw->chip_id == CHIP_ID_YUKON_EC_U 300 || hw->chip_id == CHIP_ID_YUKON_EX)) { 301 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 302 303 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 304 PHY_M_EC_MAC_S_MSK); 305 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 306 307 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 308 if (hw->chip_id == CHIP_ID_YUKON_EC) 309 /* set downshift counter to 3x and enable downshift */ 310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 311 else 312 /* set master & slave downshift counter to 1x */ 313 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 314 315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 316 } 317 318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 319 if (sky2_is_copper(hw)) { 320 if (hw->chip_id == CHIP_ID_YUKON_FE) { 321 /* enable automatic crossover */ 322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 323 } else { 324 /* disable energy detect */ 325 ctrl &= ~PHY_M_PC_EN_DET_MSK; 326 327 /* enable automatic crossover */ 328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 329 330 /* downshift on PHY 88E1112 and 88E1149 is changed */ 331 if (sky2->autoneg == AUTONEG_ENABLE 332 && (hw->chip_id == CHIP_ID_YUKON_XL 333 || hw->chip_id == CHIP_ID_YUKON_EC_U 334 || hw->chip_id == CHIP_ID_YUKON_EX)) { 335 /* set downshift counter to 3x and enable downshift */ 336 ctrl &= ~PHY_M_PC_DSC_MSK; 337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 338 } 339 } 340 } else { 341 /* disable Automatic Crossover */ 342 343 ctrl &= ~PHY_M_PC_MDIX_MSK; 344 } 345 346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 347 348 /* special setup for PHY 88E1112 Fiber */ 349 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) { 350 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 351 352 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 353 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 355 ctrl &= ~PHY_M_MAC_MD_MSK; 356 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 358 359 if (hw->pmd_type == 'P') { 360 /* select page 1 to access Fiber registers */ 361 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 362 363 /* for SFP-module set SIGDET polarity to low */ 364 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 365 ctrl |= PHY_M_FIB_SIGD_POL; 366 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 367 } 368 369 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 370 } 371 372 ctrl = PHY_CT_RESET; 373 ct1000 = 0; 374 adv = PHY_AN_CSMA; 375 reg = 0; 376 377 if (sky2->autoneg == AUTONEG_ENABLE) { 378 if (sky2_is_copper(hw)) { 379 if (sky2->advertising & ADVERTISED_1000baseT_Full) 380 ct1000 |= PHY_M_1000C_AFD; 381 if (sky2->advertising & ADVERTISED_1000baseT_Half) 382 ct1000 |= PHY_M_1000C_AHD; 383 if (sky2->advertising & ADVERTISED_100baseT_Full) 384 adv |= PHY_M_AN_100_FD; 385 if (sky2->advertising & ADVERTISED_100baseT_Half) 386 adv |= PHY_M_AN_100_HD; 387 if (sky2->advertising & ADVERTISED_10baseT_Full) 388 adv |= PHY_M_AN_10_FD; 389 if (sky2->advertising & ADVERTISED_10baseT_Half) 390 adv |= PHY_M_AN_10_HD; 391 392 adv |= copper_fc_adv[sky2->flow_mode]; 393 } else { /* special defines for FIBER (88E1040S only) */ 394 if (sky2->advertising & ADVERTISED_1000baseT_Full) 395 adv |= PHY_M_AN_1000X_AFD; 396 if (sky2->advertising & ADVERTISED_1000baseT_Half) 397 adv |= PHY_M_AN_1000X_AHD; 398 399 adv |= fiber_fc_adv[sky2->flow_mode]; 400 } 401 402 /* Restart Auto-negotiation */ 403 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 404 } else { 405 /* forced speed/duplex settings */ 406 ct1000 = PHY_M_1000C_MSE; 407 408 /* Disable auto update for duplex flow control and speed */ 409 reg |= GM_GPCR_AU_ALL_DIS; 410 411 switch (sky2->speed) { 412 case SPEED_1000: 413 ctrl |= PHY_CT_SP1000; 414 reg |= GM_GPCR_SPEED_1000; 415 break; 416 case SPEED_100: 417 ctrl |= PHY_CT_SP100; 418 reg |= GM_GPCR_SPEED_100; 419 break; 420 } 421 422 if (sky2->duplex == DUPLEX_FULL) { 423 reg |= GM_GPCR_DUP_FULL; 424 ctrl |= PHY_CT_DUP_MD; 425 } else if (sky2->speed < SPEED_1000) 426 sky2->flow_mode = FC_NONE; 427 428 429 reg |= gm_fc_disable[sky2->flow_mode]; 430 431 /* Forward pause packets to GMAC? */ 432 if (sky2->flow_mode & FC_RX) 433 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 434 else 435 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 436 } 437 438 gma_write16(hw, port, GM_GP_CTRL, reg); 439 440 if (hw->chip_id != CHIP_ID_YUKON_FE) 441 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 442 443 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 444 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 445 446 /* Setup Phy LED's */ 447 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 448 ledover = 0; 449 450 switch (hw->chip_id) { 451 case CHIP_ID_YUKON_FE: 452 /* on 88E3082 these bits are at 11..9 (shifted left) */ 453 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 454 455 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 456 457 /* delete ACT LED control bits */ 458 ctrl &= ~PHY_M_FELP_LED1_MSK; 459 /* change ACT LED control to blink mode */ 460 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 461 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 462 break; 463 464 case CHIP_ID_YUKON_XL: 465 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 466 467 /* select page 3 to access LED control register */ 468 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 469 470 /* set LED Function Control register */ 471 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 472 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 473 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 474 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 475 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 476 477 /* set Polarity Control register */ 478 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 479 (PHY_M_POLC_LS1_P_MIX(4) | 480 PHY_M_POLC_IS0_P_MIX(4) | 481 PHY_M_POLC_LOS_CTRL(2) | 482 PHY_M_POLC_INIT_CTRL(2) | 483 PHY_M_POLC_STA1_CTRL(2) | 484 PHY_M_POLC_STA0_CTRL(2))); 485 486 /* restore page register */ 487 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 488 break; 489 490 case CHIP_ID_YUKON_EC_U: 491 case CHIP_ID_YUKON_EX: 492 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 493 494 /* select page 3 to access LED control register */ 495 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 496 497 /* set LED Function Control register */ 498 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 499 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 500 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 501 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 502 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 503 504 /* set Blink Rate in LED Timer Control Register */ 505 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 506 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 507 /* restore page register */ 508 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 509 break; 510 511 default: 512 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 513 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 514 /* turn off the Rx LED (LED_RX) */ 515 ledover &= ~PHY_M_LED_MO_RX; 516 } 517 518 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 519 hw->chip_rev == CHIP_REV_YU_EC_U_A1) { 520 /* apply fixes in PHY AFE */ 521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 522 523 /* increase differential signal amplitude in 10BASE-T */ 524 gm_phy_write(hw, port, 0x18, 0xaa99); 525 gm_phy_write(hw, port, 0x17, 0x2011); 526 527 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 528 gm_phy_write(hw, port, 0x18, 0xa204); 529 gm_phy_write(hw, port, 0x17, 0x2002); 530 531 /* set page register to 0 */ 532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 533 } else if (hw->chip_id != CHIP_ID_YUKON_EX) { 534 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 535 536 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { 537 /* turn on 100 Mbps LED (LED_LINK100) */ 538 ledover |= PHY_M_LED_MO_100; 539 } 540 541 if (ledover) 542 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 543 544 } 545 546 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 547 if (sky2->autoneg == AUTONEG_ENABLE) 548 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 549 else 550 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 551} 552 553static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) 554{ 555 u32 reg1; 556 static const u32 phy_power[] 557 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 558 559 /* looks like this XL is back asswards .. */ 560 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 561 onoff = !onoff; 562 563 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 564 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 565 if (onoff) 566 /* Turn off phy power saving */ 567 reg1 &= ~phy_power[port]; 568 else 569 reg1 |= phy_power[port]; 570 571 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 572 sky2_pci_read32(hw, PCI_DEV_REG1); 573 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 574 udelay(100); 575} 576 577/* Force a renegotiation */ 578static void sky2_phy_reinit(struct sky2_port *sky2) 579{ 580 spin_lock_bh(&sky2->phy_lock); 581 sky2_phy_init(sky2->hw, sky2->port); 582 spin_unlock_bh(&sky2->phy_lock); 583} 584 585/* Put device in state to listen for Wake On Lan */ 586static void sky2_wol_init(struct sky2_port *sky2) 587{ 588 struct sky2_hw *hw = sky2->hw; 589 unsigned port = sky2->port; 590 enum flow_control save_mode; 591 u16 ctrl; 592 u32 reg1; 593 594 /* Bring hardware out of reset */ 595 sky2_write16(hw, B0_CTST, CS_RST_CLR); 596 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 597 598 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 599 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 600 601 /* Force to 10/100 602 * sky2_reset will re-enable on resume 603 */ 604 save_mode = sky2->flow_mode; 605 ctrl = sky2->advertising; 606 607 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 608 sky2->flow_mode = FC_NONE; 609 sky2_phy_power(hw, port, 1); 610 sky2_phy_reinit(sky2); 611 612 sky2->flow_mode = save_mode; 613 sky2->advertising = ctrl; 614 615 /* Set GMAC to no flow control and auto update for speed/duplex */ 616 gma_write16(hw, port, GM_GP_CTRL, 617 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 618 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 619 620 /* Set WOL address */ 621 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 622 sky2->netdev->dev_addr, ETH_ALEN); 623 624 /* Turn on appropriate WOL control bits */ 625 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 626 ctrl = 0; 627 if (sky2->wol & WAKE_PHY) 628 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 629 else 630 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 631 632 if (sky2->wol & WAKE_MAGIC) 633 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 634 else 635 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;; 636 637 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 638 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 639 640 /* Turn on legacy PCI-Express PME mode */ 641 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 642 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 643 reg1 |= PCI_Y2_PME_LEGACY; 644 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 646 647 /* block receiver */ 648 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 649 650} 651 652static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 653{ 654 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 655 u16 reg; 656 int i; 657 const u8 *addr = hw->dev[port]->dev_addr; 658 659 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 661 662 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 663 664 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { 665 /* WA DEV_472 -- looks like crossed wires on port 2 */ 666 /* clear GMAC 1 Control reset */ 667 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 668 do { 669 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 670 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 671 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 672 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 673 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 674 } 675 676 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 677 678 /* Enable Transmit FIFO Underrun */ 679 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 680 681 spin_lock_bh(&sky2->phy_lock); 682 sky2_phy_init(hw, port); 683 spin_unlock_bh(&sky2->phy_lock); 684 685 /* MIB clear */ 686 reg = gma_read16(hw, port, GM_PHY_ADDR); 687 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 688 689 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 690 gma_read16(hw, port, i); 691 gma_write16(hw, port, GM_PHY_ADDR, reg); 692 693 /* transmit control */ 694 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 695 696 /* receive control reg: unicast + multicast + no FCS */ 697 gma_write16(hw, port, GM_RX_CTRL, 698 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 699 700 /* transmit flow control */ 701 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 702 703 /* transmit parameter */ 704 gma_write16(hw, port, GM_TX_PARAM, 705 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 706 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 707 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 708 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 709 710 /* serial mode register */ 711 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 712 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 713 714 if (hw->dev[port]->mtu > ETH_DATA_LEN) 715 reg |= GM_SMOD_JUMBO_ENA; 716 717 gma_write16(hw, port, GM_SERIAL_MODE, reg); 718 719 /* virtual address for data */ 720 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 721 722 /* physical address: used for pause frames */ 723 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 724 725 /* ignore counter overflows */ 726 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 727 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 728 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 729 730 /* Configure Rx MAC FIFO */ 731 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 732 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 733 GMF_OPER_ON | GMF_RX_F_FL_ON); 734 735 /* Flush Rx MAC FIFO on any flow control or error */ 736 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 737 738 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); 739 740 /* Configure Tx MAC FIFO */ 741 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 742 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 743 744 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) { 745 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); 746 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); 747 748 /* set Tx GMAC FIFO Almost Empty Threshold */ 749 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 750 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 751 752 if (hw->dev[port]->mtu > ETH_DATA_LEN) 753 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 754 TX_JUMBO_ENA | TX_STFW_DIS); 755 else 756 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 757 TX_JUMBO_DIS | TX_STFW_ENA); 758 } 759 760} 761 762/* Assign Ram Buffer allocation to queue */ 763static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 764{ 765 u32 end; 766 767 /* convert from K bytes to qwords used for hw register */ 768 start *= 1024/8; 769 space *= 1024/8; 770 end = start + space - 1; 771 772 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 773 sky2_write32(hw, RB_ADDR(q, RB_START), start); 774 sky2_write32(hw, RB_ADDR(q, RB_END), end); 775 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 776 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 777 778 if (q == Q_R1 || q == Q_R2) { 779 u32 tp = space - space/4; 780 781 /* On receive queue's set the thresholds 782 * give receiver priority when > 3/4 full 783 * send pause when down to 2K 784 */ 785 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 786 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 787 788 tp = space - 2048/8; 789 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 790 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 791 } else { 792 /* Enable store & forward on Tx queue's because 793 * Tx FIFO is only 1K on Yukon 794 */ 795 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 796 } 797 798 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 799 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 800} 801 802/* Setup Bus Memory Interface */ 803static void sky2_qset(struct sky2_hw *hw, u16 q) 804{ 805 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 806 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 807 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 808 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 809} 810 811/* Setup prefetch unit registers. This is the interface between 812 * hardware and driver list elements 813 */ 814static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 815 u64 addr, u32 last) 816{ 817 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 818 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); 820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); 821 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 822 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 823 824 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 825} 826 827static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) 828{ 829 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; 830 831 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE); 832 le->ctrl = 0; 833 return le; 834} 835 836static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2, 837 struct sky2_tx_le *le) 838{ 839 return sky2->tx_ring + (le - sky2->tx_le); 840} 841 842/* Update chip's next pointer */ 843static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 844{ 845 /* Make sure write' to descriptors are complete before we tell hardware */ 846 wmb(); 847 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 848 849 /* Synchronize I/O on since next processor may write to tail */ 850 mmiowb(); 851} 852 853 854static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 855{ 856 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 857 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 858 le->ctrl = 0; 859 return le; 860} 861 862/* Return high part of DMA address (could be 32 or 64 bit) */ 863static inline u32 high32(dma_addr_t a) 864{ 865 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0; 866} 867 868/* Build description to hardware for one receive segment */ 869static void sky2_rx_add(struct sky2_port *sky2, u8 op, 870 dma_addr_t map, unsigned len) 871{ 872 struct sky2_rx_le *le; 873 u32 hi = high32(map); 874 875 if (sky2->rx_addr64 != hi) { 876 le = sky2_next_rx(sky2); 877 le->addr = cpu_to_le32(hi); 878 le->opcode = OP_ADDR64 | HW_OWNER; 879 sky2->rx_addr64 = high32(map + len); 880 } 881 882 le = sky2_next_rx(sky2); 883 le->addr = cpu_to_le32((u32) map); 884 le->length = cpu_to_le16(len); 885 le->opcode = op | HW_OWNER; 886} 887 888/* Build description to hardware for one possibly fragmented skb */ 889static void sky2_rx_submit(struct sky2_port *sky2, 890 const struct rx_ring_info *re) 891{ 892 int i; 893 894 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 895 896 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 897 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 898} 899 900 901static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 902 unsigned size) 903{ 904 struct sk_buff *skb = re->skb; 905 int i; 906 907 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); 908 pci_unmap_len_set(re, data_size, size); 909 910 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 911 re->frag_addr[i] = pci_map_page(pdev, 912 skb_shinfo(skb)->frags[i].page, 913 skb_shinfo(skb)->frags[i].page_offset, 914 skb_shinfo(skb)->frags[i].size, 915 PCI_DMA_FROMDEVICE); 916} 917 918static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 919{ 920 struct sk_buff *skb = re->skb; 921 int i; 922 923 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size), 924 PCI_DMA_FROMDEVICE); 925 926 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 927 pci_unmap_page(pdev, re->frag_addr[i], 928 skb_shinfo(skb)->frags[i].size, 929 PCI_DMA_FROMDEVICE); 930} 931 932/* Tell chip where to start receive checksum. 933 * Actually has two checksums, but set both same to avoid possible byte 934 * order problems. 935 */ 936static void rx_set_checksum(struct sky2_port *sky2) 937{ 938 struct sky2_rx_le *le; 939 940 le = sky2_next_rx(sky2); 941 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 942 le->ctrl = 0; 943 le->opcode = OP_TCPSTART | HW_OWNER; 944 945 sky2_write32(sky2->hw, 946 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 947 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 948 949} 950 951/* 952 * The RX Stop command will not work for Yukon-2 if the BMU does not 953 * reach the end of packet and since we can't make sure that we have 954 * incoming data, we must reset the BMU while it is not doing a DMA 955 * transfer. Since it is possible that the RX path is still active, 956 * the RX RAM buffer will be stopped first, so any possible incoming 957 * data will not trigger a DMA. After the RAM buffer is stopped, the 958 * BMU is polled until any DMA in progress is ended and only then it 959 * will be reset. 960 */ 961static void sky2_rx_stop(struct sky2_port *sky2) 962{ 963 struct sky2_hw *hw = sky2->hw; 964 unsigned rxq = rxqaddr[sky2->port]; 965 int i; 966 967 /* disable the RAM Buffer receive queue */ 968 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 969 970 for (i = 0; i < 0xffff; i++) 971 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 972 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 973 goto stopped; 974 975 printk(KERN_WARNING PFX "%s: receiver stop failed\n", 976 sky2->netdev->name); 977stopped: 978 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 979 980 /* reset the Rx prefetch unit */ 981 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 982 mmiowb(); 983} 984 985/* Clean out receive buffer area, assumes receiver hardware stopped */ 986static void sky2_rx_clean(struct sky2_port *sky2) 987{ 988 unsigned i; 989 990 memset(sky2->rx_le, 0, RX_LE_BYTES); 991 for (i = 0; i < sky2->rx_pending; i++) { 992 struct rx_ring_info *re = sky2->rx_ring + i; 993 994 if (re->skb) { 995 sky2_rx_unmap_skb(sky2->hw->pdev, re); 996 kfree_skb(re->skb); 997 re->skb = NULL; 998 } 999 } 1000} 1001 1002/* Basic MII support */ 1003static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1004{ 1005 struct mii_ioctl_data *data = if_mii(ifr); 1006 struct sky2_port *sky2 = netdev_priv(dev); 1007 struct sky2_hw *hw = sky2->hw; 1008 int err = -EOPNOTSUPP; 1009 1010 if (!netif_running(dev)) 1011 return -ENODEV; /* Phy still in reset */ 1012 1013 switch (cmd) { 1014 case SIOCGMIIPHY: 1015 data->phy_id = PHY_ADDR_MARV; 1016 1017 /* fallthru */ 1018 case SIOCGMIIREG: { 1019 u16 val = 0; 1020 1021 spin_lock_bh(&sky2->phy_lock); 1022 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1023 spin_unlock_bh(&sky2->phy_lock); 1024 1025 data->val_out = val; 1026 break; 1027 } 1028 1029 case SIOCSMIIREG: 1030 if (!capable(CAP_NET_ADMIN)) 1031 return -EPERM; 1032 1033 spin_lock_bh(&sky2->phy_lock); 1034 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1035 data->val_in); 1036 spin_unlock_bh(&sky2->phy_lock); 1037 break; 1038 } 1039 return err; 1040} 1041 1042#ifdef SKY2_VLAN_TAG_USED 1043static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) 1044{ 1045 struct sky2_port *sky2 = netdev_priv(dev); 1046 struct sky2_hw *hw = sky2->hw; 1047 u16 port = sky2->port; 1048 1049 netif_tx_lock_bh(dev); 1050 netif_poll_disable(sky2->hw->dev[0]); 1051 1052 sky2->vlgrp = grp; 1053 if (grp) { 1054 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1055 RX_VLAN_STRIP_ON); 1056 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1057 TX_VLAN_TAG_ON); 1058 } else { 1059 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1060 RX_VLAN_STRIP_OFF); 1061 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1062 TX_VLAN_TAG_OFF); 1063 } 1064 1065 netif_poll_enable(sky2->hw->dev[0]); 1066 netif_tx_unlock_bh(dev); 1067} 1068#endif 1069 1070/* 1071 * Allocate an skb for receiving. If the MTU is large enough 1072 * make the skb non-linear with a fragment list of pages. 1073 * 1074 * It appears the hardware has a bug in the FIFO logic that 1075 * cause it to hang if the FIFO gets overrun and the receive buffer 1076 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is 1077 * aligned except if slab debugging is enabled. 1078 */ 1079static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2) 1080{ 1081 struct sk_buff *skb; 1082 unsigned long p; 1083 int i; 1084 1085 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN); 1086 if (!skb) 1087 goto nomem; 1088 1089 p = (unsigned long) skb->data; 1090 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); 1091 1092 for (i = 0; i < sky2->rx_nfrags; i++) { 1093 struct page *page = alloc_page(GFP_ATOMIC); 1094 1095 if (!page) 1096 goto free_partial; 1097 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1098 } 1099 1100 return skb; 1101free_partial: 1102 kfree_skb(skb); 1103nomem: 1104 return NULL; 1105} 1106 1107/* 1108 * Allocate and setup receiver buffer pool. 1109 * Normal case this ends up creating one list element for skb 1110 * in the receive ring. Worst case if using large MTU and each 1111 * allocation falls on a different 64 bit region, that results 1112 * in 6 list elements per ring entry. 1113 * One element is used for checksum enable/disable, and one 1114 * extra to avoid wrap. 1115 */ 1116static int sky2_rx_start(struct sky2_port *sky2) 1117{ 1118 struct sky2_hw *hw = sky2->hw; 1119 struct rx_ring_info *re; 1120 unsigned rxq = rxqaddr[sky2->port]; 1121 unsigned i, size, space, thresh; 1122 1123 sky2->rx_put = sky2->rx_next = 0; 1124 sky2_qset(hw, rxq); 1125 1126 /* On PCI express lowering the watermark gives better performance */ 1127 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) 1128 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1129 1130 /* These chips have no ram buffer? 1131 * MAC Rx RAM Read is controlled by hardware */ 1132 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1133 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 1134 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) 1135 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); 1136 1137 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1138 1139 rx_set_checksum(sky2); 1140 1141 /* Space needed for frame data + headers rounded up */ 1142 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8) 1143 + 8; 1144 1145 /* Stopping point for hardware truncation */ 1146 thresh = (size - 8) / sizeof(u32); 1147 1148 /* Account for overhead of skb - to avoid order > 0 allocation */ 1149 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD 1150 + sizeof(struct skb_shared_info); 1151 1152 sky2->rx_nfrags = space >> PAGE_SHIFT; 1153 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1154 1155 if (sky2->rx_nfrags != 0) { 1156 /* Compute residue after pages */ 1157 space = sky2->rx_nfrags << PAGE_SHIFT; 1158 1159 if (space < size) 1160 size -= space; 1161 else 1162 size = 0; 1163 1164 /* Optimize to handle small packets and headers */ 1165 if (size < copybreak) 1166 size = copybreak; 1167 if (size < ETH_HLEN) 1168 size = ETH_HLEN; 1169 } 1170 sky2->rx_data_size = size; 1171 1172 /* Fill Rx ring */ 1173 for (i = 0; i < sky2->rx_pending; i++) { 1174 re = sky2->rx_ring + i; 1175 1176 re->skb = sky2_rx_alloc(sky2); 1177 if (!re->skb) 1178 goto nomem; 1179 1180 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size); 1181 sky2_rx_submit(sky2, re); 1182 } 1183 1184 if (thresh > 0x1ff) 1185 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1186 else { 1187 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1188 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1189 } 1190 1191 /* Tell chip about available buffers */ 1192 sky2_put_idx(hw, rxq, sky2->rx_put); 1193 return 0; 1194nomem: 1195 sky2_rx_clean(sky2); 1196 return -ENOMEM; 1197} 1198 1199/* Bring up network interface. */ 1200static int sky2_up(struct net_device *dev) 1201{ 1202 struct sky2_port *sky2 = netdev_priv(dev); 1203 struct sky2_hw *hw = sky2->hw; 1204 unsigned port = sky2->port; 1205 u32 ramsize, imask; 1206 int cap, err = -ENOMEM; 1207 struct net_device *otherdev = hw->dev[sky2->port^1]; 1208 1209 /* 1210 * On dual port PCI-X card, there is an problem where status 1211 * can be received out of order due to split transactions 1212 */ 1213 if (otherdev && netif_running(otherdev) && 1214 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1215 struct sky2_port *osky2 = netdev_priv(otherdev); 1216 u16 cmd; 1217 1218 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1219 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1220 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1221 1222 sky2->rx_csum = 0; 1223 osky2->rx_csum = 0; 1224 } 1225 1226 if (netif_msg_ifup(sky2)) 1227 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); 1228 1229 /* must be power of 2 */ 1230 sky2->tx_le = pci_alloc_consistent(hw->pdev, 1231 TX_RING_SIZE * 1232 sizeof(struct sky2_tx_le), 1233 &sky2->tx_le_map); 1234 if (!sky2->tx_le) 1235 goto err_out; 1236 1237 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), 1238 GFP_KERNEL); 1239 if (!sky2->tx_ring) 1240 goto err_out; 1241 sky2->tx_prod = sky2->tx_cons = 0; 1242 1243 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, 1244 &sky2->rx_le_map); 1245 if (!sky2->rx_le) 1246 goto err_out; 1247 memset(sky2->rx_le, 0, RX_LE_BYTES); 1248 1249 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), 1250 GFP_KERNEL); 1251 if (!sky2->rx_ring) 1252 goto err_out; 1253 1254 sky2_phy_power(hw, port, 1); 1255 1256 sky2_mac_init(hw, port); 1257 1258 /* Register is number of 4K blocks on internal RAM buffer. */ 1259 ramsize = sky2_read8(hw, B2_E_0) * 4; 1260 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize); 1261 1262 if (ramsize > 0) { 1263 u32 rxspace; 1264 1265 if (ramsize < 16) 1266 rxspace = ramsize / 2; 1267 else 1268 rxspace = 8 + (2*(ramsize - 16))/3; 1269 1270 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1271 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1272 1273 /* Make sure SyncQ is disabled */ 1274 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1275 RB_RST_SET); 1276 } 1277 1278 sky2_qset(hw, txqaddr[port]); 1279 1280 /* Set almost empty threshold */ 1281 if (hw->chip_id == CHIP_ID_YUKON_EC_U 1282 && hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1283 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1284 1285 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1286 TX_RING_SIZE - 1); 1287 1288 err = sky2_rx_start(sky2); 1289 if (err) 1290 goto err_out; 1291 1292 /* Enable interrupts from phy/mac for port */ 1293 imask = sky2_read32(hw, B0_IMSK); 1294 imask |= portirq_msk[port]; 1295 sky2_write32(hw, B0_IMSK, imask); 1296 1297 return 0; 1298 1299err_out: 1300 if (sky2->rx_le) { 1301 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1302 sky2->rx_le, sky2->rx_le_map); 1303 sky2->rx_le = NULL; 1304 } 1305 if (sky2->tx_le) { 1306 pci_free_consistent(hw->pdev, 1307 TX_RING_SIZE * sizeof(struct sky2_tx_le), 1308 sky2->tx_le, sky2->tx_le_map); 1309 sky2->tx_le = NULL; 1310 } 1311 kfree(sky2->tx_ring); 1312 kfree(sky2->rx_ring); 1313 1314 sky2->tx_ring = NULL; 1315 sky2->rx_ring = NULL; 1316 return err; 1317} 1318 1319/* Modular subtraction in ring */ 1320static inline int tx_dist(unsigned tail, unsigned head) 1321{ 1322 return (head - tail) & (TX_RING_SIZE - 1); 1323} 1324 1325/* Number of list elements available for next tx */ 1326static inline int tx_avail(const struct sky2_port *sky2) 1327{ 1328 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); 1329} 1330 1331/* Estimate of number of transmit list elements required */ 1332static unsigned tx_le_req(const struct sk_buff *skb) 1333{ 1334 unsigned count; 1335 1336 count = sizeof(dma_addr_t) / sizeof(u32); 1337 count += skb_shinfo(skb)->nr_frags * count; 1338 1339 if (skb_is_gso(skb)) 1340 ++count; 1341 1342 if (skb->ip_summed == CHECKSUM_PARTIAL) 1343 ++count; 1344 1345 return count; 1346} 1347 1348/* 1349 * Put one packet in ring for transmit. 1350 * A single packet can generate multiple list elements, and 1351 * the number of ring elements will probably be less than the number 1352 * of list elements used. 1353 */ 1354static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) 1355{ 1356 struct sky2_port *sky2 = netdev_priv(dev); 1357 struct sky2_hw *hw = sky2->hw; 1358 struct sky2_tx_le *le = NULL; 1359 struct tx_ring_info *re; 1360 unsigned i, len; 1361 dma_addr_t mapping; 1362 u32 addr64; 1363 u16 mss; 1364 u8 ctrl; 1365 1366 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1367 return NETDEV_TX_BUSY; 1368 1369 if (unlikely(netif_msg_tx_queued(sky2))) 1370 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", 1371 dev->name, sky2->tx_prod, skb->len); 1372 1373 len = skb_headlen(skb); 1374 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1375 addr64 = high32(mapping); 1376 1377 /* Send high bits if changed or crosses boundary */ 1378 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { 1379 le = get_tx_le(sky2); 1380 le->addr = cpu_to_le32(addr64); 1381 le->opcode = OP_ADDR64 | HW_OWNER; 1382 sky2->tx_addr64 = high32(mapping + len); 1383 } 1384 1385 /* Check for TCP Segmentation Offload */ 1386 mss = skb_shinfo(skb)->gso_size; 1387 if (mss != 0) { 1388 mss += tcp_optlen(skb); /* TCP options */ 1389 mss += ip_hdrlen(skb) + sizeof(struct tcphdr); 1390 mss += ETH_HLEN; 1391 1392 if (mss != sky2->tx_last_mss) { 1393 le = get_tx_le(sky2); 1394 le->addr = cpu_to_le32(mss); 1395 le->opcode = OP_LRGLEN | HW_OWNER; 1396 sky2->tx_last_mss = mss; 1397 } 1398 } 1399 1400 ctrl = 0; 1401#ifdef SKY2_VLAN_TAG_USED 1402 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1403 if (sky2->vlgrp && vlan_tx_tag_present(skb)) { 1404 if (!le) { 1405 le = get_tx_le(sky2); 1406 le->addr = 0; 1407 le->opcode = OP_VLAN|HW_OWNER; 1408 } else 1409 le->opcode |= OP_VLAN; 1410 le->length = cpu_to_be16(vlan_tx_tag_get(skb)); 1411 ctrl |= INS_VLAN; 1412 } 1413#endif 1414 1415 /* Handle TCP checksum offload */ 1416 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1417 const unsigned offset = skb_transport_offset(skb); 1418 u32 tcpsum; 1419 1420 tcpsum = offset << 16; /* sum start */ 1421 tcpsum |= offset + skb->csum_offset; /* sum write */ 1422 1423 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1424 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1425 ctrl |= UDPTCP; 1426 1427 if (tcpsum != sky2->tx_tcpsum) { 1428 sky2->tx_tcpsum = tcpsum; 1429 1430 le = get_tx_le(sky2); 1431 le->addr = cpu_to_le32(tcpsum); 1432 le->length = 0; /* initial checksum value */ 1433 le->ctrl = 1; /* one packet */ 1434 le->opcode = OP_TCPLISW | HW_OWNER; 1435 } 1436 } 1437 1438 le = get_tx_le(sky2); 1439 le->addr = cpu_to_le32((u32) mapping); 1440 le->length = cpu_to_le16(len); 1441 le->ctrl = ctrl; 1442 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1443 1444 re = tx_le_re(sky2, le); 1445 re->skb = skb; 1446 pci_unmap_addr_set(re, mapaddr, mapping); 1447 pci_unmap_len_set(re, maplen, len); 1448 1449 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1450 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1451 1452 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, 1453 frag->size, PCI_DMA_TODEVICE); 1454 addr64 = high32(mapping); 1455 if (addr64 != sky2->tx_addr64) { 1456 le = get_tx_le(sky2); 1457 le->addr = cpu_to_le32(addr64); 1458 le->ctrl = 0; 1459 le->opcode = OP_ADDR64 | HW_OWNER; 1460 sky2->tx_addr64 = addr64; 1461 } 1462 1463 le = get_tx_le(sky2); 1464 le->addr = cpu_to_le32((u32) mapping); 1465 le->length = cpu_to_le16(frag->size); 1466 le->ctrl = ctrl; 1467 le->opcode = OP_BUFFER | HW_OWNER; 1468 1469 re = tx_le_re(sky2, le); 1470 re->skb = skb; 1471 pci_unmap_addr_set(re, mapaddr, mapping); 1472 pci_unmap_len_set(re, maplen, frag->size); 1473 } 1474 1475 le->ctrl |= EOP; 1476 1477 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1478 netif_stop_queue(dev); 1479 1480 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1481 1482 dev->trans_start = jiffies; 1483 return NETDEV_TX_OK; 1484} 1485 1486/* 1487 * Free ring elements from starting at tx_cons until "done" 1488 * 1489 * NB: the hardware will tell us about partial completion of multi-part 1490 * buffers so make sure not to free skb to early. 1491 */ 1492static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 1493{ 1494 struct net_device *dev = sky2->netdev; 1495 struct pci_dev *pdev = sky2->hw->pdev; 1496 unsigned idx; 1497 1498 BUG_ON(done >= TX_RING_SIZE); 1499 1500 for (idx = sky2->tx_cons; idx != done; 1501 idx = RING_NEXT(idx, TX_RING_SIZE)) { 1502 struct sky2_tx_le *le = sky2->tx_le + idx; 1503 struct tx_ring_info *re = sky2->tx_ring + idx; 1504 1505 switch(le->opcode & ~HW_OWNER) { 1506 case OP_LARGESEND: 1507 case OP_PACKET: 1508 pci_unmap_single(pdev, 1509 pci_unmap_addr(re, mapaddr), 1510 pci_unmap_len(re, maplen), 1511 PCI_DMA_TODEVICE); 1512 break; 1513 case OP_BUFFER: 1514 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr), 1515 pci_unmap_len(re, maplen), 1516 PCI_DMA_TODEVICE); 1517 break; 1518 } 1519 1520 if (le->ctrl & EOP) { 1521 if (unlikely(netif_msg_tx_done(sky2))) 1522 printk(KERN_DEBUG "%s: tx done %u\n", 1523 dev->name, idx); 1524 sky2->net_stats.tx_packets++; 1525 sky2->net_stats.tx_bytes += re->skb->len; 1526 1527 dev_kfree_skb_any(re->skb); 1528 } 1529 1530 le->opcode = 0; /* paranoia */ 1531 } 1532 1533 sky2->tx_cons = idx; 1534 smp_mb(); 1535 1536 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 1537 netif_wake_queue(dev); 1538} 1539 1540/* Cleanup all untransmitted buffers, assume transmitter not running */ 1541static void sky2_tx_clean(struct net_device *dev) 1542{ 1543 struct sky2_port *sky2 = netdev_priv(dev); 1544 1545 netif_tx_lock_bh(dev); 1546 sky2_tx_complete(sky2, sky2->tx_prod); 1547 netif_tx_unlock_bh(dev); 1548} 1549 1550/* Network shutdown */ 1551static int sky2_down(struct net_device *dev) 1552{ 1553 struct sky2_port *sky2 = netdev_priv(dev); 1554 struct sky2_hw *hw = sky2->hw; 1555 unsigned port = sky2->port; 1556 u16 ctrl; 1557 u32 imask; 1558 1559 /* Never really got started! */ 1560 if (!sky2->tx_le) 1561 return 0; 1562 1563 if (netif_msg_ifdown(sky2)) 1564 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); 1565 1566 /* Stop more packets from being queued */ 1567 netif_stop_queue(dev); 1568 netif_carrier_off(dev); 1569 1570 /* Disable port IRQ */ 1571 imask = sky2_read32(hw, B0_IMSK); 1572 imask &= ~portirq_msk[port]; 1573 sky2_write32(hw, B0_IMSK, imask); 1574 1575 sky2_gmac_reset(hw, port); 1576 1577 /* Stop transmitter */ 1578 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 1579 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 1580 1581 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 1582 RB_RST_SET | RB_DIS_OP_MD); 1583 1584 ctrl = gma_read16(hw, port, GM_GP_CTRL); 1585 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 1586 gma_write16(hw, port, GM_GP_CTRL, ctrl); 1587 1588 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 1589 1590 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 1591 && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 1592 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 1593 1594 /* Disable Force Sync bit and Enable Alloc bit */ 1595 sky2_write8(hw, SK_REG(port, TXA_CTRL), 1596 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 1597 1598 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 1599 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 1600 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 1601 1602 /* Reset the PCI FIFO of the async Tx queue */ 1603 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 1604 BMU_RST_SET | BMU_FIFO_RST); 1605 1606 /* Reset the Tx prefetch units */ 1607 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 1608 PREF_UNIT_RST_SET); 1609 1610 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 1611 1612 sky2_rx_stop(sky2); 1613 1614 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 1615 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 1616 1617 sky2_phy_power(hw, port, 0); 1618 1619 /* turn off LED's */ 1620 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); 1621 1622 synchronize_irq(hw->pdev->irq); 1623 1624 sky2_tx_clean(dev); 1625 sky2_rx_clean(sky2); 1626 1627 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1628 sky2->rx_le, sky2->rx_le_map); 1629 kfree(sky2->rx_ring); 1630 1631 pci_free_consistent(hw->pdev, 1632 TX_RING_SIZE * sizeof(struct sky2_tx_le), 1633 sky2->tx_le, sky2->tx_le_map); 1634 kfree(sky2->tx_ring); 1635 1636 sky2->tx_le = NULL; 1637 sky2->rx_le = NULL; 1638 1639 sky2->rx_ring = NULL; 1640 sky2->tx_ring = NULL; 1641 1642 return 0; 1643} 1644 1645static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 1646{ 1647 if (!sky2_is_copper(hw)) 1648 return SPEED_1000; 1649 1650 if (hw->chip_id == CHIP_ID_YUKON_FE) 1651 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; 1652 1653 switch (aux & PHY_M_PS_SPEED_MSK) { 1654 case PHY_M_PS_SPEED_1000: 1655 return SPEED_1000; 1656 case PHY_M_PS_SPEED_100: 1657 return SPEED_100; 1658 default: 1659 return SPEED_10; 1660 } 1661} 1662 1663static void sky2_link_up(struct sky2_port *sky2) 1664{ 1665 struct sky2_hw *hw = sky2->hw; 1666 unsigned port = sky2->port; 1667 u16 reg; 1668 static const char *fc_name[] = { 1669 [FC_NONE] = "none", 1670 [FC_TX] = "tx", 1671 [FC_RX] = "rx", 1672 [FC_BOTH] = "both", 1673 }; 1674 1675 /* enable Rx/Tx */ 1676 reg = gma_read16(hw, port, GM_GP_CTRL); 1677 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 1678 gma_write16(hw, port, GM_GP_CTRL, reg); 1679 1680 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 1681 1682 netif_carrier_on(sky2->netdev); 1683 netif_wake_queue(sky2->netdev); 1684 1685 /* Turn on link LED */ 1686 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 1687 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 1688 1689 if (hw->chip_id == CHIP_ID_YUKON_XL 1690 || hw->chip_id == CHIP_ID_YUKON_EC_U 1691 || hw->chip_id == CHIP_ID_YUKON_EX) { 1692 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 1693 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */ 1694 1695 switch(sky2->speed) { 1696 case SPEED_10: 1697 led |= PHY_M_LEDC_INIT_CTRL(7); 1698 break; 1699 1700 case SPEED_100: 1701 led |= PHY_M_LEDC_STA1_CTRL(7); 1702 break; 1703 1704 case SPEED_1000: 1705 led |= PHY_M_LEDC_STA0_CTRL(7); 1706 break; 1707 } 1708 1709 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 1710 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led); 1711 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 1712 } 1713 1714 if (netif_msg_link(sky2)) 1715 printk(KERN_INFO PFX 1716 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", 1717 sky2->netdev->name, sky2->speed, 1718 sky2->duplex == DUPLEX_FULL ? "full" : "half", 1719 fc_name[sky2->flow_status]); 1720} 1721 1722static void sky2_link_down(struct sky2_port *sky2) 1723{ 1724 struct sky2_hw *hw = sky2->hw; 1725 unsigned port = sky2->port; 1726 u16 reg; 1727 1728 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 1729 1730 reg = gma_read16(hw, port, GM_GP_CTRL); 1731 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 1732 gma_write16(hw, port, GM_GP_CTRL, reg); 1733 1734 netif_carrier_off(sky2->netdev); 1735 netif_stop_queue(sky2->netdev); 1736 1737 /* Turn on link LED */ 1738 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 1739 1740 if (netif_msg_link(sky2)) 1741 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); 1742 1743 sky2_phy_init(hw, port); 1744} 1745 1746static enum flow_control sky2_flow(int rx, int tx) 1747{ 1748 if (rx) 1749 return tx ? FC_BOTH : FC_RX; 1750 else 1751 return tx ? FC_TX : FC_NONE; 1752} 1753 1754static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 1755{ 1756 struct sky2_hw *hw = sky2->hw; 1757 unsigned port = sky2->port; 1758 u16 advert, lpa; 1759 1760 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 1761 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 1762 if (lpa & PHY_M_AN_RF) { 1763 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); 1764 return -1; 1765 } 1766 1767 if (!(aux & PHY_M_PS_SPDUP_RES)) { 1768 printk(KERN_ERR PFX "%s: speed/duplex mismatch", 1769 sky2->netdev->name); 1770 return -1; 1771 } 1772 1773 sky2->speed = sky2_phy_speed(hw, aux); 1774 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 1775 1776 /* Since the pause result bits seem to in different positions on 1777 * different chips. look at registers. 1778 */ 1779 if (!sky2_is_copper(hw)) { 1780 /* Shift for bits in fiber PHY */ 1781 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 1782 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 1783 1784 if (advert & ADVERTISE_1000XPAUSE) 1785 advert |= ADVERTISE_PAUSE_CAP; 1786 if (advert & ADVERTISE_1000XPSE_ASYM) 1787 advert |= ADVERTISE_PAUSE_ASYM; 1788 if (lpa & LPA_1000XPAUSE) 1789 lpa |= LPA_PAUSE_CAP; 1790 if (lpa & LPA_1000XPAUSE_ASYM) 1791 lpa |= LPA_PAUSE_ASYM; 1792 } 1793 1794 sky2->flow_status = FC_NONE; 1795 if (advert & ADVERTISE_PAUSE_CAP) { 1796 if (lpa & LPA_PAUSE_CAP) 1797 sky2->flow_status = FC_BOTH; 1798 else if (advert & ADVERTISE_PAUSE_ASYM) 1799 sky2->flow_status = FC_RX; 1800 } else if (advert & ADVERTISE_PAUSE_ASYM) { 1801 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 1802 sky2->flow_status = FC_TX; 1803 } 1804 1805 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 1806 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 1807 sky2->flow_status = FC_NONE; 1808 1809 if (sky2->flow_status & FC_TX) 1810 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 1811 else 1812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 1813 1814 return 0; 1815} 1816 1817/* Interrupt from PHY */ 1818static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 1819{ 1820 struct net_device *dev = hw->dev[port]; 1821 struct sky2_port *sky2 = netdev_priv(dev); 1822 u16 istatus, phystat; 1823 1824 if (!netif_running(dev)) 1825 return; 1826 1827 spin_lock(&sky2->phy_lock); 1828 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 1829 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 1830 1831 if (netif_msg_intr(sky2)) 1832 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", 1833 sky2->netdev->name, istatus, phystat); 1834 1835 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) { 1836 if (sky2_autoneg_done(sky2, phystat) == 0) 1837 sky2_link_up(sky2); 1838 goto out; 1839 } 1840 1841 if (istatus & PHY_M_IS_LSP_CHANGE) 1842 sky2->speed = sky2_phy_speed(hw, phystat); 1843 1844 if (istatus & PHY_M_IS_DUP_CHANGE) 1845 sky2->duplex = 1846 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 1847 1848 if (istatus & PHY_M_IS_LST_CHANGE) { 1849 if (phystat & PHY_M_PS_LINK_UP) 1850 sky2_link_up(sky2); 1851 else 1852 sky2_link_down(sky2); 1853 } 1854out: 1855 spin_unlock(&sky2->phy_lock); 1856} 1857 1858/* Transmit timeout is only called if we are running, carrier is up 1859 * and tx queue is full (stopped). 1860 */ 1861static void sky2_tx_timeout(struct net_device *dev) 1862{ 1863 struct sky2_port *sky2 = netdev_priv(dev); 1864 struct sky2_hw *hw = sky2->hw; 1865 1866 if (netif_msg_timer(sky2)) 1867 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); 1868 1869 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n", 1870 dev->name, sky2->tx_cons, sky2->tx_prod, 1871 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 1872 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 1873 1874 /* can't restart safely under softirq */ 1875 schedule_work(&hw->restart_work); 1876} 1877 1878static int sky2_change_mtu(struct net_device *dev, int new_mtu) 1879{ 1880 struct sky2_port *sky2 = netdev_priv(dev); 1881 struct sky2_hw *hw = sky2->hw; 1882 unsigned port = sky2->port; 1883 int err; 1884 u16 ctl, mode; 1885 u32 imask; 1886 1887 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) 1888 return -EINVAL; 1889 1890 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE) 1891 return -EINVAL; 1892 1893 if (!netif_running(dev)) { 1894 dev->mtu = new_mtu; 1895 return 0; 1896 } 1897 1898 imask = sky2_read32(hw, B0_IMSK); 1899 sky2_write32(hw, B0_IMSK, 0); 1900 1901 dev->trans_start = jiffies; /* prevent tx timeout */ 1902 netif_stop_queue(dev); 1903 netif_poll_disable(hw->dev[0]); 1904 1905 synchronize_irq(hw->pdev->irq); 1906 1907 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) { 1908 if (new_mtu > ETH_DATA_LEN) { 1909 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1910 TX_JUMBO_ENA | TX_STFW_DIS); 1911 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM; 1912 } else 1913 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1914 TX_JUMBO_DIS | TX_STFW_ENA); 1915 } 1916 1917 ctl = gma_read16(hw, port, GM_GP_CTRL); 1918 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 1919 sky2_rx_stop(sky2); 1920 sky2_rx_clean(sky2); 1921 1922 dev->mtu = new_mtu; 1923 1924 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | 1925 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 1926 1927 if (dev->mtu > ETH_DATA_LEN) 1928 mode |= GM_SMOD_JUMBO_ENA; 1929 1930 gma_write16(hw, port, GM_SERIAL_MODE, mode); 1931 1932 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 1933 1934 err = sky2_rx_start(sky2); 1935 sky2_write32(hw, B0_IMSK, imask); 1936 1937 if (err) 1938 dev_close(dev); 1939 else { 1940 gma_write16(hw, port, GM_GP_CTRL, ctl); 1941 1942 netif_poll_enable(hw->dev[0]); 1943 netif_wake_queue(dev); 1944 } 1945 1946 return err; 1947} 1948 1949/* For small just reuse existing skb for next receive */ 1950static struct sk_buff *receive_copy(struct sky2_port *sky2, 1951 const struct rx_ring_info *re, 1952 unsigned length) 1953{ 1954 struct sk_buff *skb; 1955 1956 skb = netdev_alloc_skb(sky2->netdev, length + 2); 1957 if (likely(skb)) { 1958 skb_reserve(skb, 2); 1959 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, 1960 length, PCI_DMA_FROMDEVICE); 1961 skb_copy_from_linear_data(re->skb, skb->data, length); 1962 skb->ip_summed = re->skb->ip_summed; 1963 skb->csum = re->skb->csum; 1964 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 1965 length, PCI_DMA_FROMDEVICE); 1966 re->skb->ip_summed = CHECKSUM_NONE; 1967 skb_put(skb, length); 1968 } 1969 return skb; 1970} 1971 1972/* Adjust length of skb with fragments to match received data */ 1973static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 1974 unsigned int length) 1975{ 1976 int i, num_frags; 1977 unsigned int size; 1978 1979 /* put header into skb */ 1980 size = min(length, hdr_space); 1981 skb->tail += size; 1982 skb->len += size; 1983 length -= size; 1984 1985 num_frags = skb_shinfo(skb)->nr_frags; 1986 for (i = 0; i < num_frags; i++) { 1987 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1988 1989 if (length == 0) { 1990 /* don't need this page */ 1991 __free_page(frag->page); 1992 --skb_shinfo(skb)->nr_frags; 1993 } else { 1994 size = min(length, (unsigned) PAGE_SIZE); 1995 1996 frag->size = size; 1997 skb->data_len += size; 1998 skb->truesize += size; 1999 skb->len += size; 2000 length -= size; 2001 } 2002 } 2003} 2004 2005/* Normal packet - take skb from ring element and put in a new one */ 2006static struct sk_buff *receive_new(struct sky2_port *sky2, 2007 struct rx_ring_info *re, 2008 unsigned int length) 2009{ 2010 struct sk_buff *skb, *nskb; 2011 unsigned hdr_space = sky2->rx_data_size; 2012 2013 pr_debug(PFX "receive new length=%d\n", length); 2014 2015 /* Don't be tricky about reusing pages (yet) */ 2016 nskb = sky2_rx_alloc(sky2); 2017 if (unlikely(!nskb)) 2018 return NULL; 2019 2020 skb = re->skb; 2021 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2022 2023 prefetch(skb->data); 2024 re->skb = nskb; 2025 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space); 2026 2027 if (skb_shinfo(skb)->nr_frags) 2028 skb_put_frags(skb, hdr_space, length); 2029 else 2030 skb_put(skb, length); 2031 return skb; 2032} 2033 2034/* 2035 * Receive one packet. 2036 * For larger packets, get new buffer. 2037 */ 2038static struct sk_buff *sky2_receive(struct net_device *dev, 2039 u16 length, u32 status) 2040{ 2041 struct sky2_port *sky2 = netdev_priv(dev); 2042 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2043 struct sk_buff *skb = NULL; 2044 2045 if (unlikely(netif_msg_rx_status(sky2))) 2046 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", 2047 dev->name, sky2->rx_next, status, length); 2048 2049 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2050 prefetch(sky2->rx_ring + sky2->rx_next); 2051 2052 if (status & GMR_FS_ANY_ERR) 2053 goto error; 2054 2055 if (!(status & GMR_FS_RX_OK)) 2056 goto resubmit; 2057 2058 if (length < copybreak) 2059 skb = receive_copy(sky2, re, length); 2060 else 2061 skb = receive_new(sky2, re, length); 2062resubmit: 2063 sky2_rx_submit(sky2, re); 2064 2065 return skb; 2066 2067error: 2068 ++sky2->net_stats.rx_errors; 2069 if (status & GMR_FS_RX_FF_OV) { 2070 sky2->net_stats.rx_over_errors++; 2071 goto resubmit; 2072 } 2073 2074 if (netif_msg_rx_err(sky2) && net_ratelimit()) 2075 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", 2076 dev->name, status, length); 2077 2078 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) 2079 sky2->net_stats.rx_length_errors++; 2080 if (status & GMR_FS_FRAGMENT) 2081 sky2->net_stats.rx_frame_errors++; 2082 if (status & GMR_FS_CRC_ERR) 2083 sky2->net_stats.rx_crc_errors++; 2084 2085 goto resubmit; 2086} 2087 2088/* Transmit complete */ 2089static inline void sky2_tx_done(struct net_device *dev, u16 last) 2090{ 2091 struct sky2_port *sky2 = netdev_priv(dev); 2092 2093 if (netif_running(dev)) { 2094 netif_tx_lock(dev); 2095 sky2_tx_complete(sky2, last); 2096 netif_tx_unlock(dev); 2097 } 2098} 2099 2100/* Process status response ring */ 2101static int sky2_status_intr(struct sky2_hw *hw, int to_do) 2102{ 2103 struct sky2_port *sky2; 2104 int work_done = 0; 2105 unsigned buf_write[2] = { 0, 0 }; 2106 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX); 2107 2108 rmb(); 2109 2110 while (hw->st_idx != hwidx) { 2111 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2112 struct net_device *dev; 2113 struct sk_buff *skb; 2114 u32 status; 2115 u16 length; 2116 2117 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE); 2118 2119 BUG_ON(le->link >= 2); 2120 dev = hw->dev[le->link]; 2121 2122 sky2 = netdev_priv(dev); 2123 length = le16_to_cpu(le->length); 2124 status = le32_to_cpu(le->status); 2125 2126 switch (le->opcode & ~HW_OWNER) { 2127 case OP_RXSTAT: 2128 skb = sky2_receive(dev, length, status); 2129 if (unlikely(!skb)) { 2130 sky2->net_stats.rx_dropped++; 2131 goto force_update; 2132 } 2133 2134 skb->protocol = eth_type_trans(skb, dev); 2135 sky2->net_stats.rx_packets++; 2136 sky2->net_stats.rx_bytes += skb->len; 2137 dev->last_rx = jiffies; 2138 2139#ifdef SKY2_VLAN_TAG_USED 2140 if (sky2->vlgrp && (status & GMR_FS_VLAN)) { 2141 vlan_hwaccel_receive_skb(skb, 2142 sky2->vlgrp, 2143 be16_to_cpu(sky2->rx_tag)); 2144 } else 2145#endif 2146 netif_receive_skb(skb); 2147 2148 /* Update receiver after 16 frames */ 2149 if (++buf_write[le->link] == RX_BUF_WRITE) { 2150force_update: 2151 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put); 2152 buf_write[le->link] = 0; 2153 } 2154 2155 /* Stop after net poll weight */ 2156 if (++work_done >= to_do) 2157 goto exit_loop; 2158 break; 2159 2160#ifdef SKY2_VLAN_TAG_USED 2161 case OP_RXVLAN: 2162 sky2->rx_tag = length; 2163 break; 2164 2165 case OP_RXCHKSVLAN: 2166 sky2->rx_tag = length; 2167 /* fall through */ 2168#endif 2169 case OP_RXCHKS: 2170 if (!sky2->rx_csum) 2171 break; 2172 2173 /* Both checksum counters are programmed to start at 2174 * the same offset, so unless there is a problem they 2175 * should match. This failure is an early indication that 2176 * hardware receive checksumming won't work. 2177 */ 2178 if (likely(status >> 16 == (status & 0xffff))) { 2179 skb = sky2->rx_ring[sky2->rx_next].skb; 2180 skb->ip_summed = CHECKSUM_COMPLETE; 2181 skb->csum = status & 0xffff; 2182 } else { 2183 printk(KERN_NOTICE PFX "%s: hardware receive " 2184 "checksum problem (status = %#x)\n", 2185 dev->name, status); 2186 sky2->rx_csum = 0; 2187 sky2_write32(sky2->hw, 2188 Q_ADDR(rxqaddr[le->link], Q_CSR), 2189 BMU_DIS_RX_CHKSUM); 2190 } 2191 break; 2192 2193 case OP_TXINDEXLE: 2194 /* TX index reports status for both ports */ 2195 BUILD_BUG_ON(TX_RING_SIZE > 0x1000); 2196 sky2_tx_done(hw->dev[0], status & 0xfff); 2197 if (hw->dev[1]) 2198 sky2_tx_done(hw->dev[1], 2199 ((status >> 24) & 0xff) 2200 | (u16)(length & 0xf) << 8); 2201 break; 2202 2203 default: 2204 if (net_ratelimit()) 2205 printk(KERN_WARNING PFX 2206 "unknown status opcode 0x%x\n", le->opcode); 2207 goto exit_loop; 2208 } 2209 } 2210 2211 /* Fully processed status ring so clear irq */ 2212 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2213 mmiowb(); 2214 2215exit_loop: 2216 if (buf_write[0]) { 2217 sky2 = netdev_priv(hw->dev[0]); 2218 sky2_put_idx(hw, Q_R1, sky2->rx_put); 2219 } 2220 2221 if (buf_write[1]) { 2222 sky2 = netdev_priv(hw->dev[1]); 2223 sky2_put_idx(hw, Q_R2, sky2->rx_put); 2224 } 2225 2226 return work_done; 2227} 2228 2229static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2230{ 2231 struct net_device *dev = hw->dev[port]; 2232 2233 if (net_ratelimit()) 2234 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", 2235 dev->name, status); 2236 2237 if (status & Y2_IS_PAR_RD1) { 2238 if (net_ratelimit()) 2239 printk(KERN_ERR PFX "%s: ram data read parity error\n", 2240 dev->name); 2241 /* Clear IRQ */ 2242 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2243 } 2244 2245 if (status & Y2_IS_PAR_WR1) { 2246 if (net_ratelimit()) 2247 printk(KERN_ERR PFX "%s: ram data write parity error\n", 2248 dev->name); 2249 2250 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2251 } 2252 2253 if (status & Y2_IS_PAR_MAC1) { 2254 if (net_ratelimit()) 2255 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); 2256 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2257 } 2258 2259 if (status & Y2_IS_PAR_RX1) { 2260 if (net_ratelimit()) 2261 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); 2262 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2263 } 2264 2265 if (status & Y2_IS_TCP_TXA1) { 2266 if (net_ratelimit()) 2267 printk(KERN_ERR PFX "%s: TCP segmentation error\n", 2268 dev->name); 2269 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2270 } 2271} 2272 2273static void sky2_hw_intr(struct sky2_hw *hw) 2274{ 2275 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2276 2277 if (status & Y2_IS_TIST_OV) 2278 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2279 2280 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2281 u16 pci_err; 2282 2283 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2284 if (net_ratelimit()) 2285 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n", 2286 pci_err); 2287 2288 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2289 sky2_pci_write16(hw, PCI_STATUS, 2290 pci_err | PCI_STATUS_ERROR_BITS); 2291 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2292 } 2293 2294 if (status & Y2_IS_PCI_EXP) { 2295 /* PCI-Express uncorrectable Error occurred */ 2296 u32 pex_err; 2297 2298 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); 2299 2300 if (net_ratelimit()) 2301 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n", 2302 pex_err); 2303 2304 /* clear the interrupt */ 2305 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2306 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 2307 0xffffffffUL); 2308 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2309 2310 if (pex_err & PEX_FATAL_ERRORS) { 2311 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2312 hwmsk &= ~Y2_IS_PCI_EXP; 2313 sky2_write32(hw, B0_HWE_IMSK, hwmsk); 2314 } 2315 } 2316 2317 if (status & Y2_HWE_L1_MASK) 2318 sky2_hw_error(hw, 0, status); 2319 status >>= 8; 2320 if (status & Y2_HWE_L1_MASK) 2321 sky2_hw_error(hw, 1, status); 2322} 2323 2324static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2325{ 2326 struct net_device *dev = hw->dev[port]; 2327 struct sky2_port *sky2 = netdev_priv(dev); 2328 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2329 2330 if (netif_msg_intr(sky2)) 2331 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", 2332 dev->name, status); 2333 2334 if (status & GM_IS_RX_CO_OV) 2335 gma_read16(hw, port, GM_RX_IRQ_SRC); 2336 2337 if (status & GM_IS_TX_CO_OV) 2338 gma_read16(hw, port, GM_TX_IRQ_SRC); 2339 2340 if (status & GM_IS_RX_FF_OR) { 2341 ++sky2->net_stats.rx_fifo_errors; 2342 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2343 } 2344 2345 if (status & GM_IS_TX_FF_UR) { 2346 ++sky2->net_stats.tx_fifo_errors; 2347 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2348 } 2349} 2350 2351/* This should never happen it is a bug. */ 2352static void sky2_le_error(struct sky2_hw *hw, unsigned port, 2353 u16 q, unsigned ring_size) 2354{ 2355 struct net_device *dev = hw->dev[port]; 2356 struct sky2_port *sky2 = netdev_priv(dev); 2357 unsigned idx; 2358 const u64 *le = (q == Q_R1 || q == Q_R2) 2359 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le; 2360 2361 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2362 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n", 2363 dev->name, (unsigned) q, idx, (unsigned long long) le[idx], 2364 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2365 2366 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2367} 2368 2369static inline void sky2_idle_start(struct sky2_hw *hw) 2370{ 2371 if (idle_timeout > 0) 2372 mod_timer(&hw->idle_timer, 2373 jiffies + msecs_to_jiffies(idle_timeout)); 2374} 2375 2376static void sky2_idle(unsigned long arg) 2377{ 2378 struct sky2_hw *hw = (struct sky2_hw *) arg; 2379 struct net_device *dev = hw->dev[0]; 2380 2381 if (__netif_rx_schedule_prep(dev)) 2382 __netif_rx_schedule(dev); 2383 2384 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout)); 2385} 2386 2387/* Hardware/software error handling */ 2388static void sky2_err_intr(struct sky2_hw *hw, u32 status) 2389{ 2390 if (net_ratelimit()) 2391 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 2392 2393 if (status & Y2_IS_HW_ERR) 2394 sky2_hw_intr(hw); 2395 2396 if (status & Y2_IS_IRQ_MAC1) 2397 sky2_mac_intr(hw, 0); 2398 2399 if (status & Y2_IS_IRQ_MAC2) 2400 sky2_mac_intr(hw, 1); 2401 2402 if (status & Y2_IS_CHK_RX1) 2403 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE); 2404 2405 if (status & Y2_IS_CHK_RX2) 2406 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE); 2407 2408 if (status & Y2_IS_CHK_TXA1) 2409 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE); 2410 2411 if (status & Y2_IS_CHK_TXA2) 2412 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE); 2413} 2414 2415static int sky2_poll(struct net_device *dev0, int *budget) 2416{ 2417 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; 2418 int work_limit = min(dev0->quota, *budget); 2419 int work_done = 0; 2420 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 2421 2422 if (unlikely(status & Y2_IS_ERROR)) 2423 sky2_err_intr(hw, status); 2424 2425 if (status & Y2_IS_IRQ_PHY1) 2426 sky2_phy_intr(hw, 0); 2427 2428 if (status & Y2_IS_IRQ_PHY2) 2429 sky2_phy_intr(hw, 1); 2430 2431 work_done = sky2_status_intr(hw, work_limit); 2432 if (work_done < work_limit) { 2433 netif_rx_complete(dev0); 2434 2435 /* end of interrupt, re-enables also acts as I/O synchronization */ 2436 sky2_read32(hw, B0_Y2_SP_LISR); 2437 return 0; 2438 } else { 2439 *budget -= work_done; 2440 dev0->quota -= work_done; 2441 return 1; 2442 } 2443} 2444 2445static irqreturn_t sky2_intr(int irq, void *dev_id) 2446{ 2447 struct sky2_hw *hw = dev_id; 2448 struct net_device *dev0 = hw->dev[0]; 2449 u32 status; 2450 2451 /* Reading this mask interrupts as side effect */ 2452 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 2453 if (status == 0 || status == ~0) 2454 return IRQ_NONE; 2455 2456 prefetch(&hw->st_le[hw->st_idx]); 2457 if (likely(__netif_rx_schedule_prep(dev0))) 2458 __netif_rx_schedule(dev0); 2459 2460 return IRQ_HANDLED; 2461} 2462 2463#ifdef CONFIG_NET_POLL_CONTROLLER 2464static void sky2_netpoll(struct net_device *dev) 2465{ 2466 struct sky2_port *sky2 = netdev_priv(dev); 2467 struct net_device *dev0 = sky2->hw->dev[0]; 2468 2469 if (netif_running(dev) && __netif_rx_schedule_prep(dev0)) 2470 __netif_rx_schedule(dev0); 2471} 2472#endif 2473 2474/* Chip internal frequency for clock calculations */ 2475static inline u32 sky2_mhz(const struct sky2_hw *hw) 2476{ 2477 switch (hw->chip_id) { 2478 case CHIP_ID_YUKON_EC: 2479 case CHIP_ID_YUKON_EC_U: 2480 case CHIP_ID_YUKON_EX: 2481 return 125; /* 125 Mhz */ 2482 case CHIP_ID_YUKON_FE: 2483 return 100; /* 100 Mhz */ 2484 default: /* YUKON_XL */ 2485 return 156; /* 156 Mhz */ 2486 } 2487} 2488 2489static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 2490{ 2491 return sky2_mhz(hw) * us; 2492} 2493 2494static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 2495{ 2496 return clk / sky2_mhz(hw); 2497} 2498 2499 2500static int __devinit sky2_init(struct sky2_hw *hw) 2501{ 2502 u8 t8; 2503 2504 sky2_write8(hw, B0_CTST, CS_RST_CLR); 2505 2506 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 2507 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { 2508 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 2509 hw->chip_id); 2510 return -EOPNOTSUPP; 2511 } 2512 2513 if (hw->chip_id == CHIP_ID_YUKON_EX) 2514 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n" 2515 "Please report success or failure to <netdev@vger.kernel.org>\n"); 2516 2517 /* Make sure and enable all clocks */ 2518 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U) 2519 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 2520 2521 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 2522 2523 /* This rev is really old, and requires untested workarounds */ 2524 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) { 2525 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n", 2526 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], 2527 hw->chip_id, hw->chip_rev); 2528 return -EOPNOTSUPP; 2529 } 2530 2531 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 2532 hw->ports = 1; 2533 t8 = sky2_read8(hw, B2_Y2_HW_RES); 2534 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 2535 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 2536 ++hw->ports; 2537 } 2538 2539 return 0; 2540} 2541 2542static void sky2_reset(struct sky2_hw *hw) 2543{ 2544 u16 status; 2545 int i; 2546 2547 /* disable ASF */ 2548 if (hw->chip_id == CHIP_ID_YUKON_EX) { 2549 status = sky2_read16(hw, HCU_CCSR); 2550 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 2551 HCU_CCSR_UC_STATE_MSK); 2552 sky2_write16(hw, HCU_CCSR, status); 2553 } else 2554 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 2555 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 2556 2557 /* do a SW reset */ 2558 sky2_write8(hw, B0_CTST, CS_RST_SET); 2559 sky2_write8(hw, B0_CTST, CS_RST_CLR); 2560 2561 /* clear PCI errors, if any */ 2562 status = sky2_pci_read16(hw, PCI_STATUS); 2563 2564 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2565 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS); 2566 2567 2568 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 2569 2570 /* clear any PEX errors */ 2571 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) 2572 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); 2573 2574 2575 sky2_power_on(hw); 2576 2577 for (i = 0; i < hw->ports; i++) { 2578 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 2579 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 2580 } 2581 2582 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2583 2584 /* Clear I2C IRQ noise */ 2585 sky2_write32(hw, B2_I2C_IRQ, 1); 2586 2587 /* turn off hardware timer (unused) */ 2588 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 2589 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 2590 2591 sky2_write8(hw, B0_Y2LED, LED_STAT_ON); 2592 2593 /* Turn off descriptor polling */ 2594 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 2595 2596 /* Turn off receive timestamp */ 2597 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 2598 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2599 2600 /* enable the Tx Arbiters */ 2601 for (i = 0; i < hw->ports; i++) 2602 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 2603 2604 /* Initialize ram interface */ 2605 for (i = 0; i < hw->ports; i++) { 2606 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 2607 2608 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 2609 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 2610 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 2611 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 2612 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 2613 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 2614 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 2615 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 2616 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 2617 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 2619 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 2620 } 2621 2622 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); 2623 2624 for (i = 0; i < hw->ports; i++) 2625 sky2_gmac_reset(hw, i); 2626 2627 memset(hw->st_le, 0, STATUS_LE_BYTES); 2628 hw->st_idx = 0; 2629 2630 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 2631 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 2632 2633 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 2634 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 2635 2636 /* Set the list last index */ 2637 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); 2638 2639 sky2_write16(hw, STAT_TX_IDX_TH, 10); 2640 sky2_write8(hw, STAT_FIFO_WM, 16); 2641 2642 /* set Status-FIFO ISR watermark */ 2643 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 2644 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 2645 else 2646 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 2647 2648 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 2649 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 2650 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 2651 2652 /* enable status unit */ 2653 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 2654 2655 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 2656 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 2657 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 2658} 2659 2660static void sky2_restart(struct work_struct *work) 2661{ 2662 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 2663 struct net_device *dev; 2664 int i, err; 2665 2666 dev_dbg(&hw->pdev->dev, "restarting\n"); 2667 2668 del_timer_sync(&hw->idle_timer); 2669 2670 rtnl_lock(); 2671 sky2_write32(hw, B0_IMSK, 0); 2672 sky2_read32(hw, B0_IMSK); 2673 2674 netif_poll_disable(hw->dev[0]); 2675 2676 for (i = 0; i < hw->ports; i++) { 2677 dev = hw->dev[i]; 2678 if (netif_running(dev)) 2679 sky2_down(dev); 2680 } 2681 2682 sky2_reset(hw); 2683 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 2684 netif_poll_enable(hw->dev[0]); 2685 2686 for (i = 0; i < hw->ports; i++) { 2687 dev = hw->dev[i]; 2688 if (netif_running(dev)) { 2689 err = sky2_up(dev); 2690 if (err) { 2691 printk(KERN_INFO PFX "%s: could not restart %d\n", 2692 dev->name, err); 2693 dev_close(dev); 2694 } 2695 } 2696 } 2697 2698 sky2_idle_start(hw); 2699 2700 rtnl_unlock(); 2701} 2702 2703static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 2704{ 2705 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 2706} 2707 2708static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2709{ 2710 const struct sky2_port *sky2 = netdev_priv(dev); 2711 2712 wol->supported = sky2_wol_supported(sky2->hw); 2713 wol->wolopts = sky2->wol; 2714} 2715 2716static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2717{ 2718 struct sky2_port *sky2 = netdev_priv(dev); 2719 struct sky2_hw *hw = sky2->hw; 2720 2721 if (wol->wolopts & ~sky2_wol_supported(sky2->hw)) 2722 return -EOPNOTSUPP; 2723 2724 sky2->wol = wol->wolopts; 2725 2726 if (hw->chip_id == CHIP_ID_YUKON_EC_U) 2727 sky2_write32(hw, B0_CTST, sky2->wol 2728 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF); 2729 2730 if (!netif_running(dev)) 2731 sky2_wol_init(sky2); 2732 return 0; 2733} 2734 2735static u32 sky2_supported_modes(const struct sky2_hw *hw) 2736{ 2737 if (sky2_is_copper(hw)) { 2738 u32 modes = SUPPORTED_10baseT_Half 2739 | SUPPORTED_10baseT_Full 2740 | SUPPORTED_100baseT_Half 2741 | SUPPORTED_100baseT_Full 2742 | SUPPORTED_Autoneg | SUPPORTED_TP; 2743 2744 if (hw->chip_id != CHIP_ID_YUKON_FE) 2745 modes |= SUPPORTED_1000baseT_Half 2746 | SUPPORTED_1000baseT_Full; 2747 return modes; 2748 } else 2749 return SUPPORTED_1000baseT_Half 2750 | SUPPORTED_1000baseT_Full 2751 | SUPPORTED_Autoneg 2752 | SUPPORTED_FIBRE; 2753} 2754 2755static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2756{ 2757 struct sky2_port *sky2 = netdev_priv(dev); 2758 struct sky2_hw *hw = sky2->hw; 2759 2760 ecmd->transceiver = XCVR_INTERNAL; 2761 ecmd->supported = sky2_supported_modes(hw); 2762 ecmd->phy_address = PHY_ADDR_MARV; 2763 if (sky2_is_copper(hw)) { 2764 ecmd->supported = SUPPORTED_10baseT_Half 2765 | SUPPORTED_10baseT_Full 2766 | SUPPORTED_100baseT_Half 2767 | SUPPORTED_100baseT_Full 2768 | SUPPORTED_1000baseT_Half 2769 | SUPPORTED_1000baseT_Full 2770 | SUPPORTED_Autoneg | SUPPORTED_TP; 2771 ecmd->port = PORT_TP; 2772 ecmd->speed = sky2->speed; 2773 } else { 2774 ecmd->speed = SPEED_1000; 2775 ecmd->port = PORT_FIBRE; 2776 } 2777 2778 ecmd->advertising = sky2->advertising; 2779 ecmd->autoneg = sky2->autoneg; 2780 ecmd->duplex = sky2->duplex; 2781 return 0; 2782} 2783 2784static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2785{ 2786 struct sky2_port *sky2 = netdev_priv(dev); 2787 const struct sky2_hw *hw = sky2->hw; 2788 u32 supported = sky2_supported_modes(hw); 2789 2790 if (ecmd->autoneg == AUTONEG_ENABLE) { 2791 ecmd->advertising = supported; 2792 sky2->duplex = -1; 2793 sky2->speed = -1; 2794 } else { 2795 u32 setting; 2796 2797 switch (ecmd->speed) { 2798 case SPEED_1000: 2799 if (ecmd->duplex == DUPLEX_FULL) 2800 setting = SUPPORTED_1000baseT_Full; 2801 else if (ecmd->duplex == DUPLEX_HALF) 2802 setting = SUPPORTED_1000baseT_Half; 2803 else 2804 return -EINVAL; 2805 break; 2806 case SPEED_100: 2807 if (ecmd->duplex == DUPLEX_FULL) 2808 setting = SUPPORTED_100baseT_Full; 2809 else if (ecmd->duplex == DUPLEX_HALF) 2810 setting = SUPPORTED_100baseT_Half; 2811 else 2812 return -EINVAL; 2813 break; 2814 2815 case SPEED_10: 2816 if (ecmd->duplex == DUPLEX_FULL) 2817 setting = SUPPORTED_10baseT_Full; 2818 else if (ecmd->duplex == DUPLEX_HALF) 2819 setting = SUPPORTED_10baseT_Half; 2820 else 2821 return -EINVAL; 2822 break; 2823 default: 2824 return -EINVAL; 2825 } 2826 2827 if ((setting & supported) == 0) 2828 return -EINVAL; 2829 2830 sky2->speed = ecmd->speed; 2831 sky2->duplex = ecmd->duplex; 2832 } 2833 2834 sky2->autoneg = ecmd->autoneg; 2835 sky2->advertising = ecmd->advertising; 2836 2837 if (netif_running(dev)) 2838 sky2_phy_reinit(sky2); 2839 2840 return 0; 2841} 2842 2843static void sky2_get_drvinfo(struct net_device *dev, 2844 struct ethtool_drvinfo *info) 2845{ 2846 struct sky2_port *sky2 = netdev_priv(dev); 2847 2848 strcpy(info->driver, DRV_NAME); 2849 strcpy(info->version, DRV_VERSION); 2850 strcpy(info->fw_version, "N/A"); 2851 strcpy(info->bus_info, pci_name(sky2->hw->pdev)); 2852} 2853 2854static const struct sky2_stat { 2855 char name[ETH_GSTRING_LEN]; 2856 u16 offset; 2857} sky2_stats[] = { 2858 { "tx_bytes", GM_TXO_OK_HI }, 2859 { "rx_bytes", GM_RXO_OK_HI }, 2860 { "tx_broadcast", GM_TXF_BC_OK }, 2861 { "rx_broadcast", GM_RXF_BC_OK }, 2862 { "tx_multicast", GM_TXF_MC_OK }, 2863 { "rx_multicast", GM_RXF_MC_OK }, 2864 { "tx_unicast", GM_TXF_UC_OK }, 2865 { "rx_unicast", GM_RXF_UC_OK }, 2866 { "tx_mac_pause", GM_TXF_MPAUSE }, 2867 { "rx_mac_pause", GM_RXF_MPAUSE }, 2868 { "collisions", GM_TXF_COL }, 2869 { "late_collision",GM_TXF_LAT_COL }, 2870 { "aborted", GM_TXF_ABO_COL }, 2871 { "single_collisions", GM_TXF_SNG_COL }, 2872 { "multi_collisions", GM_TXF_MUL_COL }, 2873 2874 { "rx_short", GM_RXF_SHT }, 2875 { "rx_runt", GM_RXE_FRAG }, 2876 { "rx_64_byte_packets", GM_RXF_64B }, 2877 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 2878 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 2879 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 2880 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 2881 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 2882 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 2883 { "rx_too_long", GM_RXF_LNG_ERR }, 2884 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 2885 { "rx_jabber", GM_RXF_JAB_PKT }, 2886 { "rx_fcs_error", GM_RXF_FCS_ERR }, 2887 2888 { "tx_64_byte_packets", GM_TXF_64B }, 2889 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 2890 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 2891 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 2892 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 2893 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 2894 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 2895 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 2896}; 2897 2898static u32 sky2_get_rx_csum(struct net_device *dev) 2899{ 2900 struct sky2_port *sky2 = netdev_priv(dev); 2901 2902 return sky2->rx_csum; 2903} 2904 2905static int sky2_set_rx_csum(struct net_device *dev, u32 data) 2906{ 2907 struct sky2_port *sky2 = netdev_priv(dev); 2908 2909 sky2->rx_csum = data; 2910 2911 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2912 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 2913 2914 return 0; 2915} 2916 2917static u32 sky2_get_msglevel(struct net_device *netdev) 2918{ 2919 struct sky2_port *sky2 = netdev_priv(netdev); 2920 return sky2->msg_enable; 2921} 2922 2923static int sky2_nway_reset(struct net_device *dev) 2924{ 2925 struct sky2_port *sky2 = netdev_priv(dev); 2926 2927 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE) 2928 return -EINVAL; 2929 2930 sky2_phy_reinit(sky2); 2931 2932 return 0; 2933} 2934 2935static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 2936{ 2937 struct sky2_hw *hw = sky2->hw; 2938 unsigned port = sky2->port; 2939 int i; 2940 2941 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 2942 | (u64) gma_read32(hw, port, GM_TXO_OK_LO); 2943 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 2944 | (u64) gma_read32(hw, port, GM_RXO_OK_LO); 2945 2946 for (i = 2; i < count; i++) 2947 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); 2948} 2949 2950static void sky2_set_msglevel(struct net_device *netdev, u32 value) 2951{ 2952 struct sky2_port *sky2 = netdev_priv(netdev); 2953 sky2->msg_enable = value; 2954} 2955 2956static int sky2_get_stats_count(struct net_device *dev) 2957{ 2958 return ARRAY_SIZE(sky2_stats); 2959} 2960 2961static void sky2_get_ethtool_stats(struct net_device *dev, 2962 struct ethtool_stats *stats, u64 * data) 2963{ 2964 struct sky2_port *sky2 = netdev_priv(dev); 2965 2966 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 2967} 2968 2969static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 2970{ 2971 int i; 2972 2973 switch (stringset) { 2974 case ETH_SS_STATS: 2975 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 2976 memcpy(data + i * ETH_GSTRING_LEN, 2977 sky2_stats[i].name, ETH_GSTRING_LEN); 2978 break; 2979 } 2980} 2981 2982static struct net_device_stats *sky2_get_stats(struct net_device *dev) 2983{ 2984 struct sky2_port *sky2 = netdev_priv(dev); 2985 return &sky2->net_stats; 2986} 2987 2988static int sky2_set_mac_address(struct net_device *dev, void *p) 2989{ 2990 struct sky2_port *sky2 = netdev_priv(dev); 2991 struct sky2_hw *hw = sky2->hw; 2992 unsigned port = sky2->port; 2993 const struct sockaddr *addr = p; 2994 2995 if (!is_valid_ether_addr(addr->sa_data)) 2996 return -EADDRNOTAVAIL; 2997 2998 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 2999 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3000 dev->dev_addr, ETH_ALEN); 3001 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3002 dev->dev_addr, ETH_ALEN); 3003 3004 /* virtual address for data */ 3005 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3006 3007 /* physical address: used for pause frames */ 3008 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3009 3010 return 0; 3011} 3012 3013static void inline sky2_add_filter(u8 filter[8], const u8 *addr) 3014{ 3015 u32 bit; 3016 3017 bit = ether_crc(ETH_ALEN, addr) & 63; 3018 filter[bit >> 3] |= 1 << (bit & 7); 3019} 3020 3021static void sky2_set_multicast(struct net_device *dev) 3022{ 3023 struct sky2_port *sky2 = netdev_priv(dev); 3024 struct sky2_hw *hw = sky2->hw; 3025 unsigned port = sky2->port; 3026 struct dev_mc_list *list = dev->mc_list; 3027 u16 reg; 3028 u8 filter[8]; 3029 int rx_pause; 3030 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3031 3032 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3033 memset(filter, 0, sizeof(filter)); 3034 3035 reg = gma_read16(hw, port, GM_RX_CTRL); 3036 reg |= GM_RXCR_UCF_ENA; 3037 3038 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3039 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3040 else if (dev->flags & IFF_ALLMULTI) 3041 memset(filter, 0xff, sizeof(filter)); 3042 else if (dev->mc_count == 0 && !rx_pause) 3043 reg &= ~GM_RXCR_MCF_ENA; 3044 else { 3045 int i; 3046 reg |= GM_RXCR_MCF_ENA; 3047 3048 if (rx_pause) 3049 sky2_add_filter(filter, pause_mc_addr); 3050 3051 for (i = 0; list && i < dev->mc_count; i++, list = list->next) 3052 sky2_add_filter(filter, list->dmi_addr); 3053 } 3054 3055 gma_write16(hw, port, GM_MC_ADDR_H1, 3056 (u16) filter[0] | ((u16) filter[1] << 8)); 3057 gma_write16(hw, port, GM_MC_ADDR_H2, 3058 (u16) filter[2] | ((u16) filter[3] << 8)); 3059 gma_write16(hw, port, GM_MC_ADDR_H3, 3060 (u16) filter[4] | ((u16) filter[5] << 8)); 3061 gma_write16(hw, port, GM_MC_ADDR_H4, 3062 (u16) filter[6] | ((u16) filter[7] << 8)); 3063 3064 gma_write16(hw, port, GM_RX_CTRL, reg); 3065} 3066 3067/* Can have one global because blinking is controlled by 3068 * ethtool and that is always under RTNL mutex 3069 */ 3070static void sky2_led(struct sky2_hw *hw, unsigned port, int on) 3071{ 3072 u16 pg; 3073 3074 switch (hw->chip_id) { 3075 case CHIP_ID_YUKON_XL: 3076 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3077 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3078 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3079 on ? (PHY_M_LEDC_LOS_CTRL(1) | 3080 PHY_M_LEDC_INIT_CTRL(7) | 3081 PHY_M_LEDC_STA1_CTRL(7) | 3082 PHY_M_LEDC_STA0_CTRL(7)) 3083 : 0); 3084 3085 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3086 break; 3087 3088 default: 3089 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 3090 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3091 on ? PHY_M_LED_ALL : 0); 3092 } 3093} 3094 3095/* blink LED's for finding board */ 3096static int sky2_phys_id(struct net_device *dev, u32 data) 3097{ 3098 struct sky2_port *sky2 = netdev_priv(dev); 3099 struct sky2_hw *hw = sky2->hw; 3100 unsigned port = sky2->port; 3101 u16 ledctrl, ledover = 0; 3102 long ms; 3103 int interrupted; 3104 int onoff = 1; 3105 3106 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) 3107 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); 3108 else 3109 ms = data * 1000; 3110 3111 /* save initial values */ 3112 spin_lock_bh(&sky2->phy_lock); 3113 if (hw->chip_id == CHIP_ID_YUKON_XL) { 3114 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3115 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3116 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 3117 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3118 } else { 3119 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); 3120 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); 3121 } 3122 3123 interrupted = 0; 3124 while (!interrupted && ms > 0) { 3125 sky2_led(hw, port, onoff); 3126 onoff = !onoff; 3127 3128 spin_unlock_bh(&sky2->phy_lock); 3129 interrupted = msleep_interruptible(250); 3130 spin_lock_bh(&sky2->phy_lock); 3131 3132 ms -= 250; 3133 } 3134 3135 /* resume regularly scheduled programming */ 3136 if (hw->chip_id == CHIP_ID_YUKON_XL) { 3137 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3138 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3139 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); 3140 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3141 } else { 3142 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 3143 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 3144 } 3145 spin_unlock_bh(&sky2->phy_lock); 3146 3147 return 0; 3148} 3149 3150static void sky2_get_pauseparam(struct net_device *dev, 3151 struct ethtool_pauseparam *ecmd) 3152{ 3153 struct sky2_port *sky2 = netdev_priv(dev); 3154 3155 switch (sky2->flow_mode) { 3156 case FC_NONE: 3157 ecmd->tx_pause = ecmd->rx_pause = 0; 3158 break; 3159 case FC_TX: 3160 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 3161 break; 3162 case FC_RX: 3163 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 3164 break; 3165 case FC_BOTH: 3166 ecmd->tx_pause = ecmd->rx_pause = 1; 3167 } 3168 3169 ecmd->autoneg = sky2->autoneg; 3170} 3171 3172static int sky2_set_pauseparam(struct net_device *dev, 3173 struct ethtool_pauseparam *ecmd) 3174{ 3175 struct sky2_port *sky2 = netdev_priv(dev); 3176 3177 sky2->autoneg = ecmd->autoneg; 3178 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 3179 3180 if (netif_running(dev)) 3181 sky2_phy_reinit(sky2); 3182 3183 return 0; 3184} 3185 3186static int sky2_get_coalesce(struct net_device *dev, 3187 struct ethtool_coalesce *ecmd) 3188{ 3189 struct sky2_port *sky2 = netdev_priv(dev); 3190 struct sky2_hw *hw = sky2->hw; 3191 3192 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 3193 ecmd->tx_coalesce_usecs = 0; 3194 else { 3195 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 3196 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 3197 } 3198 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 3199 3200 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 3201 ecmd->rx_coalesce_usecs = 0; 3202 else { 3203 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 3204 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 3205 } 3206 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 3207 3208 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 3209 ecmd->rx_coalesce_usecs_irq = 0; 3210 else { 3211 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 3212 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 3213 } 3214 3215 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 3216 3217 return 0; 3218} 3219 3220/* Note: this affect both ports */ 3221static int sky2_set_coalesce(struct net_device *dev, 3222 struct ethtool_coalesce *ecmd) 3223{ 3224 struct sky2_port *sky2 = netdev_priv(dev); 3225 struct sky2_hw *hw = sky2->hw; 3226 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 3227 3228 if (ecmd->tx_coalesce_usecs > tmax || 3229 ecmd->rx_coalesce_usecs > tmax || 3230 ecmd->rx_coalesce_usecs_irq > tmax) 3231 return -EINVAL; 3232 3233 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1) 3234 return -EINVAL; 3235 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 3236 return -EINVAL; 3237 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) 3238 return -EINVAL; 3239 3240 if (ecmd->tx_coalesce_usecs == 0) 3241 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 3242 else { 3243 sky2_write32(hw, STAT_TX_TIMER_INI, 3244 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 3245 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3246 } 3247 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 3248 3249 if (ecmd->rx_coalesce_usecs == 0) 3250 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 3251 else { 3252 sky2_write32(hw, STAT_LEV_TIMER_INI, 3253 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 3254 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3255 } 3256 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 3257 3258 if (ecmd->rx_coalesce_usecs_irq == 0) 3259 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 3260 else { 3261 sky2_write32(hw, STAT_ISR_TIMER_INI, 3262 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 3263 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3264 } 3265 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 3266 return 0; 3267} 3268 3269static void sky2_get_ringparam(struct net_device *dev, 3270 struct ethtool_ringparam *ering) 3271{ 3272 struct sky2_port *sky2 = netdev_priv(dev); 3273 3274 ering->rx_max_pending = RX_MAX_PENDING; 3275 ering->rx_mini_max_pending = 0; 3276 ering->rx_jumbo_max_pending = 0; 3277 ering->tx_max_pending = TX_RING_SIZE - 1; 3278 3279 ering->rx_pending = sky2->rx_pending; 3280 ering->rx_mini_pending = 0; 3281 ering->rx_jumbo_pending = 0; 3282 ering->tx_pending = sky2->tx_pending; 3283} 3284 3285static int sky2_set_ringparam(struct net_device *dev, 3286 struct ethtool_ringparam *ering) 3287{ 3288 struct sky2_port *sky2 = netdev_priv(dev); 3289 int err = 0; 3290 3291 if (ering->rx_pending > RX_MAX_PENDING || 3292 ering->rx_pending < 8 || 3293 ering->tx_pending < MAX_SKB_TX_LE || 3294 ering->tx_pending > TX_RING_SIZE - 1) 3295 return -EINVAL; 3296 3297 if (netif_running(dev)) 3298 sky2_down(dev); 3299 3300 sky2->rx_pending = ering->rx_pending; 3301 sky2->tx_pending = ering->tx_pending; 3302 3303 if (netif_running(dev)) { 3304 err = sky2_up(dev); 3305 if (err) 3306 dev_close(dev); 3307 else 3308 sky2_set_multicast(dev); 3309 } 3310 3311 return err; 3312} 3313 3314static int sky2_get_regs_len(struct net_device *dev) 3315{ 3316 return 0x4000; 3317} 3318 3319/* 3320 * Returns copy of control register region 3321 * Note: access to the RAM address register set will cause timeouts. 3322 */ 3323static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 3324 void *p) 3325{ 3326 const struct sky2_port *sky2 = netdev_priv(dev); 3327 const void __iomem *io = sky2->hw->regs; 3328 3329 BUG_ON(regs->len < B3_RI_WTO_R1); 3330 regs->version = 1; 3331 memset(p, 0, regs->len); 3332 3333 memcpy_fromio(p, io, B3_RAM_ADDR); 3334 3335 memcpy_fromio(p + B3_RI_WTO_R1, 3336 io + B3_RI_WTO_R1, 3337 regs->len - B3_RI_WTO_R1); 3338} 3339 3340/* In order to do Jumbo packets on these chips, need to turn off the 3341 * transmit store/forward. Therefore checksum offload won't work. 3342 */ 3343static int no_tx_offload(struct net_device *dev) 3344{ 3345 const struct sky2_port *sky2 = netdev_priv(dev); 3346 const struct sky2_hw *hw = sky2->hw; 3347 3348 return dev->mtu > ETH_DATA_LEN && 3349 (hw->chip_id == CHIP_ID_YUKON_EX 3350 || hw->chip_id == CHIP_ID_YUKON_EC_U); 3351} 3352 3353static int sky2_set_tx_csum(struct net_device *dev, u32 data) 3354{ 3355 if (data && no_tx_offload(dev)) 3356 return -EINVAL; 3357 3358 return ethtool_op_set_tx_csum(dev, data); 3359} 3360 3361 3362static int sky2_set_tso(struct net_device *dev, u32 data) 3363{ 3364 if (data && no_tx_offload(dev)) 3365 return -EINVAL; 3366 3367 return ethtool_op_set_tso(dev, data); 3368} 3369 3370static const struct ethtool_ops sky2_ethtool_ops = { 3371 .get_settings = sky2_get_settings, 3372 .set_settings = sky2_set_settings, 3373 .get_drvinfo = sky2_get_drvinfo, 3374 .get_wol = sky2_get_wol, 3375 .set_wol = sky2_set_wol, 3376 .get_msglevel = sky2_get_msglevel, 3377 .set_msglevel = sky2_set_msglevel, 3378 .nway_reset = sky2_nway_reset, 3379 .get_regs_len = sky2_get_regs_len, 3380 .get_regs = sky2_get_regs, 3381 .get_link = ethtool_op_get_link, 3382 .get_sg = ethtool_op_get_sg, 3383 .set_sg = ethtool_op_set_sg, 3384 .get_tx_csum = ethtool_op_get_tx_csum, 3385 .set_tx_csum = sky2_set_tx_csum, 3386 .get_tso = ethtool_op_get_tso, 3387 .set_tso = sky2_set_tso, 3388 .get_rx_csum = sky2_get_rx_csum, 3389 .set_rx_csum = sky2_set_rx_csum, 3390 .get_strings = sky2_get_strings, 3391 .get_coalesce = sky2_get_coalesce, 3392 .set_coalesce = sky2_set_coalesce, 3393 .get_ringparam = sky2_get_ringparam, 3394 .set_ringparam = sky2_set_ringparam, 3395 .get_pauseparam = sky2_get_pauseparam, 3396 .set_pauseparam = sky2_set_pauseparam, 3397 .phys_id = sky2_phys_id, 3398 .get_stats_count = sky2_get_stats_count, 3399 .get_ethtool_stats = sky2_get_ethtool_stats, 3400 .get_perm_addr = ethtool_op_get_perm_addr, 3401}; 3402 3403/* Initialize network device */ 3404static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, 3405 unsigned port, 3406 int highmem, int wol) 3407{ 3408 struct sky2_port *sky2; 3409 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 3410 3411 if (!dev) { 3412 dev_err(&hw->pdev->dev, "etherdev alloc failed"); 3413 return NULL; 3414 } 3415 3416 SET_MODULE_OWNER(dev); 3417 SET_NETDEV_DEV(dev, &hw->pdev->dev); 3418 dev->irq = hw->pdev->irq; 3419 dev->open = sky2_up; 3420 dev->stop = sky2_down; 3421 dev->do_ioctl = sky2_ioctl; 3422 dev->hard_start_xmit = sky2_xmit_frame; 3423 dev->get_stats = sky2_get_stats; 3424 dev->set_multicast_list = sky2_set_multicast; 3425 dev->set_mac_address = sky2_set_mac_address; 3426 dev->change_mtu = sky2_change_mtu; 3427 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); 3428 dev->tx_timeout = sky2_tx_timeout; 3429 dev->watchdog_timeo = TX_WATCHDOG; 3430 if (port == 0) 3431 dev->poll = sky2_poll; 3432 dev->weight = NAPI_WEIGHT; 3433#ifdef CONFIG_NET_POLL_CONTROLLER 3434 /* Network console (only works on port 0) 3435 * because netpoll makes assumptions about NAPI 3436 */ 3437 if (port == 0) 3438 dev->poll_controller = sky2_netpoll; 3439#endif 3440 3441 sky2 = netdev_priv(dev); 3442 sky2->netdev = dev; 3443 sky2->hw = hw; 3444 sky2->msg_enable = netif_msg_init(debug, default_msg); 3445 3446 /* Auto speed and flow control */ 3447 sky2->autoneg = AUTONEG_ENABLE; 3448 sky2->flow_mode = FC_BOTH; 3449 3450 sky2->duplex = -1; 3451 sky2->speed = -1; 3452 sky2->advertising = sky2_supported_modes(hw); 3453 sky2->rx_csum = 1; 3454 sky2->wol = wol; 3455 3456 spin_lock_init(&sky2->phy_lock); 3457 sky2->tx_pending = TX_DEF_PENDING; 3458 sky2->rx_pending = RX_DEF_PENDING; 3459 3460 hw->dev[port] = dev; 3461 3462 sky2->port = port; 3463 3464 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG; 3465 if (highmem) 3466 dev->features |= NETIF_F_HIGHDMA; 3467 3468#ifdef SKY2_VLAN_TAG_USED 3469 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 3470 dev->vlan_rx_register = sky2_vlan_rx_register; 3471#endif 3472 3473 /* read the mac address */ 3474 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); 3475 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 3476 3477 /* device is off until link detection */ 3478 netif_carrier_off(dev); 3479 netif_stop_queue(dev); 3480 3481 return dev; 3482} 3483 3484static void __devinit sky2_show_addr(struct net_device *dev) 3485{ 3486 const struct sky2_port *sky2 = netdev_priv(dev); 3487 3488 if (netif_msg_probe(sky2)) 3489 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", 3490 dev->name, 3491 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], 3492 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); 3493} 3494 3495/* Handle software interrupt used during MSI test */ 3496static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id) 3497{ 3498 struct sky2_hw *hw = dev_id; 3499 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3500 3501 if (status == 0) 3502 return IRQ_NONE; 3503 3504 if (status & Y2_IS_IRQ_SW) { 3505 hw->msi = 1; 3506 wake_up(&hw->msi_wait); 3507 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 3508 } 3509 sky2_write32(hw, B0_Y2_SP_ICR, 2); 3510 3511 return IRQ_HANDLED; 3512} 3513 3514/* Test interrupt path by forcing a a software IRQ */ 3515static int __devinit sky2_test_msi(struct sky2_hw *hw) 3516{ 3517 struct pci_dev *pdev = hw->pdev; 3518 int err; 3519 3520 init_waitqueue_head (&hw->msi_wait); 3521 3522 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 3523 3524 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 3525 if (err) { 3526 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 3527 return err; 3528 } 3529 3530 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 3531 sky2_read8(hw, B0_CTST); 3532 3533 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10); 3534 3535 if (!hw->msi) { 3536 /* MSI test failed, go back to INTx mode */ 3537 dev_info(&pdev->dev, "No interrupt generated using MSI, " 3538 "switching to INTx mode.\n"); 3539 3540 err = -EOPNOTSUPP; 3541 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 3542 } 3543 3544 sky2_write32(hw, B0_IMSK, 0); 3545 sky2_read32(hw, B0_IMSK); 3546 3547 free_irq(pdev->irq, hw); 3548 3549 return err; 3550} 3551 3552static int __devinit pci_wake_enabled(struct pci_dev *dev) 3553{ 3554 int pm = pci_find_capability(dev, PCI_CAP_ID_PM); 3555 u16 value; 3556 3557 if (!pm) 3558 return 0; 3559 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value)) 3560 return 0; 3561 return value & PCI_PM_CTRL_PME_ENABLE; 3562} 3563 3564static int __devinit sky2_probe(struct pci_dev *pdev, 3565 const struct pci_device_id *ent) 3566{ 3567 struct net_device *dev; 3568 struct sky2_hw *hw; 3569 int err, using_dac = 0, wol_default; 3570 3571 err = pci_enable_device(pdev); 3572 if (err) { 3573 dev_err(&pdev->dev, "cannot enable PCI device\n"); 3574 goto err_out; 3575 } 3576 3577 err = pci_request_regions(pdev, DRV_NAME); 3578 if (err) { 3579 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 3580 goto err_out_disable; 3581 } 3582 3583 pci_set_master(pdev); 3584 3585 if (sizeof(dma_addr_t) > sizeof(u32) && 3586 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { 3587 using_dac = 1; 3588 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 3589 if (err < 0) { 3590 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 3591 "for consistent allocations\n"); 3592 goto err_out_free_regions; 3593 } 3594 } else { 3595 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 3596 if (err) { 3597 dev_err(&pdev->dev, "no usable DMA configuration\n"); 3598 goto err_out_free_regions; 3599 } 3600 } 3601 3602 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0; 3603 3604 err = -ENOMEM; 3605 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3606 if (!hw) { 3607 dev_err(&pdev->dev, "cannot allocate hardware struct\n"); 3608 goto err_out_free_regions; 3609 } 3610 3611 hw->pdev = pdev; 3612 3613 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 3614 if (!hw->regs) { 3615 dev_err(&pdev->dev, "cannot map device registers\n"); 3616 goto err_out_free_hw; 3617 } 3618 3619#ifdef __BIG_ENDIAN 3620 /* The sk98lin vendor driver uses hardware byte swapping but 3621 * this driver uses software swapping. 3622 */ 3623 { 3624 u32 reg; 3625 reg = sky2_pci_read32(hw, PCI_DEV_REG2); 3626 reg &= ~PCI_REV_DESC; 3627 sky2_pci_write32(hw, PCI_DEV_REG2, reg); 3628 } 3629#endif 3630 3631 /* ring for status responses */ 3632 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, 3633 &hw->st_dma); 3634 if (!hw->st_le) 3635 goto err_out_iounmap; 3636 3637 err = sky2_init(hw); 3638 if (err) 3639 goto err_out_iounmap; 3640 3641 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n", 3642 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0), 3643 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], 3644 hw->chip_id, hw->chip_rev); 3645 3646 sky2_reset(hw); 3647 3648 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 3649 if (!dev) { 3650 err = -ENOMEM; 3651 goto err_out_free_pci; 3652 } 3653 3654 if (!disable_msi && pci_enable_msi(pdev) == 0) { 3655 err = sky2_test_msi(hw); 3656 if (err == -EOPNOTSUPP) 3657 pci_disable_msi(pdev); 3658 else if (err) 3659 goto err_out_free_netdev; 3660 } 3661 3662 err = register_netdev(dev); 3663 if (err) { 3664 dev_err(&pdev->dev, "cannot register net device\n"); 3665 goto err_out_free_netdev; 3666 } 3667 3668 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED, 3669 dev->name, hw); 3670 if (err) { 3671 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 3672 goto err_out_unregister; 3673 } 3674 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 3675 3676 sky2_show_addr(dev); 3677 3678 if (hw->ports > 1) { 3679 struct net_device *dev1; 3680 3681 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 3682 if (!dev1) 3683 dev_warn(&pdev->dev, "allocation for second device failed\n"); 3684 else if ((err = register_netdev(dev1))) { 3685 dev_warn(&pdev->dev, 3686 "register of second port failed (%d)\n", err); 3687 hw->dev[1] = NULL; 3688 free_netdev(dev1); 3689 } else 3690 sky2_show_addr(dev1); 3691 } 3692 3693 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw); 3694 INIT_WORK(&hw->restart_work, sky2_restart); 3695 3696 sky2_idle_start(hw); 3697 3698 pci_set_drvdata(pdev, hw); 3699 3700 return 0; 3701 3702err_out_unregister: 3703 if (hw->msi) 3704 pci_disable_msi(pdev); 3705 unregister_netdev(dev); 3706err_out_free_netdev: 3707 free_netdev(dev); 3708err_out_free_pci: 3709 sky2_write8(hw, B0_CTST, CS_RST_SET); 3710 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); 3711err_out_iounmap: 3712 iounmap(hw->regs); 3713err_out_free_hw: 3714 kfree(hw); 3715err_out_free_regions: 3716 pci_release_regions(pdev); 3717err_out_disable: 3718 pci_disable_device(pdev); 3719err_out: 3720 pci_set_drvdata(pdev, NULL); 3721 return err; 3722} 3723 3724static void __devexit sky2_remove(struct pci_dev *pdev) 3725{ 3726 struct sky2_hw *hw = pci_get_drvdata(pdev); 3727 struct net_device *dev0, *dev1; 3728 3729 if (!hw) 3730 return; 3731 3732 del_timer_sync(&hw->idle_timer); 3733 3734 flush_scheduled_work(); 3735 3736 sky2_write32(hw, B0_IMSK, 0); 3737 synchronize_irq(hw->pdev->irq); 3738 3739 dev0 = hw->dev[0]; 3740 dev1 = hw->dev[1]; 3741 if (dev1) 3742 unregister_netdev(dev1); 3743 unregister_netdev(dev0); 3744 3745 sky2_power_aux(hw); 3746 3747 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); 3748 sky2_write8(hw, B0_CTST, CS_RST_SET); 3749 sky2_read8(hw, B0_CTST); 3750 3751 free_irq(pdev->irq, hw); 3752 if (hw->msi) 3753 pci_disable_msi(pdev); 3754 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); 3755 pci_release_regions(pdev); 3756 pci_disable_device(pdev); 3757 3758 if (dev1) 3759 free_netdev(dev1); 3760 free_netdev(dev0); 3761 iounmap(hw->regs); 3762 kfree(hw); 3763 3764 pci_set_drvdata(pdev, NULL); 3765} 3766 3767#ifdef CONFIG_PM 3768static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) 3769{ 3770 struct sky2_hw *hw = pci_get_drvdata(pdev); 3771 int i, wol = 0; 3772 3773 if (!hw) 3774 return 0; 3775 3776 del_timer_sync(&hw->idle_timer); 3777 netif_poll_disable(hw->dev[0]); 3778 3779 for (i = 0; i < hw->ports; i++) { 3780 struct net_device *dev = hw->dev[i]; 3781 struct sky2_port *sky2 = netdev_priv(dev); 3782 3783 if (netif_running(dev)) 3784 sky2_down(dev); 3785 3786 if (sky2->wol) 3787 sky2_wol_init(sky2); 3788 3789 wol |= sky2->wol; 3790 } 3791 3792 sky2_write32(hw, B0_IMSK, 0); 3793 sky2_power_aux(hw); 3794 3795 pci_save_state(pdev); 3796 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); 3797 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 3798 3799 return 0; 3800} 3801 3802static int sky2_resume(struct pci_dev *pdev) 3803{ 3804 struct sky2_hw *hw = pci_get_drvdata(pdev); 3805 int i, err; 3806 3807 if (!hw) 3808 return 0; 3809 3810 err = pci_set_power_state(pdev, PCI_D0); 3811 if (err) 3812 goto out; 3813 3814 err = pci_restore_state(pdev); 3815 if (err) 3816 goto out; 3817 3818 pci_enable_wake(pdev, PCI_D0, 0); 3819 3820 /* Re-enable all clocks */ 3821 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U) 3822 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3823 3824 sky2_reset(hw); 3825 3826 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 3827 3828 for (i = 0; i < hw->ports; i++) { 3829 struct net_device *dev = hw->dev[i]; 3830 if (netif_running(dev)) { 3831 err = sky2_up(dev); 3832 if (err) { 3833 printk(KERN_ERR PFX "%s: could not up: %d\n", 3834 dev->name, err); 3835 dev_close(dev); 3836 goto out; 3837 } 3838 } 3839 } 3840 3841 netif_poll_enable(hw->dev[0]); 3842 sky2_idle_start(hw); 3843 return 0; 3844out: 3845 dev_err(&pdev->dev, "resume failed (%d)\n", err); 3846 pci_disable_device(pdev); 3847 return err; 3848} 3849#endif 3850 3851static void sky2_shutdown(struct pci_dev *pdev) 3852{ 3853 struct sky2_hw *hw = pci_get_drvdata(pdev); 3854 int i, wol = 0; 3855 3856 if (!hw) 3857 return; 3858 3859 del_timer_sync(&hw->idle_timer); 3860 netif_poll_disable(hw->dev[0]); 3861 3862 for (i = 0; i < hw->ports; i++) { 3863 struct net_device *dev = hw->dev[i]; 3864 struct sky2_port *sky2 = netdev_priv(dev); 3865 3866 if (sky2->wol) { 3867 wol = 1; 3868 sky2_wol_init(sky2); 3869 } 3870 } 3871 3872 if (wol) 3873 sky2_power_aux(hw); 3874 3875 pci_enable_wake(pdev, PCI_D3hot, wol); 3876 pci_enable_wake(pdev, PCI_D3cold, wol); 3877 3878 pci_disable_device(pdev); 3879 pci_set_power_state(pdev, PCI_D3hot); 3880 3881} 3882 3883static struct pci_driver sky2_driver = { 3884 .name = DRV_NAME, 3885 .id_table = sky2_id_table, 3886 .probe = sky2_probe, 3887 .remove = __devexit_p(sky2_remove), 3888#ifdef CONFIG_PM 3889 .suspend = sky2_suspend, 3890 .resume = sky2_resume, 3891#endif 3892 .shutdown = sky2_shutdown, 3893}; 3894 3895static int __init sky2_init_module(void) 3896{ 3897 return pci_register_driver(&sky2_driver); 3898} 3899 3900static void __exit sky2_cleanup_module(void) 3901{ 3902 pci_unregister_driver(&sky2_driver); 3903} 3904 3905module_init(sky2_init_module); 3906module_exit(sky2_cleanup_module); 3907 3908MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 3909MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 3910MODULE_LICENSE("GPL"); 3911MODULE_VERSION(DRV_VERSION); 3912