1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA  02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 *    info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 */
29
30#ifndef _NETXEN_NIC_H_
31#define _NETXEN_NIC_H_
32
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/types.h>
36#include <linux/compiler.h>
37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40#include <linux/ioport.h>
41#include <linux/pci.h>
42#include <linux/netdevice.h>
43#include <linux/etherdevice.h>
44#include <linux/ip.h>
45#include <linux/in.h>
46#include <linux/tcp.h>
47#include <linux/skbuff.h>
48#include <linux/version.h>
49
50#include <linux/ethtool.h>
51#include <linux/mii.h>
52#include <linux/interrupt.h>
53#include <linux/timer.h>
54
55#include <linux/mm.h>
56#include <linux/mman.h>
57
58#include <asm/system.h>
59#include <asm/io.h>
60#include <asm/byteorder.h>
61#include <asm/uaccess.h>
62#include <asm/pgtable.h>
63
64#include "netxen_nic_hw.h"
65
66#define _NETXEN_NIC_LINUX_MAJOR 3
67#define _NETXEN_NIC_LINUX_MINOR 4
68#define _NETXEN_NIC_LINUX_SUBVERSION 2
69#define NETXEN_NIC_LINUX_VERSIONID  "3.4.2"
70
71#define NETXEN_NUM_FLASH_SECTORS (64)
72#define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
73#define NETXEN_FLASH_TOTAL_SIZE  (NETXEN_NUM_FLASH_SECTORS \
74					* NETXEN_FLASH_SECTOR_SIZE)
75
76#define PHAN_VENDOR_ID 0x4040
77
78#define RCV_DESC_RINGSIZE	\
79	(sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
80#define STATUS_DESC_RINGSIZE	\
81	(sizeof(struct status_desc)* adapter->max_rx_desc_count)
82#define LRO_DESC_RINGSIZE	\
83	(sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
84#define TX_RINGSIZE	\
85	(sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
86#define RCV_BUFFSIZE	\
87	(sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
88#define find_diff_among(a,b,range) ((a)<=(b)?((b)-(a)):((b)+(range)-(a)))
89
90#define NETXEN_NETDEV_STATUS		0x1
91#define NETXEN_RCV_PRODUCER_OFFSET	0
92#define NETXEN_RCV_PEG_DB_ID		2
93#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
94#define FLASH_SUCCESS 0
95
96#define ADDR_IN_WINDOW1(off)	\
97	((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
98/*
99 * In netxen_nic_down(), we must wait for any pending callback requests into
100 * netxen_watchdog_task() to complete; eg otherwise the watchdog_timer could be
101 * reenabled right after it is deleted in netxen_nic_down(). FLUSH_SCHEDULED_WORK()
102 * does this synchronization.
103 *
104 * Normally, schedule_work()/flush_scheduled_work() could have worked, but
105 * netxen_nic_close() is invoked with kernel rtnl lock held. netif_carrier_off()
106 * call in netxen_nic_close() triggers a schedule_work(&linkwatch_work), and a
107 * subsequent call to flush_scheduled_work() in netxen_nic_down() would cause
108 * linkwatch_event() to be executed which also attempts to acquire the rtnl
109 * lock thus causing a deadlock.
110 */
111
112#define SCHEDULE_WORK(tp)	queue_work(netxen_workq, tp)
113#define FLUSH_SCHEDULED_WORK()	flush_workqueue(netxen_workq)
114extern struct workqueue_struct *netxen_workq;
115
116/*
117 * normalize a 64MB crb address to 32MB PCI window
118 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
119 */
120#define NETXEN_CRB_NORMAL(reg)	\
121	((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
122
123#define NETXEN_CRB_NORMALIZE(adapter, reg) \
124	pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
125
126#define DB_NORMALIZE(adapter, off) \
127	(adapter->ahw.db_base + (off))
128
129#define NX_P2_C0		0x24
130#define NX_P2_C1		0x25
131
132#define FIRST_PAGE_GROUP_START	0
133#define FIRST_PAGE_GROUP_END	0x100000
134
135#define SECOND_PAGE_GROUP_START	0x6000000
136#define SECOND_PAGE_GROUP_END	0x68BC000
137
138#define THIRD_PAGE_GROUP_START	0x70E4000
139#define THIRD_PAGE_GROUP_END	0x8000000
140
141#define FIRST_PAGE_GROUP_SIZE  FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
142#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
143#define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
144
145#define MAX_RX_BUFFER_LENGTH		1760
146#define MAX_RX_JUMBO_BUFFER_LENGTH 	8062
147#define MAX_RX_LRO_BUFFER_LENGTH	((48*1024)-512)
148#define RX_DMA_MAP_LEN			(MAX_RX_BUFFER_LENGTH - 2)
149#define RX_JUMBO_DMA_MAP_LEN	\
150	(MAX_RX_JUMBO_BUFFER_LENGTH - 2)
151#define RX_LRO_DMA_MAP_LEN		(MAX_RX_LRO_BUFFER_LENGTH - 2)
152#define NETXEN_ROM_ROUNDUP		0x80000000ULL
153
154/*
155 * Maximum number of ring contexts
156 */
157#define MAX_RING_CTX 1
158
159/* Opcodes to be used with the commands */
160enum {
161	TX_ETHER_PKT = 0x01,
162/* The following opcodes are for IP checksum	*/
163	TX_TCP_PKT,
164	TX_UDP_PKT,
165	TX_IP_PKT,
166	TX_TCP_LSO,
167	TX_IPSEC,
168	TX_IPSEC_CMD
169};
170
171/* The following opcodes are for internal consumption. */
172#define NETXEN_CONTROL_OP	0x10
173#define PEGNET_REQUEST		0x11
174
175#define	MAX_NUM_CARDS		4
176
177#define MAX_BUFFERS_PER_CMD	32
178
179/*
180 * Following are the states of the Phantom. Phantom will set them and
181 * Host will read to check if the fields are correct.
182 */
183#define PHAN_INITIALIZE_START		0xff00
184#define PHAN_INITIALIZE_FAILED		0xffff
185#define PHAN_INITIALIZE_COMPLETE	0xff01
186
187/* Host writes the following to notify that it has done the init-handshake */
188#define PHAN_INITIALIZE_ACK	0xf00f
189
190#define NUM_RCV_DESC_RINGS	3	/* No of Rcv Descriptor contexts */
191
192/* descriptor types */
193#define RCV_DESC_NORMAL		0x01
194#define RCV_DESC_JUMBO		0x02
195#define RCV_DESC_LRO		0x04
196#define RCV_DESC_NORMAL_CTXID	0
197#define RCV_DESC_JUMBO_CTXID	1
198#define RCV_DESC_LRO_CTXID	2
199
200#define RCV_DESC_TYPE(ID) \
201	((ID == RCV_DESC_JUMBO_CTXID)	\
202		? RCV_DESC_JUMBO	\
203		: ((ID == RCV_DESC_LRO_CTXID)	\
204			? RCV_DESC_LRO :	\
205			(RCV_DESC_NORMAL)))
206
207#define MAX_CMD_DESCRIPTORS		1024
208#define MAX_RCV_DESCRIPTORS		16384
209#define MAX_CMD_DESCRIPTORS_HOST	(MAX_CMD_DESCRIPTORS / 4)
210#define MAX_RCV_DESCRIPTORS_1G		(MAX_RCV_DESCRIPTORS / 4)
211#define MAX_JUMBO_RCV_DESCRIPTORS	1024
212#define MAX_LRO_RCV_DESCRIPTORS		64
213#define MAX_RCVSTATUS_DESCRIPTORS	MAX_RCV_DESCRIPTORS
214#define MAX_JUMBO_RCV_DESC	MAX_JUMBO_RCV_DESCRIPTORS
215#define MAX_RCV_DESC		MAX_RCV_DESCRIPTORS
216#define MAX_RCVSTATUS_DESC	MAX_RCV_DESCRIPTORS
217#define MAX_EPG_DESCRIPTORS	(MAX_CMD_DESCRIPTORS * 8)
218#define NUM_RCV_DESC		(MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
219				 MAX_LRO_RCV_DESCRIPTORS)
220#define MIN_TX_COUNT	4096
221#define MIN_RX_COUNT	4096
222#define NETXEN_CTX_SIGNATURE	0xdee0
223#define NETXEN_RCV_PRODUCER(ringid)	(ringid)
224#define MAX_FRAME_SIZE	0x10000	/* 64K MAX size for LSO */
225
226#define PHAN_PEG_RCV_INITIALIZED	0xff01
227#define PHAN_PEG_RCV_START_INITIALIZE	0xff00
228
229#define get_next_index(index, length)	\
230	(((index) + 1) & ((length) - 1))
231
232#define get_index_range(index,length,count)	\
233	(((index) + (count)) & ((length) - 1))
234
235#define MPORT_SINGLE_FUNCTION_MODE 0x1111
236#define MPORT_MULTI_FUNCTION_MODE 0x2222
237
238#include "netxen_nic_phan_reg.h"
239extern unsigned long long netxen_dma_mask;
240extern unsigned long last_schedule_time;
241
242/*
243 * NetXen host-peg signal message structure
244 *
245 *	Bit 0-1		: peg_id => 0x2 for tx and 01 for rx
246 *	Bit 2		: priv_id => must be 1
247 *	Bit 3-17	: count => for doorbell
248 *	Bit 18-27	: ctx_id => Context id
249 *	Bit 28-31	: opcode
250 */
251
252typedef u32 netxen_ctx_msg;
253
254#define netxen_set_msg_peg_id(config_word, val)	\
255	((config_word) &= ~3, (config_word) |= val & 3)
256#define netxen_set_msg_privid(config_word)	\
257	((config_word) |= 1 << 2)
258#define netxen_set_msg_count(config_word, val)	\
259	((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
260#define netxen_set_msg_ctxid(config_word, val)	\
261	((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
262#define netxen_set_msg_opcode(config_word, val)	\
263	((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
264
265struct netxen_rcv_context {
266	__le64 rcv_ring_addr;
267	__le32 rcv_ring_size;
268	__le32 rsrvd;
269};
270
271struct netxen_ring_ctx {
272
273	/* one command ring */
274	__le64 cmd_consumer_offset;
275	__le64 cmd_ring_addr;
276	__le32 cmd_ring_size;
277	__le32 rsrvd;
278
279	/* three receive rings */
280	struct netxen_rcv_context rcv_ctx[3];
281
282	/* one status ring */
283	__le64 sts_ring_addr;
284	__le32 sts_ring_size;
285
286	__le32 ctx_id;
287} __attribute__ ((aligned(64)));
288
289/*
290 * Following data structures describe the descriptors that will be used.
291 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
292 * we are doing LSO (above the 1500 size packet) only.
293 */
294
295/*
296 * The size of reference handle been changed to 16 bits to pass the MSS fields
297 * for the LSO packet
298 */
299
300#define FLAGS_CHECKSUM_ENABLED	0x01
301#define FLAGS_LSO_ENABLED	0x02
302#define FLAGS_IPSEC_SA_ADD	0x04
303#define FLAGS_IPSEC_SA_DELETE	0x08
304#define FLAGS_VLAN_TAGGED	0x10
305
306#define netxen_set_cmd_desc_port(cmd_desc, var)	\
307	((cmd_desc)->port_ctxid |= ((var) & 0x0F))
308#define netxen_set_cmd_desc_ctxid(cmd_desc, var)	\
309	((cmd_desc)->port_ctxid |= ((var) & 0xF0))
310
311#define netxen_set_cmd_desc_flags(cmd_desc, val)	\
312	((cmd_desc)->flags_opcode &= ~cpu_to_le16(0x7f), \
313	(cmd_desc)->flags_opcode |= cpu_to_le16((val) & 0x7f))
314#define netxen_set_cmd_desc_opcode(cmd_desc, val)	\
315	((cmd_desc)->flags_opcode &= ~cpu_to_le16(0x3f<<7), \
316	(cmd_desc)->flags_opcode |= cpu_to_le16(((val & 0x3f)<<7)))
317
318#define netxen_set_cmd_desc_num_of_buff(cmd_desc, val)	\
319	((cmd_desc)->num_of_buffers_total_length &= ~cpu_to_le32(0xff), \
320	(cmd_desc)->num_of_buffers_total_length |= cpu_to_le32((val) & 0xff))
321#define netxen_set_cmd_desc_totallength(cmd_desc, val)	\
322	((cmd_desc)->num_of_buffers_total_length &= ~cpu_to_le32(0xffffff00), \
323	(cmd_desc)->num_of_buffers_total_length |= cpu_to_le32(val << 8))
324
325#define netxen_get_cmd_desc_opcode(cmd_desc)	\
326	((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003F)
327#define netxen_get_cmd_desc_totallength(cmd_desc)	\
328	(le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8)
329
330struct cmd_desc_type0 {
331	u8 tcp_hdr_offset;	/* For LSO only */
332	u8 ip_hdr_offset;	/* For LSO only */
333	/* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
334	__le16 flags_opcode;
335	/* Bit pattern: 0-7 total number of segments,
336	   8-31 Total size of the packet */
337	__le32 num_of_buffers_total_length;
338	union {
339		struct {
340			__le32 addr_low_part2;
341			__le32 addr_high_part2;
342		};
343		__le64 addr_buffer2;
344	};
345
346	__le16 reference_handle;	/* changed to u16 to add mss */
347	__le16 mss;		/* passed by NDIS_PACKET for LSO */
348	/* Bit pattern 0-3 port, 0-3 ctx id */
349	u8 port_ctxid;
350	u8 total_hdr_length;	/* LSO only : MAC+IP+TCP Hdr size */
351	__le16 conn_id;		/* IPSec offoad only */
352
353	union {
354		struct {
355			__le32 addr_low_part3;
356			__le32 addr_high_part3;
357		};
358		__le64 addr_buffer3;
359	};
360	union {
361		struct {
362			__le32 addr_low_part1;
363			__le32 addr_high_part1;
364		};
365		__le64 addr_buffer1;
366	};
367
368	__le16 buffer1_length;
369	__le16 buffer2_length;
370	__le16 buffer3_length;
371	__le16 buffer4_length;
372
373	union {
374		struct {
375			__le32 addr_low_part4;
376			__le32 addr_high_part4;
377		};
378		__le64 addr_buffer4;
379	};
380
381	__le64 unused;
382
383} __attribute__ ((aligned(64)));
384
385/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
386struct rcv_desc {
387	__le16 reference_handle;
388	__le16 reserved;
389	__le32 buffer_length;	/* allocated buffer length (usually 2K) */
390	__le64 addr_buffer;
391};
392
393/* opcode field in status_desc */
394#define RCV_NIC_PKT	(0xA)
395#define STATUS_NIC_PKT	((RCV_NIC_PKT) << 12)
396
397/* for status field in status_desc */
398#define STATUS_NEED_CKSUM	(1)
399#define STATUS_CKSUM_OK		(2)
400
401/* owner bits of status_desc */
402#define STATUS_OWNER_HOST	(0x1)
403#define STATUS_OWNER_PHANTOM	(0x2)
404
405#define NETXEN_PROT_IP		(1)
406#define NETXEN_PROT_UNKNOWN	(0)
407
408/* Note: sizeof(status_desc) should always be a mutliple of 2 */
409
410#define netxen_get_sts_desc_lro_cnt(status_desc)	\
411	((status_desc)->lro & 0x7F)
412#define netxen_get_sts_desc_lro_last_frag(status_desc)	\
413	(((status_desc)->lro & 0x80) >> 7)
414
415#define netxen_get_sts_port(status_desc)	\
416	(le64_to_cpu((status_desc)->status_desc_data) & 0x0F)
417#define netxen_get_sts_status(status_desc)	\
418	((le64_to_cpu((status_desc)->status_desc_data) >> 4) & 0x0F)
419#define netxen_get_sts_type(status_desc)	\
420	((le64_to_cpu((status_desc)->status_desc_data) >> 8) & 0x0F)
421#define netxen_get_sts_totallength(status_desc)	\
422	((le64_to_cpu((status_desc)->status_desc_data) >> 12) & 0xFFFF)
423#define netxen_get_sts_refhandle(status_desc)	\
424	((le64_to_cpu((status_desc)->status_desc_data) >> 28) & 0xFFFF)
425#define netxen_get_sts_prot(status_desc)	\
426	((le64_to_cpu((status_desc)->status_desc_data) >> 44) & 0x0F)
427#define netxen_get_sts_owner(status_desc)	\
428	((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
429#define netxen_get_sts_opcode(status_desc)	\
430	((le64_to_cpu((status_desc)->status_desc_data) >> 58) & 0x03F)
431
432#define netxen_clear_sts_owner(status_desc)	\
433	((status_desc)->status_desc_data &=	\
434	~cpu_to_le64(((unsigned long long)3) << 56 ))
435#define netxen_set_sts_owner(status_desc, val)	\
436	((status_desc)->status_desc_data |=	\
437	cpu_to_le64(((unsigned long long)((val) & 0x3)) << 56 ))
438
439struct status_desc {
440	/* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
441	   28-43 reference_handle, 44-47 protocol, 48-52 unused
442	   53-55 desc_cnt, 56-57 owner, 58-63 opcode
443	 */
444	__le64 status_desc_data;
445	__le32 hash_value;
446	u8 hash_type;
447	u8 msg_type;
448	u8 unused;
449	/* Bit pattern: 0-6 lro_count indicates frag sequence,
450	   7 last_frag indicates last frag */
451	u8 lro;
452} __attribute__ ((aligned(16)));
453
454enum {
455	NETXEN_RCV_PEG_0 = 0,
456	NETXEN_RCV_PEG_1
457};
458/* The version of the main data structure */
459#define	NETXEN_BDINFO_VERSION 1
460
461/* Magic number to let user know flash is programmed */
462#define	NETXEN_BDINFO_MAGIC 0x12345678
463
464/* Max number of Gig ports on a Phantom board */
465#define NETXEN_MAX_PORTS 4
466
467typedef enum {
468	NETXEN_BRDTYPE_P1_BD = 0x0000,
469	NETXEN_BRDTYPE_P1_SB = 0x0001,
470	NETXEN_BRDTYPE_P1_SMAX = 0x0002,
471	NETXEN_BRDTYPE_P1_SOCK = 0x0003,
472
473	NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
474	NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
475	NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
476	NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
477	NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
478
479	NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
480	NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
481	NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f
482} netxen_brdtype_t;
483
484typedef enum {
485	NETXEN_BRDMFG_INVENTEC = 1
486} netxen_brdmfg;
487
488typedef enum {
489	MEM_ORG_128Mbx4 = 0x0,	/* DDR1 only */
490	MEM_ORG_128Mbx8 = 0x1,	/* DDR1 only */
491	MEM_ORG_128Mbx16 = 0x2,	/* DDR1 only */
492	MEM_ORG_256Mbx4 = 0x3,
493	MEM_ORG_256Mbx8 = 0x4,
494	MEM_ORG_256Mbx16 = 0x5,
495	MEM_ORG_512Mbx4 = 0x6,
496	MEM_ORG_512Mbx8 = 0x7,
497	MEM_ORG_512Mbx16 = 0x8,
498	MEM_ORG_1Gbx4 = 0x9,
499	MEM_ORG_1Gbx8 = 0xa,
500	MEM_ORG_1Gbx16 = 0xb,
501	MEM_ORG_2Gbx4 = 0xc,
502	MEM_ORG_2Gbx8 = 0xd,
503	MEM_ORG_2Gbx16 = 0xe,
504	MEM_ORG_128Mbx32 = 0x10002,	/* GDDR only */
505	MEM_ORG_256Mbx32 = 0x10005	/* GDDR only */
506} netxen_mn_mem_org_t;
507
508typedef enum {
509	MEM_ORG_512Kx36 = 0x0,
510	MEM_ORG_1Mx36 = 0x1,
511	MEM_ORG_2Mx36 = 0x2
512} netxen_sn_mem_org_t;
513
514typedef enum {
515	MEM_DEPTH_4MB = 0x1,
516	MEM_DEPTH_8MB = 0x2,
517	MEM_DEPTH_16MB = 0x3,
518	MEM_DEPTH_32MB = 0x4,
519	MEM_DEPTH_64MB = 0x5,
520	MEM_DEPTH_128MB = 0x6,
521	MEM_DEPTH_256MB = 0x7,
522	MEM_DEPTH_512MB = 0x8,
523	MEM_DEPTH_1GB = 0x9,
524	MEM_DEPTH_2GB = 0xa,
525	MEM_DEPTH_4GB = 0xb,
526	MEM_DEPTH_8GB = 0xc,
527	MEM_DEPTH_16GB = 0xd,
528	MEM_DEPTH_32GB = 0xe
529} netxen_mem_depth_t;
530
531struct netxen_board_info {
532	u32 header_version;
533
534	u32 board_mfg;
535	u32 board_type;
536	u32 board_num;
537	u32 chip_id;
538	u32 chip_minor;
539	u32 chip_major;
540	u32 chip_pkg;
541	u32 chip_lot;
542
543	u32 port_mask;		/* available niu ports */
544	u32 peg_mask;		/* available pegs */
545	u32 icache_ok;		/* can we run with icache? */
546	u32 dcache_ok;		/* can we run with dcache? */
547	u32 casper_ok;
548
549	u32 mac_addr_lo_0;
550	u32 mac_addr_lo_1;
551	u32 mac_addr_lo_2;
552	u32 mac_addr_lo_3;
553
554	/* MN-related config */
555	u32 mn_sync_mode;	/* enable/ sync shift cclk/ sync shift mclk */
556	u32 mn_sync_shift_cclk;
557	u32 mn_sync_shift_mclk;
558	u32 mn_wb_en;
559	u32 mn_crystal_freq;	/* in MHz */
560	u32 mn_speed;		/* in MHz */
561	u32 mn_org;
562	u32 mn_depth;
563	u32 mn_ranks_0;		/* ranks per slot */
564	u32 mn_ranks_1;		/* ranks per slot */
565	u32 mn_rd_latency_0;
566	u32 mn_rd_latency_1;
567	u32 mn_rd_latency_2;
568	u32 mn_rd_latency_3;
569	u32 mn_rd_latency_4;
570	u32 mn_rd_latency_5;
571	u32 mn_rd_latency_6;
572	u32 mn_rd_latency_7;
573	u32 mn_rd_latency_8;
574	u32 mn_dll_val[18];
575	u32 mn_mode_reg;	/* MIU DDR Mode Register */
576	u32 mn_ext_mode_reg;	/* MIU DDR Extended Mode Register */
577	u32 mn_timing_0;	/* MIU Memory Control Timing Rgister */
578	u32 mn_timing_1;	/* MIU Extended Memory Ctrl Timing Register */
579	u32 mn_timing_2;	/* MIU Extended Memory Ctrl Timing2 Register */
580
581	/* SN-related config */
582	u32 sn_sync_mode;	/* enable/ sync shift cclk / sync shift mclk */
583	u32 sn_pt_mode;		/* pass through mode */
584	u32 sn_ecc_en;
585	u32 sn_wb_en;
586	u32 sn_crystal_freq;
587	u32 sn_speed;
588	u32 sn_org;
589	u32 sn_depth;
590	u32 sn_dll_tap;
591	u32 sn_rd_latency;
592
593	u32 mac_addr_hi_0;
594	u32 mac_addr_hi_1;
595	u32 mac_addr_hi_2;
596	u32 mac_addr_hi_3;
597
598	u32 magic;		/* indicates flash has been initialized */
599
600	u32 mn_rdimm;
601	u32 mn_dll_override;
602
603};
604
605#define FLASH_NUM_PORTS		(4)
606
607struct netxen_flash_mac_addr {
608	u32 flash_addr[32];
609};
610
611struct netxen_user_old_info {
612	u8 flash_md5[16];
613	u8 crbinit_md5[16];
614	u8 brdcfg_md5[16];
615	/* bootloader */
616	u32 bootld_version;
617	u32 bootld_size;
618	u8 bootld_md5[16];
619	/* image */
620	u32 image_version;
621	u32 image_size;
622	u8 image_md5[16];
623	/* primary image status */
624	u32 primary_status;
625	u32 secondary_present;
626
627	/* MAC address , 4 ports */
628	struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
629};
630#define FLASH_NUM_MAC_PER_PORT	32
631struct netxen_user_info {
632	u8 flash_md5[16 * 64];
633	/* bootloader */
634	u32 bootld_version;
635	u32 bootld_size;
636	/* image */
637	u32 image_version;
638	u32 image_size;
639	/* primary image status */
640	u32 primary_status;
641	u32 secondary_present;
642
643	/* MAC address , 4 ports, 32 address per port */
644	u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
645	u32 sub_sys_id;
646	u8 serial_num[32];
647
648	/* Any user defined data */
649};
650
651/*
652 * Flash Layout - new format.
653 */
654struct netxen_new_user_info {
655	u8 flash_md5[16 * 64];
656	/* bootloader */
657	u32 bootld_version;
658	u32 bootld_size;
659	/* image */
660	u32 image_version;
661	u32 image_size;
662	/* primary image status */
663	u32 primary_status;
664	u32 secondary_present;
665
666	/* MAC address , 4 ports, 32 address per port */
667	u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
668	u32 sub_sys_id;
669	u8 serial_num[32];
670
671	/* Any user defined data */
672};
673
674#define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
675#define SECONDARY_IMAGE_ABSENT	0xffffffff
676#define PRIMARY_IMAGE_GOOD	0x5a5a5a5a
677#define PRIMARY_IMAGE_BAD	0xffffffff
678
679/* Flash memory map */
680typedef enum {
681	NETXEN_CRBINIT_START = 0,	/* Crbinit section */
682	NETXEN_BRDCFG_START = 0x4000,	/* board config */
683	NETXEN_INITCODE_START = 0x6000,	/* pegtune code */
684	NETXEN_BOOTLD_START = 0x10000,	/* bootld */
685	NETXEN_IMAGE_START = 0x43000,	/* compressed image */
686	NETXEN_SECONDARY_START = 0x200000,	/* backup images */
687	NETXEN_PXE_START = 0x3E0000,	/* user defined region */
688	NETXEN_USER_START = 0x3E8000,	/* User defined region for new boards */
689	NETXEN_FIXED_START = 0x3F0000	/* backup of crbinit */
690} netxen_flash_map_t;
691
692#define NETXEN_USER_START_OLD NETXEN_PXE_START	/* for backward compatibility */
693
694#define NETXEN_FLASH_START		(NETXEN_CRBINIT_START)
695#define NETXEN_INIT_SECTOR		(0)
696#define NETXEN_PRIMARY_START 		(NETXEN_BOOTLD_START)
697#define NETXEN_FLASH_CRBINIT_SIZE 	(0x4000)
698#define NETXEN_FLASH_BRDCFG_SIZE 	(sizeof(struct netxen_board_info))
699#define NETXEN_FLASH_USER_SIZE		(sizeof(struct netxen_user_info)/sizeof(u32))
700#define NETXEN_FLASH_SECONDARY_SIZE 	(NETXEN_USER_START-NETXEN_SECONDARY_START)
701#define NETXEN_NUM_PRIMARY_SECTORS	(0x20)
702#define NETXEN_NUM_CONFIG_SECTORS 	(1)
703#define PFX "NetXen: "
704extern char netxen_nic_driver_name[];
705
706/* Note: Make sure to not call this before adapter->port is valid */
707#if !defined(NETXEN_DEBUG)
708#define DPRINTK(klevel, fmt, args...)	do { \
709	} while (0)
710#else
711#define DPRINTK(klevel, fmt, args...)	do { \
712	printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
713		(adapter != NULL && adapter->netdev != NULL) ? \
714		adapter->netdev->name : NULL, \
715		## args); } while(0)
716#endif
717
718/* Number of status descriptors to handle per interrupt */
719#define MAX_STATUS_HANDLE	(128)
720
721/*
722 * netxen_skb_frag{} is to contain mapping info for each SG list. This
723 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
724 */
725struct netxen_skb_frag {
726	u64 dma;
727	u32 length;
728};
729
730#define _netxen_set_bits(config_word, start, bits, val)	{\
731	unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
732	unsigned long long __tvalue = (val);    \
733	(config_word) &= ~__tmask;      \
734	(config_word) |= (((__tvalue) << (start)) & __tmask); \
735}
736
737#define _netxen_clear_bits(config_word, start, bits) {\
738	unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));  \
739	(config_word) &= ~__tmask; \
740}
741
742/*    Following defines are for the state of the buffers    */
743#define	NETXEN_BUFFER_FREE	0
744#define	NETXEN_BUFFER_BUSY	1
745
746/*
747 * There will be one netxen_buffer per skb packet.    These will be
748 * used to save the dma info for pci_unmap_page()
749 */
750struct netxen_cmd_buffer {
751	struct sk_buff *skb;
752	struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
753	u32 total_length;
754	u32 mss;
755	u16 port;
756	u8 cmd;
757	u8 frag_count;
758	unsigned long time_stamp;
759	u32 state;
760};
761
762/* In rx_buffer, we do not need multiple fragments as is a single buffer */
763struct netxen_rx_buffer {
764	struct sk_buff *skb;
765	u64 dma;
766	u16 ref_handle;
767	u16 state;
768	u32 lro_expected_frags;
769	u32 lro_current_frags;
770	u32 lro_length;
771};
772
773/* Board types */
774#define	NETXEN_NIC_GBE	0x01
775#define	NETXEN_NIC_XGBE	0x02
776
777/*
778 * One hardware_context{} per adapter
779 * contains interrupt info as well shared hardware info.
780 */
781struct netxen_hardware_context {
782	struct pci_dev *pdev;
783	void __iomem *pci_base0;
784	void __iomem *pci_base1;
785	void __iomem *pci_base2;
786	unsigned long first_page_group_end;
787	unsigned long first_page_group_start;
788	void __iomem *db_base;
789	unsigned long db_len;
790
791	u8 revision_id;
792	u16 board_type;
793	u16 max_ports;
794	struct netxen_board_info boardcfg;
795	u32 xg_linkup;
796	u32 qg_linksup;
797	/* Address of cmd ring in Phantom */
798	struct cmd_desc_type0 *cmd_desc_head;
799	struct pci_dev *cmd_desc_pdev;
800	dma_addr_t cmd_desc_phys_addr;
801	struct netxen_adapter *adapter;
802	int pci_func;
803};
804
805#define RCV_RING_LRO	RCV_DESC_LRO
806
807#define MINIMUM_ETHERNET_FRAME_SIZE	64	/* With FCS */
808#define ETHERNET_FCS_SIZE		4
809
810struct netxen_adapter_stats {
811	u64  rcvdbadskb;
812	u64  xmitcalled;
813	u64  xmitedframes;
814	u64  xmitfinished;
815	u64  badskblen;
816	u64  nocmddescriptor;
817	u64  polled;
818	u64  uphappy;
819	u64  updropped;
820	u64  uplcong;
821	u64  uphcong;
822	u64  upmcong;
823	u64  updunno;
824	u64  skbfreed;
825	u64  txdropped;
826	u64  txnullskb;
827	u64  csummed;
828	u64  no_rcv;
829	u64  rxbytes;
830	u64  txbytes;
831	u64  ints;
832};
833
834/*
835 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
836 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
837 */
838struct netxen_rcv_desc_ctx {
839	u32 flags;
840	u32 producer;
841	u32 rcv_pending;	/* Num of bufs posted in phantom */
842	u32 rcv_free;		/* Num of bufs in free list */
843	dma_addr_t phys_addr;
844	struct pci_dev *phys_pdev;
845	struct rcv_desc *desc_head;	/* address of rx ring in Phantom */
846	u32 max_rx_desc_count;
847	u32 dma_size;
848	u32 skb_size;
849	struct netxen_rx_buffer *rx_buf_arr;	/* rx buffers for receive   */
850	int begin_alloc;
851};
852
853/*
854 * Receive context. There is one such structure per instance of the
855 * receive processing. Any state information that is relevant to
856 * the receive, and is must be in this structure. The global data may be
857 * present elsewhere.
858 */
859struct netxen_recv_context {
860	struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS];
861	u32 status_rx_producer;
862	u32 status_rx_consumer;
863	dma_addr_t rcv_status_desc_phys_addr;
864	struct pci_dev *rcv_status_desc_pdev;
865	struct status_desc *rcv_status_desc_head;
866};
867
868#define NETXEN_NIC_MSI_ENABLED 0x02
869#define NETXEN_DMA_MASK	0xfffffffe
870#define NETXEN_DB_MAPSIZE_BYTES    0x1000
871
872struct netxen_dummy_dma {
873	void *addr;
874	dma_addr_t phys_addr;
875};
876
877struct netxen_adapter {
878	struct netxen_hardware_context ahw;
879
880	struct netxen_adapter *master;
881	struct net_device *netdev;
882	struct pci_dev *pdev;
883	struct net_device_stats net_stats;
884	unsigned char mac_addr[ETH_ALEN];
885	int mtu;
886	int portnum;
887
888	spinlock_t tx_lock;
889	spinlock_t lock;
890	struct work_struct watchdog_task;
891	struct timer_list watchdog_timer;
892	struct work_struct  tx_timeout_task;
893
894	u32 curr_window;
895
896	u32 cmd_producer;
897	u32 *cmd_consumer;
898
899	u32 last_cmd_consumer;
900	u32 max_tx_desc_count;
901	u32 max_rx_desc_count;
902	u32 max_jumbo_rx_desc_count;
903	u32 max_lro_rx_desc_count;
904	/* Num of instances active on cmd buffer ring */
905	u32 proc_cmd_buf_counter;
906
907	u32 num_threads, total_threads;	/*Use to keep track of xmit threads */
908
909	u32 flags;
910	u32 irq;
911	int driver_mismatch;
912	u32 temp;
913
914	struct netxen_adapter_stats stats;
915
916	u16 portno;
917	u16 link_speed;
918	u16 link_duplex;
919	u16 state;
920	u16 link_autoneg;
921	int rcsum;
922	int status;
923	spinlock_t stats_lock;
924
925	struct netxen_cmd_buffer *cmd_buf_arr;	/* Command buffers for xmit */
926
927	/*
928	 * Receive instances. These can be either one per port,
929	 * or one per peg, etc.
930	 */
931	struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
932
933	int is_up;
934	struct netxen_dummy_dma dummy_dma;
935
936	/* Context interface shared between card and host */
937	struct netxen_ring_ctx *ctx_desc;
938	struct pci_dev *ctx_desc_pdev;
939	dma_addr_t ctx_desc_phys_addr;
940	int intr_scheme;
941	int (*enable_phy_interrupts) (struct netxen_adapter *);
942	int (*disable_phy_interrupts) (struct netxen_adapter *);
943	void (*handle_phy_intr) (struct netxen_adapter *);
944	int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
945	int (*set_mtu) (struct netxen_adapter *, int);
946	int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
947	int (*unset_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
948	int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
949	int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
950	int (*init_port) (struct netxen_adapter *, int);
951	void (*init_niu) (struct netxen_adapter *);
952	int (*stop_port) (struct netxen_adapter *);
953};				/* netxen_adapter structure */
954
955/*
956 * NetXen dma watchdog control structure
957 *
958 *	Bit 0		: enabled => R/O: 1 watchdog active, 0 inactive
959 *	Bit 1		: disable_request => 1 req disable dma watchdog
960 *	Bit 2		: enable_request =>  1 req enable dma watchdog
961 *	Bit 3-31	: unused
962 */
963
964#define netxen_set_dma_watchdog_disable_req(config_word) \
965	_netxen_set_bits(config_word, 1, 1, 1)
966#define netxen_set_dma_watchdog_enable_req(config_word) \
967	_netxen_set_bits(config_word, 2, 1, 1)
968#define netxen_get_dma_watchdog_enabled(config_word) \
969	((config_word) & 0x1)
970#define netxen_get_dma_watchdog_disabled(config_word) \
971	(((config_word) >> 1) & 0x1)
972
973/* Max number of xmit producer threads that can run simultaneously */
974#define	MAX_XMIT_PRODUCERS		16
975
976#define PCI_OFFSET_FIRST_RANGE(adapter, off)    \
977	((adapter)->ahw.pci_base0 + (off))
978#define PCI_OFFSET_SECOND_RANGE(adapter, off)   \
979	((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
980#define PCI_OFFSET_THIRD_RANGE(adapter, off)    \
981	((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
982
983static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
984					    unsigned long off)
985{
986	if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
987		return (adapter->ahw.pci_base0 + off);
988	} else if ((off < SECOND_PAGE_GROUP_END) &&
989		   (off >= SECOND_PAGE_GROUP_START)) {
990		return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
991	} else if ((off < THIRD_PAGE_GROUP_END) &&
992		   (off >= THIRD_PAGE_GROUP_START)) {
993		return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
994	}
995	return NULL;
996}
997
998static inline void __iomem *pci_base(struct netxen_adapter *adapter,
999				     unsigned long off)
1000{
1001	if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1002		return adapter->ahw.pci_base0;
1003	} else if ((off < SECOND_PAGE_GROUP_END) &&
1004		   (off >= SECOND_PAGE_GROUP_START)) {
1005		return adapter->ahw.pci_base1;
1006	} else if ((off < THIRD_PAGE_GROUP_END) &&
1007		   (off >= THIRD_PAGE_GROUP_START)) {
1008		return adapter->ahw.pci_base2;
1009	}
1010	return NULL;
1011}
1012
1013int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1014int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1015int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1016int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1017int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter);
1018int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter);
1019void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter);
1020void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter);
1021void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port,
1022				 long enable);
1023void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port,
1024				  long enable);
1025int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1026			    __u32 * readval);
1027int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1028			     long reg, __u32 val);
1029
1030/* Functions available from netxen_nic_hw.c */
1031int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1032int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1033void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
1034void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
1035void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1036int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1037void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1038void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value);
1039
1040int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1041int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
1042			  int len);
1043int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
1044			   int len);
1045void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1046				 unsigned long off, int data);
1047int netxen_nic_erase_pxe(struct netxen_adapter *adapter);
1048
1049/* Functions from netxen_nic_init.c */
1050void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1051int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1052int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1053int netxen_load_firmware(struct netxen_adapter *adapter);
1054int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1055int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1056int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1057				u8 *bytes, size_t size);
1058int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1059				u8 *bytes, size_t size);
1060int netxen_flash_unlock(struct netxen_adapter *adapter);
1061int netxen_backup_crbinit(struct netxen_adapter *adapter);
1062int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1063int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1064void netxen_halt_pegs(struct netxen_adapter *adapter);
1065
1066int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data);
1067int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1068int netxen_do_rom_se(struct netxen_adapter *adapter, int addr);
1069
1070/* Functions from netxen_nic_isr.c */
1071int netxen_nic_link_ok(struct netxen_adapter *adapter);
1072void netxen_nic_isr_other(struct netxen_adapter *adapter);
1073void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 link);
1074void netxen_handle_port_int(struct netxen_adapter *adapter, u32 enable);
1075void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
1076void netxen_initialize_adapter_hw(struct netxen_adapter *adapter);
1077void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
1078		   struct pci_dev **used_dev);
1079void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1080int netxen_init_firmware(struct netxen_adapter *adapter);
1081void netxen_free_hw_resources(struct netxen_adapter *adapter);
1082void netxen_tso_check(struct netxen_adapter *adapter,
1083		      struct cmd_desc_type0 *desc, struct sk_buff *skb);
1084int netxen_nic_hw_resources(struct netxen_adapter *adapter);
1085void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1086int netxen_nic_rx_has_work(struct netxen_adapter *adapter);
1087int netxen_nic_tx_has_work(struct netxen_adapter *adapter);
1088void netxen_watchdog_task(struct work_struct *work);
1089void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
1090			    u32 ringid);
1091void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, u32 ctx,
1092				 u32 ringid);
1093int netxen_process_cmd_ring(unsigned long data);
1094u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1095void netxen_nic_set_multi(struct net_device *netdev);
1096int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1097int netxen_nic_set_mac(struct net_device *netdev, void *p);
1098struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1099
1100static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
1101{
1102	uint32_t	mask = 0x7ff;
1103	int retries = 32;
1104
1105	DPRINTK(1, INFO, "Entered ISR Disable \n");
1106
1107	switch (adapter->portnum) {
1108	case 0:
1109		writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
1110		break;
1111	case 1:
1112		writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
1113		break;
1114	case 2:
1115		writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
1116		break;
1117	case 3:
1118		writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
1119		break;
1120	}
1121
1122	if (adapter->intr_scheme != -1 &&
1123		adapter->intr_scheme != INTR_SCHEME_PERPORT) {
1124		writel(mask,
1125			(void *)(PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)));
1126	}
1127
1128	/* Window = 0 or 1 */
1129	if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
1130		do {
1131			writel(0xffffffff, (void *)
1132				(PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_TARGET_STATUS)));
1133			mask = readl((void *)
1134					(pci_base_offset(adapter, ISR_INT_VECTOR)));
1135			if (!(mask & 0x80))
1136				break;
1137			udelay(10);
1138		} while (--retries);
1139
1140		if (!retries) {
1141			printk(KERN_NOTICE "%s: Failed to disable interrupt completely\n",
1142					netxen_nic_driver_name);
1143		}
1144	}
1145
1146	DPRINTK(1, INFO, "Done with Disable Int\n");
1147
1148	return;
1149}
1150
1151static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
1152{
1153	u32 mask;
1154
1155	DPRINTK(1, INFO, "Entered ISR Enable \n");
1156
1157	if (adapter->intr_scheme != -1 &&
1158		adapter->intr_scheme != INTR_SCHEME_PERPORT) {
1159		switch (adapter->ahw.board_type) {
1160		case NETXEN_NIC_GBE:
1161			mask  =  0x77b;
1162			break;
1163		case NETXEN_NIC_XGBE:
1164			mask  =  0x77f;
1165			break;
1166		default:
1167			mask  =  0x7ff;
1168			break;
1169		}
1170
1171		writel(mask,
1172			(void *)(PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)));
1173	}
1174	switch (adapter->portnum) {
1175	case 0:
1176		writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
1177		break;
1178	case 1:
1179		writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
1180		break;
1181	case 2:
1182		writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
1183		break;
1184	case 3:
1185		writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
1186		break;
1187	}
1188
1189	if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
1190		mask = 0xbff;
1191		if (adapter->intr_scheme != -1 &&
1192			adapter->intr_scheme != INTR_SCHEME_PERPORT) {
1193			writel(0X0, NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR));
1194		}
1195		writel(mask,
1196			(void *)(PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_TARGET_MASK)));
1197	}
1198
1199	DPRINTK(1, INFO, "Done with enable Int\n");
1200
1201	return;
1202}
1203
1204/*
1205 * NetXen Board information
1206 */
1207
1208#define NETXEN_MAX_SHORT_NAME 16
1209struct netxen_brdinfo {
1210	netxen_brdtype_t brdtype;	/* type of board */
1211	long ports;		/* max no of physical ports */
1212	char short_name[NETXEN_MAX_SHORT_NAME];
1213};
1214
1215static const struct netxen_brdinfo netxen_boards[] = {
1216	{NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1217	{NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1218	{NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1219	{NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1220	{NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1221	{NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1222};
1223
1224#define NUM_SUPPORTED_BOARDS (sizeof(netxen_boards)/sizeof(struct netxen_brdinfo))
1225
1226static inline void get_brd_port_by_type(u32 type, int *ports)
1227{
1228	int i, found = 0;
1229	for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1230		if (netxen_boards[i].brdtype == type) {
1231			*ports = netxen_boards[i].ports;
1232			found = 1;
1233			break;
1234		}
1235	}
1236	if (!found)
1237		*ports = 0;
1238}
1239
1240static inline void get_brd_name_by_type(u32 type, char *name)
1241{
1242	int i, found = 0;
1243	for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1244		if (netxen_boards[i].brdtype == type) {
1245			strcpy(name, netxen_boards[i].short_name);
1246			found = 1;
1247			break;
1248		}
1249
1250	}
1251	if (!found)
1252		name = "Unknown";
1253}
1254
1255static inline int
1256dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1257{
1258	u32 ctrl;
1259
1260	/* check if already inactive */
1261	if (netxen_nic_hw_read_wx(adapter,
1262	    NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1263		printk(KERN_ERR "failed to read dma watchdog status\n");
1264
1265	if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1266		return 1;
1267
1268	/* Send the disable request */
1269	netxen_set_dma_watchdog_disable_req(ctrl);
1270	netxen_crb_writelit_adapter(adapter,
1271		NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1272
1273	return 0;
1274}
1275
1276static inline int
1277dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1278{
1279	u32 ctrl;
1280
1281	if (netxen_nic_hw_read_wx(adapter,
1282	    NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1283		printk(KERN_ERR "failed to read dma watchdog status\n");
1284
1285	return ((netxen_get_dma_watchdog_enabled(ctrl) == 0) &&
1286		(netxen_get_dma_watchdog_disabled(ctrl) == 0));
1287}
1288
1289static inline int
1290dma_watchdog_wakeup(struct netxen_adapter *adapter)
1291{
1292	u32 ctrl;
1293
1294	if (netxen_nic_hw_read_wx(adapter,
1295		NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1296		printk(KERN_ERR "failed to read dma watchdog status\n");
1297
1298	if (netxen_get_dma_watchdog_enabled(ctrl))
1299		return 1;
1300
1301	/* send the wakeup request */
1302	netxen_set_dma_watchdog_enable_req(ctrl);
1303
1304	netxen_crb_writelit_adapter(adapter,
1305		NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1306
1307	return 0;
1308}
1309
1310
1311int netxen_is_flash_supported(struct netxen_adapter *adapter);
1312int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]);
1313extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1314extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1315				int *valp);
1316
1317extern struct ethtool_ops netxen_nic_ethtool_ops;
1318
1319extern int physical_port[];	/* physical port # from virtual port.*/
1320#endif				/* __NETXEN_NIC_H_ */
1321