1#ifndef __MYRI10GE_MCP_H__ 2#define __MYRI10GE_MCP_H__ 3 4#define MXGEFW_VERSION_MAJOR 1 5#define MXGEFW_VERSION_MINOR 4 6 7/* 8 Bytes */ 8struct mcp_dma_addr { 9 __be32 high; 10 __be32 low; 11}; 12 13/* 4 Bytes */ 14struct mcp_slot { 15 __sum16 checksum; 16 __be16 length; 17}; 18 19/* 64 Bytes */ 20struct mcp_cmd { 21 __be32 cmd; 22 __be32 data0; /* will be low portion if data > 32 bits */ 23 /* 8 */ 24 __be32 data1; /* will be high portion if data > 32 bits */ 25 __be32 data2; /* currently unused.. */ 26 /* 16 */ 27 struct mcp_dma_addr response_addr; 28 /* 24 */ 29 u8 pad[40]; 30}; 31 32/* 8 Bytes */ 33struct mcp_cmd_response { 34 __be32 data; 35 __be32 result; 36}; 37 38/* 39 * flags used in mcp_kreq_ether_send_t: 40 * 41 * The SMALL flag is only needed in the first segment. It is raised 42 * for packets that are total less or equal 512 bytes. 43 * 44 * The CKSUM flag must be set in all segments. 45 * 46 * The PADDED flags is set if the packet needs to be padded, and it 47 * must be set for all segments. 48 * 49 * The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 50 * length of all previous segments was odd. 51 */ 52 53#define MXGEFW_FLAGS_SMALL 0x1 54#define MXGEFW_FLAGS_TSO_HDR 0x1 55#define MXGEFW_FLAGS_FIRST 0x2 56#define MXGEFW_FLAGS_ALIGN_ODD 0x4 57#define MXGEFW_FLAGS_CKSUM 0x8 58#define MXGEFW_FLAGS_TSO_LAST 0x8 59#define MXGEFW_FLAGS_NO_TSO 0x10 60#define MXGEFW_FLAGS_TSO_CHOP 0x10 61#define MXGEFW_FLAGS_TSO_PLD 0x20 62 63#define MXGEFW_SEND_SMALL_SIZE 1520 64#define MXGEFW_MAX_MTU 9400 65 66union mcp_pso_or_cumlen { 67 u16 pseudo_hdr_offset; 68 u16 cum_len; 69}; 70 71#define MXGEFW_MAX_SEND_DESC 12 72#define MXGEFW_PAD 2 73 74/* 16 Bytes */ 75struct mcp_kreq_ether_send { 76 __be32 addr_high; 77 __be32 addr_low; 78 __be16 pseudo_hdr_offset; 79 __be16 length; 80 u8 pad; 81 u8 rdma_count; 82 u8 cksum_offset; /* where to start computing cksum */ 83 u8 flags; /* as defined above */ 84}; 85 86/* 8 Bytes */ 87struct mcp_kreq_ether_recv { 88 __be32 addr_high; 89 __be32 addr_low; 90}; 91 92/* Commands */ 93 94#define MXGEFW_BOOT_HANDOFF 0xfc0000 95#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 96 97#define MXGEFW_ETH_CMD 0xf80000 98#define MXGEFW_ETH_SEND_4 0x200000 99#define MXGEFW_ETH_SEND_1 0x240000 100#define MXGEFW_ETH_SEND_2 0x280000 101#define MXGEFW_ETH_SEND_3 0x2c0000 102#define MXGEFW_ETH_RECV_SMALL 0x300000 103#define MXGEFW_ETH_RECV_BIG 0x340000 104 105#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 106#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 107 108enum myri10ge_mcp_cmd_type { 109 MXGEFW_CMD_NONE = 0, 110 /* Reset the mcp, it is left in a safe state, waiting 111 * for the driver to set all its parameters */ 112 MXGEFW_CMD_RESET, 113 114 /* get the version number of the current firmware.. 115 * (may be available in the eeprom strings..? */ 116 MXGEFW_GET_MCP_VERSION, 117 118 /* Parameters which must be set by the driver before it can 119 * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 120 * MXGEFW_CMD_RESET is issued */ 121 122 MXGEFW_CMD_SET_INTRQ_DMA, 123 MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ 124 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ 125 126 /* Parameters which refer to lanai SRAM addresses where the 127 * driver must issue PIO writes for various things */ 128 129 MXGEFW_CMD_GET_SEND_OFFSET, 130 MXGEFW_CMD_GET_SMALL_RX_OFFSET, 131 MXGEFW_CMD_GET_BIG_RX_OFFSET, 132 MXGEFW_CMD_GET_IRQ_ACK_OFFSET, 133 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 134 135 /* Parameters which refer to rings stored on the MCP, 136 * and whose size is controlled by the mcp */ 137 138 MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */ 139 MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */ 140 141 /* Parameters which refer to rings stored in the host, 142 * and whose size is controlled by the host. Note that 143 * all must be physically contiguous and must contain 144 * a power of 2 number of entries. */ 145 146 MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */ 147 148 /* command to bring ethernet interface up. Above parameters 149 * (plus mtu & mac address) must have been exchanged prior 150 * to issuing this command */ 151 MXGEFW_CMD_ETHERNET_UP, 152 153 /* command to bring ethernet interface down. No further sends 154 * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 155 * is issued, and all interrupt queues must be flushed prior 156 * to ack'ing this command */ 157 158 MXGEFW_CMD_ETHERNET_DOWN, 159 160 /* commands the driver may issue live, without resetting 161 * the nic. Note that increasing the mtu "live" should 162 * only be done if the driver has already supplied buffers 163 * sufficiently large to handle the new mtu. Decreasing 164 * the mtu live is safe */ 165 166 MXGEFW_CMD_SET_MTU, 167 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ 168 MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ 169 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */ 170 171 MXGEFW_ENABLE_PROMISC, 172 MXGEFW_DISABLE_PROMISC, 173 MXGEFW_SET_MAC_ADDRESS, 174 175 MXGEFW_ENABLE_FLOW_CONTROL, 176 MXGEFW_DISABLE_FLOW_CONTROL, 177 178 /* do a DMA test 179 * data0,data1 = DMA address 180 * data2 = RDMA length (MSH), WDMA length (LSH) 181 * command return data = repetitions (MSH), 0.5-ms ticks (LSH) 182 */ 183 MXGEFW_DMA_TEST, 184 185 MXGEFW_ENABLE_ALLMULTI, 186 MXGEFW_DISABLE_ALLMULTI, 187 188 /* returns MXGEFW_CMD_ERROR_MULTICAST 189 * if there is no room in the cache 190 * data0,MSH(data1) = multicast group address */ 191 MXGEFW_JOIN_MULTICAST_GROUP, 192 /* returns MXGEFW_CMD_ERROR_MULTICAST 193 * if the address is not in the cache, 194 * or is equal to FF-FF-FF-FF-FF-FF 195 * data0,MSH(data1) = multicast group address */ 196 MXGEFW_LEAVE_MULTICAST_GROUP, 197 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, 198 199 MXGEFW_CMD_SET_STATS_DMA_V2, 200 /* data0, data1 = bus addr, 201 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 202 * adding new stuff to mcp_irq_data without changing the ABI */ 203 204 MXGEFW_CMD_UNALIGNED_TEST, 205 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 206 * chipset */ 207 208 MXGEFW_CMD_UNALIGNED_STATUS 209 /* return data = boolean, true if the chipset is known to be unaligned */ 210}; 211 212enum myri10ge_mcp_cmd_status { 213 MXGEFW_CMD_OK = 0, 214 MXGEFW_CMD_UNKNOWN, 215 MXGEFW_CMD_ERROR_RANGE, 216 MXGEFW_CMD_ERROR_BUSY, 217 MXGEFW_CMD_ERROR_EMPTY, 218 MXGEFW_CMD_ERROR_CLOSED, 219 MXGEFW_CMD_ERROR_HASH_ERROR, 220 MXGEFW_CMD_ERROR_BAD_PORT, 221 MXGEFW_CMD_ERROR_RESOURCES, 222 MXGEFW_CMD_ERROR_MULTICAST, 223 MXGEFW_CMD_ERROR_UNALIGNED 224}; 225 226#define MXGEFW_OLD_IRQ_DATA_LEN 40 227 228struct mcp_irq_data { 229 /* add new counters at the beginning */ 230 __be32 future_use[1]; 231 __be32 dropped_pause; 232 __be32 dropped_unicast_filtered; 233 __be32 dropped_bad_crc32; 234 __be32 dropped_bad_phy; 235 __be32 dropped_multicast_filtered; 236 /* 40 Bytes */ 237 __be32 send_done_count; 238 239#define MXGEFW_LINK_DOWN 0 240#define MXGEFW_LINK_UP 1 241#define MXGEFW_LINK_MYRINET 2 242#define MXGEFW_LINK_UNKNOWN 3 243 __be32 link_up; 244 __be32 dropped_link_overflow; 245 __be32 dropped_link_error_or_filtered; 246 __be32 dropped_runt; 247 __be32 dropped_overrun; 248 __be32 dropped_no_small_buffer; 249 __be32 dropped_no_big_buffer; 250 __be32 rdma_tags_available; 251 252 u8 tx_stopped; 253 u8 link_down; 254 u8 stats_updated; 255 u8 valid; 256}; 257 258#endif /* __MYRI10GE_MCP_H__ */ 259