1/* 2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 4 * 5 * Based on the 64360 driver from: 6 * Copyright (C) 2002 rabeeh@galileo.co.il 7 * 8 * Copyright (C) 2003 PMC-Sierra, Inc., 9 * written by Manish Lachwani 10 * 11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 12 * 13 * Copyright (C) 2004-2006 MontaVista Software, Inc. 14 * Dale Farnsworth <dale@farnsworth.org> 15 * 16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 17 * <sjhill@realitydiluted.com> 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 2 22 * of the License, or (at your option) any later version. 23 * 24 * This program is distributed in the hope that it will be useful, 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * GNU General Public License for more details. 28 * 29 * You should have received a copy of the GNU General Public License 30 * along with this program; if not, write to the Free Software 31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 32 */ 33#include <linux/init.h> 34#include <linux/dma-mapping.h> 35#include <linux/in.h> 36#include <linux/ip.h> 37#include <linux/tcp.h> 38#include <linux/udp.h> 39#include <linux/etherdevice.h> 40 41#include <linux/bitops.h> 42#include <linux/delay.h> 43#include <linux/ethtool.h> 44#include <linux/platform_device.h> 45 46#include <asm/io.h> 47#include <asm/types.h> 48#include <asm/pgtable.h> 49#include <asm/system.h> 50#include <asm/delay.h> 51#include "mv643xx_eth.h" 52 53/* Static function declarations */ 54static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr); 55static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr); 56static void eth_port_set_multicast_list(struct net_device *); 57static void mv643xx_eth_port_enable_tx(unsigned int port_num, 58 unsigned int queues); 59static void mv643xx_eth_port_enable_rx(unsigned int port_num, 60 unsigned int queues); 61static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num); 62static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num); 63static int mv643xx_eth_open(struct net_device *); 64static int mv643xx_eth_stop(struct net_device *); 65static int mv643xx_eth_change_mtu(struct net_device *, int); 66static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *); 67static void eth_port_init_mac_tables(unsigned int eth_port_num); 68#ifdef MV643XX_NAPI 69static int mv643xx_poll(struct net_device *dev, int *budget); 70#endif 71static int ethernet_phy_get(unsigned int eth_port_num); 72static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); 73static int ethernet_phy_detect(unsigned int eth_port_num); 74static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location); 75static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val); 76static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); 77static const struct ethtool_ops mv643xx_ethtool_ops; 78 79static char mv643xx_driver_name[] = "mv643xx_eth"; 80static char mv643xx_driver_version[] = "1.0"; 81 82static void __iomem *mv643xx_eth_shared_base; 83 84/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */ 85static DEFINE_SPINLOCK(mv643xx_eth_phy_lock); 86 87static inline u32 mv_read(int offset) 88{ 89 void __iomem *reg_base; 90 91 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; 92 93 return readl(reg_base + offset); 94} 95 96static inline void mv_write(int offset, u32 data) 97{ 98 void __iomem *reg_base; 99 100 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; 101 writel(data, reg_base + offset); 102} 103 104/* 105 * Changes MTU (maximum transfer unit) of the gigabit ethenret port 106 * 107 * Input : pointer to ethernet interface network device structure 108 * new mtu size 109 * Output : 0 upon success, -EINVAL upon failure 110 */ 111static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) 112{ 113 if ((new_mtu > 9500) || (new_mtu < 64)) 114 return -EINVAL; 115 116 dev->mtu = new_mtu; 117 /* 118 * Stop then re-open the interface. This will allocate RX skb's with 119 * the new MTU. 120 * There is a possible danger that the open will not successed, due 121 * to memory is full, which might fail the open function. 122 */ 123 if (netif_running(dev)) { 124 mv643xx_eth_stop(dev); 125 if (mv643xx_eth_open(dev)) 126 printk(KERN_ERR 127 "%s: Fatal error on opening device\n", 128 dev->name); 129 } 130 131 return 0; 132} 133 134/* 135 * mv643xx_eth_rx_refill_descs 136 * 137 * Fills / refills RX queue on a certain gigabit ethernet port 138 * 139 * Input : pointer to ethernet interface network device structure 140 * Output : N/A 141 */ 142static void mv643xx_eth_rx_refill_descs(struct net_device *dev) 143{ 144 struct mv643xx_private *mp = netdev_priv(dev); 145 struct pkt_info pkt_info; 146 struct sk_buff *skb; 147 int unaligned; 148 149 while (mp->rx_desc_count < mp->rx_ring_size) { 150 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); 151 if (!skb) 152 break; 153 mp->rx_desc_count++; 154 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); 155 if (unaligned) 156 skb_reserve(skb, dma_get_cache_alignment() - unaligned); 157 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; 158 pkt_info.byte_cnt = ETH_RX_SKB_SIZE; 159 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, 160 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); 161 pkt_info.return_info = skb; 162 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { 163 printk(KERN_ERR 164 "%s: Error allocating RX Ring\n", dev->name); 165 break; 166 } 167 skb_reserve(skb, ETH_HW_IP_ALIGN); 168 } 169 /* 170 * If RX ring is empty of SKB, set a timer to try allocating 171 * again at a later time. 172 */ 173 if (mp->rx_desc_count == 0) { 174 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); 175 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ 176 add_timer(&mp->timeout); 177 } 178} 179 180/* 181 * mv643xx_eth_rx_refill_descs_timer_wrapper 182 * 183 * Timer routine to wake up RX queue filling task. This function is 184 * used only in case the RX queue is empty, and all alloc_skb has 185 * failed (due to out of memory event). 186 * 187 * Input : pointer to ethernet interface network device structure 188 * Output : N/A 189 */ 190static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) 191{ 192 mv643xx_eth_rx_refill_descs((struct net_device *)data); 193} 194 195/* 196 * mv643xx_eth_update_mac_address 197 * 198 * Update the MAC address of the port in the address table 199 * 200 * Input : pointer to ethernet interface network device structure 201 * Output : N/A 202 */ 203static void mv643xx_eth_update_mac_address(struct net_device *dev) 204{ 205 struct mv643xx_private *mp = netdev_priv(dev); 206 unsigned int port_num = mp->port_num; 207 208 eth_port_init_mac_tables(port_num); 209 eth_port_uc_addr_set(port_num, dev->dev_addr); 210} 211 212/* 213 * mv643xx_eth_set_rx_mode 214 * 215 * Change from promiscuos to regular rx mode 216 * 217 * Input : pointer to ethernet interface network device structure 218 * Output : N/A 219 */ 220static void mv643xx_eth_set_rx_mode(struct net_device *dev) 221{ 222 struct mv643xx_private *mp = netdev_priv(dev); 223 u32 config_reg; 224 225 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num)); 226 if (dev->flags & IFF_PROMISC) 227 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; 228 else 229 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; 230 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg); 231 232 eth_port_set_multicast_list(dev); 233} 234 235/* 236 * mv643xx_eth_set_mac_address 237 * 238 * Change the interface's mac address. 239 * No special hardware thing should be done because interface is always 240 * put in promiscuous mode. 241 * 242 * Input : pointer to ethernet interface network device structure and 243 * a pointer to the designated entry to be added to the cache. 244 * Output : zero upon success, negative upon failure 245 */ 246static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) 247{ 248 int i; 249 250 for (i = 0; i < 6; i++) 251 /* +2 is for the offset of the HW addr type */ 252 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; 253 mv643xx_eth_update_mac_address(dev); 254 return 0; 255} 256 257/* 258 * mv643xx_eth_tx_timeout 259 * 260 * Called upon a timeout on transmitting a packet 261 * 262 * Input : pointer to ethernet interface network device structure. 263 * Output : N/A 264 */ 265static void mv643xx_eth_tx_timeout(struct net_device *dev) 266{ 267 struct mv643xx_private *mp = netdev_priv(dev); 268 269 printk(KERN_INFO "%s: TX timeout ", dev->name); 270 271 /* Do the reset outside of interrupt context */ 272 schedule_work(&mp->tx_timeout_task); 273} 274 275/* 276 * mv643xx_eth_tx_timeout_task 277 * 278 * Actual routine to reset the adapter when a timeout on Tx has occurred 279 */ 280static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) 281{ 282 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, 283 tx_timeout_task); 284 struct net_device *dev = mp->mii.dev; /* yuck */ 285 286 if (!netif_running(dev)) 287 return; 288 289 netif_stop_queue(dev); 290 291 eth_port_reset(mp->port_num); 292 eth_port_start(dev); 293 294 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) 295 netif_wake_queue(dev); 296} 297 298/** 299 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors 300 * 301 * If force is non-zero, frees uncompleted descriptors as well 302 */ 303int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) 304{ 305 struct mv643xx_private *mp = netdev_priv(dev); 306 struct eth_tx_desc *desc; 307 u32 cmd_sts; 308 struct sk_buff *skb; 309 unsigned long flags; 310 int tx_index; 311 dma_addr_t addr; 312 int count; 313 int released = 0; 314 315 while (mp->tx_desc_count > 0) { 316 spin_lock_irqsave(&mp->lock, flags); 317 318 /* tx_desc_count might have changed before acquiring the lock */ 319 if (mp->tx_desc_count <= 0) { 320 spin_unlock_irqrestore(&mp->lock, flags); 321 return released; 322 } 323 324 tx_index = mp->tx_used_desc_q; 325 desc = &mp->p_tx_desc_area[tx_index]; 326 cmd_sts = desc->cmd_sts; 327 328 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { 329 spin_unlock_irqrestore(&mp->lock, flags); 330 return released; 331 } 332 333 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; 334 mp->tx_desc_count--; 335 336 addr = desc->buf_ptr; 337 count = desc->byte_cnt; 338 skb = mp->tx_skb[tx_index]; 339 if (skb) 340 mp->tx_skb[tx_index] = NULL; 341 342 if (cmd_sts & ETH_ERROR_SUMMARY) { 343 printk("%s: Error in TX\n", dev->name); 344 mp->stats.tx_errors++; 345 } 346 347 spin_unlock_irqrestore(&mp->lock, flags); 348 349 if (cmd_sts & ETH_TX_FIRST_DESC) 350 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 351 else 352 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); 353 354 if (skb) 355 dev_kfree_skb_irq(skb); 356 357 released = 1; 358 } 359 360 return released; 361} 362 363static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) 364{ 365 struct mv643xx_private *mp = netdev_priv(dev); 366 367 if (mv643xx_eth_free_tx_descs(dev, 0) && 368 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) 369 netif_wake_queue(dev); 370} 371 372static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) 373{ 374 mv643xx_eth_free_tx_descs(dev, 1); 375} 376 377/* 378 * mv643xx_eth_receive 379 * 380 * This function is forward packets that are received from the port's 381 * queues toward kernel core or FastRoute them to another interface. 382 * 383 * Input : dev - a pointer to the required interface 384 * max - maximum number to receive (0 means unlimted) 385 * 386 * Output : number of served packets 387 */ 388static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) 389{ 390 struct mv643xx_private *mp = netdev_priv(dev); 391 struct net_device_stats *stats = &mp->stats; 392 unsigned int received_packets = 0; 393 struct sk_buff *skb; 394 struct pkt_info pkt_info; 395 396 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { 397 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, 398 DMA_FROM_DEVICE); 399 mp->rx_desc_count--; 400 received_packets++; 401 402 /* 403 * Update statistics. 404 * Note byte count includes 4 byte CRC count 405 */ 406 stats->rx_packets++; 407 stats->rx_bytes += pkt_info.byte_cnt; 408 skb = pkt_info.return_info; 409 /* 410 * In case received a packet without first / last bits on OR 411 * the error summary bit is on, the packets needs to be dropeed. 412 */ 413 if (((pkt_info.cmd_sts 414 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != 415 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) 416 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { 417 stats->rx_dropped++; 418 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | 419 ETH_RX_LAST_DESC)) != 420 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { 421 if (net_ratelimit()) 422 printk(KERN_ERR 423 "%s: Received packet spread " 424 "on multiple descriptors\n", 425 dev->name); 426 } 427 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) 428 stats->rx_errors++; 429 430 dev_kfree_skb_irq(skb); 431 } else { 432 /* 433 * The -4 is for the CRC in the trailer of the 434 * received packet 435 */ 436 skb_put(skb, pkt_info.byte_cnt - 4); 437 438 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { 439 skb->ip_summed = CHECKSUM_UNNECESSARY; 440 skb->csum = htons( 441 (pkt_info.cmd_sts & 0x0007fff8) >> 3); 442 } 443 skb->protocol = eth_type_trans(skb, dev); 444#ifdef MV643XX_NAPI 445 netif_receive_skb(skb); 446#else 447 netif_rx(skb); 448#endif 449 } 450 dev->last_rx = jiffies; 451 } 452 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ 453 454 return received_packets; 455} 456 457/* Set the mv643xx port configuration register for the speed/duplex mode. */ 458static void mv643xx_eth_update_pscr(struct net_device *dev, 459 struct ethtool_cmd *ecmd) 460{ 461 struct mv643xx_private *mp = netdev_priv(dev); 462 int port_num = mp->port_num; 463 u32 o_pscr, n_pscr; 464 unsigned int queues; 465 466 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); 467 n_pscr = o_pscr; 468 469 /* clear speed, duplex and rx buffer size fields */ 470 n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 | 471 MV643XX_ETH_SET_GMII_SPEED_TO_1000 | 472 MV643XX_ETH_SET_FULL_DUPLEX_MODE | 473 MV643XX_ETH_MAX_RX_PACKET_MASK); 474 475 if (ecmd->duplex == DUPLEX_FULL) 476 n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE; 477 478 if (ecmd->speed == SPEED_1000) 479 n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 | 480 MV643XX_ETH_MAX_RX_PACKET_9700BYTE; 481 else { 482 if (ecmd->speed == SPEED_100) 483 n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100; 484 n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE; 485 } 486 487 if (n_pscr != o_pscr) { 488 if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0) 489 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), 490 n_pscr); 491 else { 492 queues = mv643xx_eth_port_disable_tx(port_num); 493 494 o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE; 495 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), 496 o_pscr); 497 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), 498 n_pscr); 499 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), 500 n_pscr); 501 if (queues) 502 mv643xx_eth_port_enable_tx(port_num, queues); 503 } 504 } 505} 506 507/* 508 * mv643xx_eth_int_handler 509 * 510 * Main interrupt handler for the gigbit ethernet ports 511 * 512 * Input : irq - irq number (not used) 513 * dev_id - a pointer to the required interface's data structure 514 * regs - not used 515 * Output : N/A 516 */ 517 518static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) 519{ 520 struct net_device *dev = (struct net_device *)dev_id; 521 struct mv643xx_private *mp = netdev_priv(dev); 522 u32 eth_int_cause, eth_int_cause_ext = 0; 523 unsigned int port_num = mp->port_num; 524 525 /* Read interrupt cause registers */ 526 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) & 527 ETH_INT_UNMASK_ALL; 528 if (eth_int_cause & ETH_INT_CAUSE_EXT) { 529 eth_int_cause_ext = mv_read( 530 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) & 531 ETH_INT_UNMASK_ALL_EXT; 532 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 533 ~eth_int_cause_ext); 534 } 535 536 /* PHY status changed */ 537 if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) { 538 struct ethtool_cmd cmd; 539 540 if (mii_link_ok(&mp->mii)) { 541 mii_ethtool_gset(&mp->mii, &cmd); 542 mv643xx_eth_update_pscr(dev, &cmd); 543 mv643xx_eth_port_enable_tx(port_num, 544 ETH_TX_QUEUES_ENABLED); 545 if (!netif_carrier_ok(dev)) { 546 netif_carrier_on(dev); 547 if (mp->tx_ring_size - mp->tx_desc_count >= 548 MAX_DESCS_PER_SKB) 549 netif_wake_queue(dev); 550 } 551 } else if (netif_carrier_ok(dev)) { 552 netif_stop_queue(dev); 553 netif_carrier_off(dev); 554 } 555 } 556 557#ifdef MV643XX_NAPI 558 if (eth_int_cause & ETH_INT_CAUSE_RX) { 559 /* schedule the NAPI poll routine to maintain port */ 560 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 561 ETH_INT_MASK_ALL); 562 /* wait for previous write to complete */ 563 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); 564 565 netif_rx_schedule(dev); 566 } 567#else 568 if (eth_int_cause & ETH_INT_CAUSE_RX) 569 mv643xx_eth_receive_queue(dev, INT_MAX); 570#endif 571 if (eth_int_cause_ext & ETH_INT_CAUSE_TX) 572 mv643xx_eth_free_completed_tx_descs(dev); 573 574 /* 575 * If no real interrupt occured, exit. 576 * This can happen when using gigE interrupt coalescing mechanism. 577 */ 578 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) 579 return IRQ_NONE; 580 581 return IRQ_HANDLED; 582} 583 584#ifdef MV643XX_COAL 585 586/* 587 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path 588 * 589 * DESCRIPTION: 590 * This routine sets the RX coalescing interrupt mechanism parameter. 591 * This parameter is a timeout counter, that counts in 64 t_clk 592 * chunks ; that when timeout event occurs a maskable interrupt 593 * occurs. 594 * The parameter is calculated using the tClk of the MV-643xx chip 595 * , and the required delay of the interrupt in usec. 596 * 597 * INPUT: 598 * unsigned int eth_port_num Ethernet port number 599 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units 600 * unsigned int delay Delay in usec 601 * 602 * OUTPUT: 603 * Interrupt coalescing mechanism value is set in MV-643xx chip. 604 * 605 * RETURN: 606 * The interrupt coalescing value set in the gigE port. 607 * 608 */ 609static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num, 610 unsigned int t_clk, unsigned int delay) 611{ 612 unsigned int coal = ((t_clk / 1000000) * delay) / 64; 613 614 /* Set RX Coalescing mechanism */ 615 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num), 616 ((coal & 0x3fff) << 8) | 617 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num)) 618 & 0xffc000ff)); 619 620 return coal; 621} 622#endif 623 624/* 625 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path 626 * 627 * DESCRIPTION: 628 * This routine sets the TX coalescing interrupt mechanism parameter. 629 * This parameter is a timeout counter, that counts in 64 t_clk 630 * chunks ; that when timeout event occurs a maskable interrupt 631 * occurs. 632 * The parameter is calculated using the t_cLK frequency of the 633 * MV-643xx chip and the required delay in the interrupt in uSec 634 * 635 * INPUT: 636 * unsigned int eth_port_num Ethernet port number 637 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units 638 * unsigned int delay Delay in uSeconds 639 * 640 * OUTPUT: 641 * Interrupt coalescing mechanism value is set in MV-643xx chip. 642 * 643 * RETURN: 644 * The interrupt coalescing value set in the gigE port. 645 * 646 */ 647static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num, 648 unsigned int t_clk, unsigned int delay) 649{ 650 unsigned int coal; 651 coal = ((t_clk / 1000000) * delay) / 64; 652 /* Set TX Coalescing mechanism */ 653 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), 654 coal << 4); 655 return coal; 656} 657 658/* 659 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. 660 * 661 * DESCRIPTION: 662 * This function prepares a Rx chained list of descriptors and packet 663 * buffers in a form of a ring. The routine must be called after port 664 * initialization routine and before port start routine. 665 * The Ethernet SDMA engine uses CPU bus addresses to access the various 666 * devices in the system (i.e. DRAM). This function uses the ethernet 667 * struct 'virtual to physical' routine (set by the user) to set the ring 668 * with physical addresses. 669 * 670 * INPUT: 671 * struct mv643xx_private *mp Ethernet Port Control srtuct. 672 * 673 * OUTPUT: 674 * The routine updates the Ethernet port control struct with information 675 * regarding the Rx descriptors and buffers. 676 * 677 * RETURN: 678 * None. 679 */ 680static void ether_init_rx_desc_ring(struct mv643xx_private *mp) 681{ 682 volatile struct eth_rx_desc *p_rx_desc; 683 int rx_desc_num = mp->rx_ring_size; 684 int i; 685 686 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 687 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; 688 for (i = 0; i < rx_desc_num; i++) { 689 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + 690 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); 691 } 692 693 /* Save Rx desc pointer to driver struct. */ 694 mp->rx_curr_desc_q = 0; 695 mp->rx_used_desc_q = 0; 696 697 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); 698} 699 700/* 701 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. 702 * 703 * DESCRIPTION: 704 * This function prepares a Tx chained list of descriptors and packet 705 * buffers in a form of a ring. The routine must be called after port 706 * initialization routine and before port start routine. 707 * The Ethernet SDMA engine uses CPU bus addresses to access the various 708 * devices in the system (i.e. DRAM). This function uses the ethernet 709 * struct 'virtual to physical' routine (set by the user) to set the ring 710 * with physical addresses. 711 * 712 * INPUT: 713 * struct mv643xx_private *mp Ethernet Port Control srtuct. 714 * 715 * OUTPUT: 716 * The routine updates the Ethernet port control struct with information 717 * regarding the Tx descriptors and buffers. 718 * 719 * RETURN: 720 * None. 721 */ 722static void ether_init_tx_desc_ring(struct mv643xx_private *mp) 723{ 724 int tx_desc_num = mp->tx_ring_size; 725 struct eth_tx_desc *p_tx_desc; 726 int i; 727 728 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 729 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; 730 for (i = 0; i < tx_desc_num; i++) { 731 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + 732 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); 733 } 734 735 mp->tx_curr_desc_q = 0; 736 mp->tx_used_desc_q = 0; 737 738 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); 739} 740 741static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 742{ 743 struct mv643xx_private *mp = netdev_priv(dev); 744 int err; 745 746 spin_lock_irq(&mp->lock); 747 err = mii_ethtool_sset(&mp->mii, cmd); 748 spin_unlock_irq(&mp->lock); 749 750 return err; 751} 752 753static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 754{ 755 struct mv643xx_private *mp = netdev_priv(dev); 756 int err; 757 758 spin_lock_irq(&mp->lock); 759 err = mii_ethtool_gset(&mp->mii, cmd); 760 spin_unlock_irq(&mp->lock); 761 762 /* The PHY may support 1000baseT_Half, but the mv643xx does not */ 763 cmd->supported &= ~SUPPORTED_1000baseT_Half; 764 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 765 766 return err; 767} 768 769/* 770 * mv643xx_eth_open 771 * 772 * This function is called when openning the network device. The function 773 * should initialize all the hardware, initialize cyclic Rx/Tx 774 * descriptors chain and buffers and allocate an IRQ to the network 775 * device. 776 * 777 * Input : a pointer to the network device structure 778 * 779 * Output : zero of success , nonzero if fails. 780 */ 781 782static int mv643xx_eth_open(struct net_device *dev) 783{ 784 struct mv643xx_private *mp = netdev_priv(dev); 785 unsigned int port_num = mp->port_num; 786 unsigned int size; 787 int err; 788 789 /* Clear any pending ethernet port interrupts */ 790 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); 791 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); 792 /* wait for previous write to complete */ 793 mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)); 794 795 err = request_irq(dev->irq, mv643xx_eth_int_handler, 796 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); 797 if (err) { 798 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n", 799 port_num); 800 return -EAGAIN; 801 } 802 803 eth_port_init(mp); 804 805 memset(&mp->timeout, 0, sizeof(struct timer_list)); 806 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; 807 mp->timeout.data = (unsigned long)dev; 808 809 /* Allocate RX and TX skb rings */ 810 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, 811 GFP_KERNEL); 812 if (!mp->rx_skb) { 813 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); 814 err = -ENOMEM; 815 goto out_free_irq; 816 } 817 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, 818 GFP_KERNEL); 819 if (!mp->tx_skb) { 820 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); 821 err = -ENOMEM; 822 goto out_free_rx_skb; 823 } 824 825 /* Allocate TX ring */ 826 mp->tx_desc_count = 0; 827 size = mp->tx_ring_size * sizeof(struct eth_tx_desc); 828 mp->tx_desc_area_size = size; 829 830 if (mp->tx_sram_size) { 831 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, 832 mp->tx_sram_size); 833 mp->tx_desc_dma = mp->tx_sram_addr; 834 } else 835 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, 836 &mp->tx_desc_dma, 837 GFP_KERNEL); 838 839 if (!mp->p_tx_desc_area) { 840 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", 841 dev->name, size); 842 err = -ENOMEM; 843 goto out_free_tx_skb; 844 } 845 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ 846 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); 847 848 ether_init_tx_desc_ring(mp); 849 850 /* Allocate RX ring */ 851 mp->rx_desc_count = 0; 852 size = mp->rx_ring_size * sizeof(struct eth_rx_desc); 853 mp->rx_desc_area_size = size; 854 855 if (mp->rx_sram_size) { 856 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, 857 mp->rx_sram_size); 858 mp->rx_desc_dma = mp->rx_sram_addr; 859 } else 860 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, 861 &mp->rx_desc_dma, 862 GFP_KERNEL); 863 864 if (!mp->p_rx_desc_area) { 865 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", 866 dev->name, size); 867 printk(KERN_ERR "%s: Freeing previously allocated TX queues...", 868 dev->name); 869 if (mp->rx_sram_size) 870 iounmap(mp->p_tx_desc_area); 871 else 872 dma_free_coherent(NULL, mp->tx_desc_area_size, 873 mp->p_tx_desc_area, mp->tx_desc_dma); 874 err = -ENOMEM; 875 goto out_free_tx_skb; 876 } 877 memset((void *)mp->p_rx_desc_area, 0, size); 878 879 ether_init_rx_desc_ring(mp); 880 881 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ 882 883 eth_port_start(dev); 884 885 /* Interrupt Coalescing */ 886 887#ifdef MV643XX_COAL 888 mp->rx_int_coal = 889 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL); 890#endif 891 892 mp->tx_int_coal = 893 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL); 894 895 /* Unmask phy and link status changes interrupts */ 896 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 897 ETH_INT_UNMASK_ALL_EXT); 898 899 /* Unmask RX buffer and TX end interrupt */ 900 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 901 902 return 0; 903 904out_free_tx_skb: 905 kfree(mp->tx_skb); 906out_free_rx_skb: 907 kfree(mp->rx_skb); 908out_free_irq: 909 free_irq(dev->irq, dev); 910 911 return err; 912} 913 914static void mv643xx_eth_free_tx_rings(struct net_device *dev) 915{ 916 struct mv643xx_private *mp = netdev_priv(dev); 917 918 /* Stop Tx Queues */ 919 mv643xx_eth_port_disable_tx(mp->port_num); 920 921 /* Free outstanding skb's on TX ring */ 922 mv643xx_eth_free_all_tx_descs(dev); 923 924 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); 925 926 /* Free TX ring */ 927 if (mp->tx_sram_size) 928 iounmap(mp->p_tx_desc_area); 929 else 930 dma_free_coherent(NULL, mp->tx_desc_area_size, 931 mp->p_tx_desc_area, mp->tx_desc_dma); 932} 933 934static void mv643xx_eth_free_rx_rings(struct net_device *dev) 935{ 936 struct mv643xx_private *mp = netdev_priv(dev); 937 unsigned int port_num = mp->port_num; 938 int curr; 939 940 /* Stop RX Queues */ 941 mv643xx_eth_port_disable_rx(port_num); 942 943 /* Free preallocated skb's on RX rings */ 944 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { 945 if (mp->rx_skb[curr]) { 946 dev_kfree_skb(mp->rx_skb[curr]); 947 mp->rx_desc_count--; 948 } 949 } 950 951 if (mp->rx_desc_count) 952 printk(KERN_ERR 953 "%s: Error in freeing Rx Ring. %d skb's still" 954 " stuck in RX Ring - ignoring them\n", dev->name, 955 mp->rx_desc_count); 956 /* Free RX ring */ 957 if (mp->rx_sram_size) 958 iounmap(mp->p_rx_desc_area); 959 else 960 dma_free_coherent(NULL, mp->rx_desc_area_size, 961 mp->p_rx_desc_area, mp->rx_desc_dma); 962} 963 964/* 965 * mv643xx_eth_stop 966 * 967 * This function is used when closing the network device. 968 * It updates the hardware, 969 * release all memory that holds buffers and descriptors and release the IRQ. 970 * Input : a pointer to the device structure 971 * Output : zero if success , nonzero if fails 972 */ 973 974static int mv643xx_eth_stop(struct net_device *dev) 975{ 976 struct mv643xx_private *mp = netdev_priv(dev); 977 unsigned int port_num = mp->port_num; 978 979 /* Mask all interrupts on ethernet port */ 980 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 981 /* wait for previous write to complete */ 982 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); 983 984#ifdef MV643XX_NAPI 985 netif_poll_disable(dev); 986#endif 987 netif_carrier_off(dev); 988 netif_stop_queue(dev); 989 990 eth_port_reset(mp->port_num); 991 992 mv643xx_eth_free_tx_rings(dev); 993 mv643xx_eth_free_rx_rings(dev); 994 995#ifdef MV643XX_NAPI 996 netif_poll_enable(dev); 997#endif 998 999 free_irq(dev->irq, dev); 1000 1001 return 0; 1002} 1003 1004#ifdef MV643XX_NAPI 1005/* 1006 * mv643xx_poll 1007 * 1008 * This function is used in case of NAPI 1009 */ 1010static int mv643xx_poll(struct net_device *dev, int *budget) 1011{ 1012 struct mv643xx_private *mp = netdev_priv(dev); 1013 int done = 1, orig_budget, work_done; 1014 unsigned int port_num = mp->port_num; 1015 1016#ifdef MV643XX_TX_FAST_REFILL 1017 if (++mp->tx_clean_threshold > 5) { 1018 mv643xx_eth_free_completed_tx_descs(dev); 1019 mp->tx_clean_threshold = 0; 1020 } 1021#endif 1022 1023 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) 1024 != (u32) mp->rx_used_desc_q) { 1025 orig_budget = *budget; 1026 if (orig_budget > dev->quota) 1027 orig_budget = dev->quota; 1028 work_done = mv643xx_eth_receive_queue(dev, orig_budget); 1029 *budget -= work_done; 1030 dev->quota -= work_done; 1031 if (work_done >= orig_budget) 1032 done = 0; 1033 } 1034 1035 if (done) { 1036 netif_rx_complete(dev); 1037 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); 1038 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); 1039 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 1040 ETH_INT_UNMASK_ALL); 1041 } 1042 1043 return done ? 0 : 1; 1044} 1045#endif 1046 1047/** 1048 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments 1049 * 1050 * Hardware can't handle unaligned fragments smaller than 9 bytes. 1051 * This helper function detects that case. 1052 */ 1053 1054static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 1055{ 1056 unsigned int frag; 1057 skb_frag_t *fragp; 1058 1059 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1060 fragp = &skb_shinfo(skb)->frags[frag]; 1061 if (fragp->size <= 8 && fragp->page_offset & 0x7) 1062 return 1; 1063 } 1064 return 0; 1065} 1066 1067/** 1068 * eth_alloc_tx_desc_index - return the index of the next available tx desc 1069 */ 1070static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) 1071{ 1072 int tx_desc_curr; 1073 1074 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); 1075 1076 tx_desc_curr = mp->tx_curr_desc_q; 1077 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; 1078 1079 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); 1080 1081 return tx_desc_curr; 1082} 1083 1084/** 1085 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. 1086 * 1087 * Ensure the data for each fragment to be transmitted is mapped properly, 1088 * then fill in descriptors in the tx hw queue. 1089 */ 1090static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, 1091 struct sk_buff *skb) 1092{ 1093 int frag; 1094 int tx_index; 1095 struct eth_tx_desc *desc; 1096 1097 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1098 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; 1099 1100 tx_index = eth_alloc_tx_desc_index(mp); 1101 desc = &mp->p_tx_desc_area[tx_index]; 1102 1103 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; 1104 /* Last Frag enables interrupt and frees the skb */ 1105 if (frag == (skb_shinfo(skb)->nr_frags - 1)) { 1106 desc->cmd_sts |= ETH_ZERO_PADDING | 1107 ETH_TX_LAST_DESC | 1108 ETH_TX_ENABLE_INTERRUPT; 1109 mp->tx_skb[tx_index] = skb; 1110 } else 1111 mp->tx_skb[tx_index] = NULL; 1112 1113 desc = &mp->p_tx_desc_area[tx_index]; 1114 desc->l4i_chk = 0; 1115 desc->byte_cnt = this_frag->size; 1116 desc->buf_ptr = dma_map_page(NULL, this_frag->page, 1117 this_frag->page_offset, 1118 this_frag->size, 1119 DMA_TO_DEVICE); 1120 } 1121} 1122 1123/** 1124 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw 1125 * 1126 * Ensure the data for an skb to be transmitted is mapped properly, 1127 * then fill in descriptors in the tx hw queue and start the hardware. 1128 */ 1129static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, 1130 struct sk_buff *skb) 1131{ 1132 int tx_index; 1133 struct eth_tx_desc *desc; 1134 u32 cmd_sts; 1135 int length; 1136 int nr_frags = skb_shinfo(skb)->nr_frags; 1137 1138 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; 1139 1140 tx_index = eth_alloc_tx_desc_index(mp); 1141 desc = &mp->p_tx_desc_area[tx_index]; 1142 1143 if (nr_frags) { 1144 eth_tx_fill_frag_descs(mp, skb); 1145 1146 length = skb_headlen(skb); 1147 mp->tx_skb[tx_index] = NULL; 1148 } else { 1149 cmd_sts |= ETH_ZERO_PADDING | 1150 ETH_TX_LAST_DESC | 1151 ETH_TX_ENABLE_INTERRUPT; 1152 length = skb->len; 1153 mp->tx_skb[tx_index] = skb; 1154 } 1155 1156 desc->byte_cnt = length; 1157 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1158 1159 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1160 BUG_ON(skb->protocol != ETH_P_IP); 1161 1162 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | 1163 ETH_GEN_IP_V_4_CHECKSUM | 1164 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; 1165 1166 switch (ip_hdr(skb)->protocol) { 1167 case IPPROTO_UDP: 1168 cmd_sts |= ETH_UDP_FRAME; 1169 desc->l4i_chk = udp_hdr(skb)->check; 1170 break; 1171 case IPPROTO_TCP: 1172 desc->l4i_chk = tcp_hdr(skb)->check; 1173 break; 1174 default: 1175 BUG(); 1176 } 1177 } else { 1178 /* Errata BTS #50, IHL must be 5 if no HW checksum */ 1179 cmd_sts |= 5 << ETH_TX_IHL_SHIFT; 1180 desc->l4i_chk = 0; 1181 } 1182 1183 /* ensure all other descriptors are written before first cmd_sts */ 1184 wmb(); 1185 desc->cmd_sts = cmd_sts; 1186 1187 /* ensure all descriptors are written before poking hardware */ 1188 wmb(); 1189 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED); 1190 1191 mp->tx_desc_count += nr_frags + 1; 1192} 1193 1194/** 1195 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission 1196 * 1197 */ 1198static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) 1199{ 1200 struct mv643xx_private *mp = netdev_priv(dev); 1201 struct net_device_stats *stats = &mp->stats; 1202 unsigned long flags; 1203 1204 BUG_ON(netif_queue_stopped(dev)); 1205 BUG_ON(skb == NULL); 1206 1207 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { 1208 printk(KERN_ERR "%s: transmit with queue full\n", dev->name); 1209 netif_stop_queue(dev); 1210 return 1; 1211 } 1212 1213 if (has_tiny_unaligned_frags(skb)) { 1214 if (__skb_linearize(skb)) { 1215 stats->tx_dropped++; 1216 printk(KERN_DEBUG "%s: failed to linearize tiny " 1217 "unaligned fragment\n", dev->name); 1218 return 1; 1219 } 1220 } 1221 1222 spin_lock_irqsave(&mp->lock, flags); 1223 1224 eth_tx_submit_descs_for_skb(mp, skb); 1225 stats->tx_bytes = skb->len; 1226 stats->tx_packets++; 1227 dev->trans_start = jiffies; 1228 1229 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) 1230 netif_stop_queue(dev); 1231 1232 spin_unlock_irqrestore(&mp->lock, flags); 1233 1234 return 0; /* success */ 1235} 1236 1237/* 1238 * mv643xx_eth_get_stats 1239 * 1240 * Returns a pointer to the interface statistics. 1241 * 1242 * Input : dev - a pointer to the required interface 1243 * 1244 * Output : a pointer to the interface's statistics 1245 */ 1246 1247static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) 1248{ 1249 struct mv643xx_private *mp = netdev_priv(dev); 1250 1251 return &mp->stats; 1252} 1253 1254#ifdef CONFIG_NET_POLL_CONTROLLER 1255static void mv643xx_netpoll(struct net_device *netdev) 1256{ 1257 struct mv643xx_private *mp = netdev_priv(netdev); 1258 int port_num = mp->port_num; 1259 1260 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 1261 /* wait for previous write to complete */ 1262 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); 1263 1264 mv643xx_eth_int_handler(netdev->irq, netdev); 1265 1266 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 1267} 1268#endif 1269 1270static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, 1271 int speed, int duplex, 1272 struct ethtool_cmd *cmd) 1273{ 1274 struct mv643xx_private *mp = netdev_priv(dev); 1275 1276 memset(cmd, 0, sizeof(*cmd)); 1277 1278 cmd->port = PORT_MII; 1279 cmd->transceiver = XCVR_INTERNAL; 1280 cmd->phy_address = phy_address; 1281 1282 if (speed == 0) { 1283 cmd->autoneg = AUTONEG_ENABLE; 1284 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ 1285 cmd->speed = SPEED_100; 1286 cmd->advertising = ADVERTISED_10baseT_Half | 1287 ADVERTISED_10baseT_Full | 1288 ADVERTISED_100baseT_Half | 1289 ADVERTISED_100baseT_Full; 1290 if (mp->mii.supports_gmii) 1291 cmd->advertising |= ADVERTISED_1000baseT_Full; 1292 } else { 1293 cmd->autoneg = AUTONEG_DISABLE; 1294 cmd->speed = speed; 1295 cmd->duplex = duplex; 1296 } 1297} 1298 1299/*/ 1300 * mv643xx_eth_probe 1301 * 1302 * First function called after registering the network device. 1303 * It's purpose is to initialize the device as an ethernet device, 1304 * fill the ethernet device structure with pointers * to functions, 1305 * and set the MAC address of the interface 1306 * 1307 * Input : struct device * 1308 * Output : -ENOMEM if failed , 0 if success 1309 */ 1310static int mv643xx_eth_probe(struct platform_device *pdev) 1311{ 1312 struct mv643xx_eth_platform_data *pd; 1313 int port_num; 1314 struct mv643xx_private *mp; 1315 struct net_device *dev; 1316 u8 *p; 1317 struct resource *res; 1318 int err; 1319 struct ethtool_cmd cmd; 1320 int duplex = DUPLEX_HALF; 1321 int speed = 0; /* default to auto-negotiation */ 1322 1323 pd = pdev->dev.platform_data; 1324 if (pd == NULL) { 1325 printk(KERN_ERR "No mv643xx_eth_platform_data\n"); 1326 return -ENODEV; 1327 } 1328 1329 dev = alloc_etherdev(sizeof(struct mv643xx_private)); 1330 if (!dev) 1331 return -ENOMEM; 1332 1333 platform_set_drvdata(pdev, dev); 1334 1335 mp = netdev_priv(dev); 1336 1337 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1338 BUG_ON(!res); 1339 dev->irq = res->start; 1340 1341 dev->open = mv643xx_eth_open; 1342 dev->stop = mv643xx_eth_stop; 1343 dev->hard_start_xmit = mv643xx_eth_start_xmit; 1344 dev->get_stats = mv643xx_eth_get_stats; 1345 dev->set_mac_address = mv643xx_eth_set_mac_address; 1346 dev->set_multicast_list = mv643xx_eth_set_rx_mode; 1347 1348 /* No need to Tx Timeout */ 1349 dev->tx_timeout = mv643xx_eth_tx_timeout; 1350#ifdef MV643XX_NAPI 1351 dev->poll = mv643xx_poll; 1352 dev->weight = 64; 1353#endif 1354 1355#ifdef CONFIG_NET_POLL_CONTROLLER 1356 dev->poll_controller = mv643xx_netpoll; 1357#endif 1358 1359 dev->watchdog_timeo = 2 * HZ; 1360 dev->tx_queue_len = mp->tx_ring_size; 1361 dev->base_addr = 0; 1362 dev->change_mtu = mv643xx_eth_change_mtu; 1363 dev->do_ioctl = mv643xx_eth_do_ioctl; 1364 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); 1365 1366#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 1367#ifdef MAX_SKB_FRAGS 1368 /* 1369 * Zero copy can only work if we use Discovery II memory. Else, we will 1370 * have to map the buffers to ISA memory which is only 16 MB 1371 */ 1372 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; 1373#endif 1374#endif 1375 1376 /* Configure the timeout task */ 1377 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); 1378 1379 spin_lock_init(&mp->lock); 1380 1381 port_num = mp->port_num = pd->port_number; 1382 1383 /* set default config values */ 1384 eth_port_uc_addr_get(port_num, dev->dev_addr); 1385 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE; 1386 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; 1387 1388 if (is_valid_ether_addr(pd->mac_addr)) 1389 memcpy(dev->dev_addr, pd->mac_addr, 6); 1390 1391 if (pd->phy_addr || pd->force_phy_addr) 1392 ethernet_phy_set(port_num, pd->phy_addr); 1393 1394 if (pd->rx_queue_size) 1395 mp->rx_ring_size = pd->rx_queue_size; 1396 1397 if (pd->tx_queue_size) 1398 mp->tx_ring_size = pd->tx_queue_size; 1399 1400 if (pd->tx_sram_size) { 1401 mp->tx_sram_size = pd->tx_sram_size; 1402 mp->tx_sram_addr = pd->tx_sram_addr; 1403 } 1404 1405 if (pd->rx_sram_size) { 1406 mp->rx_sram_size = pd->rx_sram_size; 1407 mp->rx_sram_addr = pd->rx_sram_addr; 1408 } 1409 1410 duplex = pd->duplex; 1411 speed = pd->speed; 1412 1413 /* Hook up MII support for ethtool */ 1414 mp->mii.dev = dev; 1415 mp->mii.mdio_read = mv643xx_mdio_read; 1416 mp->mii.mdio_write = mv643xx_mdio_write; 1417 mp->mii.phy_id = ethernet_phy_get(port_num); 1418 mp->mii.phy_id_mask = 0x3f; 1419 mp->mii.reg_num_mask = 0x1f; 1420 1421 err = ethernet_phy_detect(port_num); 1422 if (err) { 1423 pr_debug("MV643xx ethernet port %d: " 1424 "No PHY detected at addr %d\n", 1425 port_num, ethernet_phy_get(port_num)); 1426 goto out; 1427 } 1428 1429 ethernet_phy_reset(port_num); 1430 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); 1431 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); 1432 mv643xx_eth_update_pscr(dev, &cmd); 1433 mv643xx_set_settings(dev, &cmd); 1434 1435 SET_MODULE_OWNER(dev); 1436 SET_NETDEV_DEV(dev, &pdev->dev); 1437 err = register_netdev(dev); 1438 if (err) 1439 goto out; 1440 1441 p = dev->dev_addr; 1442 printk(KERN_NOTICE 1443 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 1444 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]); 1445 1446 if (dev->features & NETIF_F_SG) 1447 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); 1448 1449 if (dev->features & NETIF_F_IP_CSUM) 1450 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", 1451 dev->name); 1452 1453#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 1454 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); 1455#endif 1456 1457#ifdef MV643XX_COAL 1458 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", 1459 dev->name); 1460#endif 1461 1462#ifdef MV643XX_NAPI 1463 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); 1464#endif 1465 1466 if (mp->tx_sram_size > 0) 1467 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); 1468 1469 return 0; 1470 1471out: 1472 free_netdev(dev); 1473 1474 return err; 1475} 1476 1477static int mv643xx_eth_remove(struct platform_device *pdev) 1478{ 1479 struct net_device *dev = platform_get_drvdata(pdev); 1480 1481 unregister_netdev(dev); 1482 flush_scheduled_work(); 1483 1484 free_netdev(dev); 1485 platform_set_drvdata(pdev, NULL); 1486 return 0; 1487} 1488 1489static int mv643xx_eth_shared_probe(struct platform_device *pdev) 1490{ 1491 struct resource *res; 1492 1493 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); 1494 1495 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1496 if (res == NULL) 1497 return -ENODEV; 1498 1499 mv643xx_eth_shared_base = ioremap(res->start, 1500 MV643XX_ETH_SHARED_REGS_SIZE); 1501 if (mv643xx_eth_shared_base == NULL) 1502 return -ENOMEM; 1503 1504 return 0; 1505 1506} 1507 1508static int mv643xx_eth_shared_remove(struct platform_device *pdev) 1509{ 1510 iounmap(mv643xx_eth_shared_base); 1511 mv643xx_eth_shared_base = NULL; 1512 1513 return 0; 1514} 1515 1516static void mv643xx_eth_shutdown(struct platform_device *pdev) 1517{ 1518 struct net_device *dev = platform_get_drvdata(pdev); 1519 struct mv643xx_private *mp = netdev_priv(dev); 1520 unsigned int port_num = mp->port_num; 1521 1522 /* Mask all interrupts on ethernet port */ 1523 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0); 1524 mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); 1525 1526 eth_port_reset(port_num); 1527} 1528 1529static struct platform_driver mv643xx_eth_driver = { 1530 .probe = mv643xx_eth_probe, 1531 .remove = mv643xx_eth_remove, 1532 .shutdown = mv643xx_eth_shutdown, 1533 .driver = { 1534 .name = MV643XX_ETH_NAME, 1535 }, 1536}; 1537 1538static struct platform_driver mv643xx_eth_shared_driver = { 1539 .probe = mv643xx_eth_shared_probe, 1540 .remove = mv643xx_eth_shared_remove, 1541 .driver = { 1542 .name = MV643XX_ETH_SHARED_NAME, 1543 }, 1544}; 1545 1546/* 1547 * mv643xx_init_module 1548 * 1549 * Registers the network drivers into the Linux kernel 1550 * 1551 * Input : N/A 1552 * 1553 * Output : N/A 1554 */ 1555static int __init mv643xx_init_module(void) 1556{ 1557 int rc; 1558 1559 rc = platform_driver_register(&mv643xx_eth_shared_driver); 1560 if (!rc) { 1561 rc = platform_driver_register(&mv643xx_eth_driver); 1562 if (rc) 1563 platform_driver_unregister(&mv643xx_eth_shared_driver); 1564 } 1565 return rc; 1566} 1567 1568/* 1569 * mv643xx_cleanup_module 1570 * 1571 * Registers the network drivers into the Linux kernel 1572 * 1573 * Input : N/A 1574 * 1575 * Output : N/A 1576 */ 1577static void __exit mv643xx_cleanup_module(void) 1578{ 1579 platform_driver_unregister(&mv643xx_eth_driver); 1580 platform_driver_unregister(&mv643xx_eth_shared_driver); 1581} 1582 1583module_init(mv643xx_init_module); 1584module_exit(mv643xx_cleanup_module); 1585 1586MODULE_LICENSE("GPL"); 1587MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" 1588 " and Dale Farnsworth"); 1589MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 1590 1591/* 1592 * The second part is the low level driver of the gigE ethernet ports. 1593 */ 1594 1595/* 1596 * Marvell's Gigabit Ethernet controller low level driver 1597 * 1598 * DESCRIPTION: 1599 * This file introduce low level API to Marvell's Gigabit Ethernet 1600 * controller. This Gigabit Ethernet Controller driver API controls 1601 * 1) Operations (i.e. port init, start, reset etc'). 1602 * 2) Data flow (i.e. port send, receive etc'). 1603 * Each Gigabit Ethernet port is controlled via 1604 * struct mv643xx_private. 1605 * This struct includes user configuration information as well as 1606 * driver internal data needed for its operations. 1607 * 1608 * Supported Features: 1609 * - This low level driver is OS independent. Allocating memory for 1610 * the descriptor rings and buffers are not within the scope of 1611 * this driver. 1612 * - The user is free from Rx/Tx queue managing. 1613 * - This low level driver introduce functionality API that enable 1614 * the to operate Marvell's Gigabit Ethernet Controller in a 1615 * convenient way. 1616 * - Simple Gigabit Ethernet port operation API. 1617 * - Simple Gigabit Ethernet port data flow API. 1618 * - Data flow and operation API support per queue functionality. 1619 * - Support cached descriptors for better performance. 1620 * - Enable access to all four DRAM banks and internal SRAM memory 1621 * spaces. 1622 * - PHY access and control API. 1623 * - Port control register configuration API. 1624 * - Full control over Unicast and Multicast MAC configurations. 1625 * 1626 * Operation flow: 1627 * 1628 * Initialization phase 1629 * This phase complete the initialization of the the 1630 * mv643xx_private struct. 1631 * User information regarding port configuration has to be set 1632 * prior to calling the port initialization routine. 1633 * 1634 * In this phase any port Tx/Rx activity is halted, MIB counters 1635 * are cleared, PHY address is set according to user parameter and 1636 * access to DRAM and internal SRAM memory spaces. 1637 * 1638 * Driver ring initialization 1639 * Allocating memory for the descriptor rings and buffers is not 1640 * within the scope of this driver. Thus, the user is required to 1641 * allocate memory for the descriptors ring and buffers. Those 1642 * memory parameters are used by the Rx and Tx ring initialization 1643 * routines in order to curve the descriptor linked list in a form 1644 * of a ring. 1645 * Note: Pay special attention to alignment issues when using 1646 * cached descriptors/buffers. In this phase the driver store 1647 * information in the mv643xx_private struct regarding each queue 1648 * ring. 1649 * 1650 * Driver start 1651 * This phase prepares the Ethernet port for Rx and Tx activity. 1652 * It uses the information stored in the mv643xx_private struct to 1653 * initialize the various port registers. 1654 * 1655 * Data flow: 1656 * All packet references to/from the driver are done using 1657 * struct pkt_info. 1658 * This struct is a unified struct used with Rx and Tx operations. 1659 * This way the user is not required to be familiar with neither 1660 * Tx nor Rx descriptors structures. 1661 * The driver's descriptors rings are management by indexes. 1662 * Those indexes controls the ring resources and used to indicate 1663 * a SW resource error: 1664 * 'current' 1665 * This index points to the current available resource for use. For 1666 * example in Rx process this index will point to the descriptor 1667 * that will be passed to the user upon calling the receive 1668 * routine. In Tx process, this index will point to the descriptor 1669 * that will be assigned with the user packet info and transmitted. 1670 * 'used' 1671 * This index points to the descriptor that need to restore its 1672 * resources. For example in Rx process, using the Rx buffer return 1673 * API will attach the buffer returned in packet info to the 1674 * descriptor pointed by 'used'. In Tx process, using the Tx 1675 * descriptor return will merely return the user packet info with 1676 * the command status of the transmitted buffer pointed by the 1677 * 'used' index. Nevertheless, it is essential to use this routine 1678 * to update the 'used' index. 1679 * 'first' 1680 * This index supports Tx Scatter-Gather. It points to the first 1681 * descriptor of a packet assembled of multiple buffers. For 1682 * example when in middle of Such packet we have a Tx resource 1683 * error the 'curr' index get the value of 'first' to indicate 1684 * that the ring returned to its state before trying to transmit 1685 * this packet. 1686 * 1687 * Receive operation: 1688 * The eth_port_receive API set the packet information struct, 1689 * passed by the caller, with received information from the 1690 * 'current' SDMA descriptor. 1691 * It is the user responsibility to return this resource back 1692 * to the Rx descriptor ring to enable the reuse of this source. 1693 * Return Rx resource is done using the eth_rx_return_buff API. 1694 * 1695 * Prior to calling the initialization routine eth_port_init() the user 1696 * must set the following fields under mv643xx_private struct: 1697 * port_num User Ethernet port number. 1698 * port_config User port configuration value. 1699 * port_config_extend User port config extend value. 1700 * port_sdma_config User port SDMA config value. 1701 * port_serial_control User port serial control value. 1702 * 1703 * This driver data flow is done using the struct pkt_info which 1704 * is a unified struct for Rx and Tx operations: 1705 * 1706 * byte_cnt Tx/Rx descriptor buffer byte count. 1707 * l4i_chk CPU provided TCP Checksum. For Tx operation 1708 * only. 1709 * cmd_sts Tx/Rx descriptor command status. 1710 * buf_ptr Tx/Rx descriptor buffer pointer. 1711 * return_info Tx/Rx user resource return information. 1712 */ 1713 1714/* PHY routines */ 1715static int ethernet_phy_get(unsigned int eth_port_num); 1716static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); 1717 1718/* Ethernet Port routines */ 1719static void eth_port_set_filter_table_entry(int table, unsigned char entry); 1720 1721/* 1722 * eth_port_init - Initialize the Ethernet port driver 1723 * 1724 * DESCRIPTION: 1725 * This function prepares the ethernet port to start its activity: 1726 * 1) Completes the ethernet port driver struct initialization toward port 1727 * start routine. 1728 * 2) Resets the device to a quiescent state in case of warm reboot. 1729 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. 1730 * 4) Clean MAC tables. The reset status of those tables is unknown. 1731 * 5) Set PHY address. 1732 * Note: Call this routine prior to eth_port_start routine and after 1733 * setting user values in the user fields of Ethernet port control 1734 * struct. 1735 * 1736 * INPUT: 1737 * struct mv643xx_private *mp Ethernet port control struct 1738 * 1739 * OUTPUT: 1740 * See description. 1741 * 1742 * RETURN: 1743 * None. 1744 */ 1745static void eth_port_init(struct mv643xx_private *mp) 1746{ 1747 mp->rx_resource_err = 0; 1748 1749 eth_port_reset(mp->port_num); 1750 1751 eth_port_init_mac_tables(mp->port_num); 1752} 1753 1754/* 1755 * eth_port_start - Start the Ethernet port activity. 1756 * 1757 * DESCRIPTION: 1758 * This routine prepares the Ethernet port for Rx and Tx activity: 1759 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that 1760 * has been initialized a descriptor's ring (using 1761 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) 1762 * 2. Initialize and enable the Ethernet configuration port by writing to 1763 * the port's configuration and command registers. 1764 * 3. Initialize and enable the SDMA by writing to the SDMA's 1765 * configuration and command registers. After completing these steps, 1766 * the ethernet port SDMA can starts to perform Rx and Tx activities. 1767 * 1768 * Note: Each Rx and Tx queue descriptor's list must be initialized prior 1769 * to calling this function (use ether_init_tx_desc_ring for Tx queues 1770 * and ether_init_rx_desc_ring for Rx queues). 1771 * 1772 * INPUT: 1773 * dev - a pointer to the required interface 1774 * 1775 * OUTPUT: 1776 * Ethernet port is ready to receive and transmit. 1777 * 1778 * RETURN: 1779 * None. 1780 */ 1781static void eth_port_start(struct net_device *dev) 1782{ 1783 struct mv643xx_private *mp = netdev_priv(dev); 1784 unsigned int port_num = mp->port_num; 1785 int tx_curr_desc, rx_curr_desc; 1786 u32 pscr; 1787 struct ethtool_cmd ethtool_cmd; 1788 1789 /* Assignment of Tx CTRP of given queue */ 1790 tx_curr_desc = mp->tx_curr_desc_q; 1791 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num), 1792 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); 1793 1794 /* Assignment of Rx CRDP of given queue */ 1795 rx_curr_desc = mp->rx_curr_desc_q; 1796 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num), 1797 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); 1798 1799 /* Add the assigned Ethernet address to the port's address table */ 1800 eth_port_uc_addr_set(port_num, dev->dev_addr); 1801 1802 /* Assign port configuration and command. */ 1803 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), 1804 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE); 1805 1806 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num), 1807 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE); 1808 1809 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); 1810 1811 pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS); 1812 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); 1813 1814 pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1815 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII | 1816 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX | 1817 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | 1818 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED; 1819 1820 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); 1821 1822 pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE; 1823 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); 1824 1825 /* Assign port SDMA configuration */ 1826 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num), 1827 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE); 1828 1829 /* Enable port Rx. */ 1830 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED); 1831 1832 /* Disable port bandwidth limits by clearing MTU register */ 1833 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0); 1834 1835 /* save phy settings across reset */ 1836 mv643xx_get_settings(dev, ðtool_cmd); 1837 ethernet_phy_reset(mp->port_num); 1838 mv643xx_set_settings(dev, ðtool_cmd); 1839} 1840 1841/* 1842 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers 1843 */ 1844static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr) 1845{ 1846 unsigned int mac_h; 1847 unsigned int mac_l; 1848 int table; 1849 1850 mac_l = (p_addr[4] << 8) | (p_addr[5]); 1851 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | 1852 (p_addr[3] << 0); 1853 1854 mv_write(MV643XX_ETH_MAC_ADDR_LOW(port_num), mac_l); 1855 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(port_num), mac_h); 1856 1857 /* Accept frames with this address */ 1858 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port_num); 1859 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f); 1860} 1861 1862/* 1863 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers 1864 */ 1865static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr) 1866{ 1867 unsigned int mac_h; 1868 unsigned int mac_l; 1869 1870 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(port_num)); 1871 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(port_num)); 1872 1873 p_addr[0] = (mac_h >> 24) & 0xff; 1874 p_addr[1] = (mac_h >> 16) & 0xff; 1875 p_addr[2] = (mac_h >> 8) & 0xff; 1876 p_addr[3] = mac_h & 0xff; 1877 p_addr[4] = (mac_l >> 8) & 0xff; 1878 p_addr[5] = mac_l & 0xff; 1879} 1880 1881/* 1882 * The entries in each table are indexed by a hash of a packet's MAC 1883 * address. One bit in each entry determines whether the packet is 1884 * accepted. There are 4 entries (each 8 bits wide) in each register 1885 * of the table. The bits in each entry are defined as follows: 1886 * 0 Accept=1, Drop=0 1887 * 3-1 Queue (ETH_Q0=0) 1888 * 7-4 Reserved = 0; 1889 */ 1890static void eth_port_set_filter_table_entry(int table, unsigned char entry) 1891{ 1892 unsigned int table_reg; 1893 unsigned int tbl_offset; 1894 unsigned int reg_offset; 1895 1896 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ 1897 reg_offset = entry % 4; /* Entry offset within the register */ 1898 1899 /* Set "accepts frame bit" at specified table entry */ 1900 table_reg = mv_read(table + tbl_offset); 1901 table_reg |= 0x01 << (8 * reg_offset); 1902 mv_write(table + tbl_offset, table_reg); 1903} 1904 1905/* 1906 * eth_port_mc_addr - Multicast address settings. 1907 * 1908 * The MV device supports multicast using two tables: 1909 * 1) Special Multicast Table for MAC addresses of the form 1910 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). 1911 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1912 * Table entries in the DA-Filter table. 1913 * 2) Other Multicast Table for multicast of another type. A CRC-8bit 1914 * is used as an index to the Other Multicast Table entries in the 1915 * DA-Filter table. This function calculates the CRC-8bit value. 1916 * In either case, eth_port_set_filter_table_entry() is then called 1917 * to set to set the actual table entry. 1918 */ 1919static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr) 1920{ 1921 unsigned int mac_h; 1922 unsigned int mac_l; 1923 unsigned char crc_result = 0; 1924 int table; 1925 int mac_array[48]; 1926 int crc[8]; 1927 int i; 1928 1929 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && 1930 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { 1931 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE 1932 (eth_port_num); 1933 eth_port_set_filter_table_entry(table, p_addr[5]); 1934 return; 1935 } 1936 1937 /* Calculate CRC-8 out of the given address */ 1938 mac_h = (p_addr[0] << 8) | (p_addr[1]); 1939 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | 1940 (p_addr[4] << 8) | (p_addr[5] << 0); 1941 1942 for (i = 0; i < 32; i++) 1943 mac_array[i] = (mac_l >> i) & 0x1; 1944 for (i = 32; i < 48; i++) 1945 mac_array[i] = (mac_h >> (i - 32)) & 0x1; 1946 1947 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ 1948 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ 1949 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ 1950 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ 1951 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; 1952 1953 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ 1954 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ 1955 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ 1956 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ 1957 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ 1958 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ 1959 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; 1960 1961 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ 1962 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ 1963 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ 1964 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ 1965 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ 1966 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; 1967 1968 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ 1969 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ 1970 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ 1971 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ 1972 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ 1973 mac_array[3] ^ mac_array[2] ^ mac_array[1]; 1974 1975 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ 1976 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ 1977 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ 1978 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ 1979 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ 1980 mac_array[3] ^ mac_array[2]; 1981 1982 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ 1983 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ 1984 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ 1985 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ 1986 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ 1987 mac_array[4] ^ mac_array[3]; 1988 1989 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ 1990 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ 1991 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ 1992 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ 1993 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ 1994 mac_array[4]; 1995 1996 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ 1997 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ 1998 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ 1999 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ 2000 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; 2001 2002 for (i = 0; i < 8; i++) 2003 crc_result = crc_result | (crc[i] << i); 2004 2005 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num); 2006 eth_port_set_filter_table_entry(table, crc_result); 2007} 2008 2009/* 2010 * Set the entire multicast list based on dev->mc_list. 2011 */ 2012static void eth_port_set_multicast_list(struct net_device *dev) 2013{ 2014 2015 struct dev_mc_list *mc_list; 2016 int i; 2017 int table_index; 2018 struct mv643xx_private *mp = netdev_priv(dev); 2019 unsigned int eth_port_num = mp->port_num; 2020 2021 /* If the device is in promiscuous mode or in all multicast mode, 2022 * we will fully populate both multicast tables with accept. 2023 * This is guaranteed to yield a match on all multicast addresses... 2024 */ 2025 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { 2026 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 2027 /* Set all entries in DA filter special multicast 2028 * table (Ex_dFSMT) 2029 * Set for ETH_Q0 for now 2030 * Bits 2031 * 0 Accept=1, Drop=0 2032 * 3-1 Queue ETH_Q0=0 2033 * 7-4 Reserved = 0; 2034 */ 2035 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); 2036 2037 /* Set all entries in DA filter other multicast 2038 * table (Ex_dFOMT) 2039 * Set for ETH_Q0 for now 2040 * Bits 2041 * 0 Accept=1, Drop=0 2042 * 3-1 Queue ETH_Q0=0 2043 * 7-4 Reserved = 0; 2044 */ 2045 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); 2046 } 2047 return; 2048 } 2049 2050 /* We will clear out multicast tables every time we get the list. 2051 * Then add the entire new list... 2052 */ 2053 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 2054 /* Clear DA filter special multicast table (Ex_dFSMT) */ 2055 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE 2056 (eth_port_num) + table_index, 0); 2057 2058 /* Clear DA filter other multicast table (Ex_dFOMT) */ 2059 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE 2060 (eth_port_num) + table_index, 0); 2061 } 2062 2063 /* Get pointer to net_device multicast list and add each one... */ 2064 for (i = 0, mc_list = dev->mc_list; 2065 (i < 256) && (mc_list != NULL) && (i < dev->mc_count); 2066 i++, mc_list = mc_list->next) 2067 if (mc_list->dmi_addrlen == 6) 2068 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr); 2069} 2070 2071/* 2072 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables 2073 * 2074 * DESCRIPTION: 2075 * Go through all the DA filter tables (Unicast, Special Multicast & 2076 * Other Multicast) and set each entry to 0. 2077 * 2078 * INPUT: 2079 * unsigned int eth_port_num Ethernet Port number. 2080 * 2081 * OUTPUT: 2082 * Multicast and Unicast packets are rejected. 2083 * 2084 * RETURN: 2085 * None. 2086 */ 2087static void eth_port_init_mac_tables(unsigned int eth_port_num) 2088{ 2089 int table_index; 2090 2091 /* Clear DA filter unicast table (Ex_dFUT) */ 2092 for (table_index = 0; table_index <= 0xC; table_index += 4) 2093 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE 2094 (eth_port_num) + table_index, 0); 2095 2096 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 2097 /* Clear DA filter special multicast table (Ex_dFSMT) */ 2098 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE 2099 (eth_port_num) + table_index, 0); 2100 /* Clear DA filter other multicast table (Ex_dFOMT) */ 2101 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE 2102 (eth_port_num) + table_index, 0); 2103 } 2104} 2105 2106/* 2107 * eth_clear_mib_counters - Clear all MIB counters 2108 * 2109 * DESCRIPTION: 2110 * This function clears all MIB counters of a specific ethernet port. 2111 * A read from the MIB counter will reset the counter. 2112 * 2113 * INPUT: 2114 * unsigned int eth_port_num Ethernet Port number. 2115 * 2116 * OUTPUT: 2117 * After reading all MIB counters, the counters resets. 2118 * 2119 * RETURN: 2120 * MIB counter value. 2121 * 2122 */ 2123static void eth_clear_mib_counters(unsigned int eth_port_num) 2124{ 2125 int i; 2126 2127 /* Perform dummy reads from MIB counters */ 2128 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; 2129 i += 4) 2130 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i); 2131} 2132 2133static inline u32 read_mib(struct mv643xx_private *mp, int offset) 2134{ 2135 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset); 2136} 2137 2138static void eth_update_mib_counters(struct mv643xx_private *mp) 2139{ 2140 struct mv643xx_mib_counters *p = &mp->mib_counters; 2141 int offset; 2142 2143 p->good_octets_received += 2144 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); 2145 p->good_octets_received += 2146 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; 2147 2148 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; 2149 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; 2150 offset += 4) 2151 *(u32 *)((char *)p + offset) += read_mib(mp, offset); 2152 2153 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); 2154 p->good_octets_sent += 2155 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; 2156 2157 for (offset = ETH_MIB_GOOD_FRAMES_SENT; 2158 offset <= ETH_MIB_LATE_COLLISION; 2159 offset += 4) 2160 *(u32 *)((char *)p + offset) += read_mib(mp, offset); 2161} 2162 2163/* 2164 * ethernet_phy_detect - Detect whether a phy is present 2165 * 2166 * DESCRIPTION: 2167 * This function tests whether there is a PHY present on 2168 * the specified port. 2169 * 2170 * INPUT: 2171 * unsigned int eth_port_num Ethernet Port number. 2172 * 2173 * OUTPUT: 2174 * None 2175 * 2176 * RETURN: 2177 * 0 on success 2178 * -ENODEV on failure 2179 * 2180 */ 2181static int ethernet_phy_detect(unsigned int port_num) 2182{ 2183 unsigned int phy_reg_data0; 2184 int auto_neg; 2185 2186 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); 2187 auto_neg = phy_reg_data0 & 0x1000; 2188 phy_reg_data0 ^= 0x1000; /* invert auto_neg */ 2189 eth_port_write_smi_reg(port_num, 0, phy_reg_data0); 2190 2191 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); 2192 if ((phy_reg_data0 & 0x1000) == auto_neg) 2193 return -ENODEV; /* change didn't take */ 2194 2195 phy_reg_data0 ^= 0x1000; 2196 eth_port_write_smi_reg(port_num, 0, phy_reg_data0); 2197 return 0; 2198} 2199 2200/* 2201 * ethernet_phy_get - Get the ethernet port PHY address. 2202 * 2203 * DESCRIPTION: 2204 * This routine returns the given ethernet port PHY address. 2205 * 2206 * INPUT: 2207 * unsigned int eth_port_num Ethernet Port number. 2208 * 2209 * OUTPUT: 2210 * None. 2211 * 2212 * RETURN: 2213 * PHY address. 2214 * 2215 */ 2216static int ethernet_phy_get(unsigned int eth_port_num) 2217{ 2218 unsigned int reg_data; 2219 2220 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); 2221 2222 return ((reg_data >> (5 * eth_port_num)) & 0x1f); 2223} 2224 2225/* 2226 * ethernet_phy_set - Set the ethernet port PHY address. 2227 * 2228 * DESCRIPTION: 2229 * This routine sets the given ethernet port PHY address. 2230 * 2231 * INPUT: 2232 * unsigned int eth_port_num Ethernet Port number. 2233 * int phy_addr PHY address. 2234 * 2235 * OUTPUT: 2236 * None. 2237 * 2238 * RETURN: 2239 * None. 2240 * 2241 */ 2242static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr) 2243{ 2244 u32 reg_data; 2245 int addr_shift = 5 * eth_port_num; 2246 2247 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); 2248 reg_data &= ~(0x1f << addr_shift); 2249 reg_data |= (phy_addr & 0x1f) << addr_shift; 2250 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data); 2251} 2252 2253/* 2254 * ethernet_phy_reset - Reset Ethernet port PHY. 2255 * 2256 * DESCRIPTION: 2257 * This routine utilizes the SMI interface to reset the ethernet port PHY. 2258 * 2259 * INPUT: 2260 * unsigned int eth_port_num Ethernet Port number. 2261 * 2262 * OUTPUT: 2263 * The PHY is reset. 2264 * 2265 * RETURN: 2266 * None. 2267 * 2268 */ 2269static void ethernet_phy_reset(unsigned int eth_port_num) 2270{ 2271 unsigned int phy_reg_data; 2272 2273 /* Reset the PHY */ 2274 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); 2275 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ 2276 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data); 2277 2278 /* wait for PHY to come out of reset */ 2279 do { 2280 udelay(1); 2281 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); 2282 } while (phy_reg_data & 0x8000); 2283} 2284 2285static void mv643xx_eth_port_enable_tx(unsigned int port_num, 2286 unsigned int queues) 2287{ 2288 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues); 2289} 2290 2291static void mv643xx_eth_port_enable_rx(unsigned int port_num, 2292 unsigned int queues) 2293{ 2294 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues); 2295} 2296 2297static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num) 2298{ 2299 u32 queues; 2300 2301 /* Stop Tx port activity. Check port Tx activity. */ 2302 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) 2303 & 0xFF; 2304 if (queues) { 2305 /* Issue stop command for active queues only */ 2306 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 2307 (queues << 8)); 2308 2309 /* Wait for all Tx activity to terminate. */ 2310 /* Check port cause register that all Tx queues are stopped */ 2311 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) 2312 & 0xFF) 2313 udelay(PHY_WAIT_MICRO_SECONDS); 2314 2315 /* Wait for Tx FIFO to empty */ 2316 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) & 2317 ETH_PORT_TX_FIFO_EMPTY) 2318 udelay(PHY_WAIT_MICRO_SECONDS); 2319 } 2320 2321 return queues; 2322} 2323 2324static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num) 2325{ 2326 u32 queues; 2327 2328 /* Stop Rx port activity. Check port Rx activity. */ 2329 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) 2330 & 0xFF; 2331 if (queues) { 2332 /* Issue stop command for active queues only */ 2333 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 2334 (queues << 8)); 2335 2336 /* Wait for all Rx activity to terminate. */ 2337 /* Check port cause register that all Rx queues are stopped */ 2338 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) 2339 & 0xFF) 2340 udelay(PHY_WAIT_MICRO_SECONDS); 2341 } 2342 2343 return queues; 2344} 2345 2346/* 2347 * eth_port_reset - Reset Ethernet port 2348 * 2349 * DESCRIPTION: 2350 * This routine resets the chip by aborting any SDMA engine activity and 2351 * clearing the MIB counters. The Receiver and the Transmit unit are in 2352 * idle state after this command is performed and the port is disabled. 2353 * 2354 * INPUT: 2355 * unsigned int eth_port_num Ethernet Port number. 2356 * 2357 * OUTPUT: 2358 * Channel activity is halted. 2359 * 2360 * RETURN: 2361 * None. 2362 * 2363 */ 2364static void eth_port_reset(unsigned int port_num) 2365{ 2366 unsigned int reg_data; 2367 2368 mv643xx_eth_port_disable_tx(port_num); 2369 mv643xx_eth_port_disable_rx(port_num); 2370 2371 /* Clear all MIB counters */ 2372 eth_clear_mib_counters(port_num); 2373 2374 /* Reset the Enable bit in the Configuration Register */ 2375 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); 2376 reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | 2377 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | 2378 MV643XX_ETH_FORCE_LINK_PASS); 2379 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data); 2380} 2381 2382 2383/* 2384 * eth_port_read_smi_reg - Read PHY registers 2385 * 2386 * DESCRIPTION: 2387 * This routine utilize the SMI interface to interact with the PHY in 2388 * order to perform PHY register read. 2389 * 2390 * INPUT: 2391 * unsigned int port_num Ethernet Port number. 2392 * unsigned int phy_reg PHY register address offset. 2393 * unsigned int *value Register value buffer. 2394 * 2395 * OUTPUT: 2396 * Write the value of a specified PHY register into given buffer. 2397 * 2398 * RETURN: 2399 * false if the PHY is busy or read data is not in valid state. 2400 * true otherwise. 2401 * 2402 */ 2403static void eth_port_read_smi_reg(unsigned int port_num, 2404 unsigned int phy_reg, unsigned int *value) 2405{ 2406 int phy_addr = ethernet_phy_get(port_num); 2407 unsigned long flags; 2408 int i; 2409 2410 /* the SMI register is a shared resource */ 2411 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); 2412 2413 /* wait for the SMI register to become available */ 2414 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { 2415 if (i == PHY_WAIT_ITERATIONS) { 2416 printk("mv643xx PHY busy timeout, port %d\n", port_num); 2417 goto out; 2418 } 2419 udelay(PHY_WAIT_MICRO_SECONDS); 2420 } 2421 2422 mv_write(MV643XX_ETH_SMI_REG, 2423 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ); 2424 2425 /* now wait for the data to be valid */ 2426 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) { 2427 if (i == PHY_WAIT_ITERATIONS) { 2428 printk("mv643xx PHY read timeout, port %d\n", port_num); 2429 goto out; 2430 } 2431 udelay(PHY_WAIT_MICRO_SECONDS); 2432 } 2433 2434 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff; 2435out: 2436 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); 2437} 2438 2439/* 2440 * eth_port_write_smi_reg - Write to PHY registers 2441 * 2442 * DESCRIPTION: 2443 * This routine utilize the SMI interface to interact with the PHY in 2444 * order to perform writes to PHY registers. 2445 * 2446 * INPUT: 2447 * unsigned int eth_port_num Ethernet Port number. 2448 * unsigned int phy_reg PHY register address offset. 2449 * unsigned int value Register value. 2450 * 2451 * OUTPUT: 2452 * Write the given value to the specified PHY register. 2453 * 2454 * RETURN: 2455 * false if the PHY is busy. 2456 * true otherwise. 2457 * 2458 */ 2459static void eth_port_write_smi_reg(unsigned int eth_port_num, 2460 unsigned int phy_reg, unsigned int value) 2461{ 2462 int phy_addr; 2463 int i; 2464 unsigned long flags; 2465 2466 phy_addr = ethernet_phy_get(eth_port_num); 2467 2468 /* the SMI register is a shared resource */ 2469 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); 2470 2471 /* wait for the SMI register to become available */ 2472 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { 2473 if (i == PHY_WAIT_ITERATIONS) { 2474 printk("mv643xx PHY busy timeout, port %d\n", 2475 eth_port_num); 2476 goto out; 2477 } 2478 udelay(PHY_WAIT_MICRO_SECONDS); 2479 } 2480 2481 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) | 2482 ETH_SMI_OPCODE_WRITE | (value & 0xffff)); 2483out: 2484 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); 2485} 2486 2487/* 2488 * Wrappers for MII support library. 2489 */ 2490static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) 2491{ 2492 int val; 2493 struct mv643xx_private *mp = netdev_priv(dev); 2494 2495 eth_port_read_smi_reg(mp->port_num, location, &val); 2496 return val; 2497} 2498 2499static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) 2500{ 2501 struct mv643xx_private *mp = netdev_priv(dev); 2502 eth_port_write_smi_reg(mp->port_num, location, val); 2503} 2504 2505/* 2506 * eth_port_receive - Get received information from Rx ring. 2507 * 2508 * DESCRIPTION: 2509 * This routine returns the received data to the caller. There is no 2510 * data copying during routine operation. All information is returned 2511 * using pointer to packet information struct passed from the caller. 2512 * If the routine exhausts Rx ring resources then the resource error flag 2513 * is set. 2514 * 2515 * INPUT: 2516 * struct mv643xx_private *mp Ethernet Port Control srtuct. 2517 * struct pkt_info *p_pkt_info User packet buffer. 2518 * 2519 * OUTPUT: 2520 * Rx ring current and used indexes are updated. 2521 * 2522 * RETURN: 2523 * ETH_ERROR in case the routine can not access Rx desc ring. 2524 * ETH_QUEUE_FULL if Rx ring resources are exhausted. 2525 * ETH_END_OF_JOB if there is no received data. 2526 * ETH_OK otherwise. 2527 */ 2528static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, 2529 struct pkt_info *p_pkt_info) 2530{ 2531 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 2532 volatile struct eth_rx_desc *p_rx_desc; 2533 unsigned int command_status; 2534 unsigned long flags; 2535 2536 /* Do not process Rx ring in case of Rx ring resource error */ 2537 if (mp->rx_resource_err) 2538 return ETH_QUEUE_FULL; 2539 2540 spin_lock_irqsave(&mp->lock, flags); 2541 2542 /* Get the Rx Desc ring 'curr and 'used' indexes */ 2543 rx_curr_desc = mp->rx_curr_desc_q; 2544 rx_used_desc = mp->rx_used_desc_q; 2545 2546 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; 2547 2548 /* The following parameters are used to save readings from memory */ 2549 command_status = p_rx_desc->cmd_sts; 2550 rmb(); 2551 2552 /* Nothing to receive... */ 2553 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { 2554 spin_unlock_irqrestore(&mp->lock, flags); 2555 return ETH_END_OF_JOB; 2556 } 2557 2558 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; 2559 p_pkt_info->cmd_sts = command_status; 2560 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; 2561 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; 2562 p_pkt_info->l4i_chk = p_rx_desc->buf_size; 2563 2564 /* 2565 * Clean the return info field to indicate that the 2566 * packet has been moved to the upper layers 2567 */ 2568 mp->rx_skb[rx_curr_desc] = NULL; 2569 2570 /* Update current index in data structure */ 2571 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; 2572 mp->rx_curr_desc_q = rx_next_curr_desc; 2573 2574 /* Rx descriptors exhausted. Set the Rx ring resource error flag */ 2575 if (rx_next_curr_desc == rx_used_desc) 2576 mp->rx_resource_err = 1; 2577 2578 spin_unlock_irqrestore(&mp->lock, flags); 2579 2580 return ETH_OK; 2581} 2582 2583/* 2584 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. 2585 * 2586 * DESCRIPTION: 2587 * This routine returns a Rx buffer back to the Rx ring. It retrieves the 2588 * next 'used' descriptor and attached the returned buffer to it. 2589 * In case the Rx ring was in "resource error" condition, where there are 2590 * no available Rx resources, the function resets the resource error flag. 2591 * 2592 * INPUT: 2593 * struct mv643xx_private *mp Ethernet Port Control srtuct. 2594 * struct pkt_info *p_pkt_info Information on returned buffer. 2595 * 2596 * OUTPUT: 2597 * New available Rx resource in Rx descriptor ring. 2598 * 2599 * RETURN: 2600 * ETH_ERROR in case the routine can not access Rx desc ring. 2601 * ETH_OK otherwise. 2602 */ 2603static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, 2604 struct pkt_info *p_pkt_info) 2605{ 2606 int used_rx_desc; /* Where to return Rx resource */ 2607 volatile struct eth_rx_desc *p_used_rx_desc; 2608 unsigned long flags; 2609 2610 spin_lock_irqsave(&mp->lock, flags); 2611 2612 /* Get 'used' Rx descriptor */ 2613 used_rx_desc = mp->rx_used_desc_q; 2614 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; 2615 2616 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; 2617 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; 2618 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; 2619 2620 /* Flush the write pipe */ 2621 2622 /* Return the descriptor to DMA ownership */ 2623 wmb(); 2624 p_used_rx_desc->cmd_sts = 2625 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; 2626 wmb(); 2627 2628 /* Move the used descriptor pointer to the next descriptor */ 2629 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; 2630 2631 /* Any Rx return cancels the Rx resource error status */ 2632 mp->rx_resource_err = 0; 2633 2634 spin_unlock_irqrestore(&mp->lock, flags); 2635 2636 return ETH_OK; 2637} 2638 2639/************* Begin ethtool support *************************/ 2640 2641struct mv643xx_stats { 2642 char stat_string[ETH_GSTRING_LEN]; 2643 int sizeof_stat; 2644 int stat_offset; 2645}; 2646 2647#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \ 2648 offsetof(struct mv643xx_private, m) 2649 2650static const struct mv643xx_stats mv643xx_gstrings_stats[] = { 2651 { "rx_packets", MV643XX_STAT(stats.rx_packets) }, 2652 { "tx_packets", MV643XX_STAT(stats.tx_packets) }, 2653 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, 2654 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, 2655 { "rx_errors", MV643XX_STAT(stats.rx_errors) }, 2656 { "tx_errors", MV643XX_STAT(stats.tx_errors) }, 2657 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, 2658 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, 2659 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, 2660 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, 2661 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, 2662 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, 2663 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, 2664 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, 2665 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, 2666 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, 2667 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, 2668 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, 2669 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, 2670 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, 2671 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, 2672 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, 2673 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, 2674 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, 2675 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, 2676 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, 2677 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, 2678 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, 2679 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, 2680 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, 2681 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, 2682 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, 2683 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, 2684 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, 2685 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, 2686 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, 2687 { "collision", MV643XX_STAT(mib_counters.collision) }, 2688 { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, 2689}; 2690 2691#define MV643XX_STATS_LEN \ 2692 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats) 2693 2694static void mv643xx_get_drvinfo(struct net_device *netdev, 2695 struct ethtool_drvinfo *drvinfo) 2696{ 2697 strncpy(drvinfo->driver, mv643xx_driver_name, 32); 2698 strncpy(drvinfo->version, mv643xx_driver_version, 32); 2699 strncpy(drvinfo->fw_version, "N/A", 32); 2700 strncpy(drvinfo->bus_info, "mv643xx", 32); 2701 drvinfo->n_stats = MV643XX_STATS_LEN; 2702} 2703 2704static int mv643xx_get_stats_count(struct net_device *netdev) 2705{ 2706 return MV643XX_STATS_LEN; 2707} 2708 2709static void mv643xx_get_ethtool_stats(struct net_device *netdev, 2710 struct ethtool_stats *stats, uint64_t *data) 2711{ 2712 struct mv643xx_private *mp = netdev->priv; 2713 int i; 2714 2715 eth_update_mib_counters(mp); 2716 2717 for (i = 0; i < MV643XX_STATS_LEN; i++) { 2718 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; 2719 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == 2720 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; 2721 } 2722} 2723 2724static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, 2725 uint8_t *data) 2726{ 2727 int i; 2728 2729 switch(stringset) { 2730 case ETH_SS_STATS: 2731 for (i=0; i < MV643XX_STATS_LEN; i++) { 2732 memcpy(data + i * ETH_GSTRING_LEN, 2733 mv643xx_gstrings_stats[i].stat_string, 2734 ETH_GSTRING_LEN); 2735 } 2736 break; 2737 } 2738} 2739 2740static u32 mv643xx_eth_get_link(struct net_device *dev) 2741{ 2742 struct mv643xx_private *mp = netdev_priv(dev); 2743 2744 return mii_link_ok(&mp->mii); 2745} 2746 2747static int mv643xx_eth_nway_restart(struct net_device *dev) 2748{ 2749 struct mv643xx_private *mp = netdev_priv(dev); 2750 2751 return mii_nway_restart(&mp->mii); 2752} 2753 2754static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2755{ 2756 struct mv643xx_private *mp = netdev_priv(dev); 2757 2758 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); 2759} 2760 2761static const struct ethtool_ops mv643xx_ethtool_ops = { 2762 .get_settings = mv643xx_get_settings, 2763 .set_settings = mv643xx_set_settings, 2764 .get_drvinfo = mv643xx_get_drvinfo, 2765 .get_link = mv643xx_eth_get_link, 2766 .get_sg = ethtool_op_get_sg, 2767 .set_sg = ethtool_op_set_sg, 2768 .get_stats_count = mv643xx_get_stats_count, 2769 .get_ethtool_stats = mv643xx_get_ethtool_stats, 2770 .get_strings = mv643xx_get_strings, 2771 .get_stats_count = mv643xx_get_stats_count, 2772 .get_ethtool_stats = mv643xx_get_ethtool_stats, 2773 .nway_reset = mv643xx_eth_nway_restart, 2774}; 2775 2776/************* End ethtool support *************************/ 2777