1/*
2 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses.  You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 *     Redistribution and use in source and binary forms, with or
15 *     without modification, are permitted provided that the following
16 *     conditions are met:
17 *
18 *      - Redistributions of source code must retain the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer.
21 *
22 *      - Redistributions in binary form must reproduce the above
23 *        copyright notice, this list of conditions and the following
24 *        disclaimer in the documentation and/or other materials
25 *        provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
40#include <linux/radix-tree.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#define DRV_NAME	"mlx4_core"
46#define PFX		DRV_NAME ": "
47#define DRV_VERSION	"0.01"
48#define DRV_RELDATE	"May 1, 2007"
49
50enum {
51	MLX4_HCR_BASE		= 0x80680,
52	MLX4_HCR_SIZE		= 0x0001c,
53	MLX4_CLR_INT_SIZE	= 0x00008
54};
55
56enum {
57	MLX4_BOARD_ID_LEN	= 64
58};
59
60enum {
61	MLX4_MGM_ENTRY_SIZE	=  0x40,
62	MLX4_QP_PER_MGM		= 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
63	MLX4_MTT_ENTRY_PER_SEG	= 8
64};
65
66enum {
67	MLX4_EQ_ASYNC,
68	MLX4_EQ_COMP,
69	MLX4_EQ_CATAS,
70	MLX4_NUM_EQ
71};
72
73enum {
74	MLX4_NUM_PDS		= 1 << 15
75};
76
77enum {
78	MLX4_CMPT_TYPE_QP	= 0,
79	MLX4_CMPT_TYPE_SRQ	= 1,
80	MLX4_CMPT_TYPE_CQ	= 2,
81	MLX4_CMPT_TYPE_EQ	= 3,
82	MLX4_CMPT_NUM_TYPE
83};
84
85enum {
86	MLX4_CMPT_SHIFT		= 24,
87	MLX4_NUM_CMPTS		= MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
88};
89
90#ifdef CONFIG_MLX4_DEBUG
91extern int mlx4_debug_level;
92
93#define mlx4_dbg(mdev, format, arg...)					\
94	do {								\
95		if (mlx4_debug_level)					\
96			dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
97	} while (0)
98
99#else /* CONFIG_MLX4_DEBUG */
100
101#define mlx4_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
102
103#endif /* CONFIG_MLX4_DEBUG */
104
105#define mlx4_err(mdev, format, arg...) \
106	dev_err(&mdev->pdev->dev, format, ## arg)
107#define mlx4_info(mdev, format, arg...) \
108	dev_info(&mdev->pdev->dev, format, ## arg)
109#define mlx4_warn(mdev, format, arg...) \
110	dev_warn(&mdev->pdev->dev, format, ## arg)
111
112struct mlx4_bitmap {
113	u32			last;
114	u32			top;
115	u32			max;
116	u32			mask;
117	spinlock_t		lock;
118	unsigned long	       *table;
119};
120
121struct mlx4_buddy {
122	unsigned long	      **bits;
123	int			max_order;
124	spinlock_t		lock;
125};
126
127struct mlx4_icm;
128
129struct mlx4_icm_table {
130	u64			virt;
131	int			num_icm;
132	int			num_obj;
133	int			obj_size;
134	int			lowmem;
135	struct mutex		mutex;
136	struct mlx4_icm	      **icm;
137};
138
139struct mlx4_eq {
140	struct mlx4_dev	       *dev;
141	void __iomem	       *doorbell;
142	int			eqn;
143	u32			cons_index;
144	u16			irq;
145	u16			have_irq;
146	int			nent;
147	struct mlx4_buf_list   *page_list;
148	struct mlx4_mtt		mtt;
149};
150
151struct mlx4_profile {
152	int			num_qp;
153	int			rdmarc_per_qp;
154	int			num_srq;
155	int			num_cq;
156	int			num_mcg;
157	int			num_mpt;
158	int			num_mtt;
159};
160
161struct mlx4_fw {
162	u64			clr_int_base;
163	u64			catas_offset;
164	struct mlx4_icm	       *fw_icm;
165	struct mlx4_icm	       *aux_icm;
166	u32			catas_size;
167	u16			fw_pages;
168	u8			clr_int_bar;
169	u8			catas_bar;
170};
171
172struct mlx4_cmd {
173	struct pci_pool	       *pool;
174	void __iomem	       *hcr;
175	struct mutex		hcr_mutex;
176	struct semaphore	poll_sem;
177	struct semaphore	event_sem;
178	int			max_cmds;
179	spinlock_t		context_lock;
180	int			free_head;
181	struct mlx4_cmd_context *context;
182	u16			token_mask;
183	u8			use_events;
184	u8			toggle;
185};
186
187struct mlx4_uar_table {
188	struct mlx4_bitmap	bitmap;
189};
190
191struct mlx4_mr_table {
192	struct mlx4_bitmap	mpt_bitmap;
193	struct mlx4_buddy	mtt_buddy;
194	u64			mtt_base;
195	u64			mpt_base;
196	struct mlx4_icm_table	mtt_table;
197	struct mlx4_icm_table	dmpt_table;
198};
199
200struct mlx4_cq_table {
201	struct mlx4_bitmap	bitmap;
202	spinlock_t		lock;
203	struct radix_tree_root	tree;
204	struct mlx4_icm_table	table;
205	struct mlx4_icm_table	cmpt_table;
206};
207
208struct mlx4_eq_table {
209	struct mlx4_bitmap	bitmap;
210	void __iomem	       *clr_int;
211	void __iomem	       *uar_map[(MLX4_NUM_EQ + 6) / 4];
212	u32			clr_mask;
213	struct mlx4_eq		eq[MLX4_NUM_EQ];
214	u64			icm_virt;
215	struct page	       *icm_page;
216	dma_addr_t		icm_dma;
217	struct mlx4_icm_table	cmpt_table;
218	int			have_irq;
219	u8			inta_pin;
220};
221
222struct mlx4_srq_table {
223	struct mlx4_bitmap	bitmap;
224	spinlock_t		lock;
225	struct radix_tree_root	tree;
226	struct mlx4_icm_table	table;
227	struct mlx4_icm_table	cmpt_table;
228};
229
230struct mlx4_qp_table {
231	struct mlx4_bitmap	bitmap;
232	u32			rdmarc_base;
233	int			rdmarc_shift;
234	spinlock_t		lock;
235	struct mlx4_icm_table	qp_table;
236	struct mlx4_icm_table	auxc_table;
237	struct mlx4_icm_table	altc_table;
238	struct mlx4_icm_table	rdmarc_table;
239	struct mlx4_icm_table	cmpt_table;
240};
241
242struct mlx4_mcg_table {
243	struct mutex		mutex;
244	struct mlx4_bitmap	bitmap;
245	struct mlx4_icm_table	table;
246};
247
248struct mlx4_catas_err {
249	u32 __iomem	       *map;
250	int			size;
251};
252
253struct mlx4_priv {
254	struct mlx4_dev		dev;
255
256	struct list_head	dev_list;
257	struct list_head	ctx_list;
258	spinlock_t		ctx_lock;
259
260	struct mlx4_fw		fw;
261	struct mlx4_cmd		cmd;
262
263	struct mlx4_bitmap	pd_bitmap;
264	struct mlx4_uar_table	uar_table;
265	struct mlx4_mr_table	mr_table;
266	struct mlx4_cq_table	cq_table;
267	struct mlx4_eq_table	eq_table;
268	struct mlx4_srq_table	srq_table;
269	struct mlx4_qp_table	qp_table;
270	struct mlx4_mcg_table	mcg_table;
271
272	struct mlx4_catas_err	catas_err;
273
274	void __iomem	       *clr_base;
275
276	struct mlx4_uar		driver_uar;
277	void __iomem	       *kar;
278
279	u32			rev_id;
280	char			board_id[MLX4_BOARD_ID_LEN];
281};
282
283static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
284{
285	return container_of(dev, struct mlx4_priv, dev);
286}
287
288u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
289void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
290int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, u32 reserved);
291void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
292
293int mlx4_reset(struct mlx4_dev *dev);
294
295int mlx4_init_pd_table(struct mlx4_dev *dev);
296int mlx4_init_uar_table(struct mlx4_dev *dev);
297int mlx4_init_mr_table(struct mlx4_dev *dev);
298int mlx4_init_eq_table(struct mlx4_dev *dev);
299int mlx4_init_cq_table(struct mlx4_dev *dev);
300int mlx4_init_qp_table(struct mlx4_dev *dev);
301int mlx4_init_srq_table(struct mlx4_dev *dev);
302int mlx4_init_mcg_table(struct mlx4_dev *dev);
303
304void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
305void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
306void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
307void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
308void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
309void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
310void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
311void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
312
313void mlx4_map_catas_buf(struct mlx4_dev *dev);
314void mlx4_unmap_catas_buf(struct mlx4_dev *dev);
315
316int mlx4_register_device(struct mlx4_dev *dev);
317void mlx4_unregister_device(struct mlx4_dev *dev);
318void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_event type,
319			 int subtype, int port);
320
321struct mlx4_dev_cap;
322struct mlx4_init_hca_param;
323
324u64 mlx4_make_profile(struct mlx4_dev *dev,
325		      struct mlx4_profile *request,
326		      struct mlx4_dev_cap *dev_cap,
327		      struct mlx4_init_hca_param *init_hca);
328
329int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
330void mlx4_unmap_eq_icm(struct mlx4_dev *dev);
331
332int mlx4_cmd_init(struct mlx4_dev *dev);
333void mlx4_cmd_cleanup(struct mlx4_dev *dev);
334void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
335int mlx4_cmd_use_events(struct mlx4_dev *dev);
336void mlx4_cmd_use_polling(struct mlx4_dev *dev);
337
338void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
339void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
340
341void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
342
343void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
344
345void mlx4_handle_catas_err(struct mlx4_dev *dev);
346
347#endif /* MLX4_H */
348