1/* 2 * Network device driver for the MACE ethernet controller on 3 * Apple Powermacs. Assumes it's under a DBDMA controller. 4 * 5 * Copyright (C) 1996 Paul Mackerras. 6 */ 7 8#include <linux/module.h> 9#include <linux/kernel.h> 10#include <linux/netdevice.h> 11#include <linux/etherdevice.h> 12#include <linux/delay.h> 13#include <linux/string.h> 14#include <linux/timer.h> 15#include <linux/init.h> 16#include <linux/crc32.h> 17#include <linux/spinlock.h> 18#include <linux/bitrev.h> 19#include <asm/prom.h> 20#include <asm/dbdma.h> 21#include <asm/io.h> 22#include <asm/pgtable.h> 23#include <asm/macio.h> 24 25#include "mace.h" 26 27static int port_aaui = -1; 28 29#define N_RX_RING 8 30#define N_TX_RING 6 31#define MAX_TX_ACTIVE 1 32#define NCMDS_TX 1 /* dma commands per element in tx ring */ 33#define RX_BUFLEN (ETH_FRAME_LEN + 8) 34#define TX_TIMEOUT HZ /* 1 second */ 35 36#define BROKEN_ADDRCHG_REV 0x0941 37 38/* Bits in transmit DMA status */ 39#define TX_DMA_ERR 0x80 40 41struct mace_data { 42 volatile struct mace __iomem *mace; 43 volatile struct dbdma_regs __iomem *tx_dma; 44 int tx_dma_intr; 45 volatile struct dbdma_regs __iomem *rx_dma; 46 int rx_dma_intr; 47 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */ 48 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */ 49 struct sk_buff *rx_bufs[N_RX_RING]; 50 int rx_fill; 51 int rx_empty; 52 struct sk_buff *tx_bufs[N_TX_RING]; 53 int tx_fill; 54 int tx_empty; 55 unsigned char maccc; 56 unsigned char tx_fullup; 57 unsigned char tx_active; 58 unsigned char tx_bad_runt; 59 struct net_device_stats stats; 60 struct timer_list tx_timeout; 61 int timeout_active; 62 int port_aaui; 63 int chipid; 64 struct macio_dev *mdev; 65 spinlock_t lock; 66}; 67 68/* 69 * Number of bytes of private data per MACE: allow enough for 70 * the rx and tx dma commands plus a branch dma command each, 71 * and another 16 bytes to allow us to align the dma command 72 * buffers on a 16 byte boundary. 73 */ 74#define PRIV_BYTES (sizeof(struct mace_data) \ 75 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd)) 76 77static int mace_open(struct net_device *dev); 78static int mace_close(struct net_device *dev); 79static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); 80static struct net_device_stats *mace_stats(struct net_device *dev); 81static void mace_set_multicast(struct net_device *dev); 82static void mace_reset(struct net_device *dev); 83static int mace_set_address(struct net_device *dev, void *addr); 84static irqreturn_t mace_interrupt(int irq, void *dev_id); 85static irqreturn_t mace_txdma_intr(int irq, void *dev_id); 86static irqreturn_t mace_rxdma_intr(int irq, void *dev_id); 87static void mace_set_timeout(struct net_device *dev); 88static void mace_tx_timeout(unsigned long data); 89static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma); 90static inline void mace_clean_rings(struct mace_data *mp); 91static void __mace_set_address(struct net_device *dev, void *addr); 92 93/* 94 * If we can't get a skbuff when we need it, we use this area for DMA. 95 */ 96static unsigned char *dummy_buf; 97 98static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match) 99{ 100 struct device_node *mace = macio_get_of_node(mdev); 101 struct net_device *dev; 102 struct mace_data *mp; 103 const unsigned char *addr; 104 int j, rev, rc = -EBUSY; 105 106 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) { 107 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n", 108 mace->full_name); 109 return -ENODEV; 110 } 111 112 addr = of_get_property(mace, "mac-address", NULL); 113 if (addr == NULL) { 114 addr = of_get_property(mace, "local-mac-address", NULL); 115 if (addr == NULL) { 116 printk(KERN_ERR "Can't get mac-address for MACE %s\n", 117 mace->full_name); 118 return -ENODEV; 119 } 120 } 121 122 /* 123 * lazy allocate the driver-wide dummy buffer. (Note that we 124 * never have more than one MACE in the system anyway) 125 */ 126 if (dummy_buf == NULL) { 127 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL); 128 if (dummy_buf == NULL) { 129 printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n"); 130 return -ENOMEM; 131 } 132 } 133 134 if (macio_request_resources(mdev, "mace")) { 135 printk(KERN_ERR "MACE: can't request IO resources !\n"); 136 return -EBUSY; 137 } 138 139 dev = alloc_etherdev(PRIV_BYTES); 140 if (!dev) { 141 printk(KERN_ERR "MACE: can't allocate ethernet device !\n"); 142 rc = -ENOMEM; 143 goto err_release; 144 } 145 SET_MODULE_OWNER(dev); 146 SET_NETDEV_DEV(dev, &mdev->ofdev.dev); 147 148 mp = dev->priv; 149 mp->mdev = mdev; 150 macio_set_drvdata(mdev, dev); 151 152 dev->base_addr = macio_resource_start(mdev, 0); 153 mp->mace = ioremap(dev->base_addr, 0x1000); 154 if (mp->mace == NULL) { 155 printk(KERN_ERR "MACE: can't map IO resources !\n"); 156 rc = -ENOMEM; 157 goto err_free; 158 } 159 dev->irq = macio_irq(mdev, 0); 160 161 rev = addr[0] == 0 && addr[1] == 0xA0; 162 for (j = 0; j < 6; ++j) { 163 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; 164 } 165 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) | 166 in_8(&mp->mace->chipid_lo); 167 168 169 mp = (struct mace_data *) dev->priv; 170 mp->maccc = ENXMT | ENRCV; 171 172 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000); 173 if (mp->tx_dma == NULL) { 174 printk(KERN_ERR "MACE: can't map TX DMA resources !\n"); 175 rc = -ENOMEM; 176 goto err_unmap_io; 177 } 178 mp->tx_dma_intr = macio_irq(mdev, 1); 179 180 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000); 181 if (mp->rx_dma == NULL) { 182 printk(KERN_ERR "MACE: can't map RX DMA resources !\n"); 183 rc = -ENOMEM; 184 goto err_unmap_tx_dma; 185 } 186 mp->rx_dma_intr = macio_irq(mdev, 2); 187 188 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1); 189 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1; 190 191 memset(&mp->stats, 0, sizeof(mp->stats)); 192 memset((char *) mp->tx_cmds, 0, 193 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd)); 194 init_timer(&mp->tx_timeout); 195 spin_lock_init(&mp->lock); 196 mp->timeout_active = 0; 197 198 if (port_aaui >= 0) 199 mp->port_aaui = port_aaui; 200 else { 201 /* Apple Network Server uses the AAUI port */ 202 if (machine_is_compatible("AAPL,ShinerESB")) 203 mp->port_aaui = 1; 204 else { 205#ifdef CONFIG_MACE_AAUI_PORT 206 mp->port_aaui = 1; 207#else 208 mp->port_aaui = 0; 209#endif 210 } 211 } 212 213 dev->open = mace_open; 214 dev->stop = mace_close; 215 dev->hard_start_xmit = mace_xmit_start; 216 dev->get_stats = mace_stats; 217 dev->set_multicast_list = mace_set_multicast; 218 dev->set_mac_address = mace_set_address; 219 220 /* 221 * Most of what is below could be moved to mace_open() 222 */ 223 mace_reset(dev); 224 225 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev); 226 if (rc) { 227 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq); 228 goto err_unmap_rx_dma; 229 } 230 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev); 231 if (rc) { 232 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr); 233 goto err_free_irq; 234 } 235 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev); 236 if (rc) { 237 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr); 238 goto err_free_tx_irq; 239 } 240 241 rc = register_netdev(dev); 242 if (rc) { 243 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n"); 244 goto err_free_rx_irq; 245 } 246 247 printk(KERN_INFO "%s: MACE at", dev->name); 248 for (j = 0; j < 6; ++j) { 249 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]); 250 } 251 printk(", chip revision %d.%d\n", mp->chipid >> 8, mp->chipid & 0xff); 252 253 return 0; 254 255 err_free_rx_irq: 256 free_irq(macio_irq(mdev, 2), dev); 257 err_free_tx_irq: 258 free_irq(macio_irq(mdev, 1), dev); 259 err_free_irq: 260 free_irq(macio_irq(mdev, 0), dev); 261 err_unmap_rx_dma: 262 iounmap(mp->rx_dma); 263 err_unmap_tx_dma: 264 iounmap(mp->tx_dma); 265 err_unmap_io: 266 iounmap(mp->mace); 267 err_free: 268 free_netdev(dev); 269 err_release: 270 macio_release_resources(mdev); 271 272 return rc; 273} 274 275static int __devexit mace_remove(struct macio_dev *mdev) 276{ 277 struct net_device *dev = macio_get_drvdata(mdev); 278 struct mace_data *mp; 279 280 BUG_ON(dev == NULL); 281 282 macio_set_drvdata(mdev, NULL); 283 284 mp = dev->priv; 285 286 unregister_netdev(dev); 287 288 free_irq(dev->irq, dev); 289 free_irq(mp->tx_dma_intr, dev); 290 free_irq(mp->rx_dma_intr, dev); 291 292 iounmap(mp->rx_dma); 293 iounmap(mp->tx_dma); 294 iounmap(mp->mace); 295 296 free_netdev(dev); 297 298 macio_release_resources(mdev); 299 300 return 0; 301} 302 303static void dbdma_reset(volatile struct dbdma_regs __iomem *dma) 304{ 305 int i; 306 307 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); 308 309 /* 310 * Yes this looks peculiar, but apparently it needs to be this 311 * way on some machines. 312 */ 313 for (i = 200; i > 0; --i) 314 if (ld_le32(&dma->control) & RUN) 315 udelay(1); 316} 317 318static void mace_reset(struct net_device *dev) 319{ 320 struct mace_data *mp = (struct mace_data *) dev->priv; 321 volatile struct mace __iomem *mb = mp->mace; 322 int i; 323 324 /* soft-reset the chip */ 325 i = 200; 326 while (--i) { 327 out_8(&mb->biucc, SWRST); 328 if (in_8(&mb->biucc) & SWRST) { 329 udelay(10); 330 continue; 331 } 332 break; 333 } 334 if (!i) { 335 printk(KERN_ERR "mace: cannot reset chip!\n"); 336 return; 337 } 338 339 out_8(&mb->imr, 0xff); /* disable all intrs for now */ 340 i = in_8(&mb->ir); 341 out_8(&mb->maccc, 0); /* turn off tx, rx */ 342 343 out_8(&mb->biucc, XMTSP_64); 344 out_8(&mb->utr, RTRD); 345 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST); 346 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */ 347 out_8(&mb->rcvfc, 0); 348 349 /* load up the hardware address */ 350 __mace_set_address(dev, dev->dev_addr); 351 352 /* clear the multicast filter */ 353 if (mp->chipid == BROKEN_ADDRCHG_REV) 354 out_8(&mb->iac, LOGADDR); 355 else { 356 out_8(&mb->iac, ADDRCHG | LOGADDR); 357 while ((in_8(&mb->iac) & ADDRCHG) != 0) 358 ; 359 } 360 for (i = 0; i < 8; ++i) 361 out_8(&mb->ladrf, 0); 362 363 /* done changing address */ 364 if (mp->chipid != BROKEN_ADDRCHG_REV) 365 out_8(&mb->iac, 0); 366 367 if (mp->port_aaui) 368 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO); 369 else 370 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO); 371} 372 373static void __mace_set_address(struct net_device *dev, void *addr) 374{ 375 struct mace_data *mp = (struct mace_data *) dev->priv; 376 volatile struct mace __iomem *mb = mp->mace; 377 unsigned char *p = addr; 378 int i; 379 380 /* load up the hardware address */ 381 if (mp->chipid == BROKEN_ADDRCHG_REV) 382 out_8(&mb->iac, PHYADDR); 383 else { 384 out_8(&mb->iac, ADDRCHG | PHYADDR); 385 while ((in_8(&mb->iac) & ADDRCHG) != 0) 386 ; 387 } 388 for (i = 0; i < 6; ++i) 389 out_8(&mb->padr, dev->dev_addr[i] = p[i]); 390 if (mp->chipid != BROKEN_ADDRCHG_REV) 391 out_8(&mb->iac, 0); 392} 393 394static int mace_set_address(struct net_device *dev, void *addr) 395{ 396 struct mace_data *mp = (struct mace_data *) dev->priv; 397 volatile struct mace __iomem *mb = mp->mace; 398 unsigned long flags; 399 400 spin_lock_irqsave(&mp->lock, flags); 401 402 __mace_set_address(dev, addr); 403 404 /* note: setting ADDRCHG clears ENRCV */ 405 out_8(&mb->maccc, mp->maccc); 406 407 spin_unlock_irqrestore(&mp->lock, flags); 408 return 0; 409} 410 411static inline void mace_clean_rings(struct mace_data *mp) 412{ 413 int i; 414 415 /* free some skb's */ 416 for (i = 0; i < N_RX_RING; ++i) { 417 if (mp->rx_bufs[i] != 0) { 418 dev_kfree_skb(mp->rx_bufs[i]); 419 mp->rx_bufs[i] = NULL; 420 } 421 } 422 for (i = mp->tx_empty; i != mp->tx_fill; ) { 423 dev_kfree_skb(mp->tx_bufs[i]); 424 if (++i >= N_TX_RING) 425 i = 0; 426 } 427} 428 429static int mace_open(struct net_device *dev) 430{ 431 struct mace_data *mp = (struct mace_data *) dev->priv; 432 volatile struct mace __iomem *mb = mp->mace; 433 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; 434 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 435 volatile struct dbdma_cmd *cp; 436 int i; 437 struct sk_buff *skb; 438 unsigned char *data; 439 440 /* reset the chip */ 441 mace_reset(dev); 442 443 /* initialize list of sk_buffs for receiving and set up recv dma */ 444 mace_clean_rings(mp); 445 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd)); 446 cp = mp->rx_cmds; 447 for (i = 0; i < N_RX_RING - 1; ++i) { 448 skb = dev_alloc_skb(RX_BUFLEN + 2); 449 if (skb == 0) { 450 data = dummy_buf; 451 } else { 452 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */ 453 data = skb->data; 454 } 455 mp->rx_bufs[i] = skb; 456 st_le16(&cp->req_count, RX_BUFLEN); 457 st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); 458 st_le32(&cp->phy_addr, virt_to_bus(data)); 459 cp->xfer_status = 0; 460 ++cp; 461 } 462 mp->rx_bufs[i] = NULL; 463 st_le16(&cp->command, DBDMA_STOP); 464 mp->rx_fill = i; 465 mp->rx_empty = 0; 466 467 /* Put a branch back to the beginning of the receive command list */ 468 ++cp; 469 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); 470 st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds)); 471 472 /* start rx dma */ 473 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ 474 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds)); 475 out_le32(&rd->control, (RUN << 16) | RUN); 476 477 /* put a branch at the end of the tx command list */ 478 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING; 479 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); 480 st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds)); 481 482 /* reset tx dma */ 483 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); 484 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds)); 485 mp->tx_fill = 0; 486 mp->tx_empty = 0; 487 mp->tx_fullup = 0; 488 mp->tx_active = 0; 489 mp->tx_bad_runt = 0; 490 491 /* turn it on! */ 492 out_8(&mb->maccc, mp->maccc); 493 /* enable all interrupts except receive interrupts */ 494 out_8(&mb->imr, RCVINT); 495 496 return 0; 497} 498 499static int mace_close(struct net_device *dev) 500{ 501 struct mace_data *mp = (struct mace_data *) dev->priv; 502 volatile struct mace __iomem *mb = mp->mace; 503 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; 504 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 505 506 /* disable rx and tx */ 507 out_8(&mb->maccc, 0); 508 out_8(&mb->imr, 0xff); /* disable all intrs */ 509 510 /* disable rx and tx dma */ 511 st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ 512 st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ 513 514 mace_clean_rings(mp); 515 516 return 0; 517} 518 519static inline void mace_set_timeout(struct net_device *dev) 520{ 521 struct mace_data *mp = (struct mace_data *) dev->priv; 522 523 if (mp->timeout_active) 524 del_timer(&mp->tx_timeout); 525 mp->tx_timeout.expires = jiffies + TX_TIMEOUT; 526 mp->tx_timeout.function = mace_tx_timeout; 527 mp->tx_timeout.data = (unsigned long) dev; 528 add_timer(&mp->tx_timeout); 529 mp->timeout_active = 1; 530} 531 532static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) 533{ 534 struct mace_data *mp = (struct mace_data *) dev->priv; 535 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 536 volatile struct dbdma_cmd *cp, *np; 537 unsigned long flags; 538 int fill, next, len; 539 540 /* see if there's a free slot in the tx ring */ 541 spin_lock_irqsave(&mp->lock, flags); 542 fill = mp->tx_fill; 543 next = fill + 1; 544 if (next >= N_TX_RING) 545 next = 0; 546 if (next == mp->tx_empty) { 547 netif_stop_queue(dev); 548 mp->tx_fullup = 1; 549 spin_unlock_irqrestore(&mp->lock, flags); 550 return 1; /* can't take it at the moment */ 551 } 552 spin_unlock_irqrestore(&mp->lock, flags); 553 554 /* partially fill in the dma command block */ 555 len = skb->len; 556 if (len > ETH_FRAME_LEN) { 557 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len); 558 len = ETH_FRAME_LEN; 559 } 560 mp->tx_bufs[fill] = skb; 561 cp = mp->tx_cmds + NCMDS_TX * fill; 562 st_le16(&cp->req_count, len); 563 st_le32(&cp->phy_addr, virt_to_bus(skb->data)); 564 565 np = mp->tx_cmds + NCMDS_TX * next; 566 out_le16(&np->command, DBDMA_STOP); 567 568 /* poke the tx dma channel */ 569 spin_lock_irqsave(&mp->lock, flags); 570 mp->tx_fill = next; 571 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) { 572 out_le16(&cp->xfer_status, 0); 573 out_le16(&cp->command, OUTPUT_LAST); 574 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); 575 ++mp->tx_active; 576 mace_set_timeout(dev); 577 } 578 if (++next >= N_TX_RING) 579 next = 0; 580 if (next == mp->tx_empty) 581 netif_stop_queue(dev); 582 spin_unlock_irqrestore(&mp->lock, flags); 583 584 return 0; 585} 586 587static struct net_device_stats *mace_stats(struct net_device *dev) 588{ 589 struct mace_data *p = (struct mace_data *) dev->priv; 590 591 return &p->stats; 592} 593 594static void mace_set_multicast(struct net_device *dev) 595{ 596 struct mace_data *mp = (struct mace_data *) dev->priv; 597 volatile struct mace __iomem *mb = mp->mace; 598 int i, j; 599 u32 crc; 600 unsigned long flags; 601 602 spin_lock_irqsave(&mp->lock, flags); 603 mp->maccc &= ~PROM; 604 if (dev->flags & IFF_PROMISC) { 605 mp->maccc |= PROM; 606 } else { 607 unsigned char multicast_filter[8]; 608 struct dev_mc_list *dmi = dev->mc_list; 609 610 if (dev->flags & IFF_ALLMULTI) { 611 for (i = 0; i < 8; i++) 612 multicast_filter[i] = 0xff; 613 } else { 614 for (i = 0; i < 8; i++) 615 multicast_filter[i] = 0; 616 for (i = 0; i < dev->mc_count; i++) { 617 crc = ether_crc_le(6, dmi->dmi_addr); 618 j = crc >> 26; /* bit number in multicast_filter */ 619 multicast_filter[j >> 3] |= 1 << (j & 7); 620 dmi = dmi->next; 621 } 622 } 623 624 if (mp->chipid == BROKEN_ADDRCHG_REV) 625 out_8(&mb->iac, LOGADDR); 626 else { 627 out_8(&mb->iac, ADDRCHG | LOGADDR); 628 while ((in_8(&mb->iac) & ADDRCHG) != 0) 629 ; 630 } 631 for (i = 0; i < 8; ++i) 632 out_8(&mb->ladrf, multicast_filter[i]); 633 if (mp->chipid != BROKEN_ADDRCHG_REV) 634 out_8(&mb->iac, 0); 635 } 636 /* reset maccc */ 637 out_8(&mb->maccc, mp->maccc); 638 spin_unlock_irqrestore(&mp->lock, flags); 639} 640 641static void mace_handle_misc_intrs(struct mace_data *mp, int intr) 642{ 643 volatile struct mace __iomem *mb = mp->mace; 644 static int mace_babbles, mace_jabbers; 645 646 if (intr & MPCO) 647 mp->stats.rx_missed_errors += 256; 648 mp->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */ 649 if (intr & RNTPCO) 650 mp->stats.rx_length_errors += 256; 651 mp->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */ 652 if (intr & CERR) 653 ++mp->stats.tx_heartbeat_errors; 654 if (intr & BABBLE) 655 if (mace_babbles++ < 4) 656 printk(KERN_DEBUG "mace: babbling transmitter\n"); 657 if (intr & JABBER) 658 if (mace_jabbers++ < 4) 659 printk(KERN_DEBUG "mace: jabbering transceiver\n"); 660} 661 662static irqreturn_t mace_interrupt(int irq, void *dev_id) 663{ 664 struct net_device *dev = (struct net_device *) dev_id; 665 struct mace_data *mp = (struct mace_data *) dev->priv; 666 volatile struct mace __iomem *mb = mp->mace; 667 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 668 volatile struct dbdma_cmd *cp; 669 int intr, fs, i, stat, x; 670 int xcount, dstat; 671 unsigned long flags; 672 /* static int mace_last_fs, mace_last_xcount; */ 673 674 spin_lock_irqsave(&mp->lock, flags); 675 intr = in_8(&mb->ir); /* read interrupt register */ 676 in_8(&mb->xmtrc); /* get retries */ 677 mace_handle_misc_intrs(mp, intr); 678 679 i = mp->tx_empty; 680 while (in_8(&mb->pr) & XMTSV) { 681 del_timer(&mp->tx_timeout); 682 mp->timeout_active = 0; 683 /* 684 * Clear any interrupt indication associated with this status 685 * word. This appears to unlatch any error indication from 686 * the DMA controller. 687 */ 688 intr = in_8(&mb->ir); 689 if (intr != 0) 690 mace_handle_misc_intrs(mp, intr); 691 if (mp->tx_bad_runt) { 692 fs = in_8(&mb->xmtfs); 693 mp->tx_bad_runt = 0; 694 out_8(&mb->xmtfc, AUTO_PAD_XMIT); 695 continue; 696 } 697 dstat = ld_le32(&td->status); 698 /* stop DMA controller */ 699 out_le32(&td->control, RUN << 16); 700 /* 701 * xcount is the number of complete frames which have been 702 * written to the fifo but for which status has not been read. 703 */ 704 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; 705 if (xcount == 0 || (dstat & DEAD)) { 706 /* 707 * If a packet was aborted before the DMA controller has 708 * finished transferring it, it seems that there are 2 bytes 709 * which are stuck in some buffer somewhere. These will get 710 * transmitted as soon as we read the frame status (which 711 * reenables the transmit data transfer request). Turning 712 * off the DMA controller and/or resetting the MACE doesn't 713 * help. So we disable auto-padding and FCS transmission 714 * so the two bytes will only be a runt packet which should 715 * be ignored by other stations. 716 */ 717 out_8(&mb->xmtfc, DXMTFCS); 718 } 719 fs = in_8(&mb->xmtfs); 720 if ((fs & XMTSV) == 0) { 721 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n", 722 fs, xcount, dstat); 723 mace_reset(dev); 724 } 725 cp = mp->tx_cmds + NCMDS_TX * i; 726 stat = ld_le16(&cp->xfer_status); 727 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) { 728 /* 729 * Check whether there were in fact 2 bytes written to 730 * the transmit FIFO. 731 */ 732 udelay(1); 733 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; 734 if (x != 0) { 735 /* there were two bytes with an end-of-packet indication */ 736 mp->tx_bad_runt = 1; 737 mace_set_timeout(dev); 738 } else { 739 /* 740 * Either there weren't the two bytes buffered up, or they 741 * didn't have an end-of-packet indication. 742 * We flush the transmit FIFO just in case (by setting the 743 * XMTFWU bit with the transmitter disabled). 744 */ 745 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT); 746 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU); 747 udelay(1); 748 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT); 749 out_8(&mb->xmtfc, AUTO_PAD_XMIT); 750 } 751 } 752 /* dma should have finished */ 753 if (i == mp->tx_fill) { 754 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n", 755 fs, xcount, dstat); 756 continue; 757 } 758 /* Update stats */ 759 if (fs & (UFLO|LCOL|LCAR|RTRY)) { 760 ++mp->stats.tx_errors; 761 if (fs & LCAR) 762 ++mp->stats.tx_carrier_errors; 763 if (fs & (UFLO|LCOL|RTRY)) 764 ++mp->stats.tx_aborted_errors; 765 } else { 766 mp->stats.tx_bytes += mp->tx_bufs[i]->len; 767 ++mp->stats.tx_packets; 768 } 769 dev_kfree_skb_irq(mp->tx_bufs[i]); 770 --mp->tx_active; 771 if (++i >= N_TX_RING) 772 i = 0; 773 } 774 775 if (i != mp->tx_empty) { 776 mp->tx_fullup = 0; 777 netif_wake_queue(dev); 778 } 779 mp->tx_empty = i; 780 i += mp->tx_active; 781 if (i >= N_TX_RING) 782 i -= N_TX_RING; 783 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) { 784 do { 785 /* set up the next one */ 786 cp = mp->tx_cmds + NCMDS_TX * i; 787 out_le16(&cp->xfer_status, 0); 788 out_le16(&cp->command, OUTPUT_LAST); 789 ++mp->tx_active; 790 if (++i >= N_TX_RING) 791 i = 0; 792 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE); 793 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); 794 mace_set_timeout(dev); 795 } 796 spin_unlock_irqrestore(&mp->lock, flags); 797 return IRQ_HANDLED; 798} 799 800static void mace_tx_timeout(unsigned long data) 801{ 802 struct net_device *dev = (struct net_device *) data; 803 struct mace_data *mp = (struct mace_data *) dev->priv; 804 volatile struct mace __iomem *mb = mp->mace; 805 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 806 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; 807 volatile struct dbdma_cmd *cp; 808 unsigned long flags; 809 int i; 810 811 spin_lock_irqsave(&mp->lock, flags); 812 mp->timeout_active = 0; 813 if (mp->tx_active == 0 && !mp->tx_bad_runt) 814 goto out; 815 816 /* update various counters */ 817 mace_handle_misc_intrs(mp, in_8(&mb->ir)); 818 819 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty; 820 821 /* turn off both tx and rx and reset the chip */ 822 out_8(&mb->maccc, 0); 823 printk(KERN_ERR "mace: transmit timeout - resetting\n"); 824 dbdma_reset(td); 825 mace_reset(dev); 826 827 /* restart rx dma */ 828 cp = bus_to_virt(ld_le32(&rd->cmdptr)); 829 dbdma_reset(rd); 830 out_le16(&cp->xfer_status, 0); 831 out_le32(&rd->cmdptr, virt_to_bus(cp)); 832 out_le32(&rd->control, (RUN << 16) | RUN); 833 834 /* fix up the transmit side */ 835 i = mp->tx_empty; 836 mp->tx_active = 0; 837 ++mp->stats.tx_errors; 838 if (mp->tx_bad_runt) { 839 mp->tx_bad_runt = 0; 840 } else if (i != mp->tx_fill) { 841 dev_kfree_skb(mp->tx_bufs[i]); 842 if (++i >= N_TX_RING) 843 i = 0; 844 mp->tx_empty = i; 845 } 846 mp->tx_fullup = 0; 847 netif_wake_queue(dev); 848 if (i != mp->tx_fill) { 849 cp = mp->tx_cmds + NCMDS_TX * i; 850 out_le16(&cp->xfer_status, 0); 851 out_le16(&cp->command, OUTPUT_LAST); 852 out_le32(&td->cmdptr, virt_to_bus(cp)); 853 out_le32(&td->control, (RUN << 16) | RUN); 854 ++mp->tx_active; 855 mace_set_timeout(dev); 856 } 857 858 /* turn it back on */ 859 out_8(&mb->imr, RCVINT); 860 out_8(&mb->maccc, mp->maccc); 861 862out: 863 spin_unlock_irqrestore(&mp->lock, flags); 864} 865 866static irqreturn_t mace_txdma_intr(int irq, void *dev_id) 867{ 868 return IRQ_HANDLED; 869} 870 871static irqreturn_t mace_rxdma_intr(int irq, void *dev_id) 872{ 873 struct net_device *dev = (struct net_device *) dev_id; 874 struct mace_data *mp = (struct mace_data *) dev->priv; 875 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; 876 volatile struct dbdma_cmd *cp, *np; 877 int i, nb, stat, next; 878 struct sk_buff *skb; 879 unsigned frame_status; 880 static int mace_lost_status; 881 unsigned char *data; 882 unsigned long flags; 883 884 spin_lock_irqsave(&mp->lock, flags); 885 for (i = mp->rx_empty; i != mp->rx_fill; ) { 886 cp = mp->rx_cmds + i; 887 stat = ld_le16(&cp->xfer_status); 888 if ((stat & ACTIVE) == 0) { 889 next = i + 1; 890 if (next >= N_RX_RING) 891 next = 0; 892 np = mp->rx_cmds + next; 893 if (next != mp->rx_fill 894 && (ld_le16(&np->xfer_status) & ACTIVE) != 0) { 895 printk(KERN_DEBUG "mace: lost a status word\n"); 896 ++mace_lost_status; 897 } else 898 break; 899 } 900 nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count); 901 out_le16(&cp->command, DBDMA_STOP); 902 /* got a packet, have a look at it */ 903 skb = mp->rx_bufs[i]; 904 if (skb == 0) { 905 ++mp->stats.rx_dropped; 906 } else if (nb > 8) { 907 data = skb->data; 908 frame_status = (data[nb-3] << 8) + data[nb-4]; 909 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) { 910 ++mp->stats.rx_errors; 911 if (frame_status & RS_OFLO) 912 ++mp->stats.rx_over_errors; 913 if (frame_status & RS_FRAMERR) 914 ++mp->stats.rx_frame_errors; 915 if (frame_status & RS_FCSERR) 916 ++mp->stats.rx_crc_errors; 917 } else { 918 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the 919 * FCS on frames with 802.3 headers. This means that Ethernet 920 * frames have 8 extra octets at the end, while 802.3 frames 921 * have only 4. We need to correctly account for this. */ 922 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */ 923 nb -= 4; 924 else /* Ethernet header; mace includes FCS */ 925 nb -= 8; 926 skb_put(skb, nb); 927 skb->protocol = eth_type_trans(skb, dev); 928 mp->stats.rx_bytes += skb->len; 929 netif_rx(skb); 930 dev->last_rx = jiffies; 931 mp->rx_bufs[i] = NULL; 932 ++mp->stats.rx_packets; 933 } 934 } else { 935 ++mp->stats.rx_errors; 936 ++mp->stats.rx_length_errors; 937 } 938 939 /* advance to next */ 940 if (++i >= N_RX_RING) 941 i = 0; 942 } 943 mp->rx_empty = i; 944 945 i = mp->rx_fill; 946 for (;;) { 947 next = i + 1; 948 if (next >= N_RX_RING) 949 next = 0; 950 if (next == mp->rx_empty) 951 break; 952 cp = mp->rx_cmds + i; 953 skb = mp->rx_bufs[i]; 954 if (skb == 0) { 955 skb = dev_alloc_skb(RX_BUFLEN + 2); 956 if (skb != 0) { 957 skb_reserve(skb, 2); 958 mp->rx_bufs[i] = skb; 959 } 960 } 961 st_le16(&cp->req_count, RX_BUFLEN); 962 data = skb? skb->data: dummy_buf; 963 st_le32(&cp->phy_addr, virt_to_bus(data)); 964 out_le16(&cp->xfer_status, 0); 965 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); 966 i = next; 967 } 968 if (i != mp->rx_fill) { 969 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE)); 970 mp->rx_fill = i; 971 } 972 spin_unlock_irqrestore(&mp->lock, flags); 973 return IRQ_HANDLED; 974} 975 976static struct of_device_id mace_match[] = 977{ 978 { 979 .name = "mace", 980 }, 981 {}, 982}; 983MODULE_DEVICE_TABLE (of, mace_match); 984 985static struct macio_driver mace_driver = 986{ 987 .name = "mace", 988 .match_table = mace_match, 989 .probe = mace_probe, 990 .remove = mace_remove, 991}; 992 993 994static int __init mace_init(void) 995{ 996 return macio_register_driver(&mace_driver); 997} 998 999static void __exit mace_cleanup(void) 1000{ 1001 macio_unregister_driver(&mace_driver); 1002 1003 kfree(dummy_buf); 1004 dummy_buf = NULL; 1005} 1006 1007MODULE_AUTHOR("Paul Mackerras"); 1008MODULE_DESCRIPTION("PowerMac MACE driver."); 1009module_param(port_aaui, int, 0); 1010MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)"); 1011MODULE_LICENSE("GPL"); 1012 1013module_init(mace_init); 1014module_exit(mace_cleanup); 1015