1/********************************************************************* 2 * $Id: smsc-ircc2.c,v 1.1.1.1 2007-08-03 18:52:47 $ 3 * 4 * Description: Driver for the SMC Infrared Communications Controller 5 * Status: Experimental. 6 * Author: Daniele Peri (peri@csai.unipa.it) 7 * Created at: 8 * Modified at: 9 * Modified by: 10 * 11 * Copyright (c) 2002 Daniele Peri 12 * All Rights Reserved. 13 * Copyright (c) 2002 Jean Tourrilhes 14 * Copyright (c) 2006 Linus Walleij 15 * 16 * 17 * Based on smc-ircc.c: 18 * 19 * Copyright (c) 2001 Stefani Seibold 20 * Copyright (c) 1999-2001 Dag Brattli 21 * Copyright (c) 1998-1999 Thomas Davis, 22 * 23 * and irport.c: 24 * 25 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved. 26 * 27 * 28 * This program is free software; you can redistribute it and/or 29 * modify it under the terms of the GNU General Public License as 30 * published by the Free Software Foundation; either version 2 of 31 * the License, or (at your option) any later version. 32 * 33 * This program is distributed in the hope that it will be useful, 34 * but WITHOUT ANY WARRANTY; without even the implied warranty of 35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 36 * GNU General Public License for more details. 37 * 38 * You should have received a copy of the GNU General Public License 39 * along with this program; if not, write to the Free Software 40 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 41 * MA 02111-1307 USA 42 * 43 ********************************************************************/ 44 45#include <linux/module.h> 46#include <linux/kernel.h> 47#include <linux/types.h> 48#include <linux/skbuff.h> 49#include <linux/netdevice.h> 50#include <linux/ioport.h> 51#include <linux/delay.h> 52#include <linux/slab.h> 53#include <linux/init.h> 54#include <linux/rtnetlink.h> 55#include <linux/serial_reg.h> 56#include <linux/dma-mapping.h> 57#include <linux/pnp.h> 58#include <linux/platform_device.h> 59 60#include <asm/io.h> 61#include <asm/dma.h> 62#include <asm/byteorder.h> 63 64#include <linux/spinlock.h> 65#include <linux/pm.h> 66#ifdef CONFIG_PCI 67#include <linux/pci.h> 68#endif 69 70#include <net/irda/wrapper.h> 71#include <net/irda/irda.h> 72#include <net/irda/irda_device.h> 73 74#include "smsc-ircc2.h" 75#include "smsc-sio.h" 76 77 78MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>"); 79MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver"); 80MODULE_LICENSE("GPL"); 81 82static int smsc_nopnp = 1; 83module_param_named(nopnp, smsc_nopnp, bool, 0); 84MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 85 86#define DMA_INVAL 255 87static int ircc_dma = DMA_INVAL; 88module_param(ircc_dma, int, 0); 89MODULE_PARM_DESC(ircc_dma, "DMA channel"); 90 91#define IRQ_INVAL 255 92static int ircc_irq = IRQ_INVAL; 93module_param(ircc_irq, int, 0); 94MODULE_PARM_DESC(ircc_irq, "IRQ line"); 95 96static int ircc_fir; 97module_param(ircc_fir, int, 0); 98MODULE_PARM_DESC(ircc_fir, "FIR Base Address"); 99 100static int ircc_sir; 101module_param(ircc_sir, int, 0); 102MODULE_PARM_DESC(ircc_sir, "SIR Base Address"); 103 104static int ircc_cfg; 105module_param(ircc_cfg, int, 0); 106MODULE_PARM_DESC(ircc_cfg, "Configuration register base address"); 107 108static int ircc_transceiver; 109module_param(ircc_transceiver, int, 0); 110MODULE_PARM_DESC(ircc_transceiver, "Transceiver type"); 111 112/* Types */ 113 114#ifdef CONFIG_PCI 115struct smsc_ircc_subsystem_configuration { 116 unsigned short vendor; /* PCI vendor ID */ 117 unsigned short device; /* PCI vendor ID */ 118 unsigned short subvendor; /* PCI subsystem vendor ID */ 119 unsigned short subdevice; /* PCI sybsystem device ID */ 120 unsigned short sir_io; /* I/O port for SIR */ 121 unsigned short fir_io; /* I/O port for FIR */ 122 unsigned char fir_irq; /* FIR IRQ */ 123 unsigned char fir_dma; /* FIR DMA */ 124 unsigned short cfg_base; /* I/O port for chip configuration */ 125 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */ 126 const char *name; /* name shown as info */ 127}; 128#endif 129 130struct smsc_transceiver { 131 char *name; 132 void (*set_for_speed)(int fir_base, u32 speed); 133 int (*probe)(int fir_base); 134}; 135 136struct smsc_chip { 137 char *name; 138 u16 flags; 139 u8 devid; 140 u8 rev; 141}; 142 143struct smsc_chip_address { 144 unsigned int cfg_base; 145 unsigned int type; 146}; 147 148/* Private data for each instance */ 149struct smsc_ircc_cb { 150 struct net_device *netdev; /* Yes! we are some kind of netdevice */ 151 struct net_device_stats stats; 152 struct irlap_cb *irlap; /* The link layer we are binded to */ 153 154 chipio_t io; /* IrDA controller information */ 155 iobuff_t tx_buff; /* Transmit buffer */ 156 iobuff_t rx_buff; /* Receive buffer */ 157 dma_addr_t tx_buff_dma; 158 dma_addr_t rx_buff_dma; 159 160 struct qos_info qos; /* QoS capabilities for this device */ 161 162 spinlock_t lock; /* For serializing operations */ 163 164 __u32 new_speed; 165 __u32 flags; /* Interface flags */ 166 167 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */ 168 int tx_len; /* Number of frames in tx_buff */ 169 170 int transceiver; 171 struct platform_device *pldev; 172}; 173 174/* Constants */ 175 176#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2" 177 178#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600 179#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1 180#define SMSC_IRCC2_C_NET_TIMEOUT 0 181#define SMSC_IRCC2_C_SIR_STOP 0 182 183static const char *driver_name = SMSC_IRCC2_DRIVER_NAME; 184 185/* Prototypes */ 186 187static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq); 188static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base); 189static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq); 190static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self); 191static void smsc_ircc_init_chip(struct smsc_ircc_cb *self); 192static int __exit smsc_ircc_close(struct smsc_ircc_cb *self); 193static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self); 194static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self); 195static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self); 196static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev); 197static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev); 198static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs); 199static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self); 200static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed); 201static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed); 202static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id); 203static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev); 204static void smsc_ircc_sir_start(struct smsc_ircc_cb *self); 205#if SMSC_IRCC2_C_SIR_STOP 206static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self); 207#endif 208static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self); 209static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len); 210static int smsc_ircc_net_open(struct net_device *dev); 211static int smsc_ircc_net_close(struct net_device *dev); 212static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 213#if SMSC_IRCC2_C_NET_TIMEOUT 214static void smsc_ircc_timeout(struct net_device *dev); 215#endif 216static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev); 217static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self); 218static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self); 219static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed); 220static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self); 221 222/* Probing */ 223static int __init smsc_ircc_look_for_chips(void); 224static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type); 225static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type); 226static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type); 227static int __init smsc_superio_fdc(unsigned short cfg_base); 228static int __init smsc_superio_lpc(unsigned short cfg_base); 229#ifdef CONFIG_PCI 230static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf); 231static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); 232static void __init preconfigure_ali_port(struct pci_dev *dev, 233 unsigned short port); 234static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); 235static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, 236 unsigned short ircc_fir, 237 unsigned short ircc_sir, 238 unsigned char ircc_dma, 239 unsigned char ircc_irq); 240#endif 241 242/* Transceivers specific functions */ 243 244static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed); 245static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base); 246static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed); 247static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base); 248static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed); 249static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base); 250 251/* Power Management */ 252 253static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state); 254static int smsc_ircc_resume(struct platform_device *dev); 255 256static struct platform_driver smsc_ircc_driver = { 257 .suspend = smsc_ircc_suspend, 258 .resume = smsc_ircc_resume, 259 .driver = { 260 .name = SMSC_IRCC2_DRIVER_NAME, 261 }, 262}; 263 264/* Transceivers for SMSC-ircc */ 265 266static struct smsc_transceiver smsc_transceivers[] = 267{ 268 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 }, 269 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select }, 270 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc }, 271 { NULL, NULL } 272}; 273#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1) 274 275/* SMC SuperIO chipsets definitions */ 276 277#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */ 278#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */ 279#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */ 280#define SIR 0 /* SuperIO Chip has only slow IRDA */ 281#define FIR 4 /* SuperIO Chip has fast IRDA */ 282#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */ 283 284static struct smsc_chip __initdata fdc_chips_flat[] = 285{ 286 /* Base address 0x3f0 or 0x370 */ 287 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */ 288 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 }, 289 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 }, 290 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 }, 291 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */ 292 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 }, 293 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 }, 294 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 }, 295 { NULL } 296}; 297 298static struct smsc_chip __initdata fdc_chips_paged[] = 299{ 300 /* Base address 0x3f0 or 0x370 */ 301 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 }, 302 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 }, 303 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 }, 304 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 }, 305 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 }, 306 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 }, 307 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 }, 308 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 }, 309 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 }, 310 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 }, 311 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 }, 312 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 }, 313 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 }, 314 { NULL } 315}; 316 317static struct smsc_chip __initdata lpc_chips_flat[] = 318{ 319 /* Base address 0x2E or 0x4E */ 320 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 }, 321 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 }, 322 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 }, 323 { NULL } 324}; 325 326static struct smsc_chip __initdata lpc_chips_paged[] = 327{ 328 /* Base address 0x2E or 0x4E */ 329 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 }, 330 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 }, 331 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, 332 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 }, 333 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, 334 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 }, 335 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 }, 336 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 }, 337 { NULL } 338}; 339 340#define SMSCSIO_TYPE_FDC 1 341#define SMSCSIO_TYPE_LPC 2 342#define SMSCSIO_TYPE_FLAT 4 343#define SMSCSIO_TYPE_PAGED 8 344 345static struct smsc_chip_address __initdata possible_addresses[] = 346{ 347 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 348 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 349 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 350 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 351 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 352 { 0, 0 } 353}; 354 355/* Globals */ 356 357static struct smsc_ircc_cb *dev_self[] = { NULL, NULL }; 358static unsigned short dev_count; 359 360static inline void register_bank(int iobase, int bank) 361{ 362 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), 363 iobase + IRCC_MASTER); 364} 365 366/* PNP hotplug support */ 367static const struct pnp_device_id smsc_ircc_pnp_table[] = { 368 { .id = "SMCf010", .driver_data = 0 }, 369 /* and presumably others */ 370 { } 371}; 372MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table); 373 374static int pnp_driver_registered; 375 376static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev, 377 const struct pnp_device_id *dev_id) 378{ 379 unsigned int firbase, sirbase; 380 u8 dma, irq; 381 382 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) && 383 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0))) 384 return -EINVAL; 385 386 sirbase = pnp_port_start(dev, 0); 387 firbase = pnp_port_start(dev, 1); 388 dma = pnp_dma(dev, 0); 389 irq = pnp_irq(dev, 0); 390 391 if (smsc_ircc_open(firbase, sirbase, dma, irq)) 392 return -ENODEV; 393 394 return 0; 395} 396 397static struct pnp_driver smsc_ircc_pnp_driver = { 398 .name = "smsc-ircc2", 399 .id_table = smsc_ircc_pnp_table, 400 .probe = smsc_ircc_pnp_probe, 401}; 402 403 404/******************************************************************************* 405 * 406 * 407 * SMSC-ircc stuff 408 * 409 * 410 *******************************************************************************/ 411 412static int __init smsc_ircc_legacy_probe(void) 413{ 414 int ret = 0; 415 416#ifdef CONFIG_PCI 417 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) { 418 /* Ignore errors from preconfiguration */ 419 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name); 420 } 421#endif 422 423 if (ircc_fir > 0 && ircc_sir > 0) { 424 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir); 425 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir); 426 427 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq)) 428 ret = -ENODEV; 429 } else { 430 ret = -ENODEV; 431 432 /* try user provided configuration register base address */ 433 if (ircc_cfg > 0) { 434 IRDA_MESSAGE(" Overriding configuration address " 435 "0x%04x\n", ircc_cfg); 436 if (!smsc_superio_fdc(ircc_cfg)) 437 ret = 0; 438 if (!smsc_superio_lpc(ircc_cfg)) 439 ret = 0; 440 } 441 442 if (smsc_ircc_look_for_chips() > 0) 443 ret = 0; 444 } 445 return ret; 446} 447 448/* 449 * Function smsc_ircc_init () 450 * 451 * Initialize chip. Just try to find out how many chips we are dealing with 452 * and where they are 453 */ 454static int __init smsc_ircc_init(void) 455{ 456 int ret; 457 458 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 459 460 ret = platform_driver_register(&smsc_ircc_driver); 461 if (ret) { 462 IRDA_ERROR("%s, Can't register driver!\n", driver_name); 463 return ret; 464 } 465 466 dev_count = 0; 467 468 if (smsc_nopnp || !pnp_platform_devices || 469 ircc_cfg || ircc_fir || ircc_sir || 470 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) { 471 ret = smsc_ircc_legacy_probe(); 472 } else { 473 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0) 474 pnp_driver_registered = 1; 475 } 476 477 if (ret) { 478 if (pnp_driver_registered) 479 pnp_unregister_driver(&smsc_ircc_pnp_driver); 480 platform_driver_unregister(&smsc_ircc_driver); 481 } 482 483 return ret; 484} 485 486/* 487 * Function smsc_ircc_open (firbase, sirbase, dma, irq) 488 * 489 * Try to open driver instance 490 * 491 */ 492static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq) 493{ 494 struct smsc_ircc_cb *self; 495 struct net_device *dev; 496 int err; 497 498 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 499 500 err = smsc_ircc_present(fir_base, sir_base); 501 if (err) 502 goto err_out; 503 504 err = -ENOMEM; 505 if (dev_count >= ARRAY_SIZE(dev_self)) { 506 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__); 507 goto err_out1; 508 } 509 510 /* 511 * Allocate new instance of the driver 512 */ 513 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb)); 514 if (!dev) { 515 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__); 516 goto err_out1; 517 } 518 519 SET_MODULE_OWNER(dev); 520 521 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir; 522#if SMSC_IRCC2_C_NET_TIMEOUT 523 dev->tx_timeout = smsc_ircc_timeout; 524 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */ 525#endif 526 dev->open = smsc_ircc_net_open; 527 dev->stop = smsc_ircc_net_close; 528 dev->do_ioctl = smsc_ircc_net_ioctl; 529 dev->get_stats = smsc_ircc_net_get_stats; 530 531 self = netdev_priv(dev); 532 self->netdev = dev; 533 534 /* Make ifconfig display some details */ 535 dev->base_addr = self->io.fir_base = fir_base; 536 dev->irq = self->io.irq = irq; 537 538 /* Need to store self somewhere */ 539 dev_self[dev_count] = self; 540 spin_lock_init(&self->lock); 541 542 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE; 543 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE; 544 545 self->rx_buff.head = 546 dma_alloc_coherent(NULL, self->rx_buff.truesize, 547 &self->rx_buff_dma, GFP_KERNEL); 548 if (self->rx_buff.head == NULL) { 549 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n", 550 driver_name); 551 goto err_out2; 552 } 553 554 self->tx_buff.head = 555 dma_alloc_coherent(NULL, self->tx_buff.truesize, 556 &self->tx_buff_dma, GFP_KERNEL); 557 if (self->tx_buff.head == NULL) { 558 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n", 559 driver_name); 560 goto err_out3; 561 } 562 563 memset(self->rx_buff.head, 0, self->rx_buff.truesize); 564 memset(self->tx_buff.head, 0, self->tx_buff.truesize); 565 566 self->rx_buff.in_frame = FALSE; 567 self->rx_buff.state = OUTSIDE_FRAME; 568 self->tx_buff.data = self->tx_buff.head; 569 self->rx_buff.data = self->rx_buff.head; 570 571 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq); 572 smsc_ircc_setup_qos(self); 573 smsc_ircc_init_chip(self); 574 575 if (ircc_transceiver > 0 && 576 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS) 577 self->transceiver = ircc_transceiver; 578 else 579 smsc_ircc_probe_transceiver(self); 580 581 err = register_netdev(self->netdev); 582 if (err) { 583 IRDA_ERROR("%s, Network device registration failed!\n", 584 driver_name); 585 goto err_out4; 586 } 587 588 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME, 589 dev_count, NULL, 0); 590 if (IS_ERR(self->pldev)) { 591 err = PTR_ERR(self->pldev); 592 goto err_out5; 593 } 594 platform_set_drvdata(self->pldev, self); 595 596 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); 597 dev_count++; 598 599 return 0; 600 601 err_out5: 602 unregister_netdev(self->netdev); 603 604 err_out4: 605 dma_free_coherent(NULL, self->tx_buff.truesize, 606 self->tx_buff.head, self->tx_buff_dma); 607 err_out3: 608 dma_free_coherent(NULL, self->rx_buff.truesize, 609 self->rx_buff.head, self->rx_buff_dma); 610 err_out2: 611 free_netdev(self->netdev); 612 dev_self[dev_count] = NULL; 613 err_out1: 614 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); 615 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); 616 err_out: 617 return err; 618} 619 620/* 621 * Function smsc_ircc_present(fir_base, sir_base) 622 * 623 * Check the smsc-ircc chip presence 624 * 625 */ 626static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base) 627{ 628 unsigned char low, high, chip, config, dma, irq, version; 629 630 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT, 631 driver_name)) { 632 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n", 633 __FUNCTION__, fir_base); 634 goto out1; 635 } 636 637 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT, 638 driver_name)) { 639 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n", 640 __FUNCTION__, sir_base); 641 goto out2; 642 } 643 644 register_bank(fir_base, 3); 645 646 high = inb(fir_base + IRCC_ID_HIGH); 647 low = inb(fir_base + IRCC_ID_LOW); 648 chip = inb(fir_base + IRCC_CHIP_ID); 649 version = inb(fir_base + IRCC_VERSION); 650 config = inb(fir_base + IRCC_INTERFACE); 651 dma = config & IRCC_INTERFACE_DMA_MASK; 652 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; 653 654 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) { 655 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n", 656 __FUNCTION__, fir_base); 657 goto out3; 658 } 659 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, " 660 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n", 661 chip & 0x0f, version, fir_base, sir_base, dma, irq); 662 663 return 0; 664 665 out3: 666 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); 667 out2: 668 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); 669 out1: 670 return -ENODEV; 671} 672 673/* 674 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq) 675 * 676 * Setup I/O 677 * 678 */ 679static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, 680 unsigned int fir_base, unsigned int sir_base, 681 u8 dma, u8 irq) 682{ 683 unsigned char config, chip_dma, chip_irq; 684 685 register_bank(fir_base, 3); 686 config = inb(fir_base + IRCC_INTERFACE); 687 chip_dma = config & IRCC_INTERFACE_DMA_MASK; 688 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; 689 690 self->io.fir_base = fir_base; 691 self->io.sir_base = sir_base; 692 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT; 693 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT; 694 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE; 695 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED; 696 697 if (irq != IRQ_INVAL) { 698 if (irq != chip_irq) 699 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n", 700 driver_name, chip_irq, irq); 701 self->io.irq = irq; 702 } else 703 self->io.irq = chip_irq; 704 705 if (dma != DMA_INVAL) { 706 if (dma != chip_dma) 707 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n", 708 driver_name, chip_dma, dma); 709 self->io.dma = dma; 710 } else 711 self->io.dma = chip_dma; 712 713} 714 715/* 716 * Function smsc_ircc_setup_qos(self) 717 * 718 * Setup qos 719 * 720 */ 721static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self) 722{ 723 /* Initialize QoS for this device */ 724 irda_init_max_qos_capabilies(&self->qos); 725 726 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| 727 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); 728 729 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME; 730 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE; 731 irda_qos_bits_to_value(&self->qos); 732} 733 734/* 735 * Function smsc_ircc_init_chip(self) 736 * 737 * Init chip 738 * 739 */ 740static void smsc_ircc_init_chip(struct smsc_ircc_cb *self) 741{ 742 int iobase = self->io.fir_base; 743 744 register_bank(iobase, 0); 745 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); 746 outb(0x00, iobase + IRCC_MASTER); 747 748 register_bank(iobase, 1); 749 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), 750 iobase + IRCC_SCE_CFGA); 751 752#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */ 753 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), 754 iobase + IRCC_SCE_CFGB); 755#else 756 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), 757 iobase + IRCC_SCE_CFGB); 758#endif 759 (void) inb(iobase + IRCC_FIFO_THRESHOLD); 760 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); 761 762 register_bank(iobase, 4); 763 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); 764 765 register_bank(iobase, 0); 766 outb(0, iobase + IRCC_LCR_A); 767 768 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); 769 770 /* Power on device */ 771 outb(0x00, iobase + IRCC_MASTER); 772} 773 774/* 775 * Function smsc_ircc_net_ioctl (dev, rq, cmd) 776 * 777 * Process IOCTL commands for this device 778 * 779 */ 780static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 781{ 782 struct if_irda_req *irq = (struct if_irda_req *) rq; 783 struct smsc_ircc_cb *self; 784 unsigned long flags; 785 int ret = 0; 786 787 IRDA_ASSERT(dev != NULL, return -1;); 788 789 self = netdev_priv(dev); 790 791 IRDA_ASSERT(self != NULL, return -1;); 792 793 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd); 794 795 switch (cmd) { 796 case SIOCSBANDWIDTH: /* Set bandwidth */ 797 if (!capable(CAP_NET_ADMIN)) 798 ret = -EPERM; 799 else { 800 /* Make sure we are the only one touching 801 * self->io.speed and the hardware - Jean II */ 802 spin_lock_irqsave(&self->lock, flags); 803 smsc_ircc_change_speed(self, irq->ifr_baudrate); 804 spin_unlock_irqrestore(&self->lock, flags); 805 } 806 break; 807 case SIOCSMEDIABUSY: /* Set media busy */ 808 if (!capable(CAP_NET_ADMIN)) { 809 ret = -EPERM; 810 break; 811 } 812 813 irda_device_set_media_busy(self->netdev, TRUE); 814 break; 815 case SIOCGRECEIVING: /* Check if we are receiving right now */ 816 irq->ifr_receiving = smsc_ircc_is_receiving(self); 817 break; 818 default: 819 ret = -EOPNOTSUPP; 820 } 821 822 return ret; 823} 824 825static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev) 826{ 827 struct smsc_ircc_cb *self = netdev_priv(dev); 828 829 return &self->stats; 830} 831 832#if SMSC_IRCC2_C_NET_TIMEOUT 833/* 834 * Function smsc_ircc_timeout (struct net_device *dev) 835 * 836 * The networking timeout management. 837 * 838 */ 839 840static void smsc_ircc_timeout(struct net_device *dev) 841{ 842 struct smsc_ircc_cb *self = netdev_priv(dev); 843 unsigned long flags; 844 845 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n", 846 dev->name, self->io.speed); 847 spin_lock_irqsave(&self->lock, flags); 848 smsc_ircc_sir_start(self); 849 smsc_ircc_change_speed(self, self->io.speed); 850 dev->trans_start = jiffies; 851 netif_wake_queue(dev); 852 spin_unlock_irqrestore(&self->lock, flags); 853} 854#endif 855 856/* 857 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev) 858 * 859 * Transmits the current frame until FIFO is full, then 860 * waits until the next transmit interrupt, and continues until the 861 * frame is transmitted. 862 */ 863int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev) 864{ 865 struct smsc_ircc_cb *self; 866 unsigned long flags; 867 s32 speed; 868 869 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 870 871 IRDA_ASSERT(dev != NULL, return 0;); 872 873 self = netdev_priv(dev); 874 IRDA_ASSERT(self != NULL, return 0;); 875 876 netif_stop_queue(dev); 877 878 /* Make sure test of self->io.speed & speed change are atomic */ 879 spin_lock_irqsave(&self->lock, flags); 880 881 /* Check if we need to change the speed */ 882 speed = irda_get_next_speed(skb); 883 if (speed != self->io.speed && speed != -1) { 884 /* Check for empty frame */ 885 if (!skb->len) { 886 /* 887 * We send frames one by one in SIR mode (no 888 * pipelining), so at this point, if we were sending 889 * a previous frame, we just received the interrupt 890 * telling us it is finished (UART_IIR_THRI). 891 * Therefore, waiting for the transmitter to really 892 * finish draining the fifo won't take too long. 893 * And the interrupt handler is not expected to run. 894 * - Jean II */ 895 smsc_ircc_sir_wait_hw_transmitter_finish(self); 896 smsc_ircc_change_speed(self, speed); 897 spin_unlock_irqrestore(&self->lock, flags); 898 dev_kfree_skb(skb); 899 return 0; 900 } 901 self->new_speed = speed; 902 } 903 904 /* Init tx buffer */ 905 self->tx_buff.data = self->tx_buff.head; 906 907 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */ 908 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, 909 self->tx_buff.truesize); 910 911 self->stats.tx_bytes += self->tx_buff.len; 912 913 /* Turn on transmit finished interrupt. Will fire immediately! */ 914 outb(UART_IER_THRI, self->io.sir_base + UART_IER); 915 916 spin_unlock_irqrestore(&self->lock, flags); 917 918 dev_kfree_skb(skb); 919 920 return 0; 921} 922 923/* 924 * Function smsc_ircc_set_fir_speed (self, baud) 925 * 926 * Change the speed of the device 927 * 928 */ 929static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed) 930{ 931 int fir_base, ir_mode, ctrl, fast; 932 933 IRDA_ASSERT(self != NULL, return;); 934 fir_base = self->io.fir_base; 935 936 self->io.speed = speed; 937 938 switch (speed) { 939 default: 940 case 576000: 941 ir_mode = IRCC_CFGA_IRDA_HDLC; 942 ctrl = IRCC_CRC; 943 fast = 0; 944 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__); 945 break; 946 case 1152000: 947 ir_mode = IRCC_CFGA_IRDA_HDLC; 948 ctrl = IRCC_1152 | IRCC_CRC; 949 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA; 950 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", 951 __FUNCTION__); 952 break; 953 case 4000000: 954 ir_mode = IRCC_CFGA_IRDA_4PPM; 955 ctrl = IRCC_CRC; 956 fast = IRCC_LCR_A_FAST; 957 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", 958 __FUNCTION__); 959 break; 960 } 961 962 register_bank(fir_base, 1); 963 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA); 964 965 register_bank(fir_base, 4); 966 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); 967} 968 969/* 970 * Function smsc_ircc_fir_start(self) 971 * 972 * Change the speed of the device 973 * 974 */ 975static void smsc_ircc_fir_start(struct smsc_ircc_cb *self) 976{ 977 struct net_device *dev; 978 int fir_base; 979 980 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 981 982 IRDA_ASSERT(self != NULL, return;); 983 dev = self->netdev; 984 IRDA_ASSERT(dev != NULL, return;); 985 986 fir_base = self->io.fir_base; 987 988 /* Reset everything */ 989 990 /* Install FIR transmit handler */ 991 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir; 992 993 /* Clear FIFO */ 994 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); 995 996 /* Enable interrupt */ 997 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/ 998 999 register_bank(fir_base, 1); 1000 1001 /* Select the TX/RX interface */ 1002#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */ 1003 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), 1004 fir_base + IRCC_SCE_CFGB); 1005#else 1006 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), 1007 fir_base + IRCC_SCE_CFGB); 1008#endif 1009 (void) inb(fir_base + IRCC_FIFO_THRESHOLD); 1010 1011 /* Enable SCE interrupts */ 1012 outb(0, fir_base + IRCC_MASTER); 1013 register_bank(fir_base, 0); 1014 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER); 1015 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER); 1016} 1017 1018/* 1019 * Function smsc_ircc_fir_stop(self, baud) 1020 * 1021 * Change the speed of the device 1022 * 1023 */ 1024static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self) 1025{ 1026 int fir_base; 1027 1028 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1029 1030 IRDA_ASSERT(self != NULL, return;); 1031 1032 fir_base = self->io.fir_base; 1033 register_bank(fir_base, 0); 1034 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/ 1035 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); 1036} 1037 1038 1039/* 1040 * Function smsc_ircc_change_speed(self, baud) 1041 * 1042 * Change the speed of the device 1043 * 1044 * This function *must* be called with spinlock held, because it may 1045 * be called from the irq handler. - Jean II 1046 */ 1047static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed) 1048{ 1049 struct net_device *dev; 1050 int last_speed_was_sir; 1051 1052 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed); 1053 1054 IRDA_ASSERT(self != NULL, return;); 1055 dev = self->netdev; 1056 1057 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED; 1058 1059 1060 if (self->io.speed == 0) 1061 smsc_ircc_sir_start(self); 1062 1063 1064 if (self->io.speed != speed) 1065 smsc_ircc_set_transceiver_for_speed(self, speed); 1066 1067 self->io.speed = speed; 1068 1069 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) { 1070 if (!last_speed_was_sir) { 1071 smsc_ircc_fir_stop(self); 1072 smsc_ircc_sir_start(self); 1073 } 1074 smsc_ircc_set_sir_speed(self, speed); 1075 } else { 1076 if (last_speed_was_sir) { 1077 #if SMSC_IRCC2_C_SIR_STOP 1078 smsc_ircc_sir_stop(self); 1079 #endif 1080 smsc_ircc_fir_start(self); 1081 } 1082 smsc_ircc_set_fir_speed(self, speed); 1083 1084 /* Be ready for incoming frames */ 1085 smsc_ircc_dma_receive(self); 1086 } 1087 1088 netif_wake_queue(dev); 1089} 1090 1091/* 1092 * Function smsc_ircc_set_sir_speed (self, speed) 1093 * 1094 * Set speed of IrDA port to specified baudrate 1095 * 1096 */ 1097void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed) 1098{ 1099 int iobase; 1100 int fcr; /* FIFO control reg */ 1101 int lcr; /* Line control reg */ 1102 int divisor; 1103 1104 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed); 1105 1106 IRDA_ASSERT(self != NULL, return;); 1107 iobase = self->io.sir_base; 1108 1109 /* Update accounting for new speed */ 1110 self->io.speed = speed; 1111 1112 /* Turn off interrupts */ 1113 outb(0, iobase + UART_IER); 1114 1115 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed; 1116 1117 fcr = UART_FCR_ENABLE_FIFO; 1118 1119 /* 1120 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and 1121 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget 1122 * about this timeout since it will always be fast enough. 1123 */ 1124 fcr |= self->io.speed < 38400 ? 1125 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; 1126 1127 /* IrDA ports use 8N1 */ 1128 lcr = UART_LCR_WLEN8; 1129 1130 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ 1131 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ 1132 outb(divisor >> 8, iobase + UART_DLM); 1133 outb(lcr, iobase + UART_LCR); /* Set 8N1 */ 1134 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ 1135 1136 /* Turn on interrups */ 1137 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); 1138 1139 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed); 1140} 1141 1142 1143/* 1144 * Function smsc_ircc_hard_xmit_fir (skb, dev) 1145 * 1146 * Transmit the frame! 1147 * 1148 */ 1149static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev) 1150{ 1151 struct smsc_ircc_cb *self; 1152 unsigned long flags; 1153 s32 speed; 1154 int mtt; 1155 1156 IRDA_ASSERT(dev != NULL, return 0;); 1157 self = netdev_priv(dev); 1158 IRDA_ASSERT(self != NULL, return 0;); 1159 1160 netif_stop_queue(dev); 1161 1162 /* Make sure test of self->io.speed & speed change are atomic */ 1163 spin_lock_irqsave(&self->lock, flags); 1164 1165 /* Check if we need to change the speed after this frame */ 1166 speed = irda_get_next_speed(skb); 1167 if (speed != self->io.speed && speed != -1) { 1168 /* Check for empty frame */ 1169 if (!skb->len) { 1170 /* Note : you should make sure that speed changes 1171 * are not going to corrupt any outgoing frame. 1172 * Look at nsc-ircc for the gory details - Jean II */ 1173 smsc_ircc_change_speed(self, speed); 1174 spin_unlock_irqrestore(&self->lock, flags); 1175 dev_kfree_skb(skb); 1176 return 0; 1177 } 1178 1179 self->new_speed = speed; 1180 } 1181 1182 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len); 1183 1184 self->tx_buff.len = skb->len; 1185 self->tx_buff.data = self->tx_buff.head; 1186 1187 mtt = irda_get_mtt(skb); 1188 if (mtt) { 1189 int bofs; 1190 1191 /* 1192 * Compute how many BOFs (STA or PA's) we need to waste the 1193 * min turn time given the speed of the link. 1194 */ 1195 bofs = mtt * (self->io.speed / 1000) / 8000; 1196 if (bofs > 4095) 1197 bofs = 4095; 1198 1199 smsc_ircc_dma_xmit(self, bofs); 1200 } else { 1201 /* Transmit frame */ 1202 smsc_ircc_dma_xmit(self, 0); 1203 } 1204 1205 spin_unlock_irqrestore(&self->lock, flags); 1206 dev_kfree_skb(skb); 1207 1208 return 0; 1209} 1210 1211/* 1212 * Function smsc_ircc_dma_xmit (self, bofs) 1213 * 1214 * Transmit data using DMA 1215 * 1216 */ 1217static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs) 1218{ 1219 int iobase = self->io.fir_base; 1220 u8 ctrl; 1221 1222 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1223 /* Disable Rx */ 1224 register_bank(iobase, 0); 1225 outb(0x00, iobase + IRCC_LCR_B); 1226 register_bank(iobase, 1); 1227 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1228 iobase + IRCC_SCE_CFGB); 1229 1230 self->io.direction = IO_XMIT; 1231 1232 /* Set BOF additional count for generating the min turn time */ 1233 register_bank(iobase, 4); 1234 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); 1235 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; 1236 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); 1237 1238 /* Set max Tx frame size */ 1239 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); 1240 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); 1241 1242 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/ 1243 1244 /* Enable burst mode chip Tx DMA */ 1245 register_bank(iobase, 1); 1246 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | 1247 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); 1248 1249 /* Setup DMA controller (must be done after enabling chip DMA) */ 1250 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, 1251 DMA_TX_MODE); 1252 1253 /* Enable interrupt */ 1254 1255 register_bank(iobase, 0); 1256 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1257 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); 1258 1259 /* Enable transmit */ 1260 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); 1261} 1262 1263/* 1264 * Function smsc_ircc_dma_xmit_complete (self) 1265 * 1266 * The transfer of a frame in finished. This function will only be called 1267 * by the interrupt handler 1268 * 1269 */ 1270static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self) 1271{ 1272 int iobase = self->io.fir_base; 1273 1274 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1275 register_bank(iobase, 1); 1276 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1277 iobase + IRCC_SCE_CFGB); 1278 1279 /* Check for underrun! */ 1280 register_bank(iobase, 0); 1281 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { 1282 self->stats.tx_errors++; 1283 self->stats.tx_fifo_errors++; 1284 1285 /* Reset error condition */ 1286 register_bank(iobase, 0); 1287 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); 1288 outb(0x00, iobase + IRCC_MASTER); 1289 } else { 1290 self->stats.tx_packets++; 1291 self->stats.tx_bytes += self->tx_buff.len; 1292 } 1293 1294 /* Check if it's time to change the speed */ 1295 if (self->new_speed) { 1296 smsc_ircc_change_speed(self, self->new_speed); 1297 self->new_speed = 0; 1298 } 1299 1300 netif_wake_queue(self->netdev); 1301} 1302 1303/* 1304 * Function smsc_ircc_dma_receive(self) 1305 * 1306 * Get ready for receiving a frame. The device will initiate a DMA 1307 * if it starts to receive a frame. 1308 * 1309 */ 1310static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self) 1311{ 1312 int iobase = self->io.fir_base; 1313 1314 /* Disable Tx */ 1315 register_bank(iobase, 0); 1316 outb(0x00, iobase + IRCC_LCR_B); 1317 1318 /* Turn off chip DMA */ 1319 register_bank(iobase, 1); 1320 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1321 iobase + IRCC_SCE_CFGB); 1322 1323 self->io.direction = IO_RECV; 1324 self->rx_buff.data = self->rx_buff.head; 1325 1326 /* Set max Rx frame size */ 1327 register_bank(iobase, 4); 1328 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); 1329 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); 1330 1331 /* Setup DMA controller */ 1332 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, 1333 DMA_RX_MODE); 1334 1335 /* Enable burst mode chip Rx DMA */ 1336 register_bank(iobase, 1); 1337 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | 1338 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); 1339 1340 /* Enable interrupt */ 1341 register_bank(iobase, 0); 1342 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1343 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); 1344 1345 /* Enable receiver */ 1346 register_bank(iobase, 0); 1347 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE, 1348 iobase + IRCC_LCR_B); 1349 1350 return 0; 1351} 1352 1353/* 1354 * Function smsc_ircc_dma_receive_complete(self) 1355 * 1356 * Finished with receiving frames 1357 * 1358 */ 1359static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self) 1360{ 1361 struct sk_buff *skb; 1362 int len, msgcnt, lsr; 1363 int iobase = self->io.fir_base; 1364 1365 register_bank(iobase, 0); 1366 1367 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1368 register_bank(iobase, 0); 1369 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); 1370 lsr= inb(iobase + IRCC_LSR); 1371 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; 1372 1373 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__, 1374 get_dma_residue(self->io.dma)); 1375 1376 len = self->rx_buff.truesize - get_dma_residue(self->io.dma); 1377 1378 /* Look for errors */ 1379 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) { 1380 self->stats.rx_errors++; 1381 if (lsr & IRCC_LSR_FRAME_ERROR) 1382 self->stats.rx_frame_errors++; 1383 if (lsr & IRCC_LSR_CRC_ERROR) 1384 self->stats.rx_crc_errors++; 1385 if (lsr & IRCC_LSR_SIZE_ERROR) 1386 self->stats.rx_length_errors++; 1387 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) 1388 self->stats.rx_length_errors++; 1389 return; 1390 } 1391 1392 /* Remove CRC */ 1393 len -= self->io.speed < 4000000 ? 2 : 4; 1394 1395 if (len < 2 || len > 2050) { 1396 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len); 1397 return; 1398 } 1399 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len); 1400 1401 skb = dev_alloc_skb(len + 1); 1402 if (!skb) { 1403 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n", 1404 __FUNCTION__); 1405 return; 1406 } 1407 /* Make sure IP header gets aligned */ 1408 skb_reserve(skb, 1); 1409 1410 memcpy(skb_put(skb, len), self->rx_buff.data, len); 1411 self->stats.rx_packets++; 1412 self->stats.rx_bytes += len; 1413 1414 skb->dev = self->netdev; 1415 skb_reset_mac_header(skb); 1416 skb->protocol = htons(ETH_P_IRDA); 1417 netif_rx(skb); 1418} 1419 1420/* 1421 * Function smsc_ircc_sir_receive (self) 1422 * 1423 * Receive one frame from the infrared port 1424 * 1425 */ 1426static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self) 1427{ 1428 int boguscount = 0; 1429 int iobase; 1430 1431 IRDA_ASSERT(self != NULL, return;); 1432 1433 iobase = self->io.sir_base; 1434 1435 /* 1436 * Receive all characters in Rx FIFO, unwrap and unstuff them. 1437 * async_unwrap_char will deliver all found frames 1438 */ 1439 do { 1440 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff, 1441 inb(iobase + UART_RX)); 1442 1443 /* Make sure we don't stay here to long */ 1444 if (boguscount++ > 32) { 1445 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__); 1446 break; 1447 } 1448 } while (inb(iobase + UART_LSR) & UART_LSR_DR); 1449} 1450 1451 1452/* 1453 * Function smsc_ircc_interrupt (irq, dev_id, regs) 1454 * 1455 * An interrupt from the chip has arrived. Time to do some work 1456 * 1457 */ 1458static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id) 1459{ 1460 struct net_device *dev = (struct net_device *) dev_id; 1461 struct smsc_ircc_cb *self; 1462 int iobase, iir, lcra, lsr; 1463 irqreturn_t ret = IRQ_NONE; 1464 1465 if (dev == NULL) { 1466 printk(KERN_WARNING "%s: irq %d for unknown device.\n", 1467 driver_name, irq); 1468 goto irq_ret; 1469 } 1470 1471 self = netdev_priv(dev); 1472 IRDA_ASSERT(self != NULL, return IRQ_NONE;); 1473 1474 /* Serialise the interrupt handler in various CPUs, stop Tx path */ 1475 spin_lock(&self->lock); 1476 1477 /* Check if we should use the SIR interrupt handler */ 1478 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) { 1479 ret = smsc_ircc_interrupt_sir(dev); 1480 goto irq_ret_unlock; 1481 } 1482 1483 iobase = self->io.fir_base; 1484 1485 register_bank(iobase, 0); 1486 iir = inb(iobase + IRCC_IIR); 1487 if (iir == 0) 1488 goto irq_ret_unlock; 1489 ret = IRQ_HANDLED; 1490 1491 /* Disable interrupts */ 1492 outb(0, iobase + IRCC_IER); 1493 lcra = inb(iobase + IRCC_LCR_A); 1494 lsr = inb(iobase + IRCC_LSR); 1495 1496 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir); 1497 1498 if (iir & IRCC_IIR_EOM) { 1499 if (self->io.direction == IO_RECV) 1500 smsc_ircc_dma_receive_complete(self); 1501 else 1502 smsc_ircc_dma_xmit_complete(self); 1503 1504 smsc_ircc_dma_receive(self); 1505 } 1506 1507 if (iir & IRCC_IIR_ACTIVE_FRAME) { 1508 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/ 1509 } 1510 1511 /* Enable interrupts again */ 1512 1513 register_bank(iobase, 0); 1514 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1515 1516 irq_ret_unlock: 1517 spin_unlock(&self->lock); 1518 irq_ret: 1519 return ret; 1520} 1521 1522/* 1523 * Function irport_interrupt_sir (irq, dev_id) 1524 * 1525 * Interrupt handler for SIR modes 1526 */ 1527static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev) 1528{ 1529 struct smsc_ircc_cb *self = netdev_priv(dev); 1530 int boguscount = 0; 1531 int iobase; 1532 int iir, lsr; 1533 1534 /* Already locked comming here in smsc_ircc_interrupt() */ 1535 /*spin_lock(&self->lock);*/ 1536 1537 iobase = self->io.sir_base; 1538 1539 iir = inb(iobase + UART_IIR) & UART_IIR_ID; 1540 if (iir == 0) 1541 return IRQ_NONE; 1542 while (iir) { 1543 /* Clear interrupt */ 1544 lsr = inb(iobase + UART_LSR); 1545 1546 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", 1547 __FUNCTION__, iir, lsr, iobase); 1548 1549 switch (iir) { 1550 case UART_IIR_RLSI: 1551 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__); 1552 break; 1553 case UART_IIR_RDI: 1554 /* Receive interrupt */ 1555 smsc_ircc_sir_receive(self); 1556 break; 1557 case UART_IIR_THRI: 1558 if (lsr & UART_LSR_THRE) 1559 /* Transmitter ready for data */ 1560 smsc_ircc_sir_write_wakeup(self); 1561 break; 1562 default: 1563 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n", 1564 __FUNCTION__, iir); 1565 break; 1566 } 1567 1568 /* Make sure we don't stay here to long */ 1569 if (boguscount++ > 100) 1570 break; 1571 1572 iir = inb(iobase + UART_IIR) & UART_IIR_ID; 1573 } 1574 /*spin_unlock(&self->lock);*/ 1575 return IRQ_HANDLED; 1576} 1577 1578 1579 1580static int smsc_ircc_request_irq(struct smsc_ircc_cb *self) 1581{ 1582 int error; 1583 1584 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0, 1585 self->netdev->name, self->netdev); 1586 if (error) 1587 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n", 1588 __FUNCTION__, self->io.irq, error); 1589 1590 return error; 1591} 1592 1593static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self) 1594{ 1595 unsigned long flags; 1596 1597 spin_lock_irqsave(&self->lock, flags); 1598 1599 self->io.speed = 0; 1600 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); 1601 1602 spin_unlock_irqrestore(&self->lock, flags); 1603} 1604 1605static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self) 1606{ 1607 int iobase = self->io.fir_base; 1608 unsigned long flags; 1609 1610 spin_lock_irqsave(&self->lock, flags); 1611 1612 register_bank(iobase, 0); 1613 outb(0, iobase + IRCC_IER); 1614 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); 1615 outb(0x00, iobase + IRCC_MASTER); 1616 1617 spin_unlock_irqrestore(&self->lock, flags); 1618} 1619 1620 1621/* 1622 * Function smsc_ircc_net_open (dev) 1623 * 1624 * Start the device 1625 * 1626 */ 1627static int smsc_ircc_net_open(struct net_device *dev) 1628{ 1629 struct smsc_ircc_cb *self; 1630 char hwname[16]; 1631 1632 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1633 1634 IRDA_ASSERT(dev != NULL, return -1;); 1635 self = netdev_priv(dev); 1636 IRDA_ASSERT(self != NULL, return 0;); 1637 1638 if (self->io.suspended) { 1639 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__); 1640 return -EAGAIN; 1641 } 1642 1643 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name, 1644 (void *) dev)) { 1645 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n", 1646 __FUNCTION__, self->io.irq); 1647 return -EAGAIN; 1648 } 1649 1650 smsc_ircc_start_interrupts(self); 1651 1652 /* Give self a hardware name */ 1653 /* It would be cool to offer the chip revision here - Jean II */ 1654 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base); 1655 1656 /* 1657 * Open new IrLAP layer instance, now that everything should be 1658 * initialized properly 1659 */ 1660 self->irlap = irlap_open(dev, &self->qos, hwname); 1661 1662 /* 1663 * Always allocate the DMA channel after the IRQ, 1664 * and clean up on failure. 1665 */ 1666 if (request_dma(self->io.dma, dev->name)) { 1667 smsc_ircc_net_close(dev); 1668 1669 IRDA_WARNING("%s(), unable to allocate DMA=%d\n", 1670 __FUNCTION__, self->io.dma); 1671 return -EAGAIN; 1672 } 1673 1674 netif_start_queue(dev); 1675 1676 return 0; 1677} 1678 1679/* 1680 * Function smsc_ircc_net_close (dev) 1681 * 1682 * Stop the device 1683 * 1684 */ 1685static int smsc_ircc_net_close(struct net_device *dev) 1686{ 1687 struct smsc_ircc_cb *self; 1688 1689 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1690 1691 IRDA_ASSERT(dev != NULL, return -1;); 1692 self = netdev_priv(dev); 1693 IRDA_ASSERT(self != NULL, return 0;); 1694 1695 /* Stop device */ 1696 netif_stop_queue(dev); 1697 1698 /* Stop and remove instance of IrLAP */ 1699 if (self->irlap) 1700 irlap_close(self->irlap); 1701 self->irlap = NULL; 1702 1703 smsc_ircc_stop_interrupts(self); 1704 1705 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */ 1706 if (!self->io.suspended) 1707 free_irq(self->io.irq, dev); 1708 1709 disable_dma(self->io.dma); 1710 free_dma(self->io.dma); 1711 1712 return 0; 1713} 1714 1715static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state) 1716{ 1717 struct smsc_ircc_cb *self = platform_get_drvdata(dev); 1718 1719 if (!self->io.suspended) { 1720 IRDA_DEBUG(1, "%s, Suspending\n", driver_name); 1721 1722 rtnl_lock(); 1723 if (netif_running(self->netdev)) { 1724 netif_device_detach(self->netdev); 1725 smsc_ircc_stop_interrupts(self); 1726 free_irq(self->io.irq, self->netdev); 1727 disable_dma(self->io.dma); 1728 } 1729 self->io.suspended = 1; 1730 rtnl_unlock(); 1731 } 1732 1733 return 0; 1734} 1735 1736static int smsc_ircc_resume(struct platform_device *dev) 1737{ 1738 struct smsc_ircc_cb *self = platform_get_drvdata(dev); 1739 1740 if (self->io.suspended) { 1741 IRDA_DEBUG(1, "%s, Waking up\n", driver_name); 1742 1743 rtnl_lock(); 1744 smsc_ircc_init_chip(self); 1745 if (netif_running(self->netdev)) { 1746 if (smsc_ircc_request_irq(self)) { 1747 /* 1748 * Don't fail resume process, just kill this 1749 * network interface 1750 */ 1751 unregister_netdevice(self->netdev); 1752 } else { 1753 enable_dma(self->io.dma); 1754 smsc_ircc_start_interrupts(self); 1755 netif_device_attach(self->netdev); 1756 } 1757 } 1758 self->io.suspended = 0; 1759 rtnl_unlock(); 1760 } 1761 return 0; 1762} 1763 1764/* 1765 * Function smsc_ircc_close (self) 1766 * 1767 * Close driver instance 1768 * 1769 */ 1770static int __exit smsc_ircc_close(struct smsc_ircc_cb *self) 1771{ 1772 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1773 1774 IRDA_ASSERT(self != NULL, return -1;); 1775 1776 platform_device_unregister(self->pldev); 1777 1778 /* Remove netdevice */ 1779 unregister_netdev(self->netdev); 1780 1781 smsc_ircc_stop_interrupts(self); 1782 1783 /* Release the PORTS that this driver is using */ 1784 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__, 1785 self->io.fir_base); 1786 1787 release_region(self->io.fir_base, self->io.fir_ext); 1788 1789 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__, 1790 self->io.sir_base); 1791 1792 release_region(self->io.sir_base, self->io.sir_ext); 1793 1794 if (self->tx_buff.head) 1795 dma_free_coherent(NULL, self->tx_buff.truesize, 1796 self->tx_buff.head, self->tx_buff_dma); 1797 1798 if (self->rx_buff.head) 1799 dma_free_coherent(NULL, self->rx_buff.truesize, 1800 self->rx_buff.head, self->rx_buff_dma); 1801 1802 free_netdev(self->netdev); 1803 1804 return 0; 1805} 1806 1807static void __exit smsc_ircc_cleanup(void) 1808{ 1809 int i; 1810 1811 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1812 1813 for (i = 0; i < 2; i++) { 1814 if (dev_self[i]) 1815 smsc_ircc_close(dev_self[i]); 1816 } 1817 1818 if (pnp_driver_registered) 1819 pnp_unregister_driver(&smsc_ircc_pnp_driver); 1820 1821 platform_driver_unregister(&smsc_ircc_driver); 1822} 1823 1824/* 1825 * Start SIR operations 1826 * 1827 * This function *must* be called with spinlock held, because it may 1828 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II 1829 */ 1830void smsc_ircc_sir_start(struct smsc_ircc_cb *self) 1831{ 1832 struct net_device *dev; 1833 int fir_base, sir_base; 1834 1835 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1836 1837 IRDA_ASSERT(self != NULL, return;); 1838 dev = self->netdev; 1839 IRDA_ASSERT(dev != NULL, return;); 1840 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir; 1841 1842 fir_base = self->io.fir_base; 1843 sir_base = self->io.sir_base; 1844 1845 /* Reset everything */ 1846 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER); 1847 1848 #if SMSC_IRCC2_C_SIR_STOP 1849 /*smsc_ircc_sir_stop(self);*/ 1850 #endif 1851 1852 register_bank(fir_base, 1); 1853 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA); 1854 1855 /* Initialize UART */ 1856 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */ 1857 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR); 1858 1859 /* Turn on interrups */ 1860 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER); 1861 1862 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__); 1863 1864 outb(0x00, fir_base + IRCC_MASTER); 1865} 1866 1867#if SMSC_IRCC2_C_SIR_STOP 1868void smsc_ircc_sir_stop(struct smsc_ircc_cb *self) 1869{ 1870 int iobase; 1871 1872 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1873 iobase = self->io.sir_base; 1874 1875 /* Reset UART */ 1876 outb(0, iobase + UART_MCR); 1877 1878 /* Turn off interrupts */ 1879 outb(0, iobase + UART_IER); 1880} 1881#endif 1882 1883/* 1884 * Function smsc_sir_write_wakeup (self) 1885 * 1886 * Called by the SIR interrupt handler when there's room for more data. 1887 * If we have more packets to send, we send them here. 1888 * 1889 */ 1890static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self) 1891{ 1892 int actual = 0; 1893 int iobase; 1894 int fcr; 1895 1896 IRDA_ASSERT(self != NULL, return;); 1897 1898 IRDA_DEBUG(4, "%s\n", __FUNCTION__); 1899 1900 iobase = self->io.sir_base; 1901 1902 /* Finished with frame? */ 1903 if (self->tx_buff.len > 0) { 1904 /* Write data left in transmit buffer */ 1905 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size, 1906 self->tx_buff.data, self->tx_buff.len); 1907 self->tx_buff.data += actual; 1908 self->tx_buff.len -= actual; 1909 } else { 1910 1911 /*if (self->tx_buff.len ==0) {*/ 1912 1913 /* 1914 * Now serial buffer is almost free & we can start 1915 * transmission of another packet. But first we must check 1916 * if we need to change the speed of the hardware 1917 */ 1918 if (self->new_speed) { 1919 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n", 1920 __FUNCTION__, self->new_speed); 1921 smsc_ircc_sir_wait_hw_transmitter_finish(self); 1922 smsc_ircc_change_speed(self, self->new_speed); 1923 self->new_speed = 0; 1924 } else { 1925 /* Tell network layer that we want more frames */ 1926 netif_wake_queue(self->netdev); 1927 } 1928 self->stats.tx_packets++; 1929 1930 if (self->io.speed <= 115200) { 1931 /* 1932 * Reset Rx FIFO to make sure that all reflected transmit data 1933 * is discarded. This is needed for half duplex operation 1934 */ 1935 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; 1936 fcr |= self->io.speed < 38400 ? 1937 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; 1938 1939 outb(fcr, iobase + UART_FCR); 1940 1941 /* Turn on receive interrupts */ 1942 outb(UART_IER_RDI, iobase + UART_IER); 1943 } 1944 } 1945} 1946 1947/* 1948 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len) 1949 * 1950 * Fill Tx FIFO with transmit data 1951 * 1952 */ 1953static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) 1954{ 1955 int actual = 0; 1956 1957 /* Tx FIFO should be empty! */ 1958 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { 1959 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__); 1960 return 0; 1961 } 1962 1963 /* Fill FIFO with current frame */ 1964 while (fifo_size-- > 0 && actual < len) { 1965 /* Transmit next byte */ 1966 outb(buf[actual], iobase + UART_TX); 1967 actual++; 1968 } 1969 return actual; 1970} 1971 1972/* 1973 * Function smsc_ircc_is_receiving (self) 1974 * 1975 * Returns true is we are currently receiving data 1976 * 1977 */ 1978static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self) 1979{ 1980 return (self->rx_buff.state != OUTSIDE_FRAME); 1981} 1982 1983 1984/* 1985 * Function smsc_ircc_probe_transceiver(self) 1986 * 1987 * Tries to find the used Transceiver 1988 * 1989 */ 1990static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self) 1991{ 1992 unsigned int i; 1993 1994 IRDA_ASSERT(self != NULL, return;); 1995 1996 for (i = 0; smsc_transceivers[i].name != NULL; i++) 1997 if (smsc_transceivers[i].probe(self->io.fir_base)) { 1998 IRDA_MESSAGE(" %s transceiver found\n", 1999 smsc_transceivers[i].name); 2000 self->transceiver= i + 1; 2001 return; 2002 } 2003 2004 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n", 2005 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name); 2006 2007 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER; 2008} 2009 2010 2011/* 2012 * Function smsc_ircc_set_transceiver_for_speed(self, speed) 2013 * 2014 * Set the transceiver according to the speed 2015 * 2016 */ 2017static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed) 2018{ 2019 unsigned int trx; 2020 2021 trx = self->transceiver; 2022 if (trx > 0) 2023 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed); 2024} 2025 2026/* 2027 * Function smsc_ircc_wait_hw_transmitter_finish () 2028 * 2029 * Wait for the real end of HW transmission 2030 * 2031 * The UART is a strict FIFO, and we get called only when we have finished 2032 * pushing data to the FIFO, so the maximum amount of time we must wait 2033 * is only for the FIFO to drain out. 2034 * 2035 * We use a simple calibrated loop. We may need to adjust the loop 2036 * delay (udelay) to balance I/O traffic and latency. And we also need to 2037 * adjust the maximum timeout. 2038 * It would probably be better to wait for the proper interrupt, 2039 * but it doesn't seem to be available. 2040 * 2041 * We can't use jiffies or kernel timers because : 2042 * 1) We are called from the interrupt handler, which disable softirqs, 2043 * so jiffies won't be increased 2044 * 2) Jiffies granularity is usually very coarse (10ms), and we don't 2045 * want to wait that long to detect stuck hardware. 2046 * Jean II 2047 */ 2048 2049static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) 2050{ 2051 int iobase = self->io.sir_base; 2052 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US; 2053 2054 /* Calibrated busy loop */ 2055 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) 2056 udelay(1); 2057 2058 if (count == 0) 2059 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__); 2060} 2061 2062 2063/* PROBING 2064 * 2065 * REVISIT we can be told about the device by PNP, and should use that info 2066 * instead of probing hardware and creating a platform_device ... 2067 */ 2068 2069static int __init smsc_ircc_look_for_chips(void) 2070{ 2071 struct smsc_chip_address *address; 2072 char *type; 2073 unsigned int cfg_base, found; 2074 2075 found = 0; 2076 address = possible_addresses; 2077 2078 while (address->cfg_base) { 2079 cfg_base = address->cfg_base; 2080 2081 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/ 2082 2083 if (address->type & SMSCSIO_TYPE_FDC) { 2084 type = "FDC"; 2085 if (address->type & SMSCSIO_TYPE_FLAT) 2086 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type)) 2087 found++; 2088 2089 if (address->type & SMSCSIO_TYPE_PAGED) 2090 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type)) 2091 found++; 2092 } 2093 if (address->type & SMSCSIO_TYPE_LPC) { 2094 type = "LPC"; 2095 if (address->type & SMSCSIO_TYPE_FLAT) 2096 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type)) 2097 found++; 2098 2099 if (address->type & SMSCSIO_TYPE_PAGED) 2100 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type)) 2101 found++; 2102 } 2103 address++; 2104 } 2105 return found; 2106} 2107 2108/* 2109 * Function smsc_superio_flat (chip, base, type) 2110 * 2111 * Try to get configuration of a smc SuperIO chip with flat register model 2112 * 2113 */ 2114static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type) 2115{ 2116 unsigned short firbase, sirbase; 2117 u8 mode, dma, irq; 2118 int ret = -ENODEV; 2119 2120 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 2121 2122 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL) 2123 return ret; 2124 2125 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase); 2126 mode = inb(cfgbase + 1); 2127 2128 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/ 2129 2130 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA)) 2131 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__); 2132 2133 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); 2134 sirbase = inb(cfgbase + 1) << 2; 2135 2136 /* FIR iobase */ 2137 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); 2138 firbase = inb(cfgbase + 1) << 3; 2139 2140 /* DMA */ 2141 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase); 2142 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; 2143 2144 /* IRQ */ 2145 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase); 2146 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; 2147 2148 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode); 2149 2150 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0) 2151 ret = 0; 2152 2153 /* Exit configuration */ 2154 outb(SMSCSIO_CFGEXITKEY, cfgbase); 2155 2156 return ret; 2157} 2158 2159/* 2160 * Function smsc_superio_paged (chip, base, type) 2161 * 2162 * Try to get configuration of a smc SuperIO chip with paged register model 2163 * 2164 */ 2165static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type) 2166{ 2167 unsigned short fir_io, sir_io; 2168 int ret = -ENODEV; 2169 2170 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 2171 2172 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL) 2173 return ret; 2174 2175 /* Select logical device (UART2) */ 2176 outb(0x07, cfg_base); 2177 outb(0x05, cfg_base + 1); 2178 2179 /* SIR iobase */ 2180 outb(0x60, cfg_base); 2181 sir_io = inb(cfg_base + 1) << 8; 2182 outb(0x61, cfg_base); 2183 sir_io |= inb(cfg_base + 1); 2184 2185 /* Read FIR base */ 2186 outb(0x62, cfg_base); 2187 fir_io = inb(cfg_base + 1) << 8; 2188 outb(0x63, cfg_base); 2189 fir_io |= inb(cfg_base + 1); 2190 outb(0x2b, cfg_base); /* ??? */ 2191 2192 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0) 2193 ret = 0; 2194 2195 /* Exit configuration */ 2196 outb(SMSCSIO_CFGEXITKEY, cfg_base); 2197 2198 return ret; 2199} 2200 2201 2202static int __init smsc_access(unsigned short cfg_base, unsigned char reg) 2203{ 2204 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 2205 2206 outb(reg, cfg_base); 2207 return inb(cfg_base) != reg ? -1 : 0; 2208} 2209 2210static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type) 2211{ 2212 u8 devid, xdevid, rev; 2213 2214 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 2215 2216 /* Leave configuration */ 2217 2218 outb(SMSCSIO_CFGEXITKEY, cfg_base); 2219 2220 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */ 2221 return NULL; 2222 2223 outb(reg, cfg_base); 2224 2225 xdevid = inb(cfg_base + 1); 2226 2227 /* Enter configuration */ 2228 2229 outb(SMSCSIO_CFGACCESSKEY, cfg_base); 2230 2231 2232 /* probe device ID */ 2233 2234 if (smsc_access(cfg_base, reg)) 2235 return NULL; 2236 2237 devid = inb(cfg_base + 1); 2238 2239 if (devid == 0 || devid == 0xff) /* typical values for unused port */ 2240 return NULL; 2241 2242 /* probe revision ID */ 2243 2244 if (smsc_access(cfg_base, reg + 1)) 2245 return NULL; 2246 2247 rev = inb(cfg_base + 1); 2248 2249 if (rev >= 128) /* i think this will make no sense */ 2250 return NULL; 2251 2252 if (devid == xdevid) /* protection against false positives */ 2253 return NULL; 2254 2255 /* Check for expected device ID; are there others? */ 2256 2257 while (chip->devid != devid) { 2258 2259 chip++; 2260 2261 if (chip->name == NULL) 2262 return NULL; 2263 } 2264 2265 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n", 2266 devid, rev, cfg_base, type, chip->name); 2267 2268 if (chip->rev > rev) { 2269 IRDA_MESSAGE("Revision higher than expected\n"); 2270 return NULL; 2271 } 2272 2273 if (chip->flags & NoIRDA) 2274 IRDA_MESSAGE("chipset does not support IRDA\n"); 2275 2276 return chip; 2277} 2278 2279static int __init smsc_superio_fdc(unsigned short cfg_base) 2280{ 2281 int ret = -1; 2282 2283 if (!request_region(cfg_base, 2, driver_name)) { 2284 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", 2285 __FUNCTION__, cfg_base); 2286 } else { 2287 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") || 2288 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC")) 2289 ret = 0; 2290 2291 release_region(cfg_base, 2); 2292 } 2293 2294 return ret; 2295} 2296 2297static int __init smsc_superio_lpc(unsigned short cfg_base) 2298{ 2299 int ret = -1; 2300 2301 if (!request_region(cfg_base, 2, driver_name)) { 2302 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", 2303 __FUNCTION__, cfg_base); 2304 } else { 2305 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") || 2306 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC")) 2307 ret = 0; 2308 2309 release_region(cfg_base, 2); 2310 } 2311 return ret; 2312} 2313 2314/* 2315 * Look for some specific subsystem setups that need 2316 * pre-configuration not properly done by the BIOS (especially laptops) 2317 * This code is based in part on smcinit.c, tosh1800-smcinit.c 2318 * and tosh2450-smcinit.c. The table lists the device entries 2319 * for ISA bridges with an LPC (Low Pin Count) controller which 2320 * handles the communication with the SMSC device. After the LPC 2321 * controller is initialized through PCI, the SMSC device is initialized 2322 * through a dedicated port in the ISA port-mapped I/O area, this latter 2323 * area is used to configure the SMSC device with default 2324 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have 2325 * used different sets of parameters and different control port 2326 * addresses making a subsystem device table necessary. 2327 */ 2328#ifdef CONFIG_PCI 2329#define PCIID_VENDOR_INTEL 0x8086 2330#define PCIID_VENDOR_ALI 0x10b9 2331static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = { 2332 /* 2333 * Subsystems needing entries: 2334 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family 2335 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family 2336 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family 2337 */ 2338 { 2339 /* Guessed entry */ 2340 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2341 .device = 0x24cc, 2342 .subvendor = 0x103c, 2343 .subdevice = 0x08bc, 2344 .sir_io = 0x02f8, 2345 .fir_io = 0x0130, 2346 .fir_irq = 0x05, 2347 .fir_dma = 0x03, 2348 .cfg_base = 0x004e, 2349 .preconfigure = preconfigure_through_82801, 2350 .name = "HP nx5000 family", 2351 }, 2352 { 2353 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2354 .device = 0x24cc, 2355 .subvendor = 0x103c, 2356 .subdevice = 0x088c, 2357 /* Quite certain these are the same for nc8000 as for nc6000 */ 2358 .sir_io = 0x02f8, 2359 .fir_io = 0x0130, 2360 .fir_irq = 0x05, 2361 .fir_dma = 0x03, 2362 .cfg_base = 0x004e, 2363 .preconfigure = preconfigure_through_82801, 2364 .name = "HP nc8000 family", 2365 }, 2366 { 2367 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2368 .device = 0x24cc, 2369 .subvendor = 0x103c, 2370 .subdevice = 0x0890, 2371 .sir_io = 0x02f8, 2372 .fir_io = 0x0130, 2373 .fir_irq = 0x05, 2374 .fir_dma = 0x03, 2375 .cfg_base = 0x004e, 2376 .preconfigure = preconfigure_through_82801, 2377 .name = "HP nc6000 family", 2378 }, 2379 { 2380 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2381 .device = 0x24cc, 2382 .subvendor = 0x0e11, 2383 .subdevice = 0x0860, 2384 /* I assume these are the same for x1000 as for the others */ 2385 .sir_io = 0x02e8, 2386 .fir_io = 0x02f8, 2387 .fir_irq = 0x07, 2388 .fir_dma = 0x03, 2389 .cfg_base = 0x002e, 2390 .preconfigure = preconfigure_through_82801, 2391 .name = "Compaq x1000 family", 2392 }, 2393 { 2394 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */ 2395 .vendor = PCIID_VENDOR_INTEL, 2396 .device = 0x24c0, 2397 .subvendor = 0x1179, 2398 .subdevice = 0xffff, /* 0xffff is "any" */ 2399 .sir_io = 0x03f8, 2400 .fir_io = 0x0130, 2401 .fir_irq = 0x07, 2402 .fir_dma = 0x01, 2403 .cfg_base = 0x002e, 2404 .preconfigure = preconfigure_through_82801, 2405 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge", 2406 }, 2407 { 2408 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */ 2409 .device = 0x248c, 2410 .subvendor = 0x1179, 2411 .subdevice = 0xffff, /* 0xffff is "any" */ 2412 .sir_io = 0x03f8, 2413 .fir_io = 0x0130, 2414 .fir_irq = 0x03, 2415 .fir_dma = 0x03, 2416 .cfg_base = 0x002e, 2417 .preconfigure = preconfigure_through_82801, 2418 .name = "Toshiba laptop with Intel 82801CAM ISA bridge", 2419 }, 2420 { 2421 /* 82801DBM (ICH4-M) LPC Interface Bridge */ 2422 .vendor = PCIID_VENDOR_INTEL, 2423 .device = 0x24cc, 2424 .subvendor = 0x1179, 2425 .subdevice = 0xffff, /* 0xffff is "any" */ 2426 .sir_io = 0x03f8, 2427 .fir_io = 0x0130, 2428 .fir_irq = 0x03, 2429 .fir_dma = 0x03, 2430 .cfg_base = 0x002e, 2431 .preconfigure = preconfigure_through_82801, 2432 .name = "Toshiba laptop with Intel 8281DBM LPC bridge", 2433 }, 2434 { 2435 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */ 2436 .vendor = PCIID_VENDOR_ALI, 2437 .device = 0x1533, 2438 .subvendor = 0x1179, 2439 .subdevice = 0xffff, /* 0xffff is "any" */ 2440 .sir_io = 0x02e8, 2441 .fir_io = 0x02f8, 2442 .fir_irq = 0x07, 2443 .fir_dma = 0x03, 2444 .cfg_base = 0x002e, 2445 .preconfigure = preconfigure_through_ali, 2446 .name = "Toshiba laptop with ALi ISA bridge", 2447 }, 2448 { } // Terminator 2449}; 2450 2451 2452/* 2453 * This sets up the basic SMSC parameters 2454 * (FIR port, SIR port, FIR DMA, FIR IRQ) 2455 * through the chip configuration port. 2456 */ 2457static int __init preconfigure_smsc_chip(struct 2458 smsc_ircc_subsystem_configuration 2459 *conf) 2460{ 2461 unsigned short iobase = conf->cfg_base; 2462 unsigned char tmpbyte; 2463 2464 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state 2465 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID 2466 tmpbyte = inb(iobase +1); // Read device ID 2467 IRDA_DEBUG(0, 2468 "Detected Chip id: 0x%02x, setting up registers...\n", 2469 tmpbyte); 2470 2471 /* Disable UART1 and set up SIR I/O port */ 2472 outb(0x24, iobase); // select CR24 - UART1 base addr 2473 outb(0x00, iobase + 1); // disable UART1 2474 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr 2475 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8 2476 tmpbyte = inb(iobase + 1); 2477 if (tmpbyte != (conf->sir_io >> 2) ) { 2478 IRDA_WARNING("ERROR: could not configure SIR ioport.\n"); 2479 IRDA_WARNING("Try to supply ircc_cfg argument.\n"); 2480 return -ENXIO; 2481 } 2482 2483 /* Set up FIR IRQ channel for UART2 */ 2484 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select 2485 tmpbyte = inb(iobase + 1); 2486 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion 2487 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK); 2488 outb(tmpbyte, iobase + 1); 2489 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; 2490 if (tmpbyte != conf->fir_irq) { 2491 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n"); 2492 return -ENXIO; 2493 } 2494 2495 /* Set up FIR I/O port */ 2496 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr 2497 outb((conf->fir_io >> 3), iobase + 1); 2498 tmpbyte = inb(iobase + 1); 2499 if (tmpbyte != (conf->fir_io >> 3) ) { 2500 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n"); 2501 return -ENXIO; 2502 } 2503 2504 /* Set up FIR DMA channel */ 2505 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select 2506 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA 2507 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; 2508 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) { 2509 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n"); 2510 return -ENXIO; 2511 } 2512 2513 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode 2514 tmpbyte = inb(iobase + 1); 2515 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK | 2516 SMSCSIOFLAT_UART2MODE_VAL_IRDA; 2517 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed 2518 2519 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel 2520 tmpbyte = inb(iobase + 1); 2521 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down 2522 2523 /* This one was not part of tosh1800 */ 2524 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux 2525 tmpbyte = inb(iobase + 1); 2526 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port 2527 2528 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power 2529 tmpbyte = inb(iobase + 1); 2530 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down 2531 2532 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle 2533 tmpbyte = inb(iobase + 1); 2534 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done 2535 2536 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration 2537 2538 return 0; 2539} 2540 2541/* 82801CAM generic registers */ 2542#define VID 0x00 2543#define DID 0x02 2544#define PIRQ_A_D_ROUT 0x60 2545#define SIRQ_CNTL 0x64 2546#define PIRQ_E_H_ROUT 0x68 2547#define PCI_DMA_C 0x90 2548/* LPC-specific registers */ 2549#define COM_DEC 0xe0 2550#define GEN1_DEC 0xe4 2551#define LPC_EN 0xe6 2552#define GEN2_DEC 0xec 2553/* 2554 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge 2555 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge. 2556 * They all work the same way! 2557 */ 2558static int __init preconfigure_through_82801(struct pci_dev *dev, 2559 struct 2560 smsc_ircc_subsystem_configuration 2561 *conf) 2562{ 2563 unsigned short tmpword; 2564 unsigned char tmpbyte; 2565 2566 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n"); 2567 /* 2568 * Select the range for the COMA COM port (SIR) 2569 * Register COM_DEC: 2570 * Bit 7: reserved 2571 * Bit 6-4, COMB decode range 2572 * Bit 3: reserved 2573 * Bit 2-0, COMA decode range 2574 * 2575 * Decode ranges: 2576 * 000 = 0x3f8-0x3ff (COM1) 2577 * 001 = 0x2f8-0x2ff (COM2) 2578 * 010 = 0x220-0x227 2579 * 011 = 0x228-0x22f 2580 * 100 = 0x238-0x23f 2581 * 101 = 0x2e8-0x2ef (COM4) 2582 * 110 = 0x338-0x33f 2583 * 111 = 0x3e8-0x3ef (COM3) 2584 */ 2585 pci_read_config_byte(dev, COM_DEC, &tmpbyte); 2586 tmpbyte &= 0xf8; /* mask COMA bits */ 2587 switch(conf->sir_io) { 2588 case 0x3f8: 2589 tmpbyte |= 0x00; 2590 break; 2591 case 0x2f8: 2592 tmpbyte |= 0x01; 2593 break; 2594 case 0x220: 2595 tmpbyte |= 0x02; 2596 break; 2597 case 0x228: 2598 tmpbyte |= 0x03; 2599 break; 2600 case 0x238: 2601 tmpbyte |= 0x04; 2602 break; 2603 case 0x2e8: 2604 tmpbyte |= 0x05; 2605 break; 2606 case 0x338: 2607 tmpbyte |= 0x06; 2608 break; 2609 case 0x3e8: 2610 tmpbyte |= 0x07; 2611 break; 2612 default: 2613 tmpbyte |= 0x01; /* COM2 default */ 2614 } 2615 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte); 2616 pci_write_config_byte(dev, COM_DEC, tmpbyte); 2617 2618 /* Enable Low Pin Count interface */ 2619 pci_read_config_word(dev, LPC_EN, &tmpword); 2620 /* These seem to be set up at all times, 2621 * just make sure it is properly set. 2622 */ 2623 switch(conf->cfg_base) { 2624 case 0x04e: 2625 tmpword |= 0x2000; 2626 break; 2627 case 0x02e: 2628 tmpword |= 0x1000; 2629 break; 2630 case 0x062: 2631 tmpword |= 0x0800; 2632 break; 2633 case 0x060: 2634 tmpword |= 0x0400; 2635 break; 2636 default: 2637 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n", 2638 conf->cfg_base); 2639 break; 2640 } 2641 tmpword &= 0xfffd; /* disable LPC COMB */ 2642 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */ 2643 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword); 2644 pci_write_config_word(dev, LPC_EN, tmpword); 2645 2646 /* 2647 * Configure LPC DMA channel 2648 * PCI_DMA_C bits: 2649 * Bit 15-14: DMA channel 7 select 2650 * Bit 13-12: DMA channel 6 select 2651 * Bit 11-10: DMA channel 5 select 2652 * Bit 9-8: Reserved 2653 * Bit 7-6: DMA channel 3 select 2654 * Bit 5-4: DMA channel 2 select 2655 * Bit 3-2: DMA channel 1 select 2656 * Bit 1-0: DMA channel 0 select 2657 * 00 = Reserved value 2658 * 01 = PC/PCI DMA 2659 * 10 = Reserved value 2660 * 11 = LPC I/F DMA 2661 */ 2662 pci_read_config_word(dev, PCI_DMA_C, &tmpword); 2663 switch(conf->fir_dma) { 2664 case 0x07: 2665 tmpword |= 0xc000; 2666 break; 2667 case 0x06: 2668 tmpword |= 0x3000; 2669 break; 2670 case 0x05: 2671 tmpword |= 0x0c00; 2672 break; 2673 case 0x03: 2674 tmpword |= 0x00c0; 2675 break; 2676 case 0x02: 2677 tmpword |= 0x0030; 2678 break; 2679 case 0x01: 2680 tmpword |= 0x000c; 2681 break; 2682 case 0x00: 2683 tmpword |= 0x0003; 2684 break; 2685 default: 2686 break; /* do not change settings */ 2687 } 2688 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword); 2689 pci_write_config_word(dev, PCI_DMA_C, tmpword); 2690 2691 /* 2692 * GEN2_DEC bits: 2693 * Bit 15-4: Generic I/O range 2694 * Bit 3-1: reserved (read as 0) 2695 * Bit 0: enable GEN2 range on LPC I/F 2696 */ 2697 tmpword = conf->fir_io & 0xfff8; 2698 tmpword |= 0x0001; 2699 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword); 2700 pci_write_config_word(dev, GEN2_DEC, tmpword); 2701 2702 /* Pre-configure chip */ 2703 return preconfigure_smsc_chip(conf); 2704} 2705 2706/* 2707 * Pre-configure a certain port on the ALi 1533 bridge. 2708 * This is based on reverse-engineering since ALi does not 2709 * provide any data sheet for the 1533 chip. 2710 */ 2711static void __init preconfigure_ali_port(struct pci_dev *dev, 2712 unsigned short port) 2713{ 2714 unsigned char reg; 2715 /* These bits obviously control the different ports */ 2716 unsigned char mask; 2717 unsigned char tmpbyte; 2718 2719 switch(port) { 2720 case 0x0130: 2721 case 0x0178: 2722 reg = 0xb0; 2723 mask = 0x80; 2724 break; 2725 case 0x03f8: 2726 reg = 0xb4; 2727 mask = 0x80; 2728 break; 2729 case 0x02f8: 2730 reg = 0xb4; 2731 mask = 0x30; 2732 break; 2733 case 0x02e8: 2734 reg = 0xb4; 2735 mask = 0x08; 2736 break; 2737 default: 2738 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port); 2739 return; 2740 } 2741 2742 pci_read_config_byte(dev, reg, &tmpbyte); 2743 /* Turn on the right bits */ 2744 tmpbyte |= mask; 2745 pci_write_config_byte(dev, reg, tmpbyte); 2746 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port); 2747 return; 2748} 2749 2750static int __init preconfigure_through_ali(struct pci_dev *dev, 2751 struct 2752 smsc_ircc_subsystem_configuration 2753 *conf) 2754{ 2755 /* Configure the two ports on the ALi 1533 */ 2756 preconfigure_ali_port(dev, conf->sir_io); 2757 preconfigure_ali_port(dev, conf->fir_io); 2758 2759 /* Pre-configure chip */ 2760 return preconfigure_smsc_chip(conf); 2761} 2762 2763static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, 2764 unsigned short ircc_fir, 2765 unsigned short ircc_sir, 2766 unsigned char ircc_dma, 2767 unsigned char ircc_irq) 2768{ 2769 struct pci_dev *dev = NULL; 2770 unsigned short ss_vendor = 0x0000; 2771 unsigned short ss_device = 0x0000; 2772 int ret = 0; 2773 2774 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); 2775 2776 while (dev != NULL) { 2777 struct smsc_ircc_subsystem_configuration *conf; 2778 2779 /* 2780 * Cache the subsystem vendor/device: 2781 * some manufacturers fail to set this for all components, 2782 * so we save it in case there is just 0x0000 0x0000 on the 2783 * device we want to check. 2784 */ 2785 if (dev->subsystem_vendor != 0x0000U) { 2786 ss_vendor = dev->subsystem_vendor; 2787 ss_device = dev->subsystem_device; 2788 } 2789 conf = subsystem_configurations; 2790 for( ; conf->subvendor; conf++) { 2791 if(conf->vendor == dev->vendor && 2792 conf->device == dev->device && 2793 conf->subvendor == ss_vendor && 2794 /* Sometimes these are cached values */ 2795 (conf->subdevice == ss_device || 2796 conf->subdevice == 0xffff)) { 2797 struct smsc_ircc_subsystem_configuration 2798 tmpconf; 2799 2800 memcpy(&tmpconf, conf, 2801 sizeof(struct smsc_ircc_subsystem_configuration)); 2802 2803 /* 2804 * Override the default values with anything 2805 * passed in as parameter 2806 */ 2807 if (ircc_cfg != 0) 2808 tmpconf.cfg_base = ircc_cfg; 2809 if (ircc_fir != 0) 2810 tmpconf.fir_io = ircc_fir; 2811 if (ircc_sir != 0) 2812 tmpconf.sir_io = ircc_sir; 2813 if (ircc_dma != DMA_INVAL) 2814 tmpconf.fir_dma = ircc_dma; 2815 if (ircc_irq != IRQ_INVAL) 2816 tmpconf.fir_irq = ircc_irq; 2817 2818 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name); 2819 if (conf->preconfigure) 2820 ret = conf->preconfigure(dev, &tmpconf); 2821 else 2822 ret = -ENODEV; 2823 } 2824 } 2825 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); 2826 } 2827 2828 return ret; 2829} 2830#endif // CONFIG_PCI 2831 2832/************************************************ 2833 * 2834 * Transceivers specific functions 2835 * 2836 ************************************************/ 2837 2838 2839/* 2840 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed) 2841 * 2842 * Program transceiver through smsc-ircc ATC circuitry 2843 * 2844 */ 2845 2846static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed) 2847{ 2848 unsigned long jiffies_now, jiffies_timeout; 2849 u8 val; 2850 2851 jiffies_now = jiffies; 2852 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES; 2853 2854 /* ATC */ 2855 register_bank(fir_base, 4); 2856 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, 2857 fir_base + IRCC_ATC); 2858 2859 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && 2860 !time_after(jiffies, jiffies_timeout)) 2861 /* empty */; 2862 2863 if (val) 2864 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__, 2865 inb(fir_base + IRCC_ATC)); 2866} 2867 2868/* 2869 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base) 2870 * 2871 * Probe transceiver smsc-ircc ATC circuitry 2872 * 2873 */ 2874 2875static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base) 2876{ 2877 return 0; 2878} 2879 2880/* 2881 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed) 2882 * 2883 * Set transceiver 2884 * 2885 */ 2886 2887static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed) 2888{ 2889 u8 fast_mode; 2890 2891 switch (speed) { 2892 default: 2893 case 576000 : 2894 fast_mode = 0; 2895 break; 2896 case 1152000 : 2897 case 4000000 : 2898 fast_mode = IRCC_LCR_A_FAST; 2899 break; 2900 } 2901 register_bank(fir_base, 0); 2902 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); 2903} 2904 2905/* 2906 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base) 2907 * 2908 * Probe transceiver 2909 * 2910 */ 2911 2912static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base) 2913{ 2914 return 0; 2915} 2916 2917/* 2918 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed) 2919 * 2920 * Set transceiver 2921 * 2922 */ 2923 2924static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed) 2925{ 2926 u8 fast_mode; 2927 2928 switch (speed) { 2929 default: 2930 case 576000 : 2931 fast_mode = 0; 2932 break; 2933 case 1152000 : 2934 case 4000000 : 2935 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA; 2936 break; 2937 2938 } 2939 /* This causes an interrupt */ 2940 register_bank(fir_base, 0); 2941 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); 2942} 2943 2944/* 2945 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base) 2946 * 2947 * Probe transceiver 2948 * 2949 */ 2950 2951static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base) 2952{ 2953 return 0; 2954} 2955 2956 2957module_init(smsc_ircc_init); 2958module_exit(smsc_ircc_cleanup); 2959