1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2001 Patton Electronics Company 7 * Copyright (C) 2002 Momentum Computer 8 * 9 * Copyright 2000 MontaVista Software Inc. 10 * Author: MontaVista Software, Inc. 11 * stevel@mvista.com or support@mvista.com 12 * Copyright 2004, 05 Ralf Baechle (ralf@linux-mips.org) 13 * 14 * This program is free software; you can distribute it and/or modify it 15 * under the terms of the GNU General Public License (Version 2) as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope it will be useful, but WITHOUT 19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 21 * for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 26 * 27 * Ethernet driver definitions for the MIPS GT96100 Advanced 28 * Communication Controller. 29 * 30 * Modified for the Marvellous GT64240 Retarded Communication Controller. 31 */ 32#ifndef _GT64240ETH_H 33#define _GT64240ETH_H 34 35#include <asm/gt64240.h> 36 37#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400 38 39/* Translate those weanie names from Galileo/VxWorks header files: */ 40 41#define GT64240_MRR MAIN_ROUTING_REGISTER 42#define GT64240_CIU_ARBITER_CONFIG COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 43#define GT64240_CIU_ARBITER_CONTROL COMM_UNIT_ARBITER_CONTROL 44#define GT64240_MAIN_LOW_CAUSE LOW_INTERRUPT_CAUSE_REGISTER 45#define GT64240_MAIN_HIGH_CAUSE HIGH_INTERRUPT_CAUSE_REGISTER 46#define GT64240_CPU_LOW_MASK CPU_INTERRUPT_MASK_REGISTER_LOW 47#define GT64240_CPU_HIGH_MASK CPU_INTERRUPT_MASK_REGISTER_HIGH 48#define GT64240_CPU_SELECT_CAUSE CPU_SELECT_CAUSE_REGISTER 49 50#define GT64240_ETH_PHY_ADDR_REG ETHERNET_PHY_ADDRESS_REGISTER 51#define GT64240_ETH_PORT_CONFIG ETHERNET0_PORT_CONFIGURATION_REGISTER 52#define GT64240_ETH_PORT_CONFIG_EXT ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 53#define GT64240_ETH_PORT_COMMAND ETHERNET0_PORT_COMMAND_REGISTER 54#define GT64240_ETH_PORT_STATUS ETHERNET0_PORT_STATUS_REGISTER 55#define GT64240_ETH_IO_SIZE ETHERNET_PORTS_DIFFERENCE_OFFSETS 56#define GT64240_ETH_SMI_REG ETHERNET_SMI_REGISTER 57#define GT64240_ETH_MIB_COUNT_BASE ETHERNET0_MIB_COUNTER_BASE 58#define GT64240_ETH_SDMA_CONFIG ETHERNET0_SDMA_CONFIGURATION_REGISTER 59#define GT64240_ETH_SDMA_COMM ETHERNET0_SDMA_COMMAND_REGISTER 60#define GT64240_ETH_INT_MASK ETHERNET0_INTERRUPT_MASK_REGISTER 61#define GT64240_ETH_INT_CAUSE ETHERNET0_INTERRUPT_CAUSE_REGISTER 62#define GT64240_ETH_CURR_TX_DESC_PTR0 ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 63#define GT64240_ETH_CURR_TX_DESC_PTR1 ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 64#define GT64240_ETH_1ST_RX_DESC_PTR0 ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 65#define GT64240_ETH_CURR_RX_DESC_PTR0 ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 66#define GT64240_ETH_HASH_TBL_PTR ETHERNET0_HASH_TABLE_POINTER_REGISTER 67 68/* Turn on NAPI by default */ 69 70#define GT64240_NAPI 1 71 72/* Some 64240 settings that SHOULD eventually be setup in PROM monitor: */ 73/* (Board-specific to the DSL3224 Rev A board ONLY!) */ 74#define D3224_MPP_CTRL0_SETTING 0x66669900 75#define D3224_MPP_CTRL1_SETTING 0x00000000 76#define D3224_MPP_CTRL2_SETTING 0x00887700 77#define D3224_MPP_CTRL3_SETTING 0x00000044 78#define D3224_GPP_IO_CTRL_SETTING 0x0000e800 79#define D3224_GPP_LEVEL_CTRL_SETTING 0xf001f703 80#define D3224_GPP_VALUE_SETTING 0x00000000 81 82/* Keep the ring sizes a power of two for efficiency. */ 83//-#define TX_RING_SIZE 16 84#define TX_RING_SIZE 64 /* TESTING !!! */ 85#define RX_RING_SIZE 32 86#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ 87 88#define RX_HASH_TABLE_SIZE 16384 89#define HASH_HOP_NUMBER 12 90 91#define NUM_INTERFACES 3 92 93#define GT64240ETH_TX_TIMEOUT HZ/4 94 95#define MIPS_GT64240_BASE 0xf4000000 96#define GT64240_ETH0_BASE (MIPS_GT64240_BASE + GT64240_ETH_PORT_CONFIG) 97#define GT64240_ETH1_BASE (GT64240_ETH0_BASE + GT64240_ETH_IO_SIZE) 98#define GT64240_ETH2_BASE (GT64240_ETH1_BASE + GT64240_ETH_IO_SIZE) 99 100#if defined(CONFIG_MIPS_DSL3224) 101#define GT64240_ETHER0_IRQ 4 102#define GT64240_ETHER1_IRQ 4 103#else 104#define GT64240_ETHER0_IRQ -1 105#define GT64240_ETHER1_IRQ -1 106#endif 107 108#define REV_GT64240 0x1 109#define REV_GT64240A 0x10 110 111#define GT64240ETH_READ(gp, offset) \ 112 MV_READ((gp)->port_offset + (offset)) 113 114#define GT64240ETH_WRITE(gp, offset, data) \ 115 MV_WRITE((gp)->port_offset + (offset), (data)) 116 117#define GT64240ETH_SETBIT(gp, offset, bits) \ 118 GT64240ETH_WRITE((gp), (offset), \ 119 GT64240ETH_READ((gp), (offset)) | (bits)) 120 121#define GT64240ETH_CLRBIT(gp, offset, bits) \ 122 GT64240ETH_WRITE((gp), (offset), \ 123 GT64240ETH_READ((gp), (offset)) & ~(bits)) 124 125#define GT64240_READ(ofs) MV_READ(ofs) 126#define GT64240_WRITE(ofs, data) MV_WRITE((ofs), (data)) 127 128/* Bit definitions of the SMI Reg */ 129enum { 130 smirDataMask = 0xffff, 131 smirPhyAdMask = 0x1f << 16, 132 smirPhyAdBit = 16, 133 smirRegAdMask = 0x1f << 21, 134 smirRegAdBit = 21, 135 smirOpCode = 1 << 26, 136 smirReadValid = 1 << 27, 137 smirBusy = 1 << 28 138}; 139 140/* Bit definitions of the Port Config Reg */ 141enum pcr_bits { 142 pcrPM = 1 << 0, 143 pcrRBM = 1 << 1, 144 pcrPBF = 1 << 2, 145 pcrEN = 1 << 7, 146 pcrLPBKMask = 0x3 << 8, 147 pcrLPBKBit = 1 << 8, 148 pcrFC = 1 << 10, 149 pcrHS = 1 << 12, 150 pcrHM = 1 << 13, 151 pcrHDM = 1 << 14, 152 pcrHD = 1 << 15, 153 pcrISLMask = 0x7 << 28, 154 pcrISLBit = 28, 155 pcrACCS = 1 << 31 156}; 157 158/* Bit definitions of the Port Config Extend Reg */ 159enum pcxr_bits { 160 pcxrIGMP = 1, 161 pcxrSPAN = 2, 162 pcxrPAR = 4, 163 pcxrPRIOtxMask = 0x7 << 3, 164 pcxrPRIOtxBit = 3, 165 pcxrPRIOrxMask = 0x3 << 6, 166 pcxrPRIOrxBit = 6, 167 pcxrPRIOrxOverride = 1 << 8, 168 pcxrDPLXen = 1 << 9, 169 pcxrFCTLen = 1 << 10, 170 pcxrFLP = 1 << 11, 171 pcxrFCTL = 1 << 12, 172 pcxrMFLMask = 0x3 << 14, 173 pcxrMFLBit = 14, 174 pcxrMIBclrMode = 1 << 16, 175 pcxrSpeed = 1 << 18, 176 pcxrSpeeden = 1 << 19, 177 pcxrRMIIen = 1 << 20, 178 pcxrDSCPen = 1 << 21 179}; 180 181/* Bit definitions of the Port Command Reg */ 182enum pcmr_bits { 183 pcmrFJ = 1 << 15 184}; 185 186 187/* Bit definitions of the Port Status Reg */ 188enum psr_bits { 189 psrSpeed = 1, 190 psrDuplex = 2, 191 psrFctl = 4, 192 psrLink = 8, 193 psrPause = 1 << 4, 194 psrTxLow = 1 << 5, 195 psrTxHigh = 1 << 6, 196 psrTxInProg = 1 << 7 197}; 198 199/* Bit definitions of the SDMA Config Reg */ 200enum sdcr_bits { 201 sdcrRCMask = 0xf << 2, 202 sdcrRCBit = 2, 203 sdcrBLMR = 1 << 6, 204 sdcrBLMT = 1 << 7, 205 sdcrPOVR = 1 << 8, 206 sdcrRIFB = 1 << 9, 207 sdcrBSZMask = 0x3 << 12, 208 sdcrBSZBit = 12 209}; 210 211/* Bit definitions of the SDMA Command Reg */ 212enum sdcmr_bits { 213 sdcmrERD = 1 << 7, 214 sdcmrAR = 1 << 15, 215 sdcmrSTDH = 1 << 16, 216 sdcmrSTDL = 1 << 17, 217 sdcmrTXDH = 1 << 23, 218 sdcmrTXDL = 1 << 24, 219 sdcmrAT = 1 << 31 220}; 221 222/* Bit definitions of the Interrupt Cause Reg */ 223enum icr_bits { 224 icrRxBuffer = 1, 225 icrTxBufferHigh = 1 << 2, 226 icrTxBufferLow = 1 << 3, 227 icrTxEndHigh = 1 << 6, 228 icrTxEndLow = 1 << 7, 229 icrRxError = 1 << 8, 230 icrTxErrorHigh = 1 << 10, 231 icrTxErrorLow = 1 << 11, 232 icrRxOVR = 1 << 12, 233 icrTxUdr = 1 << 13, 234 icrRxBufferQ0 = 1 << 16, 235 icrRxBufferQ1 = 1 << 17, 236 icrRxBufferQ2 = 1 << 18, 237 icrRxBufferQ3 = 1 << 19, 238 icrRxErrorQ0 = 1 << 20, 239 icrRxErrorQ1 = 1 << 21, 240 icrRxErrorQ2 = 1 << 22, 241 icrRxErrorQ3 = 1 << 23, 242 icrMIIPhySTC = 1 << 28, 243 icrSMIdone = 1 << 29, 244 icrEtherIntSum = 1 << 31 245}; 246 247 248/* The Rx and Tx descriptor lists. */ 249#ifdef __LITTLE_ENDIAN 250typedef struct { 251 u32 cmdstat; 252 u16 reserved; //-prk21aug01 u32 reserved:16; 253 u16 byte_cnt; //-prk21aug01 u32 byte_cnt:16; 254 u32 buff_ptr; 255 u32 next; 256} gt64240_td_t; 257 258typedef struct { 259 u32 cmdstat; 260 u16 byte_cnt; //-prk21aug01 u32 byte_cnt:16; 261 u16 buff_sz; //-prk21aug01 u32 buff_sz:16; 262 u32 buff_ptr; 263 u32 next; 264} gt64240_rd_t; 265#elif defined(__BIG_ENDIAN) 266typedef struct { 267 u16 byte_cnt; //-prk21aug01 u32 byte_cnt:16; 268 u16 reserved; //-prk21aug01 u32 reserved:16; 269 u32 cmdstat; 270 u32 next; 271 u32 buff_ptr; 272} gt64240_td_t; 273 274typedef struct { 275 u16 buff_sz; //-prk21aug01 u32 buff_sz:16; 276 u16 byte_cnt; //-prk21aug01 u32 byte_cnt:16; 277 u32 cmdstat; 278 u32 next; 279 u32 buff_ptr; 280} gt64240_rd_t; 281#else 282#error Either __BIG_ENDIAN or __LITTLE_ENDIAN must be defined! 283#endif 284 285 286/* Values for the Tx command-status descriptor entry. */ 287enum td_cmdstat { 288 txOwn = 1 << 31, 289 txAutoMode = 1 << 30, 290 txEI = 1 << 23, 291 txGenCRC = 1 << 22, 292 txPad = 1 << 18, 293 txFirst = 1 << 17, 294 txLast = 1 << 16, 295 txErrorSummary = 1 << 15, 296 txReTxCntMask = 0x0f << 10, 297 txReTxCntBit = 10, 298 txCollision = 1 << 9, 299 txReTxLimit = 1 << 8, 300 txUnderrun = 1 << 6, 301 txLateCollision = 1 << 5 302}; 303 304 305/* Values for the Rx command-status descriptor entry. */ 306enum rd_cmdstat { 307 rxOwn = 1 << 31, 308 rxAutoMode = 1 << 30, 309 rxEI = 1 << 23, 310 rxFirst = 1 << 17, 311 rxLast = 1 << 16, 312 rxErrorSummary = 1 << 15, 313 rxIGMP = 1 << 14, 314 rxHashExpired = 1 << 13, 315 rxMissedFrame = 1 << 12, 316 rxFrameType = 1 << 11, 317 rxShortFrame = 1 << 8, 318 rxMaxFrameLen = 1 << 7, 319 rxOverrun = 1 << 6, 320 rxCollision = 1 << 4, 321 rxCRCError = 1 322}; 323 324/* Bit fields of a Hash Table Entry */ 325enum hash_table_entry { 326 hteValid = 1, 327 hteSkip = 2, 328 hteRD = 4 329}; 330 331// The MIB counters 332typedef struct { 333 u32 byteReceived; 334 u32 byteSent; 335 u32 framesReceived; 336 u32 framesSent; 337 u32 totalByteReceived; 338 u32 totalFramesReceived; 339 u32 broadcastFramesReceived; 340 u32 multicastFramesReceived; 341 u32 cRCError; 342 u32 oversizeFrames; 343 u32 fragments; 344 u32 jabber; 345 u32 collision; 346 u32 lateCollision; 347 u32 frames64; 348 u32 frames65_127; 349 u32 frames128_255; 350 u32 frames256_511; 351 u32 frames512_1023; 352 u32 frames1024_MaxSize; 353 u32 macRxError; 354 u32 droppedFrames; 355 u32 outMulticastFrames; 356 u32 outBroadcastFrames; 357 u32 undersizeFrames; 358} mib_counters_t; 359 360 361struct gt64240_private { 362 gt64240_rd_t *rx_ring; 363 gt64240_td_t *tx_ring; 364 // The Rx and Tx rings must be 16-byte aligned 365 dma_addr_t rx_ring_dma; 366 dma_addr_t tx_ring_dma; 367 char *hash_table; 368 // The Hash Table must be 8-byte aligned 369 dma_addr_t hash_table_dma; 370 int hash_mode; 371 372 // The Rx buffers must be 8-byte aligned 373 char *rx_buff; 374 dma_addr_t rx_buff_dma; 375 // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes 376 // of payload must be 8-byte aligned 377 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 378 int rx_next_out; /* The next free ring entry to receive */ 379 int tx_next_in; /* The next free ring entry to send */ 380 int tx_next_out; /* The last ring entry the ISR processed */ 381 int tx_count; /* current # of pkts waiting to be sent in Tx ring */ 382 int intr_work_done; /* number of Rx and Tx pkts processed in the isr */ 383 int tx_full; /* Tx ring is full */ 384 385 mib_counters_t mib; 386 struct net_device_stats stats; 387 388 int io_size; 389 int port_num; // 0 or 1 390 u32 port_offset; 391 392 int phy_addr; // PHY address 393 u32 last_psr; // last value of the port status register 394 395 int options; /* User-settable misc. driver options. */ 396 int drv_flags; 397 spinlock_t lock; /* Serialise access to device */ 398 struct mii_if_info mii_if; 399 400 u32 msg_enable; 401}; 402 403#endif /* _GT64240ETH_H */ 404