1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29/* e1000_hw.c 30 * Shared functions for accessing and configuring the MAC 31 */ 32 33 34#include "e1000_hw.h" 35 36static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 37static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 38static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); 39static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 40static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); 41static void e1000_release_software_semaphore(struct e1000_hw *hw); 42 43static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); 44static int32_t e1000_check_downshift(struct e1000_hw *hw); 45static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); 46static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 47static void e1000_clear_vfta(struct e1000_hw *hw); 48static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); 49static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); 50static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); 51static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); 52static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); 53static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); 54static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); 55static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); 56static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); 57static int32_t e1000_get_software_flag(struct e1000_hw *hw); 58static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); 59static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); 60static int32_t e1000_id_led_init(struct e1000_hw *hw); 61static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); 62static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); 63static void e1000_init_rx_addrs(struct e1000_hw *hw); 64static void e1000_initialize_hardware_bits(struct e1000_hw *hw); 65static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); 66static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); 67static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); 68static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); 69static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); 70static int32_t e1000_mng_write_commit(struct e1000_hw *hw); 71static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 72static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 73static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 74static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 75static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); 76static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 77static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 78static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); 79static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); 80static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); 81static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); 82static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); 83static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); 84static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 85static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 86static void e1000_release_software_flag(struct e1000_hw *hw); 87static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); 88static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); 89static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); 90static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); 91static int32_t e1000_wait_autoneg(struct e1000_hw *hw); 92static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); 93static int32_t e1000_set_phy_type(struct e1000_hw *hw); 94static void e1000_phy_init_script(struct e1000_hw *hw); 95static int32_t e1000_setup_copper_link(struct e1000_hw *hw); 96static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 97static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); 98static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); 99static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); 100static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); 101static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); 102static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, 103 uint16_t count); 104static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); 105static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); 106static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, 107 uint16_t words, uint16_t *data); 108static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, 109 uint16_t offset, uint16_t words, 110 uint16_t *data); 111static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); 112static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); 113static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); 114static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, 115 uint16_t count); 116static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 117 uint16_t phy_data); 118static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, 119 uint16_t *phy_data); 120static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); 121static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); 122static void e1000_release_eeprom(struct e1000_hw *hw); 123static void e1000_standby_eeprom(struct e1000_hw *hw); 124static int32_t e1000_set_vco_speed(struct e1000_hw *hw); 125static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); 126static int32_t e1000_set_phy_mode(struct e1000_hw *hw); 127static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); 128static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); 129static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, 130 uint16_t duplex); 131static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 132 133/* IGP cable length table */ 134static const 135uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 136 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 137 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 138 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 139 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 140 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 141 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 142 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 143 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 144 145static const 146uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 147 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 148 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 149 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 150 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 151 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 152 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 154 104, 109, 114, 118, 121, 124}; 155 156/****************************************************************************** 157 * Set the phy type member in the hw struct. 158 * 159 * hw - Struct containing variables accessed by shared code 160 *****************************************************************************/ 161static int32_t 162e1000_set_phy_type(struct e1000_hw *hw) 163{ 164 DEBUGFUNC("e1000_set_phy_type"); 165 166 if (hw->mac_type == e1000_undefined) 167 return -E1000_ERR_PHY_TYPE; 168 169 switch (hw->phy_id) { 170 case M88E1000_E_PHY_ID: 171 case M88E1000_I_PHY_ID: 172 case M88E1011_I_PHY_ID: 173 case M88E1111_I_PHY_ID: 174 hw->phy_type = e1000_phy_m88; 175 break; 176 case IGP01E1000_I_PHY_ID: 177 if (hw->mac_type == e1000_82541 || 178 hw->mac_type == e1000_82541_rev_2 || 179 hw->mac_type == e1000_82547 || 180 hw->mac_type == e1000_82547_rev_2) { 181 hw->phy_type = e1000_phy_igp; 182 break; 183 } 184 case IGP03E1000_E_PHY_ID: 185 hw->phy_type = e1000_phy_igp_3; 186 break; 187 case IFE_E_PHY_ID: 188 case IFE_PLUS_E_PHY_ID: 189 case IFE_C_E_PHY_ID: 190 hw->phy_type = e1000_phy_ife; 191 break; 192 case GG82563_E_PHY_ID: 193 if (hw->mac_type == e1000_80003es2lan) { 194 hw->phy_type = e1000_phy_gg82563; 195 break; 196 } 197 /* Fall Through */ 198 default: 199 /* Should never have loaded on this device */ 200 hw->phy_type = e1000_phy_undefined; 201 return -E1000_ERR_PHY_TYPE; 202 } 203 204 return E1000_SUCCESS; 205} 206 207/****************************************************************************** 208 * IGP phy init script - initializes the GbE PHY 209 * 210 * hw - Struct containing variables accessed by shared code 211 *****************************************************************************/ 212static void 213e1000_phy_init_script(struct e1000_hw *hw) 214{ 215 uint32_t ret_val; 216 uint16_t phy_saved_data; 217 218 DEBUGFUNC("e1000_phy_init_script"); 219 220 if (hw->phy_init_script) { 221 msleep(20); 222 223 /* Save off the current value of register 0x2F5B to be restored at 224 * the end of this routine. */ 225 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 226 227 /* Disabled the PHY transmitter */ 228 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 229 230 msleep(20); 231 232 e1000_write_phy_reg(hw,0x0000,0x0140); 233 234 msleep(5); 235 236 switch (hw->mac_type) { 237 case e1000_82541: 238 case e1000_82547: 239 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 240 241 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 242 243 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 244 245 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 246 247 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 248 249 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 250 251 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 252 253 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 254 255 e1000_write_phy_reg(hw, 0x2010, 0x0008); 256 break; 257 258 case e1000_82541_rev_2: 259 case e1000_82547_rev_2: 260 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 261 break; 262 default: 263 break; 264 } 265 266 e1000_write_phy_reg(hw, 0x0000, 0x3300); 267 268 msleep(20); 269 270 /* Now enable the transmitter */ 271 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 272 273 if (hw->mac_type == e1000_82547) { 274 uint16_t fused, fine, coarse; 275 276 /* Move to analog registers page */ 277 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 278 279 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); 281 282 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 283 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 284 285 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 286 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 287 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 288 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 289 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 290 291 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 292 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 293 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 294 295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); 296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, 297 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 298 } 299 } 300 } 301} 302 303/****************************************************************************** 304 * Set the mac type member in the hw struct. 305 * 306 * hw - Struct containing variables accessed by shared code 307 *****************************************************************************/ 308int32_t 309e1000_set_mac_type(struct e1000_hw *hw) 310{ 311 DEBUGFUNC("e1000_set_mac_type"); 312 313 switch (hw->device_id) { 314 case E1000_DEV_ID_82542: 315 switch (hw->revision_id) { 316 case E1000_82542_2_0_REV_ID: 317 hw->mac_type = e1000_82542_rev2_0; 318 break; 319 case E1000_82542_2_1_REV_ID: 320 hw->mac_type = e1000_82542_rev2_1; 321 break; 322 default: 323 /* Invalid 82542 revision ID */ 324 return -E1000_ERR_MAC_TYPE; 325 } 326 break; 327 case E1000_DEV_ID_82543GC_FIBER: 328 case E1000_DEV_ID_82543GC_COPPER: 329 hw->mac_type = e1000_82543; 330 break; 331 case E1000_DEV_ID_82544EI_COPPER: 332 case E1000_DEV_ID_82544EI_FIBER: 333 case E1000_DEV_ID_82544GC_COPPER: 334 case E1000_DEV_ID_82544GC_LOM: 335 hw->mac_type = e1000_82544; 336 break; 337 case E1000_DEV_ID_82540EM: 338 case E1000_DEV_ID_82540EM_LOM: 339 case E1000_DEV_ID_82540EP: 340 case E1000_DEV_ID_82540EP_LOM: 341 case E1000_DEV_ID_82540EP_LP: 342 hw->mac_type = e1000_82540; 343 break; 344 case E1000_DEV_ID_82545EM_COPPER: 345 case E1000_DEV_ID_82545EM_FIBER: 346 hw->mac_type = e1000_82545; 347 break; 348 case E1000_DEV_ID_82545GM_COPPER: 349 case E1000_DEV_ID_82545GM_FIBER: 350 case E1000_DEV_ID_82545GM_SERDES: 351 hw->mac_type = e1000_82545_rev_3; 352 break; 353 case E1000_DEV_ID_82546EB_COPPER: 354 case E1000_DEV_ID_82546EB_FIBER: 355 case E1000_DEV_ID_82546EB_QUAD_COPPER: 356 hw->mac_type = e1000_82546; 357 break; 358 case E1000_DEV_ID_82546GB_COPPER: 359 case E1000_DEV_ID_82546GB_FIBER: 360 case E1000_DEV_ID_82546GB_SERDES: 361 case E1000_DEV_ID_82546GB_PCIE: 362 case E1000_DEV_ID_82546GB_QUAD_COPPER: 363 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 364 hw->mac_type = e1000_82546_rev_3; 365 break; 366 case E1000_DEV_ID_82541EI: 367 case E1000_DEV_ID_82541EI_MOBILE: 368 case E1000_DEV_ID_82541ER_LOM: 369 hw->mac_type = e1000_82541; 370 break; 371 case E1000_DEV_ID_82541ER: 372 case E1000_DEV_ID_82541GI: 373 case E1000_DEV_ID_82541GI_LF: 374 case E1000_DEV_ID_82541GI_MOBILE: 375 hw->mac_type = e1000_82541_rev_2; 376 break; 377 case E1000_DEV_ID_82547EI: 378 case E1000_DEV_ID_82547EI_MOBILE: 379 hw->mac_type = e1000_82547; 380 break; 381 case E1000_DEV_ID_82547GI: 382 hw->mac_type = e1000_82547_rev_2; 383 break; 384 case E1000_DEV_ID_82571EB_COPPER: 385 case E1000_DEV_ID_82571EB_FIBER: 386 case E1000_DEV_ID_82571EB_SERDES: 387 case E1000_DEV_ID_82571EB_QUAD_COPPER: 388 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 389 hw->mac_type = e1000_82571; 390 break; 391 case E1000_DEV_ID_82572EI_COPPER: 392 case E1000_DEV_ID_82572EI_FIBER: 393 case E1000_DEV_ID_82572EI_SERDES: 394 case E1000_DEV_ID_82572EI: 395 hw->mac_type = e1000_82572; 396 break; 397 case E1000_DEV_ID_82573E: 398 case E1000_DEV_ID_82573E_IAMT: 399 case E1000_DEV_ID_82573L: 400 hw->mac_type = e1000_82573; 401 break; 402 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 403 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 404 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 405 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 406 hw->mac_type = e1000_80003es2lan; 407 break; 408 case E1000_DEV_ID_ICH8_IGP_M_AMT: 409 case E1000_DEV_ID_ICH8_IGP_AMT: 410 case E1000_DEV_ID_ICH8_IGP_C: 411 case E1000_DEV_ID_ICH8_IFE: 412 case E1000_DEV_ID_ICH8_IFE_GT: 413 case E1000_DEV_ID_ICH8_IFE_G: 414 case E1000_DEV_ID_ICH8_IGP_M: 415 hw->mac_type = e1000_ich8lan; 416 break; 417 default: 418 /* Should never have loaded on this device */ 419 return -E1000_ERR_MAC_TYPE; 420 } 421 422 switch (hw->mac_type) { 423 case e1000_ich8lan: 424 hw->swfwhw_semaphore_present = TRUE; 425 hw->asf_firmware_present = TRUE; 426 break; 427 case e1000_80003es2lan: 428 hw->swfw_sync_present = TRUE; 429 /* fall through */ 430 case e1000_82571: 431 case e1000_82572: 432 case e1000_82573: 433 hw->eeprom_semaphore_present = TRUE; 434 /* fall through */ 435 case e1000_82541: 436 case e1000_82547: 437 case e1000_82541_rev_2: 438 case e1000_82547_rev_2: 439 hw->asf_firmware_present = TRUE; 440 break; 441 default: 442 break; 443 } 444 445 /* The 82543 chip does not count tx_carrier_errors properly in 446 * FD mode 447 */ 448 if (hw->mac_type == e1000_82543) 449 hw->bad_tx_carr_stats_fd = TRUE; 450 451 /* capable of receiving management packets to the host */ 452 if (hw->mac_type >= e1000_82571) 453 hw->has_manc2h = TRUE; 454 455 /* In rare occasions, ESB2 systems would end up started without 456 * the RX unit being turned on. 457 */ 458 if (hw->mac_type == e1000_80003es2lan) 459 hw->rx_needs_kicking = TRUE; 460 461 if (hw->mac_type > e1000_82544) 462 hw->has_smbus = TRUE; 463 464 return E1000_SUCCESS; 465} 466 467/***************************************************************************** 468 * Set media type and TBI compatibility. 469 * 470 * hw - Struct containing variables accessed by shared code 471 * **************************************************************************/ 472void 473e1000_set_media_type(struct e1000_hw *hw) 474{ 475 uint32_t status; 476 477 DEBUGFUNC("e1000_set_media_type"); 478 479 if (hw->mac_type != e1000_82543) { 480 /* tbi_compatibility is only valid on 82543 */ 481 hw->tbi_compatibility_en = FALSE; 482 } 483 484 switch (hw->device_id) { 485 case E1000_DEV_ID_82545GM_SERDES: 486 case E1000_DEV_ID_82546GB_SERDES: 487 case E1000_DEV_ID_82571EB_SERDES: 488 case E1000_DEV_ID_82572EI_SERDES: 489 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 490 hw->media_type = e1000_media_type_internal_serdes; 491 break; 492 default: 493 switch (hw->mac_type) { 494 case e1000_82542_rev2_0: 495 case e1000_82542_rev2_1: 496 hw->media_type = e1000_media_type_fiber; 497 break; 498 case e1000_ich8lan: 499 case e1000_82573: 500 /* The STATUS_TBIMODE bit is reserved or reused for the this 501 * device. 502 */ 503 hw->media_type = e1000_media_type_copper; 504 break; 505 default: 506 status = E1000_READ_REG(hw, STATUS); 507 if (status & E1000_STATUS_TBIMODE) { 508 hw->media_type = e1000_media_type_fiber; 509 /* tbi_compatibility not valid on fiber */ 510 hw->tbi_compatibility_en = FALSE; 511 } else { 512 hw->media_type = e1000_media_type_copper; 513 } 514 break; 515 } 516 } 517} 518 519/****************************************************************************** 520 * Reset the transmit and receive units; mask and clear all interrupts. 521 * 522 * hw - Struct containing variables accessed by shared code 523 *****************************************************************************/ 524int32_t 525e1000_reset_hw(struct e1000_hw *hw) 526{ 527 uint32_t ctrl; 528 uint32_t ctrl_ext; 529 uint32_t icr; 530 uint32_t manc; 531 uint32_t led_ctrl; 532 uint32_t timeout; 533 uint32_t extcnf_ctrl; 534 int32_t ret_val; 535 536 DEBUGFUNC("e1000_reset_hw"); 537 538 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 539 if (hw->mac_type == e1000_82542_rev2_0) { 540 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 541 e1000_pci_clear_mwi(hw); 542 } 543 544 if (hw->bus_type == e1000_bus_type_pci_express) { 545 /* Prevent the PCI-E bus from sticking if there is no TLP connection 546 * on the last TLP read/write transaction when MAC is reset. 547 */ 548 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { 549 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 550 } 551 } 552 553 /* Clear interrupt mask to stop board from generating interrupts */ 554 DEBUGOUT("Masking off all interrupts\n"); 555 E1000_WRITE_REG(hw, IMC, 0xffffffff); 556 557 /* Disable the Transmit and Receive units. Then delay to allow 558 * any pending transactions to complete before we hit the MAC with 559 * the global reset. 560 */ 561 E1000_WRITE_REG(hw, RCTL, 0); 562 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 563 E1000_WRITE_FLUSH(hw); 564 565 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 566 hw->tbi_compatibility_on = FALSE; 567 568 /* Delay to allow any outstanding PCI transactions to complete before 569 * resetting the device 570 */ 571 msleep(10); 572 573 ctrl = E1000_READ_REG(hw, CTRL); 574 575 /* Must reset the PHY before resetting the MAC */ 576 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 577 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 578 msleep(5); 579 } 580 581 /* Must acquire the MDIO ownership before MAC reset. 582 * Ownership defaults to firmware after a reset. */ 583 if (hw->mac_type == e1000_82573) { 584 timeout = 10; 585 586 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 587 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 588 589 do { 590 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 591 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 592 593 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 594 break; 595 else 596 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 597 598 msleep(2); 599 timeout--; 600 } while (timeout); 601 } 602 603 if (hw->mac_type == e1000_ich8lan) { 604 /* Set Tx and Rx buffer allocation to 8k apiece. */ 605 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 606 /* Set Packet Buffer Size to 16k. */ 607 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 608 } 609 610 /* Issue a global reset to the MAC. This will reset the chip's 611 * transmit, receive, DMA, and link units. It will not effect 612 * the current PCI configuration. The global reset bit is self- 613 * clearing, and should clear within a microsecond. 614 */ 615 DEBUGOUT("Issuing a global reset to MAC\n"); 616 617 switch (hw->mac_type) { 618 case e1000_82544: 619 case e1000_82540: 620 case e1000_82545: 621 case e1000_82546: 622 case e1000_82541: 623 case e1000_82541_rev_2: 624 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 625 break; 626 case e1000_82545_rev_3: 627 case e1000_82546_rev_3: 628 /* Reset is performed on a shadow of the control register */ 629 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 630 break; 631 case e1000_ich8lan: 632 if (!hw->phy_reset_disable && 633 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { 634 /* e1000_ich8lan PHY HW reset requires MAC CORE reset 635 * at the same time to make sure the interface between 636 * MAC and the external PHY is reset. 637 */ 638 ctrl |= E1000_CTRL_PHY_RST; 639 } 640 641 e1000_get_software_flag(hw); 642 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 643 msleep(5); 644 break; 645 default: 646 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 647 break; 648 } 649 650 /* After MAC reset, force reload of EEPROM to restore power-on settings to 651 * device. Later controllers reload the EEPROM automatically, so just wait 652 * for reload to complete. 653 */ 654 switch (hw->mac_type) { 655 case e1000_82542_rev2_0: 656 case e1000_82542_rev2_1: 657 case e1000_82543: 658 case e1000_82544: 659 /* Wait for reset to complete */ 660 udelay(10); 661 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 662 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 663 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 664 E1000_WRITE_FLUSH(hw); 665 /* Wait for EEPROM reload */ 666 msleep(2); 667 break; 668 case e1000_82541: 669 case e1000_82541_rev_2: 670 case e1000_82547: 671 case e1000_82547_rev_2: 672 /* Wait for EEPROM reload */ 673 msleep(20); 674 break; 675 case e1000_82573: 676 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 677 udelay(10); 678 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 679 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 680 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 681 E1000_WRITE_FLUSH(hw); 682 } 683 /* fall through */ 684 default: 685 /* Auto read done will delay 5ms or poll based on mac type */ 686 ret_val = e1000_get_auto_rd_done(hw); 687 if (ret_val) 688 return ret_val; 689 break; 690 } 691 692 /* Disable HW ARPs on ASF enabled adapters */ 693 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { 694 manc = E1000_READ_REG(hw, MANC); 695 manc &= ~(E1000_MANC_ARP_EN); 696 E1000_WRITE_REG(hw, MANC, manc); 697 } 698 699 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 700 e1000_phy_init_script(hw); 701 702 /* Configure activity LED after PHY reset */ 703 led_ctrl = E1000_READ_REG(hw, LEDCTL); 704 led_ctrl &= IGP_ACTIVITY_LED_MASK; 705 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 706 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 707 } 708 709 /* Clear interrupt mask to stop board from generating interrupts */ 710 DEBUGOUT("Masking off all interrupts\n"); 711 E1000_WRITE_REG(hw, IMC, 0xffffffff); 712 713 /* Clear any pending interrupt events. */ 714 icr = E1000_READ_REG(hw, ICR); 715 716 /* If MWI was previously enabled, reenable it. */ 717 if (hw->mac_type == e1000_82542_rev2_0) { 718 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 719 e1000_pci_set_mwi(hw); 720 } 721 722 if (hw->mac_type == e1000_ich8lan) { 723 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 724 kab |= E1000_KABGTXD_BGSQLBIAS; 725 E1000_WRITE_REG(hw, KABGTXD, kab); 726 } 727 728 return E1000_SUCCESS; 729} 730 731/****************************************************************************** 732 * 733 * Initialize a number of hardware-dependent bits 734 * 735 * hw: Struct containing variables accessed by shared code 736 * 737 * This function contains hardware limitation workarounds for PCI-E adapters 738 * 739 *****************************************************************************/ 740static void 741e1000_initialize_hardware_bits(struct e1000_hw *hw) 742{ 743 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { 744 /* Settings common to all PCI-express silicon */ 745 uint32_t reg_ctrl, reg_ctrl_ext; 746 uint32_t reg_tarc0, reg_tarc1; 747 uint32_t reg_tctl; 748 uint32_t reg_txdctl, reg_txdctl1; 749 750 /* link autonegotiation/sync workarounds */ 751 reg_tarc0 = E1000_READ_REG(hw, TARC0); 752 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 753 754 /* Enable not-done TX descriptor counting */ 755 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 756 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 757 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 758 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 759 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 760 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 761 762 switch (hw->mac_type) { 763 case e1000_82571: 764 case e1000_82572: 765 /* Clear PHY TX compatible mode bits */ 766 reg_tarc1 = E1000_READ_REG(hw, TARC1); 767 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 768 769 /* link autonegotiation/sync workarounds */ 770 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 771 772 /* TX ring control fixes */ 773 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 774 775 /* Multiple read bit is reversed polarity */ 776 reg_tctl = E1000_READ_REG(hw, TCTL); 777 if (reg_tctl & E1000_TCTL_MULR) 778 reg_tarc1 &= ~(1 << 28); 779 else 780 reg_tarc1 |= (1 << 28); 781 782 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 783 break; 784 case e1000_82573: 785 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 786 reg_ctrl_ext &= ~(1 << 23); 787 reg_ctrl_ext |= (1 << 22); 788 789 /* TX byte count fix */ 790 reg_ctrl = E1000_READ_REG(hw, CTRL); 791 reg_ctrl &= ~(1 << 29); 792 793 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 794 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 795 break; 796 case e1000_80003es2lan: 797 /* improve small packet performace for fiber/serdes */ 798 if ((hw->media_type == e1000_media_type_fiber) || 799 (hw->media_type == e1000_media_type_internal_serdes)) { 800 reg_tarc0 &= ~(1 << 20); 801 } 802 803 /* Multiple read bit is reversed polarity */ 804 reg_tctl = E1000_READ_REG(hw, TCTL); 805 reg_tarc1 = E1000_READ_REG(hw, TARC1); 806 if (reg_tctl & E1000_TCTL_MULR) 807 reg_tarc1 &= ~(1 << 28); 808 else 809 reg_tarc1 |= (1 << 28); 810 811 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 812 break; 813 case e1000_ich8lan: 814 /* Reduce concurrent DMA requests to 3 from 4 */ 815 if ((hw->revision_id < 3) || 816 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 817 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 818 reg_tarc0 |= ((1 << 29)|(1 << 28)); 819 820 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 821 reg_ctrl_ext |= (1 << 22); 822 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 823 824 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 825 826 /* Multiple read bit is reversed polarity */ 827 reg_tctl = E1000_READ_REG(hw, TCTL); 828 reg_tarc1 = E1000_READ_REG(hw, TARC1); 829 if (reg_tctl & E1000_TCTL_MULR) 830 reg_tarc1 &= ~(1 << 28); 831 else 832 reg_tarc1 |= (1 << 28); 833 834 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 835 836 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 837 break; 838 default: 839 break; 840 } 841 842 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 843 } 844} 845 846/****************************************************************************** 847 * Performs basic configuration of the adapter. 848 * 849 * hw - Struct containing variables accessed by shared code 850 * 851 * Assumes that the controller has previously been reset and is in a 852 * post-reset uninitialized state. Initializes the receive address registers, 853 * multicast table, and VLAN filter table. Calls routines to setup link 854 * configuration and flow control settings. Clears all on-chip counters. Leaves 855 * the transmit and receive units disabled and uninitialized. 856 *****************************************************************************/ 857int32_t 858e1000_init_hw(struct e1000_hw *hw) 859{ 860 uint32_t ctrl; 861 uint32_t i; 862 int32_t ret_val; 863 uint16_t pcix_cmd_word; 864 uint16_t pcix_stat_hi_word; 865 uint16_t cmd_mmrbc; 866 uint16_t stat_mmrbc; 867 uint32_t mta_size; 868 uint32_t reg_data; 869 uint32_t ctrl_ext; 870 871 DEBUGFUNC("e1000_init_hw"); 872 873 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 874 if ((hw->mac_type == e1000_ich8lan) && 875 ((hw->revision_id < 3) || 876 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 877 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 878 reg_data = E1000_READ_REG(hw, STATUS); 879 reg_data &= ~0x80000000; 880 E1000_WRITE_REG(hw, STATUS, reg_data); 881 } 882 883 /* Initialize Identification LED */ 884 ret_val = e1000_id_led_init(hw); 885 if (ret_val) { 886 DEBUGOUT("Error Initializing Identification LED\n"); 887 return ret_val; 888 } 889 890 /* Set the media type and TBI compatibility */ 891 e1000_set_media_type(hw); 892 893 /* Must be called after e1000_set_media_type because media_type is used */ 894 e1000_initialize_hardware_bits(hw); 895 896 /* Disabling VLAN filtering. */ 897 DEBUGOUT("Initializing the IEEE VLAN\n"); 898 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 899 if (hw->mac_type != e1000_ich8lan) { 900 if (hw->mac_type < e1000_82545_rev_3) 901 E1000_WRITE_REG(hw, VET, 0); 902 e1000_clear_vfta(hw); 903 } 904 905 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 906 if (hw->mac_type == e1000_82542_rev2_0) { 907 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 908 e1000_pci_clear_mwi(hw); 909 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 910 E1000_WRITE_FLUSH(hw); 911 msleep(5); 912 } 913 914 /* Setup the receive address. This involves initializing all of the Receive 915 * Address Registers (RARs 0 - 15). 916 */ 917 e1000_init_rx_addrs(hw); 918 919 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 920 if (hw->mac_type == e1000_82542_rev2_0) { 921 E1000_WRITE_REG(hw, RCTL, 0); 922 E1000_WRITE_FLUSH(hw); 923 msleep(1); 924 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 925 e1000_pci_set_mwi(hw); 926 } 927 928 /* Zero out the Multicast HASH table */ 929 DEBUGOUT("Zeroing the MTA\n"); 930 mta_size = E1000_MC_TBL_SIZE; 931 if (hw->mac_type == e1000_ich8lan) 932 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 933 for (i = 0; i < mta_size; i++) { 934 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 935 /* use write flush to prevent Memory Write Block (MWB) from 936 * occuring when accessing our register space */ 937 E1000_WRITE_FLUSH(hw); 938 } 939 940 /* Set the PCI priority bit correctly in the CTRL register. This 941 * determines if the adapter gives priority to receives, or if it 942 * gives equal priority to transmits and receives. Valid only on 943 * 82542 and 82543 silicon. 944 */ 945 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 946 ctrl = E1000_READ_REG(hw, CTRL); 947 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 948 } 949 950 switch (hw->mac_type) { 951 case e1000_82545_rev_3: 952 case e1000_82546_rev_3: 953 break; 954 default: 955 if (hw->bus_type == e1000_bus_type_pcix) { 956 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); 957 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 958 &pcix_stat_hi_word); 959 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 960 PCIX_COMMAND_MMRBC_SHIFT; 961 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 962 PCIX_STATUS_HI_MMRBC_SHIFT; 963 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 964 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 965 if (cmd_mmrbc > stat_mmrbc) { 966 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 967 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 968 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 969 &pcix_cmd_word); 970 } 971 } 972 break; 973 } 974 975 /* More time needed for PHY to initialize */ 976 if (hw->mac_type == e1000_ich8lan) 977 msleep(15); 978 979 /* Call a subroutine to configure the link and setup flow control. */ 980 ret_val = e1000_setup_link(hw); 981 982 /* Set the transmit descriptor write-back policy */ 983 if (hw->mac_type > e1000_82544) { 984 ctrl = E1000_READ_REG(hw, TXDCTL); 985 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 986 E1000_WRITE_REG(hw, TXDCTL, ctrl); 987 } 988 989 if (hw->mac_type == e1000_82573) { 990 e1000_enable_tx_pkt_filtering(hw); 991 } 992 993 switch (hw->mac_type) { 994 default: 995 break; 996 case e1000_80003es2lan: 997 /* Enable retransmit on late collisions */ 998 reg_data = E1000_READ_REG(hw, TCTL); 999 reg_data |= E1000_TCTL_RTLC; 1000 E1000_WRITE_REG(hw, TCTL, reg_data); 1001 1002 /* Configure Gigabit Carry Extend Padding */ 1003 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1004 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1005 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1006 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1007 1008 /* Configure Transmit Inter-Packet Gap */ 1009 reg_data = E1000_READ_REG(hw, TIPG); 1010 reg_data &= ~E1000_TIPG_IPGT_MASK; 1011 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1012 E1000_WRITE_REG(hw, TIPG, reg_data); 1013 1014 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1015 reg_data &= ~0x00100000; 1016 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1017 /* Fall through */ 1018 case e1000_82571: 1019 case e1000_82572: 1020 case e1000_ich8lan: 1021 ctrl = E1000_READ_REG(hw, TXDCTL1); 1022 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 1023 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1024 break; 1025 } 1026 1027 1028 if (hw->mac_type == e1000_82573) { 1029 uint32_t gcr = E1000_READ_REG(hw, GCR); 1030 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1031 E1000_WRITE_REG(hw, GCR, gcr); 1032 } 1033 1034 /* Clear all of the statistics registers (clear on read). It is 1035 * important that we do this after we have tried to establish link 1036 * because the symbol error count will increment wildly if there 1037 * is no link. 1038 */ 1039 e1000_clear_hw_cntrs(hw); 1040 1041 /* ICH8 No-snoop bits are opposite polarity. 1042 * Set to snoop by default after reset. */ 1043 if (hw->mac_type == e1000_ich8lan) 1044 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1045 1046 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1047 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1048 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1049 /* Relaxed ordering must be disabled to avoid a parity 1050 * error crash in a PCI slot. */ 1051 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1052 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1053 } 1054 1055 return ret_val; 1056} 1057 1058/****************************************************************************** 1059 * Adjust SERDES output amplitude based on EEPROM setting. 1060 * 1061 * hw - Struct containing variables accessed by shared code. 1062 *****************************************************************************/ 1063static int32_t 1064e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 1065{ 1066 uint16_t eeprom_data; 1067 int32_t ret_val; 1068 1069 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 1070 1071 if (hw->media_type != e1000_media_type_internal_serdes) 1072 return E1000_SUCCESS; 1073 1074 switch (hw->mac_type) { 1075 case e1000_82545_rev_3: 1076 case e1000_82546_rev_3: 1077 break; 1078 default: 1079 return E1000_SUCCESS; 1080 } 1081 1082 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1083 if (ret_val) { 1084 return ret_val; 1085 } 1086 1087 if (eeprom_data != EEPROM_RESERVED_WORD) { 1088 /* Adjust SERDES output amplitude only. */ 1089 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1090 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 1091 if (ret_val) 1092 return ret_val; 1093 } 1094 1095 return E1000_SUCCESS; 1096} 1097 1098/****************************************************************************** 1099 * Configures flow control and link settings. 1100 * 1101 * hw - Struct containing variables accessed by shared code 1102 * 1103 * Determines which flow control settings to use. Calls the apropriate media- 1104 * specific link configuration function. Configures the flow control settings. 1105 * Assuming the adapter has a valid link partner, a valid link should be 1106 * established. Assumes the hardware has previously been reset and the 1107 * transmitter and receiver are not enabled. 1108 *****************************************************************************/ 1109int32_t 1110e1000_setup_link(struct e1000_hw *hw) 1111{ 1112 uint32_t ctrl_ext; 1113 int32_t ret_val; 1114 uint16_t eeprom_data; 1115 1116 DEBUGFUNC("e1000_setup_link"); 1117 1118 /* In the case of the phy reset being blocked, we already have a link. 1119 * We do not have to set it up again. */ 1120 if (e1000_check_phy_reset_block(hw)) 1121 return E1000_SUCCESS; 1122 1123 /* Read and store word 0x0F of the EEPROM. This word contains bits 1124 * that determine the hardware's default PAUSE (flow control) mode, 1125 * a bit that determines whether the HW defaults to enabling or 1126 * disabling auto-negotiation, and the direction of the 1127 * SW defined pins. If there is no SW over-ride of the flow 1128 * control setting, then the variable hw->fc will 1129 * be initialized based on a value in the EEPROM. 1130 */ 1131 if (hw->fc == E1000_FC_DEFAULT) { 1132 switch (hw->mac_type) { 1133 case e1000_ich8lan: 1134 case e1000_82573: 1135 hw->fc = E1000_FC_FULL; 1136 break; 1137 default: 1138 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1139 1, &eeprom_data); 1140 if (ret_val) { 1141 DEBUGOUT("EEPROM Read Error\n"); 1142 return -E1000_ERR_EEPROM; 1143 } 1144 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1145 hw->fc = E1000_FC_NONE; 1146 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1147 EEPROM_WORD0F_ASM_DIR) 1148 hw->fc = E1000_FC_TX_PAUSE; 1149 else 1150 hw->fc = E1000_FC_FULL; 1151 break; 1152 } 1153 } 1154 1155 /* We want to save off the original Flow Control configuration just 1156 * in case we get disconnected and then reconnected into a different 1157 * hub or switch with different Flow Control capabilities. 1158 */ 1159 if (hw->mac_type == e1000_82542_rev2_0) 1160 hw->fc &= (~E1000_FC_TX_PAUSE); 1161 1162 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1163 hw->fc &= (~E1000_FC_RX_PAUSE); 1164 1165 hw->original_fc = hw->fc; 1166 1167 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1168 1169 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1170 * polarity value for the SW controlled pins, and setup the 1171 * Extended Device Control reg with that info. 1172 * This is needed because one of the SW controlled pins is used for 1173 * signal detection. So this should be done before e1000_setup_pcs_link() 1174 * or e1000_phy_setup() is called. 1175 */ 1176 if (hw->mac_type == e1000_82543) { 1177 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1178 1, &eeprom_data); 1179 if (ret_val) { 1180 DEBUGOUT("EEPROM Read Error\n"); 1181 return -E1000_ERR_EEPROM; 1182 } 1183 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1184 SWDPIO__EXT_SHIFT); 1185 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1186 } 1187 1188 /* Call the necessary subroutine to configure the link. */ 1189 ret_val = (hw->media_type == e1000_media_type_copper) ? 1190 e1000_setup_copper_link(hw) : 1191 e1000_setup_fiber_serdes_link(hw); 1192 1193 /* Initialize the flow control address, type, and PAUSE timer 1194 * registers to their default values. This is done even if flow 1195 * control is disabled, because it does not hurt anything to 1196 * initialize these registers. 1197 */ 1198 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1199 1200 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1201 if (hw->mac_type != e1000_ich8lan) { 1202 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1203 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1204 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1205 } 1206 1207 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1208 1209 /* Set the flow control receive threshold registers. Normally, 1210 * these registers will be set to a default threshold that may be 1211 * adjusted later by the driver's runtime code. However, if the 1212 * ability to transmit pause frames in not enabled, then these 1213 * registers will be set to 0. 1214 */ 1215 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1216 E1000_WRITE_REG(hw, FCRTL, 0); 1217 E1000_WRITE_REG(hw, FCRTH, 0); 1218 } else { 1219 /* We need to set up the Receive Threshold high and low water marks 1220 * as well as (optionally) enabling the transmission of XON frames. 1221 */ 1222 if (hw->fc_send_xon) { 1223 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 1224 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1225 } else { 1226 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1227 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1228 } 1229 } 1230 return ret_val; 1231} 1232 1233/****************************************************************************** 1234 * Sets up link for a fiber based or serdes based adapter 1235 * 1236 * hw - Struct containing variables accessed by shared code 1237 * 1238 * Manipulates Physical Coding Sublayer functions in order to configure 1239 * link. Assumes the hardware has been previously reset and the transmitter 1240 * and receiver are not enabled. 1241 *****************************************************************************/ 1242static int32_t 1243e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 1244{ 1245 uint32_t ctrl; 1246 uint32_t status; 1247 uint32_t txcw = 0; 1248 uint32_t i; 1249 uint32_t signal = 0; 1250 int32_t ret_val; 1251 1252 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 1253 1254 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists 1255 * until explicitly turned off or a power cycle is performed. A read to 1256 * the register does not indicate its status. Therefore, we ensure 1257 * loopback mode is disabled during initialization. 1258 */ 1259 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) 1260 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1261 1262 /* On adapters with a MAC newer than 82544, SWDP 1 will be 1263 * set when the optics detect a signal. On older adapters, it will be 1264 * cleared when there is a signal. This applies to fiber media only. 1265 * If we're on serdes media, adjust the output amplitude to value 1266 * set in the EEPROM. 1267 */ 1268 ctrl = E1000_READ_REG(hw, CTRL); 1269 if (hw->media_type == e1000_media_type_fiber) 1270 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 1271 1272 ret_val = e1000_adjust_serdes_amplitude(hw); 1273 if (ret_val) 1274 return ret_val; 1275 1276 /* Take the link out of reset */ 1277 ctrl &= ~(E1000_CTRL_LRST); 1278 1279 /* Adjust VCO speed to improve BER performance */ 1280 ret_val = e1000_set_vco_speed(hw); 1281 if (ret_val) 1282 return ret_val; 1283 1284 e1000_config_collision_dist(hw); 1285 1286 /* Check for a software override of the flow control settings, and setup 1287 * the device accordingly. If auto-negotiation is enabled, then software 1288 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1289 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1290 * auto-negotiation is disabled, then software will have to manually 1291 * configure the two flow control enable bits in the CTRL register. 1292 * 1293 * The possible values of the "fc" parameter are: 1294 * 0: Flow control is completely disabled 1295 * 1: Rx flow control is enabled (we can receive pause frames, but 1296 * not send pause frames). 1297 * 2: Tx flow control is enabled (we can send pause frames but we do 1298 * not support receiving pause frames). 1299 * 3: Both Rx and TX flow control (symmetric) are enabled. 1300 */ 1301 switch (hw->fc) { 1302 case E1000_FC_NONE: 1303 /* Flow control is completely disabled by a software over-ride. */ 1304 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1305 break; 1306 case E1000_FC_RX_PAUSE: 1307 /* RX Flow control is enabled and TX Flow control is disabled by a 1308 * software over-ride. Since there really isn't a way to advertise 1309 * that we are capable of RX Pause ONLY, we will advertise that we 1310 * support both symmetric and asymmetric RX PAUSE. Later, we will 1311 * disable the adapter's ability to send PAUSE frames. 1312 */ 1313 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1314 break; 1315 case E1000_FC_TX_PAUSE: 1316 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1317 * software over-ride. 1318 */ 1319 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1320 break; 1321 case E1000_FC_FULL: 1322 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1323 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1324 break; 1325 default: 1326 DEBUGOUT("Flow control param set incorrectly\n"); 1327 return -E1000_ERR_CONFIG; 1328 break; 1329 } 1330 1331 /* Since auto-negotiation is enabled, take the link out of reset (the link 1332 * will be in reset, because we previously reset the chip). This will 1333 * restart auto-negotiation. If auto-neogtiation is successful then the 1334 * link-up status bit will be set and the flow control enable bits (RFCE 1335 * and TFCE) will be set according to their negotiated value. 1336 */ 1337 DEBUGOUT("Auto-negotiation enabled\n"); 1338 1339 E1000_WRITE_REG(hw, TXCW, txcw); 1340 E1000_WRITE_REG(hw, CTRL, ctrl); 1341 E1000_WRITE_FLUSH(hw); 1342 1343 hw->txcw = txcw; 1344 msleep(1); 1345 1346 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1347 * indication in the Device Status Register. Time-out if a link isn't 1348 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1349 * less than 500 milliseconds even if the other end is doing it in SW). 1350 * For internal serdes, we just assume a signal is present, then poll. 1351 */ 1352 if (hw->media_type == e1000_media_type_internal_serdes || 1353 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1354 DEBUGOUT("Looking for Link\n"); 1355 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1356 msleep(10); 1357 status = E1000_READ_REG(hw, STATUS); 1358 if (status & E1000_STATUS_LU) break; 1359 } 1360 if (i == (LINK_UP_TIMEOUT / 10)) { 1361 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1362 hw->autoneg_failed = 1; 1363 /* AutoNeg failed to achieve a link, so we'll call 1364 * e1000_check_for_link. This routine will force the link up if 1365 * we detect a signal. This will allow us to communicate with 1366 * non-autonegotiating link partners. 1367 */ 1368 ret_val = e1000_check_for_link(hw); 1369 if (ret_val) { 1370 DEBUGOUT("Error while checking for link\n"); 1371 return ret_val; 1372 } 1373 hw->autoneg_failed = 0; 1374 } else { 1375 hw->autoneg_failed = 0; 1376 DEBUGOUT("Valid Link Found\n"); 1377 } 1378 } else { 1379 DEBUGOUT("No Signal Detected\n"); 1380 } 1381 return E1000_SUCCESS; 1382} 1383 1384/****************************************************************************** 1385* Make sure we have a valid PHY and change PHY mode before link setup. 1386* 1387* hw - Struct containing variables accessed by shared code 1388******************************************************************************/ 1389static int32_t 1390e1000_copper_link_preconfig(struct e1000_hw *hw) 1391{ 1392 uint32_t ctrl; 1393 int32_t ret_val; 1394 uint16_t phy_data; 1395 1396 DEBUGFUNC("e1000_copper_link_preconfig"); 1397 1398 ctrl = E1000_READ_REG(hw, CTRL); 1399 /* With 82543, we need to force speed and duplex on the MAC equal to what 1400 * the PHY speed and duplex configuration is. In addition, we need to 1401 * perform a hardware reset on the PHY to take it out of reset. 1402 */ 1403 if (hw->mac_type > e1000_82543) { 1404 ctrl |= E1000_CTRL_SLU; 1405 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1406 E1000_WRITE_REG(hw, CTRL, ctrl); 1407 } else { 1408 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1409 E1000_WRITE_REG(hw, CTRL, ctrl); 1410 ret_val = e1000_phy_hw_reset(hw); 1411 if (ret_val) 1412 return ret_val; 1413 } 1414 1415 /* Make sure we have a valid PHY */ 1416 ret_val = e1000_detect_gig_phy(hw); 1417 if (ret_val) { 1418 DEBUGOUT("Error, did not detect valid phy.\n"); 1419 return ret_val; 1420 } 1421 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1422 1423 /* Set PHY to class A mode (if necessary) */ 1424 ret_val = e1000_set_phy_mode(hw); 1425 if (ret_val) 1426 return ret_val; 1427 1428 if ((hw->mac_type == e1000_82545_rev_3) || 1429 (hw->mac_type == e1000_82546_rev_3)) { 1430 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1431 phy_data |= 0x00000008; 1432 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1433 } 1434 1435 if (hw->mac_type <= e1000_82543 || 1436 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1437 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1438 hw->phy_reset_disable = FALSE; 1439 1440 return E1000_SUCCESS; 1441} 1442 1443 1444/******************************************************************** 1445* Copper link setup for e1000_phy_igp series. 1446* 1447* hw - Struct containing variables accessed by shared code 1448*********************************************************************/ 1449static int32_t 1450e1000_copper_link_igp_setup(struct e1000_hw *hw) 1451{ 1452 uint32_t led_ctrl; 1453 int32_t ret_val; 1454 uint16_t phy_data; 1455 1456 DEBUGFUNC("e1000_copper_link_igp_setup"); 1457 1458 if (hw->phy_reset_disable) 1459 return E1000_SUCCESS; 1460 1461 ret_val = e1000_phy_reset(hw); 1462 if (ret_val) { 1463 DEBUGOUT("Error Resetting the PHY\n"); 1464 return ret_val; 1465 } 1466 1467 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1468 msleep(15); 1469 if (hw->mac_type != e1000_ich8lan) { 1470 /* Configure activity LED after PHY reset */ 1471 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1472 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1473 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1474 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1475 } 1476 1477 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1478 if (hw->phy_type == e1000_phy_igp) { 1479 /* disable lplu d3 during driver init */ 1480 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1481 if (ret_val) { 1482 DEBUGOUT("Error Disabling LPLU D3\n"); 1483 return ret_val; 1484 } 1485 } 1486 1487 /* disable lplu d0 during driver init */ 1488 ret_val = e1000_set_d0_lplu_state(hw, FALSE); 1489 if (ret_val) { 1490 DEBUGOUT("Error Disabling LPLU D0\n"); 1491 return ret_val; 1492 } 1493 /* Configure mdi-mdix settings */ 1494 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1495 if (ret_val) 1496 return ret_val; 1497 1498 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1499 hw->dsp_config_state = e1000_dsp_config_disabled; 1500 /* Force MDI for earlier revs of the IGP PHY */ 1501 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); 1502 hw->mdix = 1; 1503 1504 } else { 1505 hw->dsp_config_state = e1000_dsp_config_enabled; 1506 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1507 1508 switch (hw->mdix) { 1509 case 1: 1510 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1511 break; 1512 case 2: 1513 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1514 break; 1515 case 0: 1516 default: 1517 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1518 break; 1519 } 1520 } 1521 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1522 if (ret_val) 1523 return ret_val; 1524 1525 /* set auto-master slave resolution settings */ 1526 if (hw->autoneg) { 1527 e1000_ms_type phy_ms_setting = hw->master_slave; 1528 1529 if (hw->ffe_config_state == e1000_ffe_config_active) 1530 hw->ffe_config_state = e1000_ffe_config_enabled; 1531 1532 if (hw->dsp_config_state == e1000_dsp_config_activated) 1533 hw->dsp_config_state = e1000_dsp_config_enabled; 1534 1535 /* when autonegotiation advertisment is only 1000Mbps then we 1536 * should disable SmartSpeed and enable Auto MasterSlave 1537 * resolution as hardware default. */ 1538 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1539 /* Disable SmartSpeed */ 1540 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1541 &phy_data); 1542 if (ret_val) 1543 return ret_val; 1544 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1545 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1546 phy_data); 1547 if (ret_val) 1548 return ret_val; 1549 /* Set auto Master/Slave resolution process */ 1550 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1551 if (ret_val) 1552 return ret_val; 1553 phy_data &= ~CR_1000T_MS_ENABLE; 1554 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1555 if (ret_val) 1556 return ret_val; 1557 } 1558 1559 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1560 if (ret_val) 1561 return ret_val; 1562 1563 /* load defaults for future use */ 1564 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1565 ((phy_data & CR_1000T_MS_VALUE) ? 1566 e1000_ms_force_master : 1567 e1000_ms_force_slave) : 1568 e1000_ms_auto; 1569 1570 switch (phy_ms_setting) { 1571 case e1000_ms_force_master: 1572 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1573 break; 1574 case e1000_ms_force_slave: 1575 phy_data |= CR_1000T_MS_ENABLE; 1576 phy_data &= ~(CR_1000T_MS_VALUE); 1577 break; 1578 case e1000_ms_auto: 1579 phy_data &= ~CR_1000T_MS_ENABLE; 1580 default: 1581 break; 1582 } 1583 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1584 if (ret_val) 1585 return ret_val; 1586 } 1587 1588 return E1000_SUCCESS; 1589} 1590 1591/******************************************************************** 1592* Copper link setup for e1000_phy_gg82563 series. 1593* 1594* hw - Struct containing variables accessed by shared code 1595*********************************************************************/ 1596static int32_t 1597e1000_copper_link_ggp_setup(struct e1000_hw *hw) 1598{ 1599 int32_t ret_val; 1600 uint16_t phy_data; 1601 uint32_t reg_data; 1602 1603 DEBUGFUNC("e1000_copper_link_ggp_setup"); 1604 1605 if (!hw->phy_reset_disable) { 1606 1607 /* Enable CRS on TX for half-duplex operation. */ 1608 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1609 &phy_data); 1610 if (ret_val) 1611 return ret_val; 1612 1613 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1614 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 1615 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 1616 1617 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1618 phy_data); 1619 if (ret_val) 1620 return ret_val; 1621 1622 /* Options: 1623 * MDI/MDI-X = 0 (default) 1624 * 0 - Auto for all speeds 1625 * 1 - MDI mode 1626 * 2 - MDI-X mode 1627 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1628 */ 1629 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); 1630 if (ret_val) 1631 return ret_val; 1632 1633 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1634 1635 switch (hw->mdix) { 1636 case 1: 1637 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1638 break; 1639 case 2: 1640 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1641 break; 1642 case 0: 1643 default: 1644 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1645 break; 1646 } 1647 1648 /* Options: 1649 * disable_polarity_correction = 0 (default) 1650 * Automatic Correction for Reversed Cable Polarity 1651 * 0 - Disabled 1652 * 1 - Enabled 1653 */ 1654 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1655 if (hw->disable_polarity_correction == 1) 1656 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1657 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 1658 1659 if (ret_val) 1660 return ret_val; 1661 1662 /* SW Reset the PHY so all changes take effect */ 1663 ret_val = e1000_phy_reset(hw); 1664 if (ret_val) { 1665 DEBUGOUT("Error Resetting the PHY\n"); 1666 return ret_val; 1667 } 1668 } /* phy_reset_disable */ 1669 1670 if (hw->mac_type == e1000_80003es2lan) { 1671 /* Bypass RX and TX FIFO's */ 1672 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 1673 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 1674 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 1675 if (ret_val) 1676 return ret_val; 1677 1678 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); 1679 if (ret_val) 1680 return ret_val; 1681 1682 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1683 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); 1684 1685 if (ret_val) 1686 return ret_val; 1687 1688 reg_data = E1000_READ_REG(hw, CTRL_EXT); 1689 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1690 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 1691 1692 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1693 &phy_data); 1694 if (ret_val) 1695 return ret_val; 1696 1697 /* Do not init these registers when the HW is in IAMT mode, since the 1698 * firmware will have already initialized them. We only initialize 1699 * them if the HW is not in IAMT mode. 1700 */ 1701 if (e1000_check_mng_mode(hw) == FALSE) { 1702 /* Enable Electrical Idle on the PHY */ 1703 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1704 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1705 phy_data); 1706 if (ret_val) 1707 return ret_val; 1708 1709 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1710 &phy_data); 1711 if (ret_val) 1712 return ret_val; 1713 1714 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1715 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1716 phy_data); 1717 1718 if (ret_val) 1719 return ret_val; 1720 } 1721 1722 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 1723 &phy_data); 1724 if (ret_val) 1725 return ret_val; 1726 phy_data |= GG82563_ICR_DIS_PADDING; 1727 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 1728 phy_data); 1729 if (ret_val) 1730 return ret_val; 1731 } 1732 1733 return E1000_SUCCESS; 1734} 1735 1736/******************************************************************** 1737* Copper link setup for e1000_phy_m88 series. 1738* 1739* hw - Struct containing variables accessed by shared code 1740*********************************************************************/ 1741static int32_t 1742e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1743{ 1744 int32_t ret_val; 1745 uint16_t phy_data; 1746 1747 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1748 1749 if (hw->phy_reset_disable) 1750 return E1000_SUCCESS; 1751 1752 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1753 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1754 if (ret_val) 1755 return ret_val; 1756 1757 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1758 1759 /* Options: 1760 * MDI/MDI-X = 0 (default) 1761 * 0 - Auto for all speeds 1762 * 1 - MDI mode 1763 * 2 - MDI-X mode 1764 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1765 */ 1766 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1767 1768 switch (hw->mdix) { 1769 case 1: 1770 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1771 break; 1772 case 2: 1773 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1774 break; 1775 case 3: 1776 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1777 break; 1778 case 0: 1779 default: 1780 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1781 break; 1782 } 1783 1784 /* Options: 1785 * disable_polarity_correction = 0 (default) 1786 * Automatic Correction for Reversed Cable Polarity 1787 * 0 - Disabled 1788 * 1 - Enabled 1789 */ 1790 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1791 if (hw->disable_polarity_correction == 1) 1792 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1793 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1794 if (ret_val) 1795 return ret_val; 1796 1797 if (hw->phy_revision < M88E1011_I_REV_4) { 1798 /* Force TX_CLK in the Extended PHY Specific Control Register 1799 * to 25MHz clock. 1800 */ 1801 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1802 if (ret_val) 1803 return ret_val; 1804 1805 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1806 1807 if ((hw->phy_revision == E1000_REVISION_2) && 1808 (hw->phy_id == M88E1111_I_PHY_ID)) { 1809 /* Vidalia Phy, set the downshift counter to 5x */ 1810 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1811 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1812 ret_val = e1000_write_phy_reg(hw, 1813 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1814 if (ret_val) 1815 return ret_val; 1816 } else { 1817 /* Configure Master and Slave downshift values */ 1818 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1819 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1820 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1821 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1822 ret_val = e1000_write_phy_reg(hw, 1823 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1824 if (ret_val) 1825 return ret_val; 1826 } 1827 } 1828 1829 /* SW Reset the PHY so all changes take effect */ 1830 ret_val = e1000_phy_reset(hw); 1831 if (ret_val) { 1832 DEBUGOUT("Error Resetting the PHY\n"); 1833 return ret_val; 1834 } 1835 1836 return E1000_SUCCESS; 1837} 1838 1839/******************************************************************** 1840* Setup auto-negotiation and flow control advertisements, 1841* and then perform auto-negotiation. 1842* 1843* hw - Struct containing variables accessed by shared code 1844*********************************************************************/ 1845static int32_t 1846e1000_copper_link_autoneg(struct e1000_hw *hw) 1847{ 1848 int32_t ret_val; 1849 uint16_t phy_data; 1850 1851 DEBUGFUNC("e1000_copper_link_autoneg"); 1852 1853 /* Perform some bounds checking on the hw->autoneg_advertised 1854 * parameter. If this variable is zero, then set it to the default. 1855 */ 1856 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1857 1858 /* If autoneg_advertised is zero, we assume it was not defaulted 1859 * by the calling code so we set to advertise full capability. 1860 */ 1861 if (hw->autoneg_advertised == 0) 1862 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1863 1864 /* IFE phy only supports 10/100 */ 1865 if (hw->phy_type == e1000_phy_ife) 1866 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 1867 1868 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1869 ret_val = e1000_phy_setup_autoneg(hw); 1870 if (ret_val) { 1871 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1872 return ret_val; 1873 } 1874 DEBUGOUT("Restarting Auto-Neg\n"); 1875 1876 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1877 * the Auto Neg Restart bit in the PHY control register. 1878 */ 1879 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1880 if (ret_val) 1881 return ret_val; 1882 1883 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1884 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1885 if (ret_val) 1886 return ret_val; 1887 1888 /* Does the user want to wait for Auto-Neg to complete here, or 1889 * check at a later time (for example, callback routine). 1890 */ 1891 if (hw->wait_autoneg_complete) { 1892 ret_val = e1000_wait_autoneg(hw); 1893 if (ret_val) { 1894 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1895 return ret_val; 1896 } 1897 } 1898 1899 hw->get_link_status = TRUE; 1900 1901 return E1000_SUCCESS; 1902} 1903 1904/****************************************************************************** 1905* Config the MAC and the PHY after link is up. 1906* 1) Set up the MAC to the current PHY speed/duplex 1907* if we are on 82543. If we 1908* are on newer silicon, we only need to configure 1909* collision distance in the Transmit Control Register. 1910* 2) Set up flow control on the MAC to that established with 1911* the link partner. 1912* 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1913* 1914* hw - Struct containing variables accessed by shared code 1915******************************************************************************/ 1916static int32_t 1917e1000_copper_link_postconfig(struct e1000_hw *hw) 1918{ 1919 int32_t ret_val; 1920 DEBUGFUNC("e1000_copper_link_postconfig"); 1921 1922 if (hw->mac_type >= e1000_82544) { 1923 e1000_config_collision_dist(hw); 1924 } else { 1925 ret_val = e1000_config_mac_to_phy(hw); 1926 if (ret_val) { 1927 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1928 return ret_val; 1929 } 1930 } 1931 ret_val = e1000_config_fc_after_link_up(hw); 1932 if (ret_val) { 1933 DEBUGOUT("Error Configuring Flow Control\n"); 1934 return ret_val; 1935 } 1936 1937 /* Config DSP to improve Giga link quality */ 1938 if (hw->phy_type == e1000_phy_igp) { 1939 ret_val = e1000_config_dsp_after_link_change(hw, TRUE); 1940 if (ret_val) { 1941 DEBUGOUT("Error Configuring DSP after link up\n"); 1942 return ret_val; 1943 } 1944 } 1945 1946 return E1000_SUCCESS; 1947} 1948 1949/****************************************************************************** 1950* Detects which PHY is present and setup the speed and duplex 1951* 1952* hw - Struct containing variables accessed by shared code 1953******************************************************************************/ 1954static int32_t 1955e1000_setup_copper_link(struct e1000_hw *hw) 1956{ 1957 int32_t ret_val; 1958 uint16_t i; 1959 uint16_t phy_data; 1960 uint16_t reg_data; 1961 1962 DEBUGFUNC("e1000_setup_copper_link"); 1963 1964 switch (hw->mac_type) { 1965 case e1000_80003es2lan: 1966 case e1000_ich8lan: 1967 /* Set the mac to wait the maximum time between each 1968 * iteration and increase the max iterations when 1969 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 1970 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 1971 if (ret_val) 1972 return ret_val; 1973 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 1974 if (ret_val) 1975 return ret_val; 1976 reg_data |= 0x3F; 1977 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 1978 if (ret_val) 1979 return ret_val; 1980 default: 1981 break; 1982 } 1983 1984 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1985 ret_val = e1000_copper_link_preconfig(hw); 1986 if (ret_val) 1987 return ret_val; 1988 1989 switch (hw->mac_type) { 1990 case e1000_80003es2lan: 1991 /* Kumeran registers are written-only */ 1992 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 1993 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 1994 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1995 reg_data); 1996 if (ret_val) 1997 return ret_val; 1998 break; 1999 default: 2000 break; 2001 } 2002 2003 if (hw->phy_type == e1000_phy_igp || 2004 hw->phy_type == e1000_phy_igp_3 || 2005 hw->phy_type == e1000_phy_igp_2) { 2006 ret_val = e1000_copper_link_igp_setup(hw); 2007 if (ret_val) 2008 return ret_val; 2009 } else if (hw->phy_type == e1000_phy_m88) { 2010 ret_val = e1000_copper_link_mgp_setup(hw); 2011 if (ret_val) 2012 return ret_val; 2013 } else if (hw->phy_type == e1000_phy_gg82563) { 2014 ret_val = e1000_copper_link_ggp_setup(hw); 2015 if (ret_val) 2016 return ret_val; 2017 } 2018 2019 if (hw->autoneg) { 2020 /* Setup autoneg and flow control advertisement 2021 * and perform autonegotiation */ 2022 ret_val = e1000_copper_link_autoneg(hw); 2023 if (ret_val) 2024 return ret_val; 2025 } else { 2026 /* PHY will be set to 10H, 10F, 100H,or 100F 2027 * depending on value from forced_speed_duplex. */ 2028 DEBUGOUT("Forcing speed and duplex\n"); 2029 ret_val = e1000_phy_force_speed_duplex(hw); 2030 if (ret_val) { 2031 DEBUGOUT("Error Forcing Speed and Duplex\n"); 2032 return ret_val; 2033 } 2034 } 2035 2036 /* Check link status. Wait up to 100 microseconds for link to become 2037 * valid. 2038 */ 2039 for (i = 0; i < 10; i++) { 2040 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2041 if (ret_val) 2042 return ret_val; 2043 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2044 if (ret_val) 2045 return ret_val; 2046 2047 if (phy_data & MII_SR_LINK_STATUS) { 2048 /* Config the MAC and PHY after link is up */ 2049 ret_val = e1000_copper_link_postconfig(hw); 2050 if (ret_val) 2051 return ret_val; 2052 2053 DEBUGOUT("Valid link established!!!\n"); 2054 return E1000_SUCCESS; 2055 } 2056 udelay(10); 2057 } 2058 2059 DEBUGOUT("Unable to establish link!!!\n"); 2060 return E1000_SUCCESS; 2061} 2062 2063/****************************************************************************** 2064* Configure the MAC-to-PHY interface for 10/100Mbps 2065* 2066* hw - Struct containing variables accessed by shared code 2067******************************************************************************/ 2068static int32_t 2069e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 2070{ 2071 int32_t ret_val = E1000_SUCCESS; 2072 uint32_t tipg; 2073 uint16_t reg_data; 2074 2075 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 2076 2077 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 2078 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2079 reg_data); 2080 if (ret_val) 2081 return ret_val; 2082 2083 /* Configure Transmit Inter-Packet Gap */ 2084 tipg = E1000_READ_REG(hw, TIPG); 2085 tipg &= ~E1000_TIPG_IPGT_MASK; 2086 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2087 E1000_WRITE_REG(hw, TIPG, tipg); 2088 2089 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2090 2091 if (ret_val) 2092 return ret_val; 2093 2094 if (duplex == HALF_DUPLEX) 2095 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 2096 else 2097 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2098 2099 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2100 2101 return ret_val; 2102} 2103 2104static int32_t 2105e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 2106{ 2107 int32_t ret_val = E1000_SUCCESS; 2108 uint16_t reg_data; 2109 uint32_t tipg; 2110 2111 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 2112 2113 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 2114 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2115 reg_data); 2116 if (ret_val) 2117 return ret_val; 2118 2119 /* Configure Transmit Inter-Packet Gap */ 2120 tipg = E1000_READ_REG(hw, TIPG); 2121 tipg &= ~E1000_TIPG_IPGT_MASK; 2122 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2123 E1000_WRITE_REG(hw, TIPG, tipg); 2124 2125 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2126 2127 if (ret_val) 2128 return ret_val; 2129 2130 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2131 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2132 2133 return ret_val; 2134} 2135 2136/****************************************************************************** 2137* Configures PHY autoneg and flow control advertisement settings 2138* 2139* hw - Struct containing variables accessed by shared code 2140******************************************************************************/ 2141int32_t 2142e1000_phy_setup_autoneg(struct e1000_hw *hw) 2143{ 2144 int32_t ret_val; 2145 uint16_t mii_autoneg_adv_reg; 2146 uint16_t mii_1000t_ctrl_reg; 2147 2148 DEBUGFUNC("e1000_phy_setup_autoneg"); 2149 2150 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2151 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2152 if (ret_val) 2153 return ret_val; 2154 2155 if (hw->phy_type != e1000_phy_ife) { 2156 /* Read the MII 1000Base-T Control Register (Address 9). */ 2157 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 2158 if (ret_val) 2159 return ret_val; 2160 } else 2161 mii_1000t_ctrl_reg=0; 2162 2163 /* Need to parse both autoneg_advertised and fc and set up 2164 * the appropriate PHY registers. First we will parse for 2165 * autoneg_advertised software override. Since we can advertise 2166 * a plethora of combinations, we need to check each bit 2167 * individually. 2168 */ 2169 2170 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2171 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2172 * the 1000Base-T Control Register (Address 9). 2173 */ 2174 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 2175 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 2176 2177 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2178 2179 /* Do we want to advertise 10 Mb Half Duplex? */ 2180 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 2181 DEBUGOUT("Advertise 10mb Half duplex\n"); 2182 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2183 } 2184 2185 /* Do we want to advertise 10 Mb Full Duplex? */ 2186 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 2187 DEBUGOUT("Advertise 10mb Full duplex\n"); 2188 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2189 } 2190 2191 /* Do we want to advertise 100 Mb Half Duplex? */ 2192 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 2193 DEBUGOUT("Advertise 100mb Half duplex\n"); 2194 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2195 } 2196 2197 /* Do we want to advertise 100 Mb Full Duplex? */ 2198 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 2199 DEBUGOUT("Advertise 100mb Full duplex\n"); 2200 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2201 } 2202 2203 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2204 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2205 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); 2206 } 2207 2208 /* Do we want to advertise 1000 Mb Full Duplex? */ 2209 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2210 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2211 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2212 if (hw->phy_type == e1000_phy_ife) { 2213 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); 2214 } 2215 } 2216 2217 /* Check for a software override of the flow control settings, and 2218 * setup the PHY advertisement registers accordingly. If 2219 * auto-negotiation is enabled, then software will have to set the 2220 * "PAUSE" bits to the correct value in the Auto-Negotiation 2221 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 2222 * 2223 * The possible values of the "fc" parameter are: 2224 * 0: Flow control is completely disabled 2225 * 1: Rx flow control is enabled (we can receive pause frames 2226 * but not send pause frames). 2227 * 2: Tx flow control is enabled (we can send pause frames 2228 * but we do not support receiving pause frames). 2229 * 3: Both Rx and TX flow control (symmetric) are enabled. 2230 * other: No software override. The flow control configuration 2231 * in the EEPROM is used. 2232 */ 2233 switch (hw->fc) { 2234 case E1000_FC_NONE: /* 0 */ 2235 /* Flow control (RX & TX) is completely disabled by a 2236 * software over-ride. 2237 */ 2238 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2239 break; 2240 case E1000_FC_RX_PAUSE: /* 1 */ 2241 /* RX Flow control is enabled, and TX Flow control is 2242 * disabled, by a software over-ride. 2243 */ 2244 /* Since there really isn't a way to advertise that we are 2245 * capable of RX Pause ONLY, we will advertise that we 2246 * support both symmetric and asymmetric RX PAUSE. Later 2247 * (in e1000_config_fc_after_link_up) we will disable the 2248 *hw's ability to send PAUSE frames. 2249 */ 2250 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2251 break; 2252 case E1000_FC_TX_PAUSE: /* 2 */ 2253 /* TX Flow control is enabled, and RX Flow control is 2254 * disabled, by a software over-ride. 2255 */ 2256 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 2257 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 2258 break; 2259 case E1000_FC_FULL: /* 3 */ 2260 /* Flow control (both RX and TX) is enabled by a software 2261 * over-ride. 2262 */ 2263 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2264 break; 2265 default: 2266 DEBUGOUT("Flow control param set incorrectly\n"); 2267 return -E1000_ERR_CONFIG; 2268 } 2269 2270 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2271 if (ret_val) 2272 return ret_val; 2273 2274 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2275 2276 if (hw->phy_type != e1000_phy_ife) { 2277 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 2278 if (ret_val) 2279 return ret_val; 2280 } 2281 2282 return E1000_SUCCESS; 2283} 2284 2285/****************************************************************************** 2286* Force PHY speed and duplex settings to hw->forced_speed_duplex 2287* 2288* hw - Struct containing variables accessed by shared code 2289******************************************************************************/ 2290static int32_t 2291e1000_phy_force_speed_duplex(struct e1000_hw *hw) 2292{ 2293 uint32_t ctrl; 2294 int32_t ret_val; 2295 uint16_t mii_ctrl_reg; 2296 uint16_t mii_status_reg; 2297 uint16_t phy_data; 2298 uint16_t i; 2299 2300 DEBUGFUNC("e1000_phy_force_speed_duplex"); 2301 2302 /* Turn off Flow control if we are forcing speed and duplex. */ 2303 hw->fc = E1000_FC_NONE; 2304 2305 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2306 2307 /* Read the Device Control Register. */ 2308 ctrl = E1000_READ_REG(hw, CTRL); 2309 2310 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 2311 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2312 ctrl &= ~(DEVICE_SPEED_MASK); 2313 2314 /* Clear the Auto Speed Detect Enable bit. */ 2315 ctrl &= ~E1000_CTRL_ASDE; 2316 2317 /* Read the MII Control Register. */ 2318 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2319 if (ret_val) 2320 return ret_val; 2321 2322 /* We need to disable autoneg in order to force link and duplex. */ 2323 2324 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2325 2326 /* Are we forcing Full or Half Duplex? */ 2327 if (hw->forced_speed_duplex == e1000_100_full || 2328 hw->forced_speed_duplex == e1000_10_full) { 2329 /* We want to force full duplex so we SET the full duplex bits in the 2330 * Device and MII Control Registers. 2331 */ 2332 ctrl |= E1000_CTRL_FD; 2333 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 2334 DEBUGOUT("Full Duplex\n"); 2335 } else { 2336 /* We want to force half duplex so we CLEAR the full duplex bits in 2337 * the Device and MII Control Registers. 2338 */ 2339 ctrl &= ~E1000_CTRL_FD; 2340 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 2341 DEBUGOUT("Half Duplex\n"); 2342 } 2343 2344 /* Are we forcing 100Mbps??? */ 2345 if (hw->forced_speed_duplex == e1000_100_full || 2346 hw->forced_speed_duplex == e1000_100_half) { 2347 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 2348 ctrl |= E1000_CTRL_SPD_100; 2349 mii_ctrl_reg |= MII_CR_SPEED_100; 2350 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 2351 DEBUGOUT("Forcing 100mb "); 2352 } else { 2353 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 2354 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2355 mii_ctrl_reg |= MII_CR_SPEED_10; 2356 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2357 DEBUGOUT("Forcing 10mb "); 2358 } 2359 2360 e1000_config_collision_dist(hw); 2361 2362 /* Write the configured values back to the Device Control Reg. */ 2363 E1000_WRITE_REG(hw, CTRL, ctrl); 2364 2365 if ((hw->phy_type == e1000_phy_m88) || 2366 (hw->phy_type == e1000_phy_gg82563)) { 2367 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2368 if (ret_val) 2369 return ret_val; 2370 2371 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 2372 * forced whenever speed are duplex are forced. 2373 */ 2374 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2375 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2376 if (ret_val) 2377 return ret_val; 2378 2379 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 2380 2381 /* Need to reset the PHY or these changes will be ignored */ 2382 mii_ctrl_reg |= MII_CR_RESET; 2383 2384 /* Disable MDI-X support for 10/100 */ 2385 } else if (hw->phy_type == e1000_phy_ife) { 2386 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 2387 if (ret_val) 2388 return ret_val; 2389 2390 phy_data &= ~IFE_PMC_AUTO_MDIX; 2391 phy_data &= ~IFE_PMC_FORCE_MDIX; 2392 2393 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 2394 if (ret_val) 2395 return ret_val; 2396 2397 } else { 2398 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2399 * forced whenever speed or duplex are forced. 2400 */ 2401 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2402 if (ret_val) 2403 return ret_val; 2404 2405 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2406 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2407 2408 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2409 if (ret_val) 2410 return ret_val; 2411 } 2412 2413 /* Write back the modified PHY MII control register. */ 2414 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 2415 if (ret_val) 2416 return ret_val; 2417 2418 udelay(1); 2419 2420 /* The wait_autoneg_complete flag may be a little misleading here. 2421 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 2422 * But we do want to delay for a period while forcing only so we 2423 * don't generate false No Link messages. So we will wait here 2424 * only if the user has set wait_autoneg_complete to 1, which is 2425 * the default. 2426 */ 2427 if (hw->wait_autoneg_complete) { 2428 /* We will wait for autoneg to complete. */ 2429 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 2430 mii_status_reg = 0; 2431 2432 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2433 for (i = PHY_FORCE_TIME; i > 0; i--) { 2434 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2435 * to be set. 2436 */ 2437 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2438 if (ret_val) 2439 return ret_val; 2440 2441 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2442 if (ret_val) 2443 return ret_val; 2444 2445 if (mii_status_reg & MII_SR_LINK_STATUS) break; 2446 msleep(100); 2447 } 2448 if ((i == 0) && 2449 ((hw->phy_type == e1000_phy_m88) || 2450 (hw->phy_type == e1000_phy_gg82563))) { 2451 /* We didn't get link. Reset the DSP and wait again for link. */ 2452 ret_val = e1000_phy_reset_dsp(hw); 2453 if (ret_val) { 2454 DEBUGOUT("Error Resetting PHY DSP\n"); 2455 return ret_val; 2456 } 2457 } 2458 /* This loop will early-out if the link condition has been met. */ 2459 for (i = PHY_FORCE_TIME; i > 0; i--) { 2460 if (mii_status_reg & MII_SR_LINK_STATUS) break; 2461 msleep(100); 2462 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2463 * to be set. 2464 */ 2465 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2466 if (ret_val) 2467 return ret_val; 2468 2469 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2470 if (ret_val) 2471 return ret_val; 2472 } 2473 } 2474 2475 if (hw->phy_type == e1000_phy_m88) { 2476 /* Because we reset the PHY above, we need to re-force TX_CLK in the 2477 * Extended PHY Specific Control Register to 25MHz clock. This value 2478 * defaults back to a 2.5MHz clock when the PHY is reset. 2479 */ 2480 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2481 if (ret_val) 2482 return ret_val; 2483 2484 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2485 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2486 if (ret_val) 2487 return ret_val; 2488 2489 /* In addition, because of the s/w reset above, we need to enable CRS on 2490 * TX. This must be set for both full and half duplex operation. 2491 */ 2492 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2493 if (ret_val) 2494 return ret_val; 2495 2496 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2497 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2498 if (ret_val) 2499 return ret_val; 2500 2501 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2502 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || 2503 hw->forced_speed_duplex == e1000_10_half)) { 2504 ret_val = e1000_polarity_reversal_workaround(hw); 2505 if (ret_val) 2506 return ret_val; 2507 } 2508 } else if (hw->phy_type == e1000_phy_gg82563) { 2509 /* The TX_CLK of the Extended PHY Specific Control Register defaults 2510 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if 2511 * we're not in a forced 10/duplex configuration. */ 2512 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2513 if (ret_val) 2514 return ret_val; 2515 2516 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 2517 if ((hw->forced_speed_duplex == e1000_10_full) || 2518 (hw->forced_speed_duplex == e1000_10_half)) 2519 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 2520 else 2521 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 2522 2523 /* Also due to the reset, we need to enable CRS on Tx. */ 2524 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2525 2526 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2527 if (ret_val) 2528 return ret_val; 2529 } 2530 return E1000_SUCCESS; 2531} 2532 2533/****************************************************************************** 2534* Sets the collision distance in the Transmit Control register 2535* 2536* hw - Struct containing variables accessed by shared code 2537* 2538* Link should have been established previously. Reads the speed and duplex 2539* information from the Device Status register. 2540******************************************************************************/ 2541void 2542e1000_config_collision_dist(struct e1000_hw *hw) 2543{ 2544 uint32_t tctl, coll_dist; 2545 2546 DEBUGFUNC("e1000_config_collision_dist"); 2547 2548 if (hw->mac_type < e1000_82543) 2549 coll_dist = E1000_COLLISION_DISTANCE_82542; 2550 else 2551 coll_dist = E1000_COLLISION_DISTANCE; 2552 2553 tctl = E1000_READ_REG(hw, TCTL); 2554 2555 tctl &= ~E1000_TCTL_COLD; 2556 tctl |= coll_dist << E1000_COLD_SHIFT; 2557 2558 E1000_WRITE_REG(hw, TCTL, tctl); 2559 E1000_WRITE_FLUSH(hw); 2560} 2561 2562/****************************************************************************** 2563* Sets MAC speed and duplex settings to reflect the those in the PHY 2564* 2565* hw - Struct containing variables accessed by shared code 2566* mii_reg - data to write to the MII control register 2567* 2568* The contents of the PHY register containing the needed information need to 2569* be passed in. 2570******************************************************************************/ 2571static int32_t 2572e1000_config_mac_to_phy(struct e1000_hw *hw) 2573{ 2574 uint32_t ctrl; 2575 int32_t ret_val; 2576 uint16_t phy_data; 2577 2578 DEBUGFUNC("e1000_config_mac_to_phy"); 2579 2580 /* 82544 or newer MAC, Auto Speed Detection takes care of 2581 * MAC speed/duplex configuration.*/ 2582 if (hw->mac_type >= e1000_82544) 2583 return E1000_SUCCESS; 2584 2585 /* Read the Device Control Register and set the bits to Force Speed 2586 * and Duplex. 2587 */ 2588 ctrl = E1000_READ_REG(hw, CTRL); 2589 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2590 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 2591 2592 /* Set up duplex in the Device Control and Transmit Control 2593 * registers depending on negotiated values. 2594 */ 2595 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2596 if (ret_val) 2597 return ret_val; 2598 2599 if (phy_data & M88E1000_PSSR_DPLX) 2600 ctrl |= E1000_CTRL_FD; 2601 else 2602 ctrl &= ~E1000_CTRL_FD; 2603 2604 e1000_config_collision_dist(hw); 2605 2606 /* Set up speed in the Device Control register depending on 2607 * negotiated values. 2608 */ 2609 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 2610 ctrl |= E1000_CTRL_SPD_1000; 2611 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 2612 ctrl |= E1000_CTRL_SPD_100; 2613 2614 /* Write the configured values back to the Device Control Reg. */ 2615 E1000_WRITE_REG(hw, CTRL, ctrl); 2616 return E1000_SUCCESS; 2617} 2618 2619/****************************************************************************** 2620 * Forces the MAC's flow control settings. 2621 * 2622 * hw - Struct containing variables accessed by shared code 2623 * 2624 * Sets the TFCE and RFCE bits in the device control register to reflect 2625 * the adapter settings. TFCE and RFCE need to be explicitly set by 2626 * software when a Copper PHY is used because autonegotiation is managed 2627 * by the PHY rather than the MAC. Software must also configure these 2628 * bits when link is forced on a fiber connection. 2629 *****************************************************************************/ 2630int32_t 2631e1000_force_mac_fc(struct e1000_hw *hw) 2632{ 2633 uint32_t ctrl; 2634 2635 DEBUGFUNC("e1000_force_mac_fc"); 2636 2637 /* Get the current configuration of the Device Control Register */ 2638 ctrl = E1000_READ_REG(hw, CTRL); 2639 2640 /* Because we didn't get link via the internal auto-negotiation 2641 * mechanism (we either forced link or we got link via PHY 2642 * auto-neg), we have to manually enable/disable transmit an 2643 * receive flow control. 2644 * 2645 * The "Case" statement below enables/disable flow control 2646 * according to the "hw->fc" parameter. 2647 * 2648 * The possible values of the "fc" parameter are: 2649 * 0: Flow control is completely disabled 2650 * 1: Rx flow control is enabled (we can receive pause 2651 * frames but not send pause frames). 2652 * 2: Tx flow control is enabled (we can send pause frames 2653 * frames but we do not receive pause frames). 2654 * 3: Both Rx and TX flow control (symmetric) is enabled. 2655 * other: No other values should be possible at this point. 2656 */ 2657 2658 switch (hw->fc) { 2659 case E1000_FC_NONE: 2660 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 2661 break; 2662 case E1000_FC_RX_PAUSE: 2663 ctrl &= (~E1000_CTRL_TFCE); 2664 ctrl |= E1000_CTRL_RFCE; 2665 break; 2666 case E1000_FC_TX_PAUSE: 2667 ctrl &= (~E1000_CTRL_RFCE); 2668 ctrl |= E1000_CTRL_TFCE; 2669 break; 2670 case E1000_FC_FULL: 2671 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 2672 break; 2673 default: 2674 DEBUGOUT("Flow control param set incorrectly\n"); 2675 return -E1000_ERR_CONFIG; 2676 } 2677 2678 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2679 if (hw->mac_type == e1000_82542_rev2_0) 2680 ctrl &= (~E1000_CTRL_TFCE); 2681 2682 E1000_WRITE_REG(hw, CTRL, ctrl); 2683 return E1000_SUCCESS; 2684} 2685 2686/****************************************************************************** 2687 * Configures flow control settings after link is established 2688 * 2689 * hw - Struct containing variables accessed by shared code 2690 * 2691 * Should be called immediately after a valid link has been established. 2692 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 2693 * and autonegotiation is enabled, the MAC flow control settings will be set 2694 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2695 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 2696 *****************************************************************************/ 2697static int32_t 2698e1000_config_fc_after_link_up(struct e1000_hw *hw) 2699{ 2700 int32_t ret_val; 2701 uint16_t mii_status_reg; 2702 uint16_t mii_nway_adv_reg; 2703 uint16_t mii_nway_lp_ability_reg; 2704 uint16_t speed; 2705 uint16_t duplex; 2706 2707 DEBUGFUNC("e1000_config_fc_after_link_up"); 2708 2709 /* Check for the case where we have fiber media and auto-neg failed 2710 * so we had to force link. In this case, we need to force the 2711 * configuration of the MAC to match the "fc" parameter. 2712 */ 2713 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || 2714 ((hw->media_type == e1000_media_type_internal_serdes) && 2715 (hw->autoneg_failed)) || 2716 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { 2717 ret_val = e1000_force_mac_fc(hw); 2718 if (ret_val) { 2719 DEBUGOUT("Error forcing flow control settings\n"); 2720 return ret_val; 2721 } 2722 } 2723 2724 /* Check for the case where we have copper media and auto-neg is 2725 * enabled. In this case, we need to check and see if Auto-Neg 2726 * has completed, and if so, how the PHY and link partner has 2727 * flow control configured. 2728 */ 2729 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2730 /* Read the MII Status Register and check to see if AutoNeg 2731 * has completed. We read this twice because this reg has 2732 * some "sticky" (latched) bits. 2733 */ 2734 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2735 if (ret_val) 2736 return ret_val; 2737 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2738 if (ret_val) 2739 return ret_val; 2740 2741 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2742 /* The AutoNeg process has completed, so we now need to 2743 * read both the Auto Negotiation Advertisement Register 2744 * (Address 4) and the Auto_Negotiation Base Page Ability 2745 * Register (Address 5) to determine how flow control was 2746 * negotiated. 2747 */ 2748 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2749 &mii_nway_adv_reg); 2750 if (ret_val) 2751 return ret_val; 2752 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2753 &mii_nway_lp_ability_reg); 2754 if (ret_val) 2755 return ret_val; 2756 2757 /* Two bits in the Auto Negotiation Advertisement Register 2758 * (Address 4) and two bits in the Auto Negotiation Base 2759 * Page Ability Register (Address 5) determine flow control 2760 * for both the PHY and the link partner. The following 2761 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 2762 * 1999, describes these PAUSE resolution bits and how flow 2763 * control is determined based upon these settings. 2764 * NOTE: DC = Don't Care 2765 * 2766 * LOCAL DEVICE | LINK PARTNER 2767 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2768 *-------|---------|-------|---------|-------------------- 2769 * 0 | 0 | DC | DC | E1000_FC_NONE 2770 * 0 | 1 | 0 | DC | E1000_FC_NONE 2771 * 0 | 1 | 1 | 0 | E1000_FC_NONE 2772 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2773 * 1 | 0 | 0 | DC | E1000_FC_NONE 2774 * 1 | DC | 1 | DC | E1000_FC_FULL 2775 * 1 | 1 | 0 | 0 | E1000_FC_NONE 2776 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2777 * 2778 */ 2779 /* Are both PAUSE bits set to 1? If so, this implies 2780 * Symmetric Flow Control is enabled at both ends. The 2781 * ASM_DIR bits are irrelevant per the spec. 2782 * 2783 * For Symmetric Flow Control: 2784 * 2785 * LOCAL DEVICE | LINK PARTNER 2786 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2787 *-------|---------|-------|---------|-------------------- 2788 * 1 | DC | 1 | DC | E1000_FC_FULL 2789 * 2790 */ 2791 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2792 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2793 /* Now we need to check if the user selected RX ONLY 2794 * of pause frames. In this case, we had to advertise 2795 * FULL flow control because we could not advertise RX 2796 * ONLY. Hence, we must now check to see if we need to 2797 * turn OFF the TRANSMISSION of PAUSE frames. 2798 */ 2799 if (hw->original_fc == E1000_FC_FULL) { 2800 hw->fc = E1000_FC_FULL; 2801 DEBUGOUT("Flow Control = FULL.\n"); 2802 } else { 2803 hw->fc = E1000_FC_RX_PAUSE; 2804 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2805 } 2806 } 2807 /* For receiving PAUSE frames ONLY. 2808 * 2809 * LOCAL DEVICE | LINK PARTNER 2810 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2811 *-------|---------|-------|---------|-------------------- 2812 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2813 * 2814 */ 2815 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2816 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2817 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2818 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2819 hw->fc = E1000_FC_TX_PAUSE; 2820 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2821 } 2822 /* For transmitting PAUSE frames ONLY. 2823 * 2824 * LOCAL DEVICE | LINK PARTNER 2825 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2826 *-------|---------|-------|---------|-------------------- 2827 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2828 * 2829 */ 2830 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2831 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2832 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2833 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2834 hw->fc = E1000_FC_RX_PAUSE; 2835 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2836 } 2837 /* Per the IEEE spec, at this point flow control should be 2838 * disabled. However, we want to consider that we could 2839 * be connected to a legacy switch that doesn't advertise 2840 * desired flow control, but can be forced on the link 2841 * partner. So if we advertised no flow control, that is 2842 * what we will resolve to. If we advertised some kind of 2843 * receive capability (Rx Pause Only or Full Flow Control) 2844 * and the link partner advertised none, we will configure 2845 * ourselves to enable Rx Flow Control only. We can do 2846 * this safely for two reasons: If the link partner really 2847 * didn't want flow control enabled, and we enable Rx, no 2848 * harm done since we won't be receiving any PAUSE frames 2849 * anyway. If the intent on the link partner was to have 2850 * flow control enabled, then by us enabling RX only, we 2851 * can at least receive pause frames and process them. 2852 * This is a good idea because in most cases, since we are 2853 * predominantly a server NIC, more times than not we will 2854 * be asked to delay transmission of packets than asking 2855 * our link partner to pause transmission of frames. 2856 */ 2857 else if ((hw->original_fc == E1000_FC_NONE || 2858 hw->original_fc == E1000_FC_TX_PAUSE) || 2859 hw->fc_strict_ieee) { 2860 hw->fc = E1000_FC_NONE; 2861 DEBUGOUT("Flow Control = NONE.\n"); 2862 } else { 2863 hw->fc = E1000_FC_RX_PAUSE; 2864 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2865 } 2866 2867 /* Now we need to do one last check... If we auto- 2868 * negotiated to HALF DUPLEX, flow control should not be 2869 * enabled per IEEE 802.3 spec. 2870 */ 2871 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2872 if (ret_val) { 2873 DEBUGOUT("Error getting link speed and duplex\n"); 2874 return ret_val; 2875 } 2876 2877 if (duplex == HALF_DUPLEX) 2878 hw->fc = E1000_FC_NONE; 2879 2880 /* Now we call a subroutine to actually force the MAC 2881 * controller to use the correct flow control settings. 2882 */ 2883 ret_val = e1000_force_mac_fc(hw); 2884 if (ret_val) { 2885 DEBUGOUT("Error forcing flow control settings\n"); 2886 return ret_val; 2887 } 2888 } else { 2889 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 2890 } 2891 } 2892 return E1000_SUCCESS; 2893} 2894 2895/****************************************************************************** 2896 * Checks to see if the link status of the hardware has changed. 2897 * 2898 * hw - Struct containing variables accessed by shared code 2899 * 2900 * Called by any function that needs to check the link status of the adapter. 2901 *****************************************************************************/ 2902int32_t 2903e1000_check_for_link(struct e1000_hw *hw) 2904{ 2905 uint32_t rxcw = 0; 2906 uint32_t ctrl; 2907 uint32_t status; 2908 uint32_t rctl; 2909 uint32_t icr; 2910 uint32_t signal = 0; 2911 int32_t ret_val; 2912 uint16_t phy_data; 2913 2914 DEBUGFUNC("e1000_check_for_link"); 2915 2916 ctrl = E1000_READ_REG(hw, CTRL); 2917 status = E1000_READ_REG(hw, STATUS); 2918 2919 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 2920 * set when the optics detect a signal. On older adapters, it will be 2921 * cleared when there is a signal. This applies to fiber media only. 2922 */ 2923 if ((hw->media_type == e1000_media_type_fiber) || 2924 (hw->media_type == e1000_media_type_internal_serdes)) { 2925 rxcw = E1000_READ_REG(hw, RXCW); 2926 2927 if (hw->media_type == e1000_media_type_fiber) { 2928 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2929 if (status & E1000_STATUS_LU) 2930 hw->get_link_status = FALSE; 2931 } 2932 } 2933 2934 /* If we have a copper PHY then we only want to go out to the PHY 2935 * registers to see if Auto-Neg has completed and/or if our link 2936 * status has changed. The get_link_status flag will be set if we 2937 * receive a Link Status Change interrupt or we have Rx Sequence 2938 * Errors. 2939 */ 2940 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2941 /* First we want to see if the MII Status Register reports 2942 * link. If so, then we want to get the current speed/duplex 2943 * of the PHY. 2944 * Read the register twice since the link bit is sticky. 2945 */ 2946 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2947 if (ret_val) 2948 return ret_val; 2949 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2950 if (ret_val) 2951 return ret_val; 2952 2953 if (phy_data & MII_SR_LINK_STATUS) { 2954 hw->get_link_status = FALSE; 2955 /* Check if there was DownShift, must be checked immediately after 2956 * link-up */ 2957 e1000_check_downshift(hw); 2958 2959 2960 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2961 (!hw->autoneg) && 2962 (hw->forced_speed_duplex == e1000_10_full || 2963 hw->forced_speed_duplex == e1000_10_half)) { 2964 E1000_WRITE_REG(hw, IMC, 0xffffffff); 2965 ret_val = e1000_polarity_reversal_workaround(hw); 2966 icr = E1000_READ_REG(hw, ICR); 2967 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); 2968 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 2969 } 2970 2971 } else { 2972 /* No link detected */ 2973 e1000_config_dsp_after_link_change(hw, FALSE); 2974 return 0; 2975 } 2976 2977 /* If we are forcing speed/duplex, then we simply return since 2978 * we have already determined whether we have link or not. 2979 */ 2980 if (!hw->autoneg) return -E1000_ERR_CONFIG; 2981 2982 /* optimize the dsp settings for the igp phy */ 2983 e1000_config_dsp_after_link_change(hw, TRUE); 2984 2985 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2986 * have Si on board that is 82544 or newer, Auto 2987 * Speed Detection takes care of MAC speed/duplex 2988 * configuration. So we only need to configure Collision 2989 * Distance in the MAC. Otherwise, we need to force 2990 * speed/duplex on the MAC to the current PHY speed/duplex 2991 * settings. 2992 */ 2993 if (hw->mac_type >= e1000_82544) 2994 e1000_config_collision_dist(hw); 2995 else { 2996 ret_val = e1000_config_mac_to_phy(hw); 2997 if (ret_val) { 2998 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2999 return ret_val; 3000 } 3001 } 3002 3003 /* Configure Flow Control now that Auto-Neg has completed. First, we 3004 * need to restore the desired flow control settings because we may 3005 * have had to re-autoneg with a different link partner. 3006 */ 3007 ret_val = e1000_config_fc_after_link_up(hw); 3008 if (ret_val) { 3009 DEBUGOUT("Error configuring flow control\n"); 3010 return ret_val; 3011 } 3012 3013 /* At this point we know that we are on copper and we have 3014 * auto-negotiated link. These are conditions for checking the link 3015 * partner capability register. We use the link speed to determine if 3016 * TBI compatibility needs to be turned on or off. If the link is not 3017 * at gigabit speed, then TBI compatibility is not needed. If we are 3018 * at gigabit speed, we turn on TBI compatibility. 3019 */ 3020 if (hw->tbi_compatibility_en) { 3021 uint16_t speed, duplex; 3022 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 3023 if (ret_val) { 3024 DEBUGOUT("Error getting link speed and duplex\n"); 3025 return ret_val; 3026 } 3027 if (speed != SPEED_1000) { 3028 /* If link speed is not set to gigabit speed, we do not need 3029 * to enable TBI compatibility. 3030 */ 3031 if (hw->tbi_compatibility_on) { 3032 /* If we previously were in the mode, turn it off. */ 3033 rctl = E1000_READ_REG(hw, RCTL); 3034 rctl &= ~E1000_RCTL_SBP; 3035 E1000_WRITE_REG(hw, RCTL, rctl); 3036 hw->tbi_compatibility_on = FALSE; 3037 } 3038 } else { 3039 /* If TBI compatibility is was previously off, turn it on. For 3040 * compatibility with a TBI link partner, we will store bad 3041 * packets. Some frames have an additional byte on the end and 3042 * will look like CRC errors to to the hardware. 3043 */ 3044 if (!hw->tbi_compatibility_on) { 3045 hw->tbi_compatibility_on = TRUE; 3046 rctl = E1000_READ_REG(hw, RCTL); 3047 rctl |= E1000_RCTL_SBP; 3048 E1000_WRITE_REG(hw, RCTL, rctl); 3049 } 3050 } 3051 } 3052 } 3053 /* If we don't have link (auto-negotiation failed or link partner cannot 3054 * auto-negotiate), the cable is plugged in (we have signal), and our 3055 * link partner is not trying to auto-negotiate with us (we are receiving 3056 * idles or data), we need to force link up. We also need to give 3057 * auto-negotiation time to complete, in case the cable was just plugged 3058 * in. The autoneg_failed flag does this. 3059 */ 3060 else if ((((hw->media_type == e1000_media_type_fiber) && 3061 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 3062 (hw->media_type == e1000_media_type_internal_serdes)) && 3063 (!(status & E1000_STATUS_LU)) && 3064 (!(rxcw & E1000_RXCW_C))) { 3065 if (hw->autoneg_failed == 0) { 3066 hw->autoneg_failed = 1; 3067 return 0; 3068 } 3069 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 3070 3071 /* Disable auto-negotiation in the TXCW register */ 3072 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3073 3074 /* Force link-up and also force full-duplex. */ 3075 ctrl = E1000_READ_REG(hw, CTRL); 3076 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3077 E1000_WRITE_REG(hw, CTRL, ctrl); 3078 3079 /* Configure Flow Control after forcing link up. */ 3080 ret_val = e1000_config_fc_after_link_up(hw); 3081 if (ret_val) { 3082 DEBUGOUT("Error configuring flow control\n"); 3083 return ret_val; 3084 } 3085 } 3086 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3087 * auto-negotiation in the TXCW register and disable forced link in the 3088 * Device Control register in an attempt to auto-negotiate with our link 3089 * partner. 3090 */ 3091 else if (((hw->media_type == e1000_media_type_fiber) || 3092 (hw->media_type == e1000_media_type_internal_serdes)) && 3093 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3094 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 3095 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3096 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3097 3098 hw->serdes_link_down = FALSE; 3099 } 3100 /* If we force link for non-auto-negotiation switch, check link status 3101 * based on MAC synchronization for internal serdes media type. 3102 */ 3103 else if ((hw->media_type == e1000_media_type_internal_serdes) && 3104 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3105 /* SYNCH bit and IV bit are sticky. */ 3106 udelay(10); 3107 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3108 if (!(rxcw & E1000_RXCW_IV)) { 3109 hw->serdes_link_down = FALSE; 3110 DEBUGOUT("SERDES: Link is up.\n"); 3111 } 3112 } else { 3113 hw->serdes_link_down = TRUE; 3114 DEBUGOUT("SERDES: Link is down.\n"); 3115 } 3116 } 3117 if ((hw->media_type == e1000_media_type_internal_serdes) && 3118 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3119 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); 3120 } 3121 return E1000_SUCCESS; 3122} 3123 3124/****************************************************************************** 3125 * Detects the current speed and duplex settings of the hardware. 3126 * 3127 * hw - Struct containing variables accessed by shared code 3128 * speed - Speed of the connection 3129 * duplex - Duplex setting of the connection 3130 *****************************************************************************/ 3131int32_t 3132e1000_get_speed_and_duplex(struct e1000_hw *hw, 3133 uint16_t *speed, 3134 uint16_t *duplex) 3135{ 3136 uint32_t status; 3137 int32_t ret_val; 3138 uint16_t phy_data; 3139 3140 DEBUGFUNC("e1000_get_speed_and_duplex"); 3141 3142 if (hw->mac_type >= e1000_82543) { 3143 status = E1000_READ_REG(hw, STATUS); 3144 if (status & E1000_STATUS_SPEED_1000) { 3145 *speed = SPEED_1000; 3146 DEBUGOUT("1000 Mbs, "); 3147 } else if (status & E1000_STATUS_SPEED_100) { 3148 *speed = SPEED_100; 3149 DEBUGOUT("100 Mbs, "); 3150 } else { 3151 *speed = SPEED_10; 3152 DEBUGOUT("10 Mbs, "); 3153 } 3154 3155 if (status & E1000_STATUS_FD) { 3156 *duplex = FULL_DUPLEX; 3157 DEBUGOUT("Full Duplex\n"); 3158 } else { 3159 *duplex = HALF_DUPLEX; 3160 DEBUGOUT(" Half Duplex\n"); 3161 } 3162 } else { 3163 DEBUGOUT("1000 Mbs, Full Duplex\n"); 3164 *speed = SPEED_1000; 3165 *duplex = FULL_DUPLEX; 3166 } 3167 3168 /* IGP01 PHY may advertise full duplex operation after speed downgrade even 3169 * if it is operating at half duplex. Here we set the duplex settings to 3170 * match the duplex in the link partner's capabilities. 3171 */ 3172 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3173 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3174 if (ret_val) 3175 return ret_val; 3176 3177 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3178 *duplex = HALF_DUPLEX; 3179 else { 3180 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 3181 if (ret_val) 3182 return ret_val; 3183 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 3184 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3185 *duplex = HALF_DUPLEX; 3186 } 3187 } 3188 3189 if ((hw->mac_type == e1000_80003es2lan) && 3190 (hw->media_type == e1000_media_type_copper)) { 3191 if (*speed == SPEED_1000) 3192 ret_val = e1000_configure_kmrn_for_1000(hw); 3193 else 3194 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 3195 if (ret_val) 3196 return ret_val; 3197 } 3198 3199 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 3200 ret_val = e1000_kumeran_lock_loss_workaround(hw); 3201 if (ret_val) 3202 return ret_val; 3203 } 3204 3205 return E1000_SUCCESS; 3206} 3207 3208/****************************************************************************** 3209* Blocks until autoneg completes or times out (~4.5 seconds) 3210* 3211* hw - Struct containing variables accessed by shared code 3212******************************************************************************/ 3213static int32_t 3214e1000_wait_autoneg(struct e1000_hw *hw) 3215{ 3216 int32_t ret_val; 3217 uint16_t i; 3218 uint16_t phy_data; 3219 3220 DEBUGFUNC("e1000_wait_autoneg"); 3221 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3222 3223 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3224 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3225 /* Read the MII Status Register and wait for Auto-Neg 3226 * Complete bit to be set. 3227 */ 3228 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3229 if (ret_val) 3230 return ret_val; 3231 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3232 if (ret_val) 3233 return ret_val; 3234 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 3235 return E1000_SUCCESS; 3236 } 3237 msleep(100); 3238 } 3239 return E1000_SUCCESS; 3240} 3241 3242/****************************************************************************** 3243* Raises the Management Data Clock 3244* 3245* hw - Struct containing variables accessed by shared code 3246* ctrl - Device control register's current value 3247******************************************************************************/ 3248static void 3249e1000_raise_mdi_clk(struct e1000_hw *hw, 3250 uint32_t *ctrl) 3251{ 3252 /* Raise the clock input to the Management Data Clock (by setting the MDC 3253 * bit), and then delay 10 microseconds. 3254 */ 3255 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 3256 E1000_WRITE_FLUSH(hw); 3257 udelay(10); 3258} 3259 3260/****************************************************************************** 3261* Lowers the Management Data Clock 3262* 3263* hw - Struct containing variables accessed by shared code 3264* ctrl - Device control register's current value 3265******************************************************************************/ 3266static void 3267e1000_lower_mdi_clk(struct e1000_hw *hw, 3268 uint32_t *ctrl) 3269{ 3270 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3271 * bit), and then delay 10 microseconds. 3272 */ 3273 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 3274 E1000_WRITE_FLUSH(hw); 3275 udelay(10); 3276} 3277 3278/****************************************************************************** 3279* Shifts data bits out to the PHY 3280* 3281* hw - Struct containing variables accessed by shared code 3282* data - Data to send out to the PHY 3283* count - Number of bits to shift out 3284* 3285* Bits are shifted out in MSB to LSB order. 3286******************************************************************************/ 3287static void 3288e1000_shift_out_mdi_bits(struct e1000_hw *hw, 3289 uint32_t data, 3290 uint16_t count) 3291{ 3292 uint32_t ctrl; 3293 uint32_t mask; 3294 3295 /* We need to shift "count" number of bits out to the PHY. So, the value 3296 * in the "data" parameter will be shifted out to the PHY one bit at a 3297 * time. In order to do this, "data" must be broken down into bits. 3298 */ 3299 mask = 0x01; 3300 mask <<= (count - 1); 3301 3302 ctrl = E1000_READ_REG(hw, CTRL); 3303 3304 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3305 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3306 3307 while (mask) { 3308 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3309 * then raising and lowering the Management Data Clock. A "0" is 3310 * shifted out to the PHY by setting the MDIO bit to "0" and then 3311 * raising and lowering the clock. 3312 */ 3313 if (data & mask) 3314 ctrl |= E1000_CTRL_MDIO; 3315 else 3316 ctrl &= ~E1000_CTRL_MDIO; 3317 3318 E1000_WRITE_REG(hw, CTRL, ctrl); 3319 E1000_WRITE_FLUSH(hw); 3320 3321 udelay(10); 3322 3323 e1000_raise_mdi_clk(hw, &ctrl); 3324 e1000_lower_mdi_clk(hw, &ctrl); 3325 3326 mask = mask >> 1; 3327 } 3328} 3329 3330/****************************************************************************** 3331* Shifts data bits in from the PHY 3332* 3333* hw - Struct containing variables accessed by shared code 3334* 3335* Bits are shifted in in MSB to LSB order. 3336******************************************************************************/ 3337static uint16_t 3338e1000_shift_in_mdi_bits(struct e1000_hw *hw) 3339{ 3340 uint32_t ctrl; 3341 uint16_t data = 0; 3342 uint8_t i; 3343 3344 /* In order to read a register from the PHY, we need to shift in a total 3345 * of 18 bits from the PHY. The first two bit (turnaround) times are used 3346 * to avoid contention on the MDIO pin when a read operation is performed. 3347 * These two bits are ignored by us and thrown away. Bits are "shifted in" 3348 * by raising the input to the Management Data Clock (setting the MDC bit), 3349 * and then reading the value of the MDIO bit. 3350 */ 3351 ctrl = E1000_READ_REG(hw, CTRL); 3352 3353 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 3354 ctrl &= ~E1000_CTRL_MDIO_DIR; 3355 ctrl &= ~E1000_CTRL_MDIO; 3356 3357 E1000_WRITE_REG(hw, CTRL, ctrl); 3358 E1000_WRITE_FLUSH(hw); 3359 3360 /* Raise and Lower the clock before reading in the data. This accounts for 3361 * the turnaround bits. The first clock occurred when we clocked out the 3362 * last bit of the Register Address. 3363 */ 3364 e1000_raise_mdi_clk(hw, &ctrl); 3365 e1000_lower_mdi_clk(hw, &ctrl); 3366 3367 for (data = 0, i = 0; i < 16; i++) { 3368 data = data << 1; 3369 e1000_raise_mdi_clk(hw, &ctrl); 3370 ctrl = E1000_READ_REG(hw, CTRL); 3371 /* Check to see if we shifted in a "1". */ 3372 if (ctrl & E1000_CTRL_MDIO) 3373 data |= 1; 3374 e1000_lower_mdi_clk(hw, &ctrl); 3375 } 3376 3377 e1000_raise_mdi_clk(hw, &ctrl); 3378 e1000_lower_mdi_clk(hw, &ctrl); 3379 3380 return data; 3381} 3382 3383static int32_t 3384e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 3385{ 3386 uint32_t swfw_sync = 0; 3387 uint32_t swmask = mask; 3388 uint32_t fwmask = mask << 16; 3389 int32_t timeout = 200; 3390 3391 DEBUGFUNC("e1000_swfw_sync_acquire"); 3392 3393 if (hw->swfwhw_semaphore_present) 3394 return e1000_get_software_flag(hw); 3395 3396 if (!hw->swfw_sync_present) 3397 return e1000_get_hw_eeprom_semaphore(hw); 3398 3399 while (timeout) { 3400 if (e1000_get_hw_eeprom_semaphore(hw)) 3401 return -E1000_ERR_SWFW_SYNC; 3402 3403 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 3404 if (!(swfw_sync & (fwmask | swmask))) { 3405 break; 3406 } 3407 3408 /* firmware currently using resource (fwmask) */ 3409 /* or other software thread currently using resource (swmask) */ 3410 e1000_put_hw_eeprom_semaphore(hw); 3411 mdelay(5); 3412 timeout--; 3413 } 3414 3415 if (!timeout) { 3416 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 3417 return -E1000_ERR_SWFW_SYNC; 3418 } 3419 3420 swfw_sync |= swmask; 3421 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 3422 3423 e1000_put_hw_eeprom_semaphore(hw); 3424 return E1000_SUCCESS; 3425} 3426 3427static void 3428e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 3429{ 3430 uint32_t swfw_sync; 3431 uint32_t swmask = mask; 3432 3433 DEBUGFUNC("e1000_swfw_sync_release"); 3434 3435 if (hw->swfwhw_semaphore_present) { 3436 e1000_release_software_flag(hw); 3437 return; 3438 } 3439 3440 if (!hw->swfw_sync_present) { 3441 e1000_put_hw_eeprom_semaphore(hw); 3442 return; 3443 } 3444 3445 /* if (e1000_get_hw_eeprom_semaphore(hw)) 3446 * return -E1000_ERR_SWFW_SYNC; */ 3447 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 3448 /* empty */ 3449 3450 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 3451 swfw_sync &= ~swmask; 3452 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 3453 3454 e1000_put_hw_eeprom_semaphore(hw); 3455} 3456 3457/***************************************************************************** 3458* Reads the value from a PHY register, if the value is on a specific non zero 3459* page, sets the page first. 3460* hw - Struct containing variables accessed by shared code 3461* reg_addr - address of the PHY register to read 3462******************************************************************************/ 3463int32_t 3464e1000_read_phy_reg(struct e1000_hw *hw, 3465 uint32_t reg_addr, 3466 uint16_t *phy_data) 3467{ 3468 uint32_t ret_val; 3469 uint16_t swfw; 3470 3471 DEBUGFUNC("e1000_read_phy_reg"); 3472 3473 if ((hw->mac_type == e1000_80003es2lan) && 3474 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3475 swfw = E1000_SWFW_PHY1_SM; 3476 } else { 3477 swfw = E1000_SWFW_PHY0_SM; 3478 } 3479 if (e1000_swfw_sync_acquire(hw, swfw)) 3480 return -E1000_ERR_SWFW_SYNC; 3481 3482 if ((hw->phy_type == e1000_phy_igp || 3483 hw->phy_type == e1000_phy_igp_3 || 3484 hw->phy_type == e1000_phy_igp_2) && 3485 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3486 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3487 (uint16_t)reg_addr); 3488 if (ret_val) { 3489 e1000_swfw_sync_release(hw, swfw); 3490 return ret_val; 3491 } 3492 } else if (hw->phy_type == e1000_phy_gg82563) { 3493 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 3494 (hw->mac_type == e1000_80003es2lan)) { 3495 /* Select Configuration Page */ 3496 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 3497 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, 3498 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3499 } else { 3500 /* Use Alternative Page Select register to access 3501 * registers 30 and 31 3502 */ 3503 ret_val = e1000_write_phy_reg_ex(hw, 3504 GG82563_PHY_PAGE_SELECT_ALT, 3505 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3506 } 3507 3508 if (ret_val) { 3509 e1000_swfw_sync_release(hw, swfw); 3510 return ret_val; 3511 } 3512 } 3513 } 3514 3515 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 3516 phy_data); 3517 3518 e1000_swfw_sync_release(hw, swfw); 3519 return ret_val; 3520} 3521 3522static int32_t 3523e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 3524 uint16_t *phy_data) 3525{ 3526 uint32_t i; 3527 uint32_t mdic = 0; 3528 const uint32_t phy_addr = 1; 3529 3530 DEBUGFUNC("e1000_read_phy_reg_ex"); 3531 3532 if (reg_addr > MAX_PHY_REG_ADDRESS) { 3533 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3534 return -E1000_ERR_PARAM; 3535 } 3536 3537 if (hw->mac_type > e1000_82543) { 3538 /* Set up Op-code, Phy Address, and register address in the MDI 3539 * Control register. The MAC will take care of interfacing with the 3540 * PHY to retrieve the desired data. 3541 */ 3542 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 3543 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3544 (E1000_MDIC_OP_READ)); 3545 3546 E1000_WRITE_REG(hw, MDIC, mdic); 3547 3548 /* Poll the ready bit to see if the MDI read completed */ 3549 for (i = 0; i < 64; i++) { 3550 udelay(50); 3551 mdic = E1000_READ_REG(hw, MDIC); 3552 if (mdic & E1000_MDIC_READY) break; 3553 } 3554 if (!(mdic & E1000_MDIC_READY)) { 3555 DEBUGOUT("MDI Read did not complete\n"); 3556 return -E1000_ERR_PHY; 3557 } 3558 if (mdic & E1000_MDIC_ERROR) { 3559 DEBUGOUT("MDI Error\n"); 3560 return -E1000_ERR_PHY; 3561 } 3562 *phy_data = (uint16_t) mdic; 3563 } else { 3564 /* We must first send a preamble through the MDIO pin to signal the 3565 * beginning of an MII instruction. This is done by sending 32 3566 * consecutive "1" bits. 3567 */ 3568 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 3569 3570 /* Now combine the next few fields that are required for a read 3571 * operation. We use this method instead of calling the 3572 * e1000_shift_out_mdi_bits routine five different times. The format of 3573 * a MII read instruction consists of a shift out of 14 bits and is 3574 * defined as follows: 3575 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 3576 * followed by a shift in of 18 bits. This first two bits shifted in 3577 * are TurnAround bits used to avoid contention on the MDIO pin when a 3578 * READ operation is performed. These two bits are thrown away 3579 * followed by a shift in of 16 bits which contains the desired data. 3580 */ 3581 mdic = ((reg_addr) | (phy_addr << 5) | 3582 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 3583 3584 e1000_shift_out_mdi_bits(hw, mdic, 14); 3585 3586 /* Now that we've shifted out the read command to the MII, we need to 3587 * "shift in" the 16-bit value (18 total bits) of the requested PHY 3588 * register address. 3589 */ 3590 *phy_data = e1000_shift_in_mdi_bits(hw); 3591 } 3592 return E1000_SUCCESS; 3593} 3594 3595/****************************************************************************** 3596* Writes a value to a PHY register 3597* 3598* hw - Struct containing variables accessed by shared code 3599* reg_addr - address of the PHY register to write 3600* data - data to write to the PHY 3601******************************************************************************/ 3602int32_t 3603e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 3604 uint16_t phy_data) 3605{ 3606 uint32_t ret_val; 3607 uint16_t swfw; 3608 3609 DEBUGFUNC("e1000_write_phy_reg"); 3610 3611 if ((hw->mac_type == e1000_80003es2lan) && 3612 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3613 swfw = E1000_SWFW_PHY1_SM; 3614 } else { 3615 swfw = E1000_SWFW_PHY0_SM; 3616 } 3617 if (e1000_swfw_sync_acquire(hw, swfw)) 3618 return -E1000_ERR_SWFW_SYNC; 3619 3620 if ((hw->phy_type == e1000_phy_igp || 3621 hw->phy_type == e1000_phy_igp_3 || 3622 hw->phy_type == e1000_phy_igp_2) && 3623 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3624 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3625 (uint16_t)reg_addr); 3626 if (ret_val) { 3627 e1000_swfw_sync_release(hw, swfw); 3628 return ret_val; 3629 } 3630 } else if (hw->phy_type == e1000_phy_gg82563) { 3631 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 3632 (hw->mac_type == e1000_80003es2lan)) { 3633 /* Select Configuration Page */ 3634 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 3635 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, 3636 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3637 } else { 3638 /* Use Alternative Page Select register to access 3639 * registers 30 and 31 3640 */ 3641 ret_val = e1000_write_phy_reg_ex(hw, 3642 GG82563_PHY_PAGE_SELECT_ALT, 3643 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3644 } 3645 3646 if (ret_val) { 3647 e1000_swfw_sync_release(hw, swfw); 3648 return ret_val; 3649 } 3650 } 3651 } 3652 3653 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 3654 phy_data); 3655 3656 e1000_swfw_sync_release(hw, swfw); 3657 return ret_val; 3658} 3659 3660static int32_t 3661e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 3662 uint16_t phy_data) 3663{ 3664 uint32_t i; 3665 uint32_t mdic = 0; 3666 const uint32_t phy_addr = 1; 3667 3668 DEBUGFUNC("e1000_write_phy_reg_ex"); 3669 3670 if (reg_addr > MAX_PHY_REG_ADDRESS) { 3671 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3672 return -E1000_ERR_PARAM; 3673 } 3674 3675 if (hw->mac_type > e1000_82543) { 3676 /* Set up Op-code, Phy Address, register address, and data intended 3677 * for the PHY register in the MDI Control register. The MAC will take 3678 * care of interfacing with the PHY to send the desired data. 3679 */ 3680 mdic = (((uint32_t) phy_data) | 3681 (reg_addr << E1000_MDIC_REG_SHIFT) | 3682 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3683 (E1000_MDIC_OP_WRITE)); 3684 3685 E1000_WRITE_REG(hw, MDIC, mdic); 3686 3687 /* Poll the ready bit to see if the MDI read completed */ 3688 for (i = 0; i < 641; i++) { 3689 udelay(5); 3690 mdic = E1000_READ_REG(hw, MDIC); 3691 if (mdic & E1000_MDIC_READY) break; 3692 } 3693 if (!(mdic & E1000_MDIC_READY)) { 3694 DEBUGOUT("MDI Write did not complete\n"); 3695 return -E1000_ERR_PHY; 3696 } 3697 } else { 3698 /* We'll need to use the SW defined pins to shift the write command 3699 * out to the PHY. We first send a preamble to the PHY to signal the 3700 * beginning of the MII instruction. This is done by sending 32 3701 * consecutive "1" bits. 3702 */ 3703 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 3704 3705 /* Now combine the remaining required fields that will indicate a 3706 * write operation. We use this method instead of calling the 3707 * e1000_shift_out_mdi_bits routine for each field in the command. The 3708 * format of a MII write instruction is as follows: 3709 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 3710 */ 3711 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3712 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3713 mdic <<= 16; 3714 mdic |= (uint32_t) phy_data; 3715 3716 e1000_shift_out_mdi_bits(hw, mdic, 32); 3717 } 3718 3719 return E1000_SUCCESS; 3720} 3721 3722static int32_t 3723e1000_read_kmrn_reg(struct e1000_hw *hw, 3724 uint32_t reg_addr, 3725 uint16_t *data) 3726{ 3727 uint32_t reg_val; 3728 uint16_t swfw; 3729 DEBUGFUNC("e1000_read_kmrn_reg"); 3730 3731 if ((hw->mac_type == e1000_80003es2lan) && 3732 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3733 swfw = E1000_SWFW_PHY1_SM; 3734 } else { 3735 swfw = E1000_SWFW_PHY0_SM; 3736 } 3737 if (e1000_swfw_sync_acquire(hw, swfw)) 3738 return -E1000_ERR_SWFW_SYNC; 3739 3740 /* Write register address */ 3741 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 3742 E1000_KUMCTRLSTA_OFFSET) | 3743 E1000_KUMCTRLSTA_REN; 3744 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 3745 udelay(2); 3746 3747 /* Read the data returned */ 3748 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 3749 *data = (uint16_t)reg_val; 3750 3751 e1000_swfw_sync_release(hw, swfw); 3752 return E1000_SUCCESS; 3753} 3754 3755static int32_t 3756e1000_write_kmrn_reg(struct e1000_hw *hw, 3757 uint32_t reg_addr, 3758 uint16_t data) 3759{ 3760 uint32_t reg_val; 3761 uint16_t swfw; 3762 DEBUGFUNC("e1000_write_kmrn_reg"); 3763 3764 if ((hw->mac_type == e1000_80003es2lan) && 3765 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3766 swfw = E1000_SWFW_PHY1_SM; 3767 } else { 3768 swfw = E1000_SWFW_PHY0_SM; 3769 } 3770 if (e1000_swfw_sync_acquire(hw, swfw)) 3771 return -E1000_ERR_SWFW_SYNC; 3772 3773 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 3774 E1000_KUMCTRLSTA_OFFSET) | data; 3775 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 3776 udelay(2); 3777 3778 e1000_swfw_sync_release(hw, swfw); 3779 return E1000_SUCCESS; 3780} 3781 3782/****************************************************************************** 3783* Returns the PHY to the power-on reset state 3784* 3785* hw - Struct containing variables accessed by shared code 3786******************************************************************************/ 3787int32_t 3788e1000_phy_hw_reset(struct e1000_hw *hw) 3789{ 3790 uint32_t ctrl, ctrl_ext; 3791 uint32_t led_ctrl; 3792 int32_t ret_val; 3793 uint16_t swfw; 3794 3795 DEBUGFUNC("e1000_phy_hw_reset"); 3796 3797 /* In the case of the phy reset being blocked, it's not an error, we 3798 * simply return success without performing the reset. */ 3799 ret_val = e1000_check_phy_reset_block(hw); 3800 if (ret_val) 3801 return E1000_SUCCESS; 3802 3803 DEBUGOUT("Resetting Phy...\n"); 3804 3805 if (hw->mac_type > e1000_82543) { 3806 if ((hw->mac_type == e1000_80003es2lan) && 3807 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3808 swfw = E1000_SWFW_PHY1_SM; 3809 } else { 3810 swfw = E1000_SWFW_PHY0_SM; 3811 } 3812 if (e1000_swfw_sync_acquire(hw, swfw)) { 3813 DEBUGOUT("Unable to acquire swfw sync\n"); 3814 return -E1000_ERR_SWFW_SYNC; 3815 } 3816 /* Read the device control register and assert the E1000_CTRL_PHY_RST 3817 * bit. Then, take it out of reset. 3818 * For pre-e1000_82571 hardware, we delay for 10ms between the assert 3819 * and deassert. For e1000_82571 hardware and later, we instead delay 3820 * for 50us between and 10ms after the deassertion. 3821 */ 3822 ctrl = E1000_READ_REG(hw, CTRL); 3823 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 3824 E1000_WRITE_FLUSH(hw); 3825 3826 if (hw->mac_type < e1000_82571) 3827 msleep(10); 3828 else 3829 udelay(100); 3830 3831 E1000_WRITE_REG(hw, CTRL, ctrl); 3832 E1000_WRITE_FLUSH(hw); 3833 3834 if (hw->mac_type >= e1000_82571) 3835 mdelay(10); 3836 3837 e1000_swfw_sync_release(hw, swfw); 3838 } else { 3839 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3840 * bit to put the PHY into reset. Then, take it out of reset. 3841 */ 3842 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3843 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3844 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3845 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3846 E1000_WRITE_FLUSH(hw); 3847 msleep(10); 3848 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3849 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3850 E1000_WRITE_FLUSH(hw); 3851 } 3852 udelay(150); 3853 3854 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3855 /* Configure activity LED after PHY reset */ 3856 led_ctrl = E1000_READ_REG(hw, LEDCTL); 3857 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3858 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 3859 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 3860 } 3861 3862 /* Wait for FW to finish PHY configuration. */ 3863 ret_val = e1000_get_phy_cfg_done(hw); 3864 if (ret_val != E1000_SUCCESS) 3865 return ret_val; 3866 e1000_release_software_semaphore(hw); 3867 3868 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) 3869 ret_val = e1000_init_lcd_from_nvm(hw); 3870 3871 return ret_val; 3872} 3873 3874/****************************************************************************** 3875* Resets the PHY 3876* 3877* hw - Struct containing variables accessed by shared code 3878* 3879* Sets bit 15 of the MII Control register 3880******************************************************************************/ 3881int32_t 3882e1000_phy_reset(struct e1000_hw *hw) 3883{ 3884 int32_t ret_val; 3885 uint16_t phy_data; 3886 3887 DEBUGFUNC("e1000_phy_reset"); 3888 3889 /* In the case of the phy reset being blocked, it's not an error, we 3890 * simply return success without performing the reset. */ 3891 ret_val = e1000_check_phy_reset_block(hw); 3892 if (ret_val) 3893 return E1000_SUCCESS; 3894 3895 switch (hw->phy_type) { 3896 case e1000_phy_igp: 3897 case e1000_phy_igp_2: 3898 case e1000_phy_igp_3: 3899 case e1000_phy_ife: 3900 ret_val = e1000_phy_hw_reset(hw); 3901 if (ret_val) 3902 return ret_val; 3903 break; 3904 default: 3905 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3906 if (ret_val) 3907 return ret_val; 3908 3909 phy_data |= MII_CR_RESET; 3910 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3911 if (ret_val) 3912 return ret_val; 3913 3914 udelay(1); 3915 break; 3916 } 3917 3918 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 3919 e1000_phy_init_script(hw); 3920 3921 return E1000_SUCCESS; 3922} 3923 3924void 3925e1000_phy_powerdown_workaround(struct e1000_hw *hw) 3926{ 3927 int32_t reg; 3928 uint16_t phy_data; 3929 int32_t retry = 0; 3930 3931 DEBUGFUNC("e1000_phy_powerdown_workaround"); 3932 3933 if (hw->phy_type != e1000_phy_igp_3) 3934 return; 3935 3936 do { 3937 /* Disable link */ 3938 reg = E1000_READ_REG(hw, PHY_CTRL); 3939 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 3940 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3941 3942 /* Write VR power-down enable - bits 9:8 should be 10b */ 3943 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); 3944 phy_data |= (1 << 9); 3945 phy_data &= ~(1 << 8); 3946 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); 3947 3948 /* Read it back and test */ 3949 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); 3950 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) 3951 break; 3952 3953 /* Issue PHY reset and repeat at most one more time */ 3954 reg = E1000_READ_REG(hw, CTRL); 3955 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); 3956 retry++; 3957 } while (retry); 3958 3959 return; 3960 3961} 3962 3963static int32_t 3964e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) 3965{ 3966 int32_t ret_val; 3967 int32_t reg; 3968 int32_t cnt; 3969 uint16_t phy_data; 3970 3971 if (hw->kmrn_lock_loss_workaround_disabled) 3972 return E1000_SUCCESS; 3973 3974 /* Make sure link is up before proceeding. If not just return. 3975 * Attempting this while link is negotiating fouled up link 3976 * stability */ 3977 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3978 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3979 3980 if (phy_data & MII_SR_LINK_STATUS) { 3981 for (cnt = 0; cnt < 10; cnt++) { 3982 /* read once to clear */ 3983 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 3984 if (ret_val) 3985 return ret_val; 3986 /* and again to get new status */ 3987 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 3988 if (ret_val) 3989 return ret_val; 3990 3991 /* check for PCS lock */ 3992 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 3993 return E1000_SUCCESS; 3994 3995 /* Issue PHY reset */ 3996 e1000_phy_hw_reset(hw); 3997 mdelay(5); 3998 } 3999 /* Disable GigE link negotiation */ 4000 reg = E1000_READ_REG(hw, PHY_CTRL); 4001 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 4002 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 4003 4004 /* unable to acquire PCS lock */ 4005 return E1000_ERR_PHY; 4006 } 4007 4008 return E1000_SUCCESS; 4009} 4010 4011/****************************************************************************** 4012* Probes the expected PHY address for known PHY IDs 4013* 4014* hw - Struct containing variables accessed by shared code 4015******************************************************************************/ 4016static int32_t 4017e1000_detect_gig_phy(struct e1000_hw *hw) 4018{ 4019 int32_t phy_init_status, ret_val; 4020 uint16_t phy_id_high, phy_id_low; 4021 boolean_t match = FALSE; 4022 4023 DEBUGFUNC("e1000_detect_gig_phy"); 4024 4025 if (hw->phy_id != 0) 4026 return E1000_SUCCESS; 4027 4028 /* The 82571 firmware may still be configuring the PHY. In this 4029 * case, we cannot access the PHY until the configuration is done. So 4030 * we explicitly set the PHY values. */ 4031 if (hw->mac_type == e1000_82571 || 4032 hw->mac_type == e1000_82572) { 4033 hw->phy_id = IGP01E1000_I_PHY_ID; 4034 hw->phy_type = e1000_phy_igp_2; 4035 return E1000_SUCCESS; 4036 } 4037 4038 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- 4039 * around that forces PHY page 0 to be set or the reads fail. The rest of 4040 * the code in this routine uses e1000_read_phy_reg to read the PHY ID. 4041 * So for ESB-2 we need to have this set so our reads won't fail. If the 4042 * attached PHY is not a e1000_phy_gg82563, the routines below will figure 4043 * this out as well. */ 4044 if (hw->mac_type == e1000_80003es2lan) 4045 hw->phy_type = e1000_phy_gg82563; 4046 4047 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4048 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4049 if (ret_val) 4050 return ret_val; 4051 4052 hw->phy_id = (uint32_t) (phy_id_high << 16); 4053 udelay(20); 4054 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4055 if (ret_val) 4056 return ret_val; 4057 4058 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4059 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4060 4061 switch (hw->mac_type) { 4062 case e1000_82543: 4063 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; 4064 break; 4065 case e1000_82544: 4066 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; 4067 break; 4068 case e1000_82540: 4069 case e1000_82545: 4070 case e1000_82545_rev_3: 4071 case e1000_82546: 4072 case e1000_82546_rev_3: 4073 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; 4074 break; 4075 case e1000_82541: 4076 case e1000_82541_rev_2: 4077 case e1000_82547: 4078 case e1000_82547_rev_2: 4079 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 4080 break; 4081 case e1000_82573: 4082 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; 4083 break; 4084 case e1000_80003es2lan: 4085 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 4086 break; 4087 case e1000_ich8lan: 4088 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; 4089 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; 4090 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; 4091 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; 4092 break; 4093 default: 4094 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 4095 return -E1000_ERR_CONFIG; 4096 } 4097 phy_init_status = e1000_set_phy_type(hw); 4098 4099 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4100 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 4101 return E1000_SUCCESS; 4102 } 4103 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 4104 return -E1000_ERR_PHY; 4105} 4106 4107/****************************************************************************** 4108* Resets the PHY's DSP 4109* 4110* hw - Struct containing variables accessed by shared code 4111******************************************************************************/ 4112static int32_t 4113e1000_phy_reset_dsp(struct e1000_hw *hw) 4114{ 4115 int32_t ret_val; 4116 DEBUGFUNC("e1000_phy_reset_dsp"); 4117 4118 do { 4119 if (hw->phy_type != e1000_phy_gg82563) { 4120 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 4121 if (ret_val) break; 4122 } 4123 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 4124 if (ret_val) break; 4125 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 4126 if (ret_val) break; 4127 ret_val = E1000_SUCCESS; 4128 } while (0); 4129 4130 return ret_val; 4131} 4132 4133/****************************************************************************** 4134* Get PHY information from various PHY registers for igp PHY only. 4135* 4136* hw - Struct containing variables accessed by shared code 4137* phy_info - PHY information structure 4138******************************************************************************/ 4139static int32_t 4140e1000_phy_igp_get_info(struct e1000_hw *hw, 4141 struct e1000_phy_info *phy_info) 4142{ 4143 int32_t ret_val; 4144 uint16_t phy_data, min_length, max_length, average; 4145 e1000_rev_polarity polarity; 4146 4147 DEBUGFUNC("e1000_phy_igp_get_info"); 4148 4149 /* The downshift status is checked only once, after link is established, 4150 * and it stored in the hw->speed_downgraded parameter. */ 4151 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 4152 4153 /* IGP01E1000 does not need to support it. */ 4154 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 4155 4156 /* IGP01E1000 always correct polarity reversal */ 4157 phy_info->polarity_correction = e1000_polarity_reversal_enabled; 4158 4159 /* Check polarity status */ 4160 ret_val = e1000_check_polarity(hw, &polarity); 4161 if (ret_val) 4162 return ret_val; 4163 4164 phy_info->cable_polarity = polarity; 4165 4166 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 4167 if (ret_val) 4168 return ret_val; 4169 4170 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> 4171 IGP01E1000_PSSR_MDIX_SHIFT); 4172 4173 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 4174 IGP01E1000_PSSR_SPEED_1000MBPS) { 4175 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 4176 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4177 if (ret_val) 4178 return ret_val; 4179 4180 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4181 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 4182 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 4183 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 4184 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 4185 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 4186 4187 /* Get cable length */ 4188 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 4189 if (ret_val) 4190 return ret_val; 4191 4192 /* Translate to old method */ 4193 average = (max_length + min_length) / 2; 4194 4195 if (average <= e1000_igp_cable_length_50) 4196 phy_info->cable_length = e1000_cable_length_50; 4197 else if (average <= e1000_igp_cable_length_80) 4198 phy_info->cable_length = e1000_cable_length_50_80; 4199 else if (average <= e1000_igp_cable_length_110) 4200 phy_info->cable_length = e1000_cable_length_80_110; 4201 else if (average <= e1000_igp_cable_length_140) 4202 phy_info->cable_length = e1000_cable_length_110_140; 4203 else 4204 phy_info->cable_length = e1000_cable_length_140; 4205 } 4206 4207 return E1000_SUCCESS; 4208} 4209 4210/****************************************************************************** 4211* Get PHY information from various PHY registers for ife PHY only. 4212* 4213* hw - Struct containing variables accessed by shared code 4214* phy_info - PHY information structure 4215******************************************************************************/ 4216static int32_t 4217e1000_phy_ife_get_info(struct e1000_hw *hw, 4218 struct e1000_phy_info *phy_info) 4219{ 4220 int32_t ret_val; 4221 uint16_t phy_data; 4222 e1000_rev_polarity polarity; 4223 4224 DEBUGFUNC("e1000_phy_ife_get_info"); 4225 4226 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 4227 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 4228 4229 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); 4230 if (ret_val) 4231 return ret_val; 4232 phy_info->polarity_correction = 4233 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> 4234 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? 4235 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 4236 4237 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { 4238 ret_val = e1000_check_polarity(hw, &polarity); 4239 if (ret_val) 4240 return ret_val; 4241 } else { 4242 /* Polarity is forced. */ 4243 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> 4244 IFE_PSC_FORCE_POLARITY_SHIFT) ? 4245 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 4246 } 4247 phy_info->cable_polarity = polarity; 4248 4249 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 4250 if (ret_val) 4251 return ret_val; 4252 4253 phy_info->mdix_mode = (e1000_auto_x_mode) 4254 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> 4255 IFE_PMC_MDIX_MODE_SHIFT); 4256 4257 return E1000_SUCCESS; 4258} 4259 4260/****************************************************************************** 4261* Get PHY information from various PHY registers fot m88 PHY only. 4262* 4263* hw - Struct containing variables accessed by shared code 4264* phy_info - PHY information structure 4265******************************************************************************/ 4266static int32_t 4267e1000_phy_m88_get_info(struct e1000_hw *hw, 4268 struct e1000_phy_info *phy_info) 4269{ 4270 int32_t ret_val; 4271 uint16_t phy_data; 4272 e1000_rev_polarity polarity; 4273 4274 DEBUGFUNC("e1000_phy_m88_get_info"); 4275 4276 /* The downshift status is checked only once, after link is established, 4277 * and it stored in the hw->speed_downgraded parameter. */ 4278 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 4279 4280 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 4281 if (ret_val) 4282 return ret_val; 4283 4284 phy_info->extended_10bt_distance = 4285 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 4286 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 4287 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; 4288 4289 phy_info->polarity_correction = 4290 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 4291 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 4292 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 4293 4294 /* Check polarity status */ 4295 ret_val = e1000_check_polarity(hw, &polarity); 4296 if (ret_val) 4297 return ret_val; 4298 phy_info->cable_polarity = polarity; 4299 4300 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 4301 if (ret_val) 4302 return ret_val; 4303 4304 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> 4305 M88E1000_PSSR_MDIX_SHIFT); 4306 4307 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 4308 /* Cable Length Estimation and Local/Remote Receiver Information 4309 * are only valid at 1000 Mbps. 4310 */ 4311 if (hw->phy_type != e1000_phy_gg82563) { 4312 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4313 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 4314 } else { 4315 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 4316 &phy_data); 4317 if (ret_val) 4318 return ret_val; 4319 4320 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); 4321 } 4322 4323 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4324 if (ret_val) 4325 return ret_val; 4326 4327 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4328 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 4329 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 4330 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 4331 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 4332 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 4333 4334 } 4335 4336 return E1000_SUCCESS; 4337} 4338 4339/****************************************************************************** 4340* Get PHY information from various PHY registers 4341* 4342* hw - Struct containing variables accessed by shared code 4343* phy_info - PHY information structure 4344******************************************************************************/ 4345int32_t 4346e1000_phy_get_info(struct e1000_hw *hw, 4347 struct e1000_phy_info *phy_info) 4348{ 4349 int32_t ret_val; 4350 uint16_t phy_data; 4351 4352 DEBUGFUNC("e1000_phy_get_info"); 4353 4354 phy_info->cable_length = e1000_cable_length_undefined; 4355 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 4356 phy_info->cable_polarity = e1000_rev_polarity_undefined; 4357 phy_info->downshift = e1000_downshift_undefined; 4358 phy_info->polarity_correction = e1000_polarity_reversal_undefined; 4359 phy_info->mdix_mode = e1000_auto_x_mode_undefined; 4360 phy_info->local_rx = e1000_1000t_rx_status_undefined; 4361 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 4362 4363 if (hw->media_type != e1000_media_type_copper) { 4364 DEBUGOUT("PHY info is only valid for copper media\n"); 4365 return -E1000_ERR_CONFIG; 4366 } 4367 4368 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 4369 if (ret_val) 4370 return ret_val; 4371 4372 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 4373 if (ret_val) 4374 return ret_val; 4375 4376 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 4377 DEBUGOUT("PHY info is only valid if link is up\n"); 4378 return -E1000_ERR_CONFIG; 4379 } 4380 4381 if (hw->phy_type == e1000_phy_igp || 4382 hw->phy_type == e1000_phy_igp_3 || 4383 hw->phy_type == e1000_phy_igp_2) 4384 return e1000_phy_igp_get_info(hw, phy_info); 4385 else if (hw->phy_type == e1000_phy_ife) 4386 return e1000_phy_ife_get_info(hw, phy_info); 4387 else 4388 return e1000_phy_m88_get_info(hw, phy_info); 4389} 4390 4391int32_t 4392e1000_validate_mdi_setting(struct e1000_hw *hw) 4393{ 4394 DEBUGFUNC("e1000_validate_mdi_settings"); 4395 4396 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 4397 DEBUGOUT("Invalid MDI setting detected\n"); 4398 hw->mdix = 1; 4399 return -E1000_ERR_CONFIG; 4400 } 4401 return E1000_SUCCESS; 4402} 4403 4404 4405/****************************************************************************** 4406 * Sets up eeprom variables in the hw struct. Must be called after mac_type 4407 * is configured. Additionally, if this is ICH8, the flash controller GbE 4408 * registers must be mapped, or this will crash. 4409 * 4410 * hw - Struct containing variables accessed by shared code 4411 *****************************************************************************/ 4412int32_t 4413e1000_init_eeprom_params(struct e1000_hw *hw) 4414{ 4415 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4416 uint32_t eecd = E1000_READ_REG(hw, EECD); 4417 int32_t ret_val = E1000_SUCCESS; 4418 uint16_t eeprom_size; 4419 4420 DEBUGFUNC("e1000_init_eeprom_params"); 4421 4422 switch (hw->mac_type) { 4423 case e1000_82542_rev2_0: 4424 case e1000_82542_rev2_1: 4425 case e1000_82543: 4426 case e1000_82544: 4427 eeprom->type = e1000_eeprom_microwire; 4428 eeprom->word_size = 64; 4429 eeprom->opcode_bits = 3; 4430 eeprom->address_bits = 6; 4431 eeprom->delay_usec = 50; 4432 eeprom->use_eerd = FALSE; 4433 eeprom->use_eewr = FALSE; 4434 break; 4435 case e1000_82540: 4436 case e1000_82545: 4437 case e1000_82545_rev_3: 4438 case e1000_82546: 4439 case e1000_82546_rev_3: 4440 eeprom->type = e1000_eeprom_microwire; 4441 eeprom->opcode_bits = 3; 4442 eeprom->delay_usec = 50; 4443 if (eecd & E1000_EECD_SIZE) { 4444 eeprom->word_size = 256; 4445 eeprom->address_bits = 8; 4446 } else { 4447 eeprom->word_size = 64; 4448 eeprom->address_bits = 6; 4449 } 4450 eeprom->use_eerd = FALSE; 4451 eeprom->use_eewr = FALSE; 4452 break; 4453 case e1000_82541: 4454 case e1000_82541_rev_2: 4455 case e1000_82547: 4456 case e1000_82547_rev_2: 4457 if (eecd & E1000_EECD_TYPE) { 4458 eeprom->type = e1000_eeprom_spi; 4459 eeprom->opcode_bits = 8; 4460 eeprom->delay_usec = 1; 4461 if (eecd & E1000_EECD_ADDR_BITS) { 4462 eeprom->page_size = 32; 4463 eeprom->address_bits = 16; 4464 } else { 4465 eeprom->page_size = 8; 4466 eeprom->address_bits = 8; 4467 } 4468 } else { 4469 eeprom->type = e1000_eeprom_microwire; 4470 eeprom->opcode_bits = 3; 4471 eeprom->delay_usec = 50; 4472 if (eecd & E1000_EECD_ADDR_BITS) { 4473 eeprom->word_size = 256; 4474 eeprom->address_bits = 8; 4475 } else { 4476 eeprom->word_size = 64; 4477 eeprom->address_bits = 6; 4478 } 4479 } 4480 eeprom->use_eerd = FALSE; 4481 eeprom->use_eewr = FALSE; 4482 break; 4483 case e1000_82571: 4484 case e1000_82572: 4485 eeprom->type = e1000_eeprom_spi; 4486 eeprom->opcode_bits = 8; 4487 eeprom->delay_usec = 1; 4488 if (eecd & E1000_EECD_ADDR_BITS) { 4489 eeprom->page_size = 32; 4490 eeprom->address_bits = 16; 4491 } else { 4492 eeprom->page_size = 8; 4493 eeprom->address_bits = 8; 4494 } 4495 eeprom->use_eerd = FALSE; 4496 eeprom->use_eewr = FALSE; 4497 break; 4498 case e1000_82573: 4499 eeprom->type = e1000_eeprom_spi; 4500 eeprom->opcode_bits = 8; 4501 eeprom->delay_usec = 1; 4502 if (eecd & E1000_EECD_ADDR_BITS) { 4503 eeprom->page_size = 32; 4504 eeprom->address_bits = 16; 4505 } else { 4506 eeprom->page_size = 8; 4507 eeprom->address_bits = 8; 4508 } 4509 eeprom->use_eerd = TRUE; 4510 eeprom->use_eewr = TRUE; 4511 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 4512 eeprom->type = e1000_eeprom_flash; 4513 eeprom->word_size = 2048; 4514 4515 /* Ensure that the Autonomous FLASH update bit is cleared due to 4516 * Flash update issue on parts which use a FLASH for NVM. */ 4517 eecd &= ~E1000_EECD_AUPDEN; 4518 E1000_WRITE_REG(hw, EECD, eecd); 4519 } 4520 break; 4521 case e1000_80003es2lan: 4522 eeprom->type = e1000_eeprom_spi; 4523 eeprom->opcode_bits = 8; 4524 eeprom->delay_usec = 1; 4525 if (eecd & E1000_EECD_ADDR_BITS) { 4526 eeprom->page_size = 32; 4527 eeprom->address_bits = 16; 4528 } else { 4529 eeprom->page_size = 8; 4530 eeprom->address_bits = 8; 4531 } 4532 eeprom->use_eerd = TRUE; 4533 eeprom->use_eewr = FALSE; 4534 break; 4535 case e1000_ich8lan: 4536 { 4537 int32_t i = 0; 4538 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 4539 4540 eeprom->type = e1000_eeprom_ich8; 4541 eeprom->use_eerd = FALSE; 4542 eeprom->use_eewr = FALSE; 4543 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 4544 4545 /* Zero the shadow RAM structure. But don't load it from NVM 4546 * so as to save time for driver init */ 4547 if (hw->eeprom_shadow_ram != NULL) { 4548 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4549 hw->eeprom_shadow_ram[i].modified = FALSE; 4550 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 4551 } 4552 } 4553 4554 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 4555 ICH_FLASH_SECTOR_SIZE; 4556 4557 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; 4558 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 4559 4560 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 4561 4562 hw->flash_bank_size /= 2 * sizeof(uint16_t); 4563 4564 break; 4565 } 4566 default: 4567 break; 4568 } 4569 4570 if (eeprom->type == e1000_eeprom_spi) { 4571 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 4572 * 32KB (incremented by powers of 2). 4573 */ 4574 if (hw->mac_type <= e1000_82547_rev_2) { 4575 /* Set to default value for initial eeprom read. */ 4576 eeprom->word_size = 64; 4577 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 4578 if (ret_val) 4579 return ret_val; 4580 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 4581 /* 256B eeprom size was not supported in earlier hardware, so we 4582 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 4583 * is never the result used in the shifting logic below. */ 4584 if (eeprom_size) 4585 eeprom_size++; 4586 } else { 4587 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> 4588 E1000_EECD_SIZE_EX_SHIFT); 4589 } 4590 4591 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 4592 } 4593 return ret_val; 4594} 4595 4596/****************************************************************************** 4597 * Raises the EEPROM's clock input. 4598 * 4599 * hw - Struct containing variables accessed by shared code 4600 * eecd - EECD's current value 4601 *****************************************************************************/ 4602static void 4603e1000_raise_ee_clk(struct e1000_hw *hw, 4604 uint32_t *eecd) 4605{ 4606 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 4607 * wait <delay> microseconds. 4608 */ 4609 *eecd = *eecd | E1000_EECD_SK; 4610 E1000_WRITE_REG(hw, EECD, *eecd); 4611 E1000_WRITE_FLUSH(hw); 4612 udelay(hw->eeprom.delay_usec); 4613} 4614 4615/****************************************************************************** 4616 * Lowers the EEPROM's clock input. 4617 * 4618 * hw - Struct containing variables accessed by shared code 4619 * eecd - EECD's current value 4620 *****************************************************************************/ 4621static void 4622e1000_lower_ee_clk(struct e1000_hw *hw, 4623 uint32_t *eecd) 4624{ 4625 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 4626 * wait 50 microseconds. 4627 */ 4628 *eecd = *eecd & ~E1000_EECD_SK; 4629 E1000_WRITE_REG(hw, EECD, *eecd); 4630 E1000_WRITE_FLUSH(hw); 4631 udelay(hw->eeprom.delay_usec); 4632} 4633 4634/****************************************************************************** 4635 * Shift data bits out to the EEPROM. 4636 * 4637 * hw - Struct containing variables accessed by shared code 4638 * data - data to send to the EEPROM 4639 * count - number of bits to shift out 4640 *****************************************************************************/ 4641static void 4642e1000_shift_out_ee_bits(struct e1000_hw *hw, 4643 uint16_t data, 4644 uint16_t count) 4645{ 4646 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4647 uint32_t eecd; 4648 uint32_t mask; 4649 4650 /* We need to shift "count" bits out to the EEPROM. So, value in the 4651 * "data" parameter will be shifted out to the EEPROM one bit at a time. 4652 * In order to do this, "data" must be broken down into bits. 4653 */ 4654 mask = 0x01 << (count - 1); 4655 eecd = E1000_READ_REG(hw, EECD); 4656 if (eeprom->type == e1000_eeprom_microwire) { 4657 eecd &= ~E1000_EECD_DO; 4658 } else if (eeprom->type == e1000_eeprom_spi) { 4659 eecd |= E1000_EECD_DO; 4660 } 4661 do { 4662 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 4663 * and then raising and then lowering the clock (the SK bit controls 4664 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 4665 * by setting "DI" to "0" and then raising and then lowering the clock. 4666 */ 4667 eecd &= ~E1000_EECD_DI; 4668 4669 if (data & mask) 4670 eecd |= E1000_EECD_DI; 4671 4672 E1000_WRITE_REG(hw, EECD, eecd); 4673 E1000_WRITE_FLUSH(hw); 4674 4675 udelay(eeprom->delay_usec); 4676 4677 e1000_raise_ee_clk(hw, &eecd); 4678 e1000_lower_ee_clk(hw, &eecd); 4679 4680 mask = mask >> 1; 4681 4682 } while (mask); 4683 4684 /* We leave the "DI" bit set to "0" when we leave this routine. */ 4685 eecd &= ~E1000_EECD_DI; 4686 E1000_WRITE_REG(hw, EECD, eecd); 4687} 4688 4689/****************************************************************************** 4690 * Shift data bits in from the EEPROM 4691 * 4692 * hw - Struct containing variables accessed by shared code 4693 *****************************************************************************/ 4694static uint16_t 4695e1000_shift_in_ee_bits(struct e1000_hw *hw, 4696 uint16_t count) 4697{ 4698 uint32_t eecd; 4699 uint32_t i; 4700 uint16_t data; 4701 4702 /* In order to read a register from the EEPROM, we need to shift 'count' 4703 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 4704 * input to the EEPROM (setting the SK bit), and then reading the value of 4705 * the "DO" bit. During this "shifting in" process the "DI" bit should 4706 * always be clear. 4707 */ 4708 4709 eecd = E1000_READ_REG(hw, EECD); 4710 4711 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 4712 data = 0; 4713 4714 for (i = 0; i < count; i++) { 4715 data = data << 1; 4716 e1000_raise_ee_clk(hw, &eecd); 4717 4718 eecd = E1000_READ_REG(hw, EECD); 4719 4720 eecd &= ~(E1000_EECD_DI); 4721 if (eecd & E1000_EECD_DO) 4722 data |= 1; 4723 4724 e1000_lower_ee_clk(hw, &eecd); 4725 } 4726 4727 return data; 4728} 4729 4730/****************************************************************************** 4731 * Prepares EEPROM for access 4732 * 4733 * hw - Struct containing variables accessed by shared code 4734 * 4735 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 4736 * function should be called before issuing a command to the EEPROM. 4737 *****************************************************************************/ 4738static int32_t 4739e1000_acquire_eeprom(struct e1000_hw *hw) 4740{ 4741 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4742 uint32_t eecd, i=0; 4743 4744 DEBUGFUNC("e1000_acquire_eeprom"); 4745 4746 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 4747 return -E1000_ERR_SWFW_SYNC; 4748 eecd = E1000_READ_REG(hw, EECD); 4749 4750 if (hw->mac_type != e1000_82573) { 4751 /* Request EEPROM Access */ 4752 if (hw->mac_type > e1000_82544) { 4753 eecd |= E1000_EECD_REQ; 4754 E1000_WRITE_REG(hw, EECD, eecd); 4755 eecd = E1000_READ_REG(hw, EECD); 4756 while ((!(eecd & E1000_EECD_GNT)) && 4757 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 4758 i++; 4759 udelay(5); 4760 eecd = E1000_READ_REG(hw, EECD); 4761 } 4762 if (!(eecd & E1000_EECD_GNT)) { 4763 eecd &= ~E1000_EECD_REQ; 4764 E1000_WRITE_REG(hw, EECD, eecd); 4765 DEBUGOUT("Could not acquire EEPROM grant\n"); 4766 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4767 return -E1000_ERR_EEPROM; 4768 } 4769 } 4770 } 4771 4772 /* Setup EEPROM for Read/Write */ 4773 4774 if (eeprom->type == e1000_eeprom_microwire) { 4775 /* Clear SK and DI */ 4776 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 4777 E1000_WRITE_REG(hw, EECD, eecd); 4778 4779 /* Set CS */ 4780 eecd |= E1000_EECD_CS; 4781 E1000_WRITE_REG(hw, EECD, eecd); 4782 } else if (eeprom->type == e1000_eeprom_spi) { 4783 /* Clear SK and CS */ 4784 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4785 E1000_WRITE_REG(hw, EECD, eecd); 4786 udelay(1); 4787 } 4788 4789 return E1000_SUCCESS; 4790} 4791 4792/****************************************************************************** 4793 * Returns EEPROM to a "standby" state 4794 * 4795 * hw - Struct containing variables accessed by shared code 4796 *****************************************************************************/ 4797static void 4798e1000_standby_eeprom(struct e1000_hw *hw) 4799{ 4800 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4801 uint32_t eecd; 4802 4803 eecd = E1000_READ_REG(hw, EECD); 4804 4805 if (eeprom->type == e1000_eeprom_microwire) { 4806 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4807 E1000_WRITE_REG(hw, EECD, eecd); 4808 E1000_WRITE_FLUSH(hw); 4809 udelay(eeprom->delay_usec); 4810 4811 /* Clock high */ 4812 eecd |= E1000_EECD_SK; 4813 E1000_WRITE_REG(hw, EECD, eecd); 4814 E1000_WRITE_FLUSH(hw); 4815 udelay(eeprom->delay_usec); 4816 4817 /* Select EEPROM */ 4818 eecd |= E1000_EECD_CS; 4819 E1000_WRITE_REG(hw, EECD, eecd); 4820 E1000_WRITE_FLUSH(hw); 4821 udelay(eeprom->delay_usec); 4822 4823 /* Clock low */ 4824 eecd &= ~E1000_EECD_SK; 4825 E1000_WRITE_REG(hw, EECD, eecd); 4826 E1000_WRITE_FLUSH(hw); 4827 udelay(eeprom->delay_usec); 4828 } else if (eeprom->type == e1000_eeprom_spi) { 4829 /* Toggle CS to flush commands */ 4830 eecd |= E1000_EECD_CS; 4831 E1000_WRITE_REG(hw, EECD, eecd); 4832 E1000_WRITE_FLUSH(hw); 4833 udelay(eeprom->delay_usec); 4834 eecd &= ~E1000_EECD_CS; 4835 E1000_WRITE_REG(hw, EECD, eecd); 4836 E1000_WRITE_FLUSH(hw); 4837 udelay(eeprom->delay_usec); 4838 } 4839} 4840 4841/****************************************************************************** 4842 * Terminates a command by inverting the EEPROM's chip select pin 4843 * 4844 * hw - Struct containing variables accessed by shared code 4845 *****************************************************************************/ 4846static void 4847e1000_release_eeprom(struct e1000_hw *hw) 4848{ 4849 uint32_t eecd; 4850 4851 DEBUGFUNC("e1000_release_eeprom"); 4852 4853 eecd = E1000_READ_REG(hw, EECD); 4854 4855 if (hw->eeprom.type == e1000_eeprom_spi) { 4856 eecd |= E1000_EECD_CS; /* Pull CS high */ 4857 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 4858 4859 E1000_WRITE_REG(hw, EECD, eecd); 4860 4861 udelay(hw->eeprom.delay_usec); 4862 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 4863 /* cleanup eeprom */ 4864 4865 /* CS on Microwire is active-high */ 4866 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 4867 4868 E1000_WRITE_REG(hw, EECD, eecd); 4869 4870 /* Rising edge of clock */ 4871 eecd |= E1000_EECD_SK; 4872 E1000_WRITE_REG(hw, EECD, eecd); 4873 E1000_WRITE_FLUSH(hw); 4874 udelay(hw->eeprom.delay_usec); 4875 4876 /* Falling edge of clock */ 4877 eecd &= ~E1000_EECD_SK; 4878 E1000_WRITE_REG(hw, EECD, eecd); 4879 E1000_WRITE_FLUSH(hw); 4880 udelay(hw->eeprom.delay_usec); 4881 } 4882 4883 /* Stop requesting EEPROM access */ 4884 if (hw->mac_type > e1000_82544) { 4885 eecd &= ~E1000_EECD_REQ; 4886 E1000_WRITE_REG(hw, EECD, eecd); 4887 } 4888 4889 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4890} 4891 4892/****************************************************************************** 4893 * Reads a 16 bit word from the EEPROM. 4894 * 4895 * hw - Struct containing variables accessed by shared code 4896 *****************************************************************************/ 4897static int32_t 4898e1000_spi_eeprom_ready(struct e1000_hw *hw) 4899{ 4900 uint16_t retry_count = 0; 4901 uint8_t spi_stat_reg; 4902 4903 DEBUGFUNC("e1000_spi_eeprom_ready"); 4904 4905 /* Read "Status Register" repeatedly until the LSB is cleared. The 4906 * EEPROM will signal that the command has been completed by clearing 4907 * bit 0 of the internal status register. If it's not cleared within 4908 * 5 milliseconds, then error out. 4909 */ 4910 retry_count = 0; 4911 do { 4912 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 4913 hw->eeprom.opcode_bits); 4914 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 4915 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 4916 break; 4917 4918 udelay(5); 4919 retry_count += 5; 4920 4921 e1000_standby_eeprom(hw); 4922 } while (retry_count < EEPROM_MAX_RETRY_SPI); 4923 4924 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 4925 * only 0-5mSec on 5V devices) 4926 */ 4927 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 4928 DEBUGOUT("SPI EEPROM Status error\n"); 4929 return -E1000_ERR_EEPROM; 4930 } 4931 4932 return E1000_SUCCESS; 4933} 4934 4935/****************************************************************************** 4936 * Reads a 16 bit word from the EEPROM. 4937 * 4938 * hw - Struct containing variables accessed by shared code 4939 * offset - offset of word in the EEPROM to read 4940 * data - word read from the EEPROM 4941 * words - number of words to read 4942 *****************************************************************************/ 4943int32_t 4944e1000_read_eeprom(struct e1000_hw *hw, 4945 uint16_t offset, 4946 uint16_t words, 4947 uint16_t *data) 4948{ 4949 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4950 uint32_t i = 0; 4951 4952 DEBUGFUNC("e1000_read_eeprom"); 4953 4954 /* If eeprom is not yet detected, do so now */ 4955 if (eeprom->word_size == 0) 4956 e1000_init_eeprom_params(hw); 4957 4958 /* A check for invalid values: offset too large, too many words, and not 4959 * enough words. 4960 */ 4961 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 4962 (words == 0)) { 4963 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); 4964 return -E1000_ERR_EEPROM; 4965 } 4966 4967 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 4968 * directly. In this case, we need to acquire the EEPROM so that 4969 * FW or other port software does not interrupt. 4970 */ 4971 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 4972 hw->eeprom.use_eerd == FALSE) { 4973 /* Prepare the EEPROM for bit-bang reading */ 4974 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4975 return -E1000_ERR_EEPROM; 4976 } 4977 4978 /* Eerd register EEPROM access requires no eeprom aquire/release */ 4979 if (eeprom->use_eerd == TRUE) 4980 return e1000_read_eeprom_eerd(hw, offset, words, data); 4981 4982 /* ICH EEPROM access is done via the ICH flash controller */ 4983 if (eeprom->type == e1000_eeprom_ich8) 4984 return e1000_read_eeprom_ich8(hw, offset, words, data); 4985 4986 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 4987 * acquired the EEPROM at this point, so any returns should relase it */ 4988 if (eeprom->type == e1000_eeprom_spi) { 4989 uint16_t word_in; 4990 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4991 4992 if (e1000_spi_eeprom_ready(hw)) { 4993 e1000_release_eeprom(hw); 4994 return -E1000_ERR_EEPROM; 4995 } 4996 4997 e1000_standby_eeprom(hw); 4998 4999 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 5000 if ((eeprom->address_bits == 8) && (offset >= 128)) 5001 read_opcode |= EEPROM_A8_OPCODE_SPI; 5002 5003 /* Send the READ command (opcode + addr) */ 5004 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 5005 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); 5006 5007 /* Read the data. The address of the eeprom internally increments with 5008 * each byte (spi) being read, saving on the overhead of eeprom setup 5009 * and tear-down. The address counter will roll over if reading beyond 5010 * the size of the eeprom, thus allowing the entire memory to be read 5011 * starting from any offset. */ 5012 for (i = 0; i < words; i++) { 5013 word_in = e1000_shift_in_ee_bits(hw, 16); 5014 data[i] = (word_in >> 8) | (word_in << 8); 5015 } 5016 } else if (eeprom->type == e1000_eeprom_microwire) { 5017 for (i = 0; i < words; i++) { 5018 /* Send the READ command (opcode + addr) */ 5019 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 5020 eeprom->opcode_bits); 5021 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 5022 eeprom->address_bits); 5023 5024 /* Read the data. For microwire, each word requires the overhead 5025 * of eeprom setup and tear-down. */ 5026 data[i] = e1000_shift_in_ee_bits(hw, 16); 5027 e1000_standby_eeprom(hw); 5028 } 5029 } 5030 5031 /* End this read operation */ 5032 e1000_release_eeprom(hw); 5033 5034 return E1000_SUCCESS; 5035} 5036 5037/****************************************************************************** 5038 * Reads a 16 bit word from the EEPROM using the EERD register. 5039 * 5040 * hw - Struct containing variables accessed by shared code 5041 * offset - offset of word in the EEPROM to read 5042 * data - word read from the EEPROM 5043 * words - number of words to read 5044 *****************************************************************************/ 5045static int32_t 5046e1000_read_eeprom_eerd(struct e1000_hw *hw, 5047 uint16_t offset, 5048 uint16_t words, 5049 uint16_t *data) 5050{ 5051 uint32_t i, eerd = 0; 5052 int32_t error = 0; 5053 5054 for (i = 0; i < words; i++) { 5055 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 5056 E1000_EEPROM_RW_REG_START; 5057 5058 E1000_WRITE_REG(hw, EERD, eerd); 5059 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 5060 5061 if (error) { 5062 break; 5063 } 5064 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); 5065 5066 } 5067 5068 return error; 5069} 5070 5071/****************************************************************************** 5072 * Writes a 16 bit word from the EEPROM using the EEWR register. 5073 * 5074 * hw - Struct containing variables accessed by shared code 5075 * offset - offset of word in the EEPROM to read 5076 * data - word read from the EEPROM 5077 * words - number of words to read 5078 *****************************************************************************/ 5079static int32_t 5080e1000_write_eeprom_eewr(struct e1000_hw *hw, 5081 uint16_t offset, 5082 uint16_t words, 5083 uint16_t *data) 5084{ 5085 uint32_t register_value = 0; 5086 uint32_t i = 0; 5087 int32_t error = 0; 5088 5089 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 5090 return -E1000_ERR_SWFW_SYNC; 5091 5092 for (i = 0; i < words; i++) { 5093 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 5094 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | 5095 E1000_EEPROM_RW_REG_START; 5096 5097 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5098 if (error) { 5099 break; 5100 } 5101 5102 E1000_WRITE_REG(hw, EEWR, register_value); 5103 5104 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5105 5106 if (error) { 5107 break; 5108 } 5109 } 5110 5111 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5112 return error; 5113} 5114 5115/****************************************************************************** 5116 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 5117 * 5118 * hw - Struct containing variables accessed by shared code 5119 *****************************************************************************/ 5120static int32_t 5121e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 5122{ 5123 uint32_t attempts = 100000; 5124 uint32_t i, reg = 0; 5125 int32_t done = E1000_ERR_EEPROM; 5126 5127 for (i = 0; i < attempts; i++) { 5128 if (eerd == E1000_EEPROM_POLL_READ) 5129 reg = E1000_READ_REG(hw, EERD); 5130 else 5131 reg = E1000_READ_REG(hw, EEWR); 5132 5133 if (reg & E1000_EEPROM_RW_REG_DONE) { 5134 done = E1000_SUCCESS; 5135 break; 5136 } 5137 udelay(5); 5138 } 5139 5140 return done; 5141} 5142 5143/*************************************************************************** 5144* Description: Determines if the onboard NVM is FLASH or EEPROM. 5145* 5146* hw - Struct containing variables accessed by shared code 5147****************************************************************************/ 5148static boolean_t 5149e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 5150{ 5151 uint32_t eecd = 0; 5152 5153 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 5154 5155 if (hw->mac_type == e1000_ich8lan) 5156 return FALSE; 5157 5158 if (hw->mac_type == e1000_82573) { 5159 eecd = E1000_READ_REG(hw, EECD); 5160 5161 /* Isolate bits 15 & 16 */ 5162 eecd = ((eecd >> 15) & 0x03); 5163 5164 /* If both bits are set, device is Flash type */ 5165 if (eecd == 0x03) { 5166 return FALSE; 5167 } 5168 } 5169 return TRUE; 5170} 5171 5172/****************************************************************************** 5173 * Verifies that the EEPROM has a valid checksum 5174 * 5175 * hw - Struct containing variables accessed by shared code 5176 * 5177 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 5178 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 5179 * valid. 5180 *****************************************************************************/ 5181int32_t 5182e1000_validate_eeprom_checksum(struct e1000_hw *hw) 5183{ 5184 uint16_t checksum = 0; 5185 uint16_t i, eeprom_data; 5186 5187 DEBUGFUNC("e1000_validate_eeprom_checksum"); 5188 5189 if ((hw->mac_type == e1000_82573) && 5190 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { 5191 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 5192 * 10h-12h. Checksum may need to be fixed. */ 5193 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); 5194 if ((eeprom_data & 0x10) == 0) { 5195 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum 5196 * has already been fixed. If the checksum is still wrong and this 5197 * bit is a 1, we need to return bad checksum. Otherwise, we need 5198 * to set this bit to a 1 and update the checksum. */ 5199 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); 5200 if ((eeprom_data & 0x8000) == 0) { 5201 eeprom_data |= 0x8000; 5202 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); 5203 e1000_update_eeprom_checksum(hw); 5204 } 5205 } 5206 } 5207 5208 if (hw->mac_type == e1000_ich8lan) { 5209 /* Drivers must allocate the shadow ram structure for the 5210 * EEPROM checksum to be updated. Otherwise, this bit as well 5211 * as the checksum must both be set correctly for this 5212 * validation to pass. 5213 */ 5214 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); 5215 if ((eeprom_data & 0x40) == 0) { 5216 eeprom_data |= 0x40; 5217 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); 5218 e1000_update_eeprom_checksum(hw); 5219 } 5220 } 5221 5222 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 5223 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5224 DEBUGOUT("EEPROM Read Error\n"); 5225 return -E1000_ERR_EEPROM; 5226 } 5227 checksum += eeprom_data; 5228 } 5229 5230 if (checksum == (uint16_t) EEPROM_SUM) 5231 return E1000_SUCCESS; 5232 else { 5233 DEBUGOUT("EEPROM Checksum Invalid\n"); 5234 return -E1000_ERR_EEPROM; 5235 } 5236} 5237 5238/****************************************************************************** 5239 * Calculates the EEPROM checksum and writes it to the EEPROM 5240 * 5241 * hw - Struct containing variables accessed by shared code 5242 * 5243 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 5244 * Writes the difference to word offset 63 of the EEPROM. 5245 *****************************************************************************/ 5246int32_t 5247e1000_update_eeprom_checksum(struct e1000_hw *hw) 5248{ 5249 uint32_t ctrl_ext; 5250 uint16_t checksum = 0; 5251 uint16_t i, eeprom_data; 5252 5253 DEBUGFUNC("e1000_update_eeprom_checksum"); 5254 5255 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 5256 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5257 DEBUGOUT("EEPROM Read Error\n"); 5258 return -E1000_ERR_EEPROM; 5259 } 5260 checksum += eeprom_data; 5261 } 5262 checksum = (uint16_t) EEPROM_SUM - checksum; 5263 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 5264 DEBUGOUT("EEPROM Write Error\n"); 5265 return -E1000_ERR_EEPROM; 5266 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5267 e1000_commit_shadow_ram(hw); 5268 } else if (hw->eeprom.type == e1000_eeprom_ich8) { 5269 e1000_commit_shadow_ram(hw); 5270 /* Reload the EEPROM, or else modifications will not appear 5271 * until after next adapter reset. */ 5272 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5273 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 5274 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5275 msleep(10); 5276 } 5277 return E1000_SUCCESS; 5278} 5279 5280/****************************************************************************** 5281 * Parent function for writing words to the different EEPROM types. 5282 * 5283 * hw - Struct containing variables accessed by shared code 5284 * offset - offset within the EEPROM to be written to 5285 * words - number of words to write 5286 * data - 16 bit word to be written to the EEPROM 5287 * 5288 * If e1000_update_eeprom_checksum is not called after this function, the 5289 * EEPROM will most likely contain an invalid checksum. 5290 *****************************************************************************/ 5291int32_t 5292e1000_write_eeprom(struct e1000_hw *hw, 5293 uint16_t offset, 5294 uint16_t words, 5295 uint16_t *data) 5296{ 5297 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5298 int32_t status = 0; 5299 5300 DEBUGFUNC("e1000_write_eeprom"); 5301 5302 /* If eeprom is not yet detected, do so now */ 5303 if (eeprom->word_size == 0) 5304 e1000_init_eeprom_params(hw); 5305 5306 /* A check for invalid values: offset too large, too many words, and not 5307 * enough words. 5308 */ 5309 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 5310 (words == 0)) { 5311 DEBUGOUT("\"words\" parameter out of bounds\n"); 5312 return -E1000_ERR_EEPROM; 5313 } 5314 5315 /* 82573 writes only through eewr */ 5316 if (eeprom->use_eewr == TRUE) 5317 return e1000_write_eeprom_eewr(hw, offset, words, data); 5318 5319 if (eeprom->type == e1000_eeprom_ich8) 5320 return e1000_write_eeprom_ich8(hw, offset, words, data); 5321 5322 /* Prepare the EEPROM for writing */ 5323 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5324 return -E1000_ERR_EEPROM; 5325 5326 if (eeprom->type == e1000_eeprom_microwire) { 5327 status = e1000_write_eeprom_microwire(hw, offset, words, data); 5328 } else { 5329 status = e1000_write_eeprom_spi(hw, offset, words, data); 5330 msleep(10); 5331 } 5332 5333 /* Done with writing */ 5334 e1000_release_eeprom(hw); 5335 5336 return status; 5337} 5338 5339/****************************************************************************** 5340 * Writes a 16 bit word to a given offset in an SPI EEPROM. 5341 * 5342 * hw - Struct containing variables accessed by shared code 5343 * offset - offset within the EEPROM to be written to 5344 * words - number of words to write 5345 * data - pointer to array of 8 bit words to be written to the EEPROM 5346 * 5347 *****************************************************************************/ 5348static int32_t 5349e1000_write_eeprom_spi(struct e1000_hw *hw, 5350 uint16_t offset, 5351 uint16_t words, 5352 uint16_t *data) 5353{ 5354 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5355 uint16_t widx = 0; 5356 5357 DEBUGFUNC("e1000_write_eeprom_spi"); 5358 5359 while (widx < words) { 5360 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 5361 5362 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 5363 5364 e1000_standby_eeprom(hw); 5365 5366 /* Send the WRITE ENABLE command (8 bit opcode ) */ 5367 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 5368 eeprom->opcode_bits); 5369 5370 e1000_standby_eeprom(hw); 5371 5372 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 5373 if ((eeprom->address_bits == 8) && (offset >= 128)) 5374 write_opcode |= EEPROM_A8_OPCODE_SPI; 5375 5376 /* Send the Write command (8-bit opcode + addr) */ 5377 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 5378 5379 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), 5380 eeprom->address_bits); 5381 5382 /* Send the data */ 5383 5384 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 5385 while (widx < words) { 5386 uint16_t word_out = data[widx]; 5387 word_out = (word_out >> 8) | (word_out << 8); 5388 e1000_shift_out_ee_bits(hw, word_out, 16); 5389 widx++; 5390 5391 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE 5392 * operation, while the smaller eeproms are capable of an 8-byte 5393 * PAGE WRITE operation. Break the inner loop to pass new address 5394 */ 5395 if ((((offset + widx)*2) % eeprom->page_size) == 0) { 5396 e1000_standby_eeprom(hw); 5397 break; 5398 } 5399 } 5400 } 5401 5402 return E1000_SUCCESS; 5403} 5404 5405/****************************************************************************** 5406 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 5407 * 5408 * hw - Struct containing variables accessed by shared code 5409 * offset - offset within the EEPROM to be written to 5410 * words - number of words to write 5411 * data - pointer to array of 16 bit words to be written to the EEPROM 5412 * 5413 *****************************************************************************/ 5414static int32_t 5415e1000_write_eeprom_microwire(struct e1000_hw *hw, 5416 uint16_t offset, 5417 uint16_t words, 5418 uint16_t *data) 5419{ 5420 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5421 uint32_t eecd; 5422 uint16_t words_written = 0; 5423 uint16_t i = 0; 5424 5425 DEBUGFUNC("e1000_write_eeprom_microwire"); 5426 5427 /* Send the write enable command to the EEPROM (3-bit opcode plus 5428 * 6/8-bit dummy address beginning with 11). It's less work to include 5429 * the 11 of the dummy address as part of the opcode than it is to shift 5430 * it over the correct number of bits for the address. This puts the 5431 * EEPROM into write/erase mode. 5432 */ 5433 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 5434 (uint16_t)(eeprom->opcode_bits + 2)); 5435 5436 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 5437 5438 /* Prepare the EEPROM */ 5439 e1000_standby_eeprom(hw); 5440 5441 while (words_written < words) { 5442 /* Send the Write command (3-bit opcode + addr) */ 5443 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 5444 eeprom->opcode_bits); 5445 5446 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), 5447 eeprom->address_bits); 5448 5449 /* Send the data */ 5450 e1000_shift_out_ee_bits(hw, data[words_written], 16); 5451 5452 /* Toggle the CS line. This in effect tells the EEPROM to execute 5453 * the previous command. 5454 */ 5455 e1000_standby_eeprom(hw); 5456 5457 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will 5458 * signal that the command has been completed by raising the DO signal. 5459 * If DO does not go high in 10 milliseconds, then error out. 5460 */ 5461 for (i = 0; i < 200; i++) { 5462 eecd = E1000_READ_REG(hw, EECD); 5463 if (eecd & E1000_EECD_DO) break; 5464 udelay(50); 5465 } 5466 if (i == 200) { 5467 DEBUGOUT("EEPROM Write did not complete\n"); 5468 return -E1000_ERR_EEPROM; 5469 } 5470 5471 /* Recover from write */ 5472 e1000_standby_eeprom(hw); 5473 5474 words_written++; 5475 } 5476 5477 /* Send the write disable command to the EEPROM (3-bit opcode plus 5478 * 6/8-bit dummy address beginning with 10). It's less work to include 5479 * the 10 of the dummy address as part of the opcode than it is to shift 5480 * it over the correct number of bits for the address. This takes the 5481 * EEPROM out of write/erase mode. 5482 */ 5483 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 5484 (uint16_t)(eeprom->opcode_bits + 2)); 5485 5486 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 5487 5488 return E1000_SUCCESS; 5489} 5490 5491/****************************************************************************** 5492 * Flushes the cached eeprom to NVM. This is done by saving the modified values 5493 * in the eeprom cache and the non modified values in the currently active bank 5494 * to the new bank. 5495 * 5496 * hw - Struct containing variables accessed by shared code 5497 * offset - offset of word in the EEPROM to read 5498 * data - word read from the EEPROM 5499 * words - number of words to read 5500 *****************************************************************************/ 5501static int32_t 5502e1000_commit_shadow_ram(struct e1000_hw *hw) 5503{ 5504 uint32_t attempts = 100000; 5505 uint32_t eecd = 0; 5506 uint32_t flop = 0; 5507 uint32_t i = 0; 5508 int32_t error = E1000_SUCCESS; 5509 uint32_t old_bank_offset = 0; 5510 uint32_t new_bank_offset = 0; 5511 uint8_t low_byte = 0; 5512 uint8_t high_byte = 0; 5513 boolean_t sector_write_failed = FALSE; 5514 5515 if (hw->mac_type == e1000_82573) { 5516 /* The flop register will be used to determine if flash type is STM */ 5517 flop = E1000_READ_REG(hw, FLOP); 5518 for (i=0; i < attempts; i++) { 5519 eecd = E1000_READ_REG(hw, EECD); 5520 if ((eecd & E1000_EECD_FLUPD) == 0) { 5521 break; 5522 } 5523 udelay(5); 5524 } 5525 5526 if (i == attempts) { 5527 return -E1000_ERR_EEPROM; 5528 } 5529 5530 /* If STM opcode located in bits 15:8 of flop, reset firmware */ 5531 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 5532 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 5533 } 5534 5535 /* Perform the flash update */ 5536 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 5537 5538 for (i=0; i < attempts; i++) { 5539 eecd = E1000_READ_REG(hw, EECD); 5540 if ((eecd & E1000_EECD_FLUPD) == 0) { 5541 break; 5542 } 5543 udelay(5); 5544 } 5545 5546 if (i == attempts) { 5547 return -E1000_ERR_EEPROM; 5548 } 5549 } 5550 5551 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { 5552 /* We're writing to the opposite bank so if we're on bank 1, 5553 * write to bank 0 etc. We also need to erase the segment that 5554 * is going to be written */ 5555 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 5556 new_bank_offset = hw->flash_bank_size * 2; 5557 old_bank_offset = 0; 5558 e1000_erase_ich8_4k_segment(hw, 1); 5559 } else { 5560 old_bank_offset = hw->flash_bank_size * 2; 5561 new_bank_offset = 0; 5562 e1000_erase_ich8_4k_segment(hw, 0); 5563 } 5564 5565 sector_write_failed = FALSE; 5566 /* Loop for every byte in the shadow RAM, 5567 * which is in units of words. */ 5568 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5569 /* Determine whether to write the value stored 5570 * in the other NVM bank or a modified value stored 5571 * in the shadow RAM */ 5572 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 5573 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; 5574 udelay(100); 5575 error = e1000_verify_write_ich8_byte(hw, 5576 (i << 1) + new_bank_offset, low_byte); 5577 5578 if (error != E1000_SUCCESS) 5579 sector_write_failed = TRUE; 5580 else { 5581 high_byte = 5582 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); 5583 udelay(100); 5584 } 5585 } else { 5586 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, 5587 &low_byte); 5588 udelay(100); 5589 error = e1000_verify_write_ich8_byte(hw, 5590 (i << 1) + new_bank_offset, low_byte); 5591 5592 if (error != E1000_SUCCESS) 5593 sector_write_failed = TRUE; 5594 else { 5595 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, 5596 &high_byte); 5597 udelay(100); 5598 } 5599 } 5600 5601 /* If the write of the low byte was successful, go ahread and 5602 * write the high byte while checking to make sure that if it 5603 * is the signature byte, then it is handled properly */ 5604 if (sector_write_failed == FALSE) { 5605 /* If the word is 0x13, then make sure the signature bits 5606 * (15:14) are 11b until the commit has completed. 5607 * This will allow us to write 10b which indicates the 5608 * signature is valid. We want to do this after the write 5609 * has completed so that we don't mark the segment valid 5610 * while the write is still in progress */ 5611 if (i == E1000_ICH_NVM_SIG_WORD) 5612 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; 5613 5614 error = e1000_verify_write_ich8_byte(hw, 5615 (i << 1) + new_bank_offset + 1, high_byte); 5616 if (error != E1000_SUCCESS) 5617 sector_write_failed = TRUE; 5618 5619 } else { 5620 /* If the write failed then break from the loop and 5621 * return an error */ 5622 break; 5623 } 5624 } 5625 5626 /* Don't bother writing the segment valid bits if sector 5627 * programming failed. */ 5628 if (sector_write_failed == FALSE) { 5629 /* Finally validate the new segment by setting bit 15:14 5630 * to 10b in word 0x13 , this can be done without an 5631 * erase as well since these bits are 11 to start with 5632 * and we need to change bit 14 to 0b */ 5633 e1000_read_ich8_byte(hw, 5634 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 5635 &high_byte); 5636 high_byte &= 0xBF; 5637 error = e1000_verify_write_ich8_byte(hw, 5638 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); 5639 /* And invalidate the previously valid segment by setting 5640 * its signature word (0x13) high_byte to 0b. This can be 5641 * done without an erase because flash erase sets all bits 5642 * to 1's. We can write 1's to 0's without an erase */ 5643 if (error == E1000_SUCCESS) { 5644 error = e1000_verify_write_ich8_byte(hw, 5645 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); 5646 } 5647 5648 /* Clear the now not used entry in the cache */ 5649 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5650 hw->eeprom_shadow_ram[i].modified = FALSE; 5651 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 5652 } 5653 } 5654 } 5655 5656 return error; 5657} 5658 5659/****************************************************************************** 5660 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 5661 * second function of dual function devices 5662 * 5663 * hw - Struct containing variables accessed by shared code 5664 *****************************************************************************/ 5665int32_t 5666e1000_read_mac_addr(struct e1000_hw * hw) 5667{ 5668 uint16_t offset; 5669 uint16_t eeprom_data, i; 5670 5671 DEBUGFUNC("e1000_read_mac_addr"); 5672 5673 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 5674 offset = i >> 1; 5675 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 5676 DEBUGOUT("EEPROM Read Error\n"); 5677 return -E1000_ERR_EEPROM; 5678 } 5679 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 5680 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); 5681 } 5682 5683 switch (hw->mac_type) { 5684 default: 5685 break; 5686 case e1000_82546: 5687 case e1000_82546_rev_3: 5688 case e1000_82571: 5689 case e1000_80003es2lan: 5690 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 5691 hw->perm_mac_addr[5] ^= 0x01; 5692 break; 5693 } 5694 5695 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 5696 hw->mac_addr[i] = hw->perm_mac_addr[i]; 5697 return E1000_SUCCESS; 5698} 5699 5700/****************************************************************************** 5701 * Initializes receive address filters. 5702 * 5703 * hw - Struct containing variables accessed by shared code 5704 * 5705 * Places the MAC address in receive address register 0 and clears the rest 5706 * of the receive addresss registers. Clears the multicast table. Assumes 5707 * the receiver is in reset when the routine is called. 5708 *****************************************************************************/ 5709static void 5710e1000_init_rx_addrs(struct e1000_hw *hw) 5711{ 5712 uint32_t i; 5713 uint32_t rar_num; 5714 5715 DEBUGFUNC("e1000_init_rx_addrs"); 5716 5717 /* Setup the receive address. */ 5718 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 5719 5720 e1000_rar_set(hw, hw->mac_addr, 0); 5721 5722 rar_num = E1000_RAR_ENTRIES; 5723 5724 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5725 rar_num -= 1; 5726 if (hw->mac_type == e1000_ich8lan) 5727 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 5728 5729 /* Zero out the other 15 receive addresses. */ 5730 DEBUGOUT("Clearing RAR[1-15]\n"); 5731 for (i = 1; i < rar_num; i++) { 5732 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5733 E1000_WRITE_FLUSH(hw); 5734 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5735 E1000_WRITE_FLUSH(hw); 5736 } 5737} 5738 5739/****************************************************************************** 5740 * Hashes an address to determine its location in the multicast table 5741 * 5742 * hw - Struct containing variables accessed by shared code 5743 * mc_addr - the multicast address to hash 5744 *****************************************************************************/ 5745uint32_t 5746e1000_hash_mc_addr(struct e1000_hw *hw, 5747 uint8_t *mc_addr) 5748{ 5749 uint32_t hash_value = 0; 5750 5751 /* The portion of the address that is used for the hash table is 5752 * determined by the mc_filter_type setting. 5753 */ 5754 switch (hw->mc_filter_type) { 5755 /* [0] [1] [2] [3] [4] [5] 5756 * 01 AA 00 12 34 56 5757 * LSB MSB 5758 */ 5759 case 0: 5760 if (hw->mac_type == e1000_ich8lan) { 5761 /* [47:38] i.e. 0x158 for above example address */ 5762 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); 5763 } else { 5764 /* [47:36] i.e. 0x563 for above example address */ 5765 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5766 } 5767 break; 5768 case 1: 5769 if (hw->mac_type == e1000_ich8lan) { 5770 /* [46:37] i.e. 0x2B1 for above example address */ 5771 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); 5772 } else { 5773 /* [46:35] i.e. 0xAC6 for above example address */ 5774 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5775 } 5776 break; 5777 case 2: 5778 if (hw->mac_type == e1000_ich8lan) { 5779 /*[45:36] i.e. 0x163 for above example address */ 5780 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5781 } else { 5782 /* [45:34] i.e. 0x5D8 for above example address */ 5783 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5784 } 5785 break; 5786 case 3: 5787 if (hw->mac_type == e1000_ich8lan) { 5788 /* [43:34] i.e. 0x18D for above example address */ 5789 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5790 } else { 5791 /* [43:32] i.e. 0x634 for above example address */ 5792 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5793 } 5794 break; 5795 } 5796 5797 hash_value &= 0xFFF; 5798 if (hw->mac_type == e1000_ich8lan) 5799 hash_value &= 0x3FF; 5800 5801 return hash_value; 5802} 5803 5804/****************************************************************************** 5805 * Sets the bit in the multicast table corresponding to the hash value. 5806 * 5807 * hw - Struct containing variables accessed by shared code 5808 * hash_value - Multicast address hash value 5809 *****************************************************************************/ 5810void 5811e1000_mta_set(struct e1000_hw *hw, 5812 uint32_t hash_value) 5813{ 5814 uint32_t hash_bit, hash_reg; 5815 uint32_t mta; 5816 uint32_t temp; 5817 5818 /* The MTA is a register array of 128 32-bit registers. 5819 * It is treated like an array of 4096 bits. We want to set 5820 * bit BitArray[hash_value]. So we figure out what register 5821 * the bit is in, read it, OR in the new bit, then write 5822 * back the new value. The register is determined by the 5823 * upper 7 bits of the hash value and the bit within that 5824 * register are determined by the lower 5 bits of the value. 5825 */ 5826 hash_reg = (hash_value >> 5) & 0x7F; 5827 if (hw->mac_type == e1000_ich8lan) 5828 hash_reg &= 0x1F; 5829 5830 hash_bit = hash_value & 0x1F; 5831 5832 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5833 5834 mta |= (1 << hash_bit); 5835 5836 /* If we are on an 82544 and we are trying to write an odd offset 5837 * in the MTA, save off the previous entry before writing and 5838 * restore the old value after writing. 5839 */ 5840 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5841 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5842 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5843 E1000_WRITE_FLUSH(hw); 5844 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 5845 E1000_WRITE_FLUSH(hw); 5846 } else { 5847 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5848 E1000_WRITE_FLUSH(hw); 5849 } 5850} 5851 5852/****************************************************************************** 5853 * Puts an ethernet address into a receive address register. 5854 * 5855 * hw - Struct containing variables accessed by shared code 5856 * addr - Address to put into receive address register 5857 * index - Receive address register to write 5858 *****************************************************************************/ 5859void 5860e1000_rar_set(struct e1000_hw *hw, 5861 uint8_t *addr, 5862 uint32_t index) 5863{ 5864 uint32_t rar_low, rar_high; 5865 5866 /* HW expects these in little endian so we reverse the byte order 5867 * from network order (big endian) to little endian 5868 */ 5869 rar_low = ((uint32_t) addr[0] | 5870 ((uint32_t) addr[1] << 8) | 5871 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 5872 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 5873 5874 switch (hw->mac_type) { 5875 case e1000_82571: 5876 case e1000_82572: 5877 case e1000_80003es2lan: 5878 if (hw->leave_av_bit_off == TRUE) 5879 break; 5880 default: 5881 /* Indicate to hardware the Address is Valid. */ 5882 rar_high |= E1000_RAH_AV; 5883 break; 5884 } 5885 5886 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 5887 E1000_WRITE_FLUSH(hw); 5888 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 5889 E1000_WRITE_FLUSH(hw); 5890} 5891 5892/****************************************************************************** 5893 * Writes a value to the specified offset in the VLAN filter table. 5894 * 5895 * hw - Struct containing variables accessed by shared code 5896 * offset - Offset in VLAN filer table to write 5897 * value - Value to write into VLAN filter table 5898 *****************************************************************************/ 5899void 5900e1000_write_vfta(struct e1000_hw *hw, 5901 uint32_t offset, 5902 uint32_t value) 5903{ 5904 uint32_t temp; 5905 5906 if (hw->mac_type == e1000_ich8lan) 5907 return; 5908 5909 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 5910 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 5911 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5912 E1000_WRITE_FLUSH(hw); 5913 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 5914 E1000_WRITE_FLUSH(hw); 5915 } else { 5916 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5917 E1000_WRITE_FLUSH(hw); 5918 } 5919} 5920 5921/****************************************************************************** 5922 * Clears the VLAN filer table 5923 * 5924 * hw - Struct containing variables accessed by shared code 5925 *****************************************************************************/ 5926static void 5927e1000_clear_vfta(struct e1000_hw *hw) 5928{ 5929 uint32_t offset; 5930 uint32_t vfta_value = 0; 5931 uint32_t vfta_offset = 0; 5932 uint32_t vfta_bit_in_reg = 0; 5933 5934 if (hw->mac_type == e1000_ich8lan) 5935 return; 5936 5937 if (hw->mac_type == e1000_82573) { 5938 if (hw->mng_cookie.vlan_id != 0) { 5939 /* The VFTA is a 4096b bit-field, each identifying a single VLAN 5940 * ID. The following operations determine which 32b entry 5941 * (i.e. offset) into the array we want to set the VLAN ID 5942 * (i.e. bit) of the manageability unit. */ 5943 vfta_offset = (hw->mng_cookie.vlan_id >> 5944 E1000_VFTA_ENTRY_SHIFT) & 5945 E1000_VFTA_ENTRY_MASK; 5946 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 5947 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 5948 } 5949 } 5950 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 5951 /* If the offset we want to clear is the same offset of the 5952 * manageability VLAN ID, then clear all bits except that of the 5953 * manageability unit */ 5954 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 5955 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 5956 E1000_WRITE_FLUSH(hw); 5957 } 5958} 5959 5960static int32_t 5961e1000_id_led_init(struct e1000_hw * hw) 5962{ 5963 uint32_t ledctl; 5964 const uint32_t ledctl_mask = 0x000000FF; 5965 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 5966 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 5967 uint16_t eeprom_data, i, temp; 5968 const uint16_t led_mask = 0x0F; 5969 5970 DEBUGFUNC("e1000_id_led_init"); 5971 5972 if (hw->mac_type < e1000_82540) { 5973 /* Nothing to do */ 5974 return E1000_SUCCESS; 5975 } 5976 5977 ledctl = E1000_READ_REG(hw, LEDCTL); 5978 hw->ledctl_default = ledctl; 5979 hw->ledctl_mode1 = hw->ledctl_default; 5980 hw->ledctl_mode2 = hw->ledctl_default; 5981 5982 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 5983 DEBUGOUT("EEPROM Read Error\n"); 5984 return -E1000_ERR_EEPROM; 5985 } 5986 5987 if ((hw->mac_type == e1000_82573) && 5988 (eeprom_data == ID_LED_RESERVED_82573)) 5989 eeprom_data = ID_LED_DEFAULT_82573; 5990 else if ((eeprom_data == ID_LED_RESERVED_0000) || 5991 (eeprom_data == ID_LED_RESERVED_FFFF)) { 5992 if (hw->mac_type == e1000_ich8lan) 5993 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 5994 else 5995 eeprom_data = ID_LED_DEFAULT; 5996 } 5997 5998 for (i = 0; i < 4; i++) { 5999 temp = (eeprom_data >> (i << 2)) & led_mask; 6000 switch (temp) { 6001 case ID_LED_ON1_DEF2: 6002 case ID_LED_ON1_ON2: 6003 case ID_LED_ON1_OFF2: 6004 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 6005 hw->ledctl_mode1 |= ledctl_on << (i << 3); 6006 break; 6007 case ID_LED_OFF1_DEF2: 6008 case ID_LED_OFF1_ON2: 6009 case ID_LED_OFF1_OFF2: 6010 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 6011 hw->ledctl_mode1 |= ledctl_off << (i << 3); 6012 break; 6013 default: 6014 /* Do nothing */ 6015 break; 6016 } 6017 switch (temp) { 6018 case ID_LED_DEF1_ON2: 6019 case ID_LED_ON1_ON2: 6020 case ID_LED_OFF1_ON2: 6021 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 6022 hw->ledctl_mode2 |= ledctl_on << (i << 3); 6023 break; 6024 case ID_LED_DEF1_OFF2: 6025 case ID_LED_ON1_OFF2: 6026 case ID_LED_OFF1_OFF2: 6027 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 6028 hw->ledctl_mode2 |= ledctl_off << (i << 3); 6029 break; 6030 default: 6031 /* Do nothing */ 6032 break; 6033 } 6034 } 6035 return E1000_SUCCESS; 6036} 6037 6038/****************************************************************************** 6039 * Prepares SW controlable LED for use and saves the current state of the LED. 6040 * 6041 * hw - Struct containing variables accessed by shared code 6042 *****************************************************************************/ 6043int32_t 6044e1000_setup_led(struct e1000_hw *hw) 6045{ 6046 uint32_t ledctl; 6047 int32_t ret_val = E1000_SUCCESS; 6048 6049 DEBUGFUNC("e1000_setup_led"); 6050 6051 switch (hw->mac_type) { 6052 case e1000_82542_rev2_0: 6053 case e1000_82542_rev2_1: 6054 case e1000_82543: 6055 case e1000_82544: 6056 /* No setup necessary */ 6057 break; 6058 case e1000_82541: 6059 case e1000_82547: 6060 case e1000_82541_rev_2: 6061 case e1000_82547_rev_2: 6062 /* Turn off PHY Smart Power Down (if enabled) */ 6063 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 6064 &hw->phy_spd_default); 6065 if (ret_val) 6066 return ret_val; 6067 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6068 (uint16_t)(hw->phy_spd_default & 6069 ~IGP01E1000_GMII_SPD)); 6070 if (ret_val) 6071 return ret_val; 6072 /* Fall Through */ 6073 default: 6074 if (hw->media_type == e1000_media_type_fiber) { 6075 ledctl = E1000_READ_REG(hw, LEDCTL); 6076 /* Save current LEDCTL settings */ 6077 hw->ledctl_default = ledctl; 6078 /* Turn off LED0 */ 6079 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 6080 E1000_LEDCTL_LED0_BLINK | 6081 E1000_LEDCTL_LED0_MODE_MASK); 6082 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 6083 E1000_LEDCTL_LED0_MODE_SHIFT); 6084 E1000_WRITE_REG(hw, LEDCTL, ledctl); 6085 } else if (hw->media_type == e1000_media_type_copper) 6086 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6087 break; 6088 } 6089 6090 return E1000_SUCCESS; 6091} 6092 6093 6094/****************************************************************************** 6095 * Used on 82571 and later Si that has LED blink bits. 6096 * Callers must use their own timer and should have already called 6097 * e1000_id_led_init() 6098 * Call e1000_cleanup led() to stop blinking 6099 * 6100 * hw - Struct containing variables accessed by shared code 6101 *****************************************************************************/ 6102int32_t 6103e1000_blink_led_start(struct e1000_hw *hw) 6104{ 6105 int16_t i; 6106 uint32_t ledctl_blink = 0; 6107 6108 DEBUGFUNC("e1000_id_led_blink_on"); 6109 6110 if (hw->mac_type < e1000_82571) { 6111 /* Nothing to do */ 6112 return E1000_SUCCESS; 6113 } 6114 if (hw->media_type == e1000_media_type_fiber) { 6115 /* always blink LED0 for PCI-E fiber */ 6116 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 6117 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 6118 } else { 6119 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ 6120 ledctl_blink = hw->ledctl_mode2; 6121 for (i=0; i < 4; i++) 6122 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == 6123 E1000_LEDCTL_MODE_LED_ON) 6124 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); 6125 } 6126 6127 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); 6128 6129 return E1000_SUCCESS; 6130} 6131 6132/****************************************************************************** 6133 * Restores the saved state of the SW controlable LED. 6134 * 6135 * hw - Struct containing variables accessed by shared code 6136 *****************************************************************************/ 6137int32_t 6138e1000_cleanup_led(struct e1000_hw *hw) 6139{ 6140 int32_t ret_val = E1000_SUCCESS; 6141 6142 DEBUGFUNC("e1000_cleanup_led"); 6143 6144 switch (hw->mac_type) { 6145 case e1000_82542_rev2_0: 6146 case e1000_82542_rev2_1: 6147 case e1000_82543: 6148 case e1000_82544: 6149 /* No cleanup necessary */ 6150 break; 6151 case e1000_82541: 6152 case e1000_82547: 6153 case e1000_82541_rev_2: 6154 case e1000_82547_rev_2: 6155 /* Turn on PHY Smart Power Down (if previously enabled) */ 6156 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6157 hw->phy_spd_default); 6158 if (ret_val) 6159 return ret_val; 6160 /* Fall Through */ 6161 default: 6162 if (hw->phy_type == e1000_phy_ife) { 6163 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 6164 break; 6165 } 6166 /* Restore LEDCTL settings */ 6167 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 6168 break; 6169 } 6170 6171 return E1000_SUCCESS; 6172} 6173 6174/****************************************************************************** 6175 * Turns on the software controllable LED 6176 * 6177 * hw - Struct containing variables accessed by shared code 6178 *****************************************************************************/ 6179int32_t 6180e1000_led_on(struct e1000_hw *hw) 6181{ 6182 uint32_t ctrl = E1000_READ_REG(hw, CTRL); 6183 6184 DEBUGFUNC("e1000_led_on"); 6185 6186 switch (hw->mac_type) { 6187 case e1000_82542_rev2_0: 6188 case e1000_82542_rev2_1: 6189 case e1000_82543: 6190 /* Set SW Defineable Pin 0 to turn on the LED */ 6191 ctrl |= E1000_CTRL_SWDPIN0; 6192 ctrl |= E1000_CTRL_SWDPIO0; 6193 break; 6194 case e1000_82544: 6195 if (hw->media_type == e1000_media_type_fiber) { 6196 /* Set SW Defineable Pin 0 to turn on the LED */ 6197 ctrl |= E1000_CTRL_SWDPIN0; 6198 ctrl |= E1000_CTRL_SWDPIO0; 6199 } else { 6200 /* Clear SW Defineable Pin 0 to turn on the LED */ 6201 ctrl &= ~E1000_CTRL_SWDPIN0; 6202 ctrl |= E1000_CTRL_SWDPIO0; 6203 } 6204 break; 6205 default: 6206 if (hw->media_type == e1000_media_type_fiber) { 6207 /* Clear SW Defineable Pin 0 to turn on the LED */ 6208 ctrl &= ~E1000_CTRL_SWDPIN0; 6209 ctrl |= E1000_CTRL_SWDPIO0; 6210 } else if (hw->phy_type == e1000_phy_ife) { 6211 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 6212 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 6213 } else if (hw->media_type == e1000_media_type_copper) { 6214 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 6215 return E1000_SUCCESS; 6216 } 6217 break; 6218 } 6219 6220 E1000_WRITE_REG(hw, CTRL, ctrl); 6221 6222 return E1000_SUCCESS; 6223} 6224 6225/****************************************************************************** 6226 * Turns off the software controllable LED 6227 * 6228 * hw - Struct containing variables accessed by shared code 6229 *****************************************************************************/ 6230int32_t 6231e1000_led_off(struct e1000_hw *hw) 6232{ 6233 uint32_t ctrl = E1000_READ_REG(hw, CTRL); 6234 6235 DEBUGFUNC("e1000_led_off"); 6236 6237 switch (hw->mac_type) { 6238 case e1000_82542_rev2_0: 6239 case e1000_82542_rev2_1: 6240 case e1000_82543: 6241 /* Clear SW Defineable Pin 0 to turn off the LED */ 6242 ctrl &= ~E1000_CTRL_SWDPIN0; 6243 ctrl |= E1000_CTRL_SWDPIO0; 6244 break; 6245 case e1000_82544: 6246 if (hw->media_type == e1000_media_type_fiber) { 6247 /* Clear SW Defineable Pin 0 to turn off the LED */ 6248 ctrl &= ~E1000_CTRL_SWDPIN0; 6249 ctrl |= E1000_CTRL_SWDPIO0; 6250 } else { 6251 /* Set SW Defineable Pin 0 to turn off the LED */ 6252 ctrl |= E1000_CTRL_SWDPIN0; 6253 ctrl |= E1000_CTRL_SWDPIO0; 6254 } 6255 break; 6256 default: 6257 if (hw->media_type == e1000_media_type_fiber) { 6258 /* Set SW Defineable Pin 0 to turn off the LED */ 6259 ctrl |= E1000_CTRL_SWDPIN0; 6260 ctrl |= E1000_CTRL_SWDPIO0; 6261 } else if (hw->phy_type == e1000_phy_ife) { 6262 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 6263 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 6264 } else if (hw->media_type == e1000_media_type_copper) { 6265 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6266 return E1000_SUCCESS; 6267 } 6268 break; 6269 } 6270 6271 E1000_WRITE_REG(hw, CTRL, ctrl); 6272 6273 return E1000_SUCCESS; 6274} 6275 6276/****************************************************************************** 6277 * Clears all hardware statistics counters. 6278 * 6279 * hw - Struct containing variables accessed by shared code 6280 *****************************************************************************/ 6281static void 6282e1000_clear_hw_cntrs(struct e1000_hw *hw) 6283{ 6284 volatile uint32_t temp; 6285 6286 temp = E1000_READ_REG(hw, CRCERRS); 6287 temp = E1000_READ_REG(hw, SYMERRS); 6288 temp = E1000_READ_REG(hw, MPC); 6289 temp = E1000_READ_REG(hw, SCC); 6290 temp = E1000_READ_REG(hw, ECOL); 6291 temp = E1000_READ_REG(hw, MCC); 6292 temp = E1000_READ_REG(hw, LATECOL); 6293 temp = E1000_READ_REG(hw, COLC); 6294 temp = E1000_READ_REG(hw, DC); 6295 temp = E1000_READ_REG(hw, SEC); 6296 temp = E1000_READ_REG(hw, RLEC); 6297 temp = E1000_READ_REG(hw, XONRXC); 6298 temp = E1000_READ_REG(hw, XONTXC); 6299 temp = E1000_READ_REG(hw, XOFFRXC); 6300 temp = E1000_READ_REG(hw, XOFFTXC); 6301 temp = E1000_READ_REG(hw, FCRUC); 6302 6303 if (hw->mac_type != e1000_ich8lan) { 6304 temp = E1000_READ_REG(hw, PRC64); 6305 temp = E1000_READ_REG(hw, PRC127); 6306 temp = E1000_READ_REG(hw, PRC255); 6307 temp = E1000_READ_REG(hw, PRC511); 6308 temp = E1000_READ_REG(hw, PRC1023); 6309 temp = E1000_READ_REG(hw, PRC1522); 6310 } 6311 6312 temp = E1000_READ_REG(hw, GPRC); 6313 temp = E1000_READ_REG(hw, BPRC); 6314 temp = E1000_READ_REG(hw, MPRC); 6315 temp = E1000_READ_REG(hw, GPTC); 6316 temp = E1000_READ_REG(hw, GORCL); 6317 temp = E1000_READ_REG(hw, GORCH); 6318 temp = E1000_READ_REG(hw, GOTCL); 6319 temp = E1000_READ_REG(hw, GOTCH); 6320 temp = E1000_READ_REG(hw, RNBC); 6321 temp = E1000_READ_REG(hw, RUC); 6322 temp = E1000_READ_REG(hw, RFC); 6323 temp = E1000_READ_REG(hw, ROC); 6324 temp = E1000_READ_REG(hw, RJC); 6325 temp = E1000_READ_REG(hw, TORL); 6326 temp = E1000_READ_REG(hw, TORH); 6327 temp = E1000_READ_REG(hw, TOTL); 6328 temp = E1000_READ_REG(hw, TOTH); 6329 temp = E1000_READ_REG(hw, TPR); 6330 temp = E1000_READ_REG(hw, TPT); 6331 6332 if (hw->mac_type != e1000_ich8lan) { 6333 temp = E1000_READ_REG(hw, PTC64); 6334 temp = E1000_READ_REG(hw, PTC127); 6335 temp = E1000_READ_REG(hw, PTC255); 6336 temp = E1000_READ_REG(hw, PTC511); 6337 temp = E1000_READ_REG(hw, PTC1023); 6338 temp = E1000_READ_REG(hw, PTC1522); 6339 } 6340 6341 temp = E1000_READ_REG(hw, MPTC); 6342 temp = E1000_READ_REG(hw, BPTC); 6343 6344 if (hw->mac_type < e1000_82543) return; 6345 6346 temp = E1000_READ_REG(hw, ALGNERRC); 6347 temp = E1000_READ_REG(hw, RXERRC); 6348 temp = E1000_READ_REG(hw, TNCRS); 6349 temp = E1000_READ_REG(hw, CEXTERR); 6350 temp = E1000_READ_REG(hw, TSCTC); 6351 temp = E1000_READ_REG(hw, TSCTFC); 6352 6353 if (hw->mac_type <= e1000_82544) return; 6354 6355 temp = E1000_READ_REG(hw, MGTPRC); 6356 temp = E1000_READ_REG(hw, MGTPDC); 6357 temp = E1000_READ_REG(hw, MGTPTC); 6358 6359 if (hw->mac_type <= e1000_82547_rev_2) return; 6360 6361 temp = E1000_READ_REG(hw, IAC); 6362 temp = E1000_READ_REG(hw, ICRXOC); 6363 6364 if (hw->mac_type == e1000_ich8lan) return; 6365 6366 temp = E1000_READ_REG(hw, ICRXPTC); 6367 temp = E1000_READ_REG(hw, ICRXATC); 6368 temp = E1000_READ_REG(hw, ICTXPTC); 6369 temp = E1000_READ_REG(hw, ICTXATC); 6370 temp = E1000_READ_REG(hw, ICTXQEC); 6371 temp = E1000_READ_REG(hw, ICTXQMTC); 6372 temp = E1000_READ_REG(hw, ICRXDMTC); 6373} 6374 6375/****************************************************************************** 6376 * Resets Adaptive IFS to its default state. 6377 * 6378 * hw - Struct containing variables accessed by shared code 6379 * 6380 * Call this after e1000_init_hw. You may override the IFS defaults by setting 6381 * hw->ifs_params_forced to TRUE. However, you must initialize hw-> 6382 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 6383 * before calling this function. 6384 *****************************************************************************/ 6385void 6386e1000_reset_adaptive(struct e1000_hw *hw) 6387{ 6388 DEBUGFUNC("e1000_reset_adaptive"); 6389 6390 if (hw->adaptive_ifs) { 6391 if (!hw->ifs_params_forced) { 6392 hw->current_ifs_val = 0; 6393 hw->ifs_min_val = IFS_MIN; 6394 hw->ifs_max_val = IFS_MAX; 6395 hw->ifs_step_size = IFS_STEP; 6396 hw->ifs_ratio = IFS_RATIO; 6397 } 6398 hw->in_ifs_mode = FALSE; 6399 E1000_WRITE_REG(hw, AIT, 0); 6400 } else { 6401 DEBUGOUT("Not in Adaptive IFS mode!\n"); 6402 } 6403} 6404 6405/****************************************************************************** 6406 * Called during the callback/watchdog routine to update IFS value based on 6407 * the ratio of transmits to collisions. 6408 * 6409 * hw - Struct containing variables accessed by shared code 6410 * tx_packets - Number of transmits since last callback 6411 * total_collisions - Number of collisions since last callback 6412 *****************************************************************************/ 6413void 6414e1000_update_adaptive(struct e1000_hw *hw) 6415{ 6416 DEBUGFUNC("e1000_update_adaptive"); 6417 6418 if (hw->adaptive_ifs) { 6419 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { 6420 if (hw->tx_packet_delta > MIN_NUM_XMITS) { 6421 hw->in_ifs_mode = TRUE; 6422 if (hw->current_ifs_val < hw->ifs_max_val) { 6423 if (hw->current_ifs_val == 0) 6424 hw->current_ifs_val = hw->ifs_min_val; 6425 else 6426 hw->current_ifs_val += hw->ifs_step_size; 6427 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); 6428 } 6429 } 6430 } else { 6431 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 6432 hw->current_ifs_val = 0; 6433 hw->in_ifs_mode = FALSE; 6434 E1000_WRITE_REG(hw, AIT, 0); 6435 } 6436 } 6437 } else { 6438 DEBUGOUT("Not in Adaptive IFS mode!\n"); 6439 } 6440} 6441 6442/****************************************************************************** 6443 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 6444 * 6445 * hw - Struct containing variables accessed by shared code 6446 * frame_len - The length of the frame in question 6447 * mac_addr - The Ethernet destination address of the frame in question 6448 *****************************************************************************/ 6449void 6450e1000_tbi_adjust_stats(struct e1000_hw *hw, 6451 struct e1000_hw_stats *stats, 6452 uint32_t frame_len, 6453 uint8_t *mac_addr) 6454{ 6455 uint64_t carry_bit; 6456 6457 /* First adjust the frame length. */ 6458 frame_len--; 6459 /* We need to adjust the statistics counters, since the hardware 6460 * counters overcount this packet as a CRC error and undercount 6461 * the packet as a good packet 6462 */ 6463 /* This packet should not be counted as a CRC error. */ 6464 stats->crcerrs--; 6465 /* This packet does count as a Good Packet Received. */ 6466 stats->gprc++; 6467 6468 /* Adjust the Good Octets received counters */ 6469 carry_bit = 0x80000000 & stats->gorcl; 6470 stats->gorcl += frame_len; 6471 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 6472 * Received Count) was one before the addition, 6473 * AND it is zero after, then we lost the carry out, 6474 * need to add one to Gorch (Good Octets Received Count High). 6475 * This could be simplified if all environments supported 6476 * 64-bit integers. 6477 */ 6478 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 6479 stats->gorch++; 6480 /* Is this a broadcast or multicast? Check broadcast first, 6481 * since the test for a multicast frame will test positive on 6482 * a broadcast frame. 6483 */ 6484 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 6485 /* Broadcast packet */ 6486 stats->bprc++; 6487 else if (*mac_addr & 0x01) 6488 /* Multicast packet */ 6489 stats->mprc++; 6490 6491 if (frame_len == hw->max_frame_size) { 6492 /* In this case, the hardware has overcounted the number of 6493 * oversize frames. 6494 */ 6495 if (stats->roc > 0) 6496 stats->roc--; 6497 } 6498 6499 /* Adjust the bin counters when the extra byte put the frame in the 6500 * wrong bin. Remember that the frame_len was adjusted above. 6501 */ 6502 if (frame_len == 64) { 6503 stats->prc64++; 6504 stats->prc127--; 6505 } else if (frame_len == 127) { 6506 stats->prc127++; 6507 stats->prc255--; 6508 } else if (frame_len == 255) { 6509 stats->prc255++; 6510 stats->prc511--; 6511 } else if (frame_len == 511) { 6512 stats->prc511++; 6513 stats->prc1023--; 6514 } else if (frame_len == 1023) { 6515 stats->prc1023++; 6516 stats->prc1522--; 6517 } else if (frame_len == 1522) { 6518 stats->prc1522++; 6519 } 6520} 6521 6522/****************************************************************************** 6523 * Gets the current PCI bus type, speed, and width of the hardware 6524 * 6525 * hw - Struct containing variables accessed by shared code 6526 *****************************************************************************/ 6527void 6528e1000_get_bus_info(struct e1000_hw *hw) 6529{ 6530 int32_t ret_val; 6531 uint16_t pci_ex_link_status; 6532 uint32_t status; 6533 6534 switch (hw->mac_type) { 6535 case e1000_82542_rev2_0: 6536 case e1000_82542_rev2_1: 6537 hw->bus_type = e1000_bus_type_pci; 6538 hw->bus_speed = e1000_bus_speed_unknown; 6539 hw->bus_width = e1000_bus_width_unknown; 6540 break; 6541 case e1000_82571: 6542 case e1000_82572: 6543 case e1000_82573: 6544 case e1000_80003es2lan: 6545 hw->bus_type = e1000_bus_type_pci_express; 6546 hw->bus_speed = e1000_bus_speed_2500; 6547 ret_val = e1000_read_pcie_cap_reg(hw, 6548 PCI_EX_LINK_STATUS, 6549 &pci_ex_link_status); 6550 if (ret_val) 6551 hw->bus_width = e1000_bus_width_unknown; 6552 else 6553 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> 6554 PCI_EX_LINK_WIDTH_SHIFT; 6555 break; 6556 case e1000_ich8lan: 6557 hw->bus_type = e1000_bus_type_pci_express; 6558 hw->bus_speed = e1000_bus_speed_2500; 6559 hw->bus_width = e1000_bus_width_pciex_1; 6560 break; 6561 default: 6562 status = E1000_READ_REG(hw, STATUS); 6563 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 6564 e1000_bus_type_pcix : e1000_bus_type_pci; 6565 6566 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 6567 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 6568 e1000_bus_speed_66 : e1000_bus_speed_120; 6569 } else if (hw->bus_type == e1000_bus_type_pci) { 6570 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 6571 e1000_bus_speed_66 : e1000_bus_speed_33; 6572 } else { 6573 switch (status & E1000_STATUS_PCIX_SPEED) { 6574 case E1000_STATUS_PCIX_SPEED_66: 6575 hw->bus_speed = e1000_bus_speed_66; 6576 break; 6577 case E1000_STATUS_PCIX_SPEED_100: 6578 hw->bus_speed = e1000_bus_speed_100; 6579 break; 6580 case E1000_STATUS_PCIX_SPEED_133: 6581 hw->bus_speed = e1000_bus_speed_133; 6582 break; 6583 default: 6584 hw->bus_speed = e1000_bus_speed_reserved; 6585 break; 6586 } 6587 } 6588 hw->bus_width = (status & E1000_STATUS_BUS64) ? 6589 e1000_bus_width_64 : e1000_bus_width_32; 6590 break; 6591 } 6592} 6593 6594/****************************************************************************** 6595 * Writes a value to one of the devices registers using port I/O (as opposed to 6596 * memory mapped I/O). Only 82544 and newer devices support port I/O. 6597 * 6598 * hw - Struct containing variables accessed by shared code 6599 * offset - offset to write to 6600 * value - value to write 6601 *****************************************************************************/ 6602static void 6603e1000_write_reg_io(struct e1000_hw *hw, 6604 uint32_t offset, 6605 uint32_t value) 6606{ 6607 unsigned long io_addr = hw->io_base; 6608 unsigned long io_data = hw->io_base + 4; 6609 6610 e1000_io_write(hw, io_addr, offset); 6611 e1000_io_write(hw, io_data, value); 6612} 6613 6614/****************************************************************************** 6615 * Estimates the cable length. 6616 * 6617 * hw - Struct containing variables accessed by shared code 6618 * min_length - The estimated minimum length 6619 * max_length - The estimated maximum length 6620 * 6621 * returns: - E1000_ERR_XXX 6622 * E1000_SUCCESS 6623 * 6624 * This function always returns a ranged length (minimum & maximum). 6625 * So for M88 phy's, this function interprets the one value returned from the 6626 * register to the minimum and maximum range. 6627 * For IGP phy's, the function calculates the range by the AGC registers. 6628 *****************************************************************************/ 6629static int32_t 6630e1000_get_cable_length(struct e1000_hw *hw, 6631 uint16_t *min_length, 6632 uint16_t *max_length) 6633{ 6634 int32_t ret_val; 6635 uint16_t agc_value = 0; 6636 uint16_t i, phy_data; 6637 uint16_t cable_length; 6638 6639 DEBUGFUNC("e1000_get_cable_length"); 6640 6641 *min_length = *max_length = 0; 6642 6643 /* Use old method for Phy older than IGP */ 6644 if (hw->phy_type == e1000_phy_m88) { 6645 6646 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6647 &phy_data); 6648 if (ret_val) 6649 return ret_val; 6650 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 6651 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 6652 6653 /* Convert the enum value to ranged values */ 6654 switch (cable_length) { 6655 case e1000_cable_length_50: 6656 *min_length = 0; 6657 *max_length = e1000_igp_cable_length_50; 6658 break; 6659 case e1000_cable_length_50_80: 6660 *min_length = e1000_igp_cable_length_50; 6661 *max_length = e1000_igp_cable_length_80; 6662 break; 6663 case e1000_cable_length_80_110: 6664 *min_length = e1000_igp_cable_length_80; 6665 *max_length = e1000_igp_cable_length_110; 6666 break; 6667 case e1000_cable_length_110_140: 6668 *min_length = e1000_igp_cable_length_110; 6669 *max_length = e1000_igp_cable_length_140; 6670 break; 6671 case e1000_cable_length_140: 6672 *min_length = e1000_igp_cable_length_140; 6673 *max_length = e1000_igp_cable_length_170; 6674 break; 6675 default: 6676 return -E1000_ERR_PHY; 6677 break; 6678 } 6679 } else if (hw->phy_type == e1000_phy_gg82563) { 6680 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 6681 &phy_data); 6682 if (ret_val) 6683 return ret_val; 6684 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 6685 6686 switch (cable_length) { 6687 case e1000_gg_cable_length_60: 6688 *min_length = 0; 6689 *max_length = e1000_igp_cable_length_60; 6690 break; 6691 case e1000_gg_cable_length_60_115: 6692 *min_length = e1000_igp_cable_length_60; 6693 *max_length = e1000_igp_cable_length_115; 6694 break; 6695 case e1000_gg_cable_length_115_150: 6696 *min_length = e1000_igp_cable_length_115; 6697 *max_length = e1000_igp_cable_length_150; 6698 break; 6699 case e1000_gg_cable_length_150: 6700 *min_length = e1000_igp_cable_length_150; 6701 *max_length = e1000_igp_cable_length_180; 6702 break; 6703 default: 6704 return -E1000_ERR_PHY; 6705 break; 6706 } 6707 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6708 uint16_t cur_agc_value; 6709 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 6710 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6711 {IGP01E1000_PHY_AGC_A, 6712 IGP01E1000_PHY_AGC_B, 6713 IGP01E1000_PHY_AGC_C, 6714 IGP01E1000_PHY_AGC_D}; 6715 /* Read the AGC registers for all channels */ 6716 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6717 6718 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 6719 if (ret_val) 6720 return ret_val; 6721 6722 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6723 6724 /* Value bound check. */ 6725 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 6726 (cur_agc_value == 0)) 6727 return -E1000_ERR_PHY; 6728 6729 agc_value += cur_agc_value; 6730 6731 /* Update minimal AGC value. */ 6732 if (min_agc_value > cur_agc_value) 6733 min_agc_value = cur_agc_value; 6734 } 6735 6736 /* Remove the minimal AGC result for length < 50m */ 6737 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 6738 agc_value -= min_agc_value; 6739 6740 /* Get the average length of the remaining 3 channels */ 6741 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 6742 } else { 6743 /* Get the average length of all the 4 channels. */ 6744 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 6745 } 6746 6747 /* Set the range of the calculated length. */ 6748 *min_length = ((e1000_igp_cable_length_table[agc_value] - 6749 IGP01E1000_AGC_RANGE) > 0) ? 6750 (e1000_igp_cable_length_table[agc_value] - 6751 IGP01E1000_AGC_RANGE) : 0; 6752 *max_length = e1000_igp_cable_length_table[agc_value] + 6753 IGP01E1000_AGC_RANGE; 6754 } else if (hw->phy_type == e1000_phy_igp_2 || 6755 hw->phy_type == e1000_phy_igp_3) { 6756 uint16_t cur_agc_index, max_agc_index = 0; 6757 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 6758 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6759 {IGP02E1000_PHY_AGC_A, 6760 IGP02E1000_PHY_AGC_B, 6761 IGP02E1000_PHY_AGC_C, 6762 IGP02E1000_PHY_AGC_D}; 6763 /* Read the AGC registers for all channels */ 6764 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 6765 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 6766 if (ret_val) 6767 return ret_val; 6768 6769 /* Getting bits 15:9, which represent the combination of course and 6770 * fine gain values. The result is a number that can be put into 6771 * the lookup table to obtain the approximate cable length. */ 6772 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6773 IGP02E1000_AGC_LENGTH_MASK; 6774 6775 /* Array index bound check. */ 6776 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || 6777 (cur_agc_index == 0)) 6778 return -E1000_ERR_PHY; 6779 6780 /* Remove min & max AGC values from calculation. */ 6781 if (e1000_igp_2_cable_length_table[min_agc_index] > 6782 e1000_igp_2_cable_length_table[cur_agc_index]) 6783 min_agc_index = cur_agc_index; 6784 if (e1000_igp_2_cable_length_table[max_agc_index] < 6785 e1000_igp_2_cable_length_table[cur_agc_index]) 6786 max_agc_index = cur_agc_index; 6787 6788 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 6789 } 6790 6791 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 6792 e1000_igp_2_cable_length_table[max_agc_index]); 6793 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 6794 6795 /* Calculate cable length with the error range of +/- 10 meters. */ 6796 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 6797 (agc_value - IGP02E1000_AGC_RANGE) : 0; 6798 *max_length = agc_value + IGP02E1000_AGC_RANGE; 6799 } 6800 6801 return E1000_SUCCESS; 6802} 6803 6804/****************************************************************************** 6805 * Check the cable polarity 6806 * 6807 * hw - Struct containing variables accessed by shared code 6808 * polarity - output parameter : 0 - Polarity is not reversed 6809 * 1 - Polarity is reversed. 6810 * 6811 * returns: - E1000_ERR_XXX 6812 * E1000_SUCCESS 6813 * 6814 * For phy's older then IGP, this function simply reads the polarity bit in the 6815 * Phy Status register. For IGP phy's, this bit is valid only if link speed is 6816 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 6817 * return 0. If the link speed is 1000 Mbps the polarity status is in the 6818 * IGP01E1000_PHY_PCS_INIT_REG. 6819 *****************************************************************************/ 6820static int32_t 6821e1000_check_polarity(struct e1000_hw *hw, 6822 e1000_rev_polarity *polarity) 6823{ 6824 int32_t ret_val; 6825 uint16_t phy_data; 6826 6827 DEBUGFUNC("e1000_check_polarity"); 6828 6829 if ((hw->phy_type == e1000_phy_m88) || 6830 (hw->phy_type == e1000_phy_gg82563)) { 6831 /* return the Polarity bit in the Status register. */ 6832 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6833 &phy_data); 6834 if (ret_val) 6835 return ret_val; 6836 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 6837 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 6838 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 6839 6840 } else if (hw->phy_type == e1000_phy_igp || 6841 hw->phy_type == e1000_phy_igp_3 || 6842 hw->phy_type == e1000_phy_igp_2) { 6843 /* Read the Status register to check the speed */ 6844 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6845 &phy_data); 6846 if (ret_val) 6847 return ret_val; 6848 6849 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 6850 * find the polarity status */ 6851 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 6852 IGP01E1000_PSSR_SPEED_1000MBPS) { 6853 6854 /* Read the GIG initialization PCS register (0x00B4) */ 6855 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 6856 &phy_data); 6857 if (ret_val) 6858 return ret_val; 6859 6860 /* Check the polarity bits */ 6861 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 6862 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 6863 } else { 6864 /* For 10 Mbps, read the polarity bit in the status register. (for 6865 * 100 Mbps this bit is always 0) */ 6866 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 6867 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 6868 } 6869 } else if (hw->phy_type == e1000_phy_ife) { 6870 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, 6871 &phy_data); 6872 if (ret_val) 6873 return ret_val; 6874 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> 6875 IFE_PESC_POLARITY_REVERSED_SHIFT) ? 6876 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 6877 } 6878 return E1000_SUCCESS; 6879} 6880 6881/****************************************************************************** 6882 * Check if Downshift occured 6883 * 6884 * hw - Struct containing variables accessed by shared code 6885 * downshift - output parameter : 0 - No Downshift ocured. 6886 * 1 - Downshift ocured. 6887 * 6888 * returns: - E1000_ERR_XXX 6889 * E1000_SUCCESS 6890 * 6891 * For phy's older then IGP, this function reads the Downshift bit in the Phy 6892 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 6893 * Link Health register. In IGP this bit is latched high, so the driver must 6894 * read it immediately after link is established. 6895 *****************************************************************************/ 6896static int32_t 6897e1000_check_downshift(struct e1000_hw *hw) 6898{ 6899 int32_t ret_val; 6900 uint16_t phy_data; 6901 6902 DEBUGFUNC("e1000_check_downshift"); 6903 6904 if (hw->phy_type == e1000_phy_igp || 6905 hw->phy_type == e1000_phy_igp_3 || 6906 hw->phy_type == e1000_phy_igp_2) { 6907 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6908 &phy_data); 6909 if (ret_val) 6910 return ret_val; 6911 6912 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 6913 } else if ((hw->phy_type == e1000_phy_m88) || 6914 (hw->phy_type == e1000_phy_gg82563)) { 6915 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6916 &phy_data); 6917 if (ret_val) 6918 return ret_val; 6919 6920 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6921 M88E1000_PSSR_DOWNSHIFT_SHIFT; 6922 } else if (hw->phy_type == e1000_phy_ife) { 6923 /* e1000_phy_ife supports 10/100 speed only */ 6924 hw->speed_downgraded = FALSE; 6925 } 6926 6927 return E1000_SUCCESS; 6928} 6929 6930/***************************************************************************** 6931 * 6932 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 6933 * gigabit link is achieved to improve link quality. 6934 * 6935 * hw: Struct containing variables accessed by shared code 6936 * 6937 * returns: - E1000_ERR_PHY if fail to read/write the PHY 6938 * E1000_SUCCESS at any other case. 6939 * 6940 ****************************************************************************/ 6941 6942static int32_t 6943e1000_config_dsp_after_link_change(struct e1000_hw *hw, 6944 boolean_t link_up) 6945{ 6946 int32_t ret_val; 6947 uint16_t phy_data, phy_saved_data, speed, duplex, i; 6948 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6949 {IGP01E1000_PHY_AGC_PARAM_A, 6950 IGP01E1000_PHY_AGC_PARAM_B, 6951 IGP01E1000_PHY_AGC_PARAM_C, 6952 IGP01E1000_PHY_AGC_PARAM_D}; 6953 uint16_t min_length, max_length; 6954 6955 DEBUGFUNC("e1000_config_dsp_after_link_change"); 6956 6957 if (hw->phy_type != e1000_phy_igp) 6958 return E1000_SUCCESS; 6959 6960 if (link_up) { 6961 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 6962 if (ret_val) { 6963 DEBUGOUT("Error getting link speed and duplex\n"); 6964 return ret_val; 6965 } 6966 6967 if (speed == SPEED_1000) { 6968 6969 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 6970 if (ret_val) 6971 return ret_val; 6972 6973 if ((hw->dsp_config_state == e1000_dsp_config_enabled) && 6974 min_length >= e1000_igp_cable_length_50) { 6975 6976 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6977 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 6978 &phy_data); 6979 if (ret_val) 6980 return ret_val; 6981 6982 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 6983 6984 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 6985 phy_data); 6986 if (ret_val) 6987 return ret_val; 6988 } 6989 hw->dsp_config_state = e1000_dsp_config_activated; 6990 } 6991 6992 if ((hw->ffe_config_state == e1000_ffe_config_enabled) && 6993 (min_length < e1000_igp_cable_length_50)) { 6994 6995 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 6996 uint32_t idle_errs = 0; 6997 6998 /* clear previous idle error counts */ 6999 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7000 &phy_data); 7001 if (ret_val) 7002 return ret_val; 7003 7004 for (i = 0; i < ffe_idle_err_timeout; i++) { 7005 udelay(1000); 7006 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7007 &phy_data); 7008 if (ret_val) 7009 return ret_val; 7010 7011 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 7012 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 7013 hw->ffe_config_state = e1000_ffe_config_active; 7014 7015 ret_val = e1000_write_phy_reg(hw, 7016 IGP01E1000_PHY_DSP_FFE, 7017 IGP01E1000_PHY_DSP_FFE_CM_CP); 7018 if (ret_val) 7019 return ret_val; 7020 break; 7021 } 7022 7023 if (idle_errs) 7024 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; 7025 } 7026 } 7027 } 7028 } else { 7029 if (hw->dsp_config_state == e1000_dsp_config_activated) { 7030 /* Save off the current value of register 0x2F5B to be restored at 7031 * the end of the routines. */ 7032 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7033 7034 if (ret_val) 7035 return ret_val; 7036 7037 /* Disable the PHY transmitter */ 7038 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 7039 7040 if (ret_val) 7041 return ret_val; 7042 7043 mdelay(20); 7044 7045 ret_val = e1000_write_phy_reg(hw, 0x0000, 7046 IGP01E1000_IEEE_FORCE_GIGA); 7047 if (ret_val) 7048 return ret_val; 7049 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7050 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); 7051 if (ret_val) 7052 return ret_val; 7053 7054 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7055 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 7056 7057 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); 7058 if (ret_val) 7059 return ret_val; 7060 } 7061 7062 ret_val = e1000_write_phy_reg(hw, 0x0000, 7063 IGP01E1000_IEEE_RESTART_AUTONEG); 7064 if (ret_val) 7065 return ret_val; 7066 7067 mdelay(20); 7068 7069 /* Now enable the transmitter */ 7070 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7071 7072 if (ret_val) 7073 return ret_val; 7074 7075 hw->dsp_config_state = e1000_dsp_config_enabled; 7076 } 7077 7078 if (hw->ffe_config_state == e1000_ffe_config_active) { 7079 /* Save off the current value of register 0x2F5B to be restored at 7080 * the end of the routines. */ 7081 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7082 7083 if (ret_val) 7084 return ret_val; 7085 7086 /* Disable the PHY transmitter */ 7087 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 7088 7089 if (ret_val) 7090 return ret_val; 7091 7092 mdelay(20); 7093 7094 ret_val = e1000_write_phy_reg(hw, 0x0000, 7095 IGP01E1000_IEEE_FORCE_GIGA); 7096 if (ret_val) 7097 return ret_val; 7098 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 7099 IGP01E1000_PHY_DSP_FFE_DEFAULT); 7100 if (ret_val) 7101 return ret_val; 7102 7103 ret_val = e1000_write_phy_reg(hw, 0x0000, 7104 IGP01E1000_IEEE_RESTART_AUTONEG); 7105 if (ret_val) 7106 return ret_val; 7107 7108 mdelay(20); 7109 7110 /* Now enable the transmitter */ 7111 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7112 7113 if (ret_val) 7114 return ret_val; 7115 7116 hw->ffe_config_state = e1000_ffe_config_enabled; 7117 } 7118 } 7119 return E1000_SUCCESS; 7120} 7121 7122/***************************************************************************** 7123 * Set PHY to class A mode 7124 * Assumes the following operations will follow to enable the new class mode. 7125 * 1. Do a PHY soft reset 7126 * 2. Restart auto-negotiation or force link. 7127 * 7128 * hw - Struct containing variables accessed by shared code 7129 ****************************************************************************/ 7130static int32_t 7131e1000_set_phy_mode(struct e1000_hw *hw) 7132{ 7133 int32_t ret_val; 7134 uint16_t eeprom_data; 7135 7136 DEBUGFUNC("e1000_set_phy_mode"); 7137 7138 if ((hw->mac_type == e1000_82545_rev_3) && 7139 (hw->media_type == e1000_media_type_copper)) { 7140 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); 7141 if (ret_val) { 7142 return ret_val; 7143 } 7144 7145 if ((eeprom_data != EEPROM_RESERVED_WORD) && 7146 (eeprom_data & EEPROM_PHY_CLASS_A)) { 7147 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); 7148 if (ret_val) 7149 return ret_val; 7150 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); 7151 if (ret_val) 7152 return ret_val; 7153 7154 hw->phy_reset_disable = FALSE; 7155 } 7156 } 7157 7158 return E1000_SUCCESS; 7159} 7160 7161/***************************************************************************** 7162 * 7163 * This function sets the lplu state according to the active flag. When 7164 * activating lplu this function also disables smart speed and vise versa. 7165 * lplu will not be activated unless the device autonegotiation advertisment 7166 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 7167 * hw: Struct containing variables accessed by shared code 7168 * active - true to enable lplu false to disable lplu. 7169 * 7170 * returns: - E1000_ERR_PHY if fail to read/write the PHY 7171 * E1000_SUCCESS at any other case. 7172 * 7173 ****************************************************************************/ 7174 7175static int32_t 7176e1000_set_d3_lplu_state(struct e1000_hw *hw, 7177 boolean_t active) 7178{ 7179 uint32_t phy_ctrl = 0; 7180 int32_t ret_val; 7181 uint16_t phy_data; 7182 DEBUGFUNC("e1000_set_d3_lplu_state"); 7183 7184 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 7185 && hw->phy_type != e1000_phy_igp_3) 7186 return E1000_SUCCESS; 7187 7188 /* During driver activity LPLU should not be used or it will attain link 7189 * from the lowest speeds starting from 10Mbps. The capability is used for 7190 * Dx transitions and states */ 7191 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { 7192 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 7193 if (ret_val) 7194 return ret_val; 7195 } else if (hw->mac_type == e1000_ich8lan) { 7196 /* MAC writes into PHY register based on the state transition 7197 * and start auto-negotiation. SW driver can overwrite the settings 7198 * in CSR PHY power control E1000_PHY_CTRL register. */ 7199 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7200 } else { 7201 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7202 if (ret_val) 7203 return ret_val; 7204 } 7205 7206 if (!active) { 7207 if (hw->mac_type == e1000_82541_rev_2 || 7208 hw->mac_type == e1000_82547_rev_2) { 7209 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 7210 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7211 if (ret_val) 7212 return ret_val; 7213 } else { 7214 if (hw->mac_type == e1000_ich8lan) { 7215 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 7216 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7217 } else { 7218 phy_data &= ~IGP02E1000_PM_D3_LPLU; 7219 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7220 phy_data); 7221 if (ret_val) 7222 return ret_val; 7223 } 7224 } 7225 7226 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7227 * Dx states where the power conservation is most important. During 7228 * driver activity we should enable SmartSpeed, so performance is 7229 * maintained. */ 7230 if (hw->smart_speed == e1000_smart_speed_on) { 7231 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7232 &phy_data); 7233 if (ret_val) 7234 return ret_val; 7235 7236 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 7237 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7238 phy_data); 7239 if (ret_val) 7240 return ret_val; 7241 } else if (hw->smart_speed == e1000_smart_speed_off) { 7242 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7243 &phy_data); 7244 if (ret_val) 7245 return ret_val; 7246 7247 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7248 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7249 phy_data); 7250 if (ret_val) 7251 return ret_val; 7252 } 7253 7254 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || 7255 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 7256 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7257 7258 if (hw->mac_type == e1000_82541_rev_2 || 7259 hw->mac_type == e1000_82547_rev_2) { 7260 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7261 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7262 if (ret_val) 7263 return ret_val; 7264 } else { 7265 if (hw->mac_type == e1000_ich8lan) { 7266 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 7267 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7268 } else { 7269 phy_data |= IGP02E1000_PM_D3_LPLU; 7270 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7271 phy_data); 7272 if (ret_val) 7273 return ret_val; 7274 } 7275 } 7276 7277 /* When LPLU is enabled we should disable SmartSpeed */ 7278 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7279 if (ret_val) 7280 return ret_val; 7281 7282 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7283 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 7284 if (ret_val) 7285 return ret_val; 7286 7287 } 7288 return E1000_SUCCESS; 7289} 7290 7291/***************************************************************************** 7292 * 7293 * This function sets the lplu d0 state according to the active flag. When 7294 * activating lplu this function also disables smart speed and vise versa. 7295 * lplu will not be activated unless the device autonegotiation advertisment 7296 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 7297 * hw: Struct containing variables accessed by shared code 7298 * active - true to enable lplu false to disable lplu. 7299 * 7300 * returns: - E1000_ERR_PHY if fail to read/write the PHY 7301 * E1000_SUCCESS at any other case. 7302 * 7303 ****************************************************************************/ 7304 7305static int32_t 7306e1000_set_d0_lplu_state(struct e1000_hw *hw, 7307 boolean_t active) 7308{ 7309 uint32_t phy_ctrl = 0; 7310 int32_t ret_val; 7311 uint16_t phy_data; 7312 DEBUGFUNC("e1000_set_d0_lplu_state"); 7313 7314 if (hw->mac_type <= e1000_82547_rev_2) 7315 return E1000_SUCCESS; 7316 7317 if (hw->mac_type == e1000_ich8lan) { 7318 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7319 } else { 7320 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7321 if (ret_val) 7322 return ret_val; 7323 } 7324 7325 if (!active) { 7326 if (hw->mac_type == e1000_ich8lan) { 7327 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 7328 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7329 } else { 7330 phy_data &= ~IGP02E1000_PM_D0_LPLU; 7331 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7332 if (ret_val) 7333 return ret_val; 7334 } 7335 7336 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7337 * Dx states where the power conservation is most important. During 7338 * driver activity we should enable SmartSpeed, so performance is 7339 * maintained. */ 7340 if (hw->smart_speed == e1000_smart_speed_on) { 7341 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7342 &phy_data); 7343 if (ret_val) 7344 return ret_val; 7345 7346 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 7347 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7348 phy_data); 7349 if (ret_val) 7350 return ret_val; 7351 } else if (hw->smart_speed == e1000_smart_speed_off) { 7352 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7353 &phy_data); 7354 if (ret_val) 7355 return ret_val; 7356 7357 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7358 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7359 phy_data); 7360 if (ret_val) 7361 return ret_val; 7362 } 7363 7364 7365 } else { 7366 7367 if (hw->mac_type == e1000_ich8lan) { 7368 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 7369 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7370 } else { 7371 phy_data |= IGP02E1000_PM_D0_LPLU; 7372 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7373 if (ret_val) 7374 return ret_val; 7375 } 7376 7377 /* When LPLU is enabled we should disable SmartSpeed */ 7378 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7379 if (ret_val) 7380 return ret_val; 7381 7382 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7383 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 7384 if (ret_val) 7385 return ret_val; 7386 7387 } 7388 return E1000_SUCCESS; 7389} 7390 7391/****************************************************************************** 7392 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 7393 * 7394 * hw - Struct containing variables accessed by shared code 7395 *****************************************************************************/ 7396static int32_t 7397e1000_set_vco_speed(struct e1000_hw *hw) 7398{ 7399 int32_t ret_val; 7400 uint16_t default_page = 0; 7401 uint16_t phy_data; 7402 7403 DEBUGFUNC("e1000_set_vco_speed"); 7404 7405 switch (hw->mac_type) { 7406 case e1000_82545_rev_3: 7407 case e1000_82546_rev_3: 7408 break; 7409 default: 7410 return E1000_SUCCESS; 7411 } 7412 7413 /* Set PHY register 30, page 5, bit 8 to 0 */ 7414 7415 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 7416 if (ret_val) 7417 return ret_val; 7418 7419 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 7420 if (ret_val) 7421 return ret_val; 7422 7423 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 7424 if (ret_val) 7425 return ret_val; 7426 7427 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 7428 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 7429 if (ret_val) 7430 return ret_val; 7431 7432 /* Set PHY register 30, page 4, bit 11 to 1 */ 7433 7434 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 7435 if (ret_val) 7436 return ret_val; 7437 7438 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 7439 if (ret_val) 7440 return ret_val; 7441 7442 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 7443 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 7444 if (ret_val) 7445 return ret_val; 7446 7447 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 7448 if (ret_val) 7449 return ret_val; 7450 7451 return E1000_SUCCESS; 7452} 7453 7454 7455/***************************************************************************** 7456 * This function reads the cookie from ARC ram. 7457 * 7458 * returns: - E1000_SUCCESS . 7459 ****************************************************************************/ 7460static int32_t 7461e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) 7462{ 7463 uint8_t i; 7464 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 7465 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 7466 7467 length = (length >> 2); 7468 offset = (offset >> 2); 7469 7470 for (i = 0; i < length; i++) { 7471 *((uint32_t *) buffer + i) = 7472 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 7473 } 7474 return E1000_SUCCESS; 7475} 7476 7477 7478/***************************************************************************** 7479 * This function checks whether the HOST IF is enabled for command operaton 7480 * and also checks whether the previous command is completed. 7481 * It busy waits in case of previous command is not completed. 7482 * 7483 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 7484 * timeout 7485 * - E1000_SUCCESS for success. 7486 ****************************************************************************/ 7487static int32_t 7488e1000_mng_enable_host_if(struct e1000_hw * hw) 7489{ 7490 uint32_t hicr; 7491 uint8_t i; 7492 7493 /* Check that the host interface is enabled. */ 7494 hicr = E1000_READ_REG(hw, HICR); 7495 if ((hicr & E1000_HICR_EN) == 0) { 7496 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 7497 return -E1000_ERR_HOST_INTERFACE_COMMAND; 7498 } 7499 /* check the previous command is completed */ 7500 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 7501 hicr = E1000_READ_REG(hw, HICR); 7502 if (!(hicr & E1000_HICR_C)) 7503 break; 7504 mdelay(1); 7505 } 7506 7507 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 7508 DEBUGOUT("Previous command timeout failed .\n"); 7509 return -E1000_ERR_HOST_INTERFACE_COMMAND; 7510 } 7511 return E1000_SUCCESS; 7512} 7513 7514/***************************************************************************** 7515 * This function writes the buffer content at the offset given on the host if. 7516 * It also does alignment considerations to do the writes in most efficient way. 7517 * Also fills up the sum of the buffer in *buffer parameter. 7518 * 7519 * returns - E1000_SUCCESS for success. 7520 ****************************************************************************/ 7521static int32_t 7522e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, 7523 uint16_t length, uint16_t offset, uint8_t *sum) 7524{ 7525 uint8_t *tmp; 7526 uint8_t *bufptr = buffer; 7527 uint32_t data = 0; 7528 uint16_t remaining, i, j, prev_bytes; 7529 7530 /* sum = only sum of the data and it is not checksum */ 7531 7532 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { 7533 return -E1000_ERR_PARAM; 7534 } 7535 7536 tmp = (uint8_t *)&data; 7537 prev_bytes = offset & 0x3; 7538 offset &= 0xFFFC; 7539 offset >>= 2; 7540 7541 if (prev_bytes) { 7542 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); 7543 for (j = prev_bytes; j < sizeof(uint32_t); j++) { 7544 *(tmp + j) = *bufptr++; 7545 *sum += *(tmp + j); 7546 } 7547 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); 7548 length -= j - prev_bytes; 7549 offset++; 7550 } 7551 7552 remaining = length & 0x3; 7553 length -= remaining; 7554 7555 /* Calculate length in DWORDs */ 7556 length >>= 2; 7557 7558 /* The device driver writes the relevant command block into the 7559 * ram area. */ 7560 for (i = 0; i < length; i++) { 7561 for (j = 0; j < sizeof(uint32_t); j++) { 7562 *(tmp + j) = *bufptr++; 7563 *sum += *(tmp + j); 7564 } 7565 7566 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); 7567 } 7568 if (remaining) { 7569 for (j = 0; j < sizeof(uint32_t); j++) { 7570 if (j < remaining) 7571 *(tmp + j) = *bufptr++; 7572 else 7573 *(tmp + j) = 0; 7574 7575 *sum += *(tmp + j); 7576 } 7577 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); 7578 } 7579 7580 return E1000_SUCCESS; 7581} 7582 7583 7584/***************************************************************************** 7585 * This function writes the command header after does the checksum calculation. 7586 * 7587 * returns - E1000_SUCCESS for success. 7588 ****************************************************************************/ 7589static int32_t 7590e1000_mng_write_cmd_header(struct e1000_hw * hw, 7591 struct e1000_host_mng_command_header * hdr) 7592{ 7593 uint16_t i; 7594 uint8_t sum; 7595 uint8_t *buffer; 7596 7597 /* Write the whole command header structure which includes sum of 7598 * the buffer */ 7599 7600 uint16_t length = sizeof(struct e1000_host_mng_command_header); 7601 7602 sum = hdr->checksum; 7603 hdr->checksum = 0; 7604 7605 buffer = (uint8_t *) hdr; 7606 i = length; 7607 while (i--) 7608 sum += buffer[i]; 7609 7610 hdr->checksum = 0 - sum; 7611 7612 length >>= 2; 7613 /* The device driver writes the relevant command block into the ram area. */ 7614 for (i = 0; i < length; i++) { 7615 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); 7616 E1000_WRITE_FLUSH(hw); 7617 } 7618 7619 return E1000_SUCCESS; 7620} 7621 7622 7623/***************************************************************************** 7624 * This function indicates to ARC that a new command is pending which completes 7625 * one write operation by the driver. 7626 * 7627 * returns - E1000_SUCCESS for success. 7628 ****************************************************************************/ 7629static int32_t 7630e1000_mng_write_commit(struct e1000_hw * hw) 7631{ 7632 uint32_t hicr; 7633 7634 hicr = E1000_READ_REG(hw, HICR); 7635 /* Setting this bit tells the ARC that a new command is pending. */ 7636 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); 7637 7638 return E1000_SUCCESS; 7639} 7640 7641 7642/***************************************************************************** 7643 * This function checks the mode of the firmware. 7644 * 7645 * returns - TRUE when the mode is IAMT or FALSE. 7646 ****************************************************************************/ 7647boolean_t 7648e1000_check_mng_mode(struct e1000_hw *hw) 7649{ 7650 uint32_t fwsm; 7651 7652 fwsm = E1000_READ_REG(hw, FWSM); 7653 7654 if (hw->mac_type == e1000_ich8lan) { 7655 if ((fwsm & E1000_FWSM_MODE_MASK) == 7656 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7657 return TRUE; 7658 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 7659 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7660 return TRUE; 7661 7662 return FALSE; 7663} 7664 7665 7666/***************************************************************************** 7667 * This function writes the dhcp info . 7668 ****************************************************************************/ 7669int32_t 7670e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, 7671 uint16_t length) 7672{ 7673 int32_t ret_val; 7674 struct e1000_host_mng_command_header hdr; 7675 7676 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; 7677 hdr.command_length = length; 7678 hdr.reserved1 = 0; 7679 hdr.reserved2 = 0; 7680 hdr.checksum = 0; 7681 7682 ret_val = e1000_mng_enable_host_if(hw); 7683 if (ret_val == E1000_SUCCESS) { 7684 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), 7685 &(hdr.checksum)); 7686 if (ret_val == E1000_SUCCESS) { 7687 ret_val = e1000_mng_write_cmd_header(hw, &hdr); 7688 if (ret_val == E1000_SUCCESS) 7689 ret_val = e1000_mng_write_commit(hw); 7690 } 7691 } 7692 return ret_val; 7693} 7694 7695 7696/***************************************************************************** 7697 * This function calculates the checksum. 7698 * 7699 * returns - checksum of buffer contents. 7700 ****************************************************************************/ 7701static uint8_t 7702e1000_calculate_mng_checksum(char *buffer, uint32_t length) 7703{ 7704 uint8_t sum = 0; 7705 uint32_t i; 7706 7707 if (!buffer) 7708 return 0; 7709 7710 for (i=0; i < length; i++) 7711 sum += buffer[i]; 7712 7713 return (uint8_t) (0 - sum); 7714} 7715 7716/***************************************************************************** 7717 * This function checks whether tx pkt filtering needs to be enabled or not. 7718 * 7719 * returns - TRUE for packet filtering or FALSE. 7720 ****************************************************************************/ 7721boolean_t 7722e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) 7723{ 7724 /* called in init as well as watchdog timer functions */ 7725 7726 int32_t ret_val, checksum; 7727 boolean_t tx_filter = FALSE; 7728 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 7729 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); 7730 7731 if (e1000_check_mng_mode(hw)) { 7732 ret_val = e1000_mng_enable_host_if(hw); 7733 if (ret_val == E1000_SUCCESS) { 7734 ret_val = e1000_host_if_read_cookie(hw, buffer); 7735 if (ret_val == E1000_SUCCESS) { 7736 checksum = hdr->checksum; 7737 hdr->checksum = 0; 7738 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 7739 checksum == e1000_calculate_mng_checksum((char *)buffer, 7740 E1000_MNG_DHCP_COOKIE_LENGTH)) { 7741 if (hdr->status & 7742 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 7743 tx_filter = TRUE; 7744 } else 7745 tx_filter = TRUE; 7746 } else 7747 tx_filter = TRUE; 7748 } 7749 } 7750 7751 hw->tx_pkt_filtering = tx_filter; 7752 return tx_filter; 7753} 7754 7755/****************************************************************************** 7756 * Verifies the hardware needs to allow ARPs to be processed by the host 7757 * 7758 * hw - Struct containing variables accessed by shared code 7759 * 7760 * returns: - TRUE/FALSE 7761 * 7762 *****************************************************************************/ 7763uint32_t 7764e1000_enable_mng_pass_thru(struct e1000_hw *hw) 7765{ 7766 uint32_t manc; 7767 uint32_t fwsm, factps; 7768 7769 if (hw->asf_firmware_present) { 7770 manc = E1000_READ_REG(hw, MANC); 7771 7772 if (!(manc & E1000_MANC_RCV_TCO_EN) || 7773 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 7774 return FALSE; 7775 if (e1000_arc_subsystem_valid(hw) == TRUE) { 7776 fwsm = E1000_READ_REG(hw, FWSM); 7777 factps = E1000_READ_REG(hw, FACTPS); 7778 7779 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == 7780 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) 7781 return TRUE; 7782 } else 7783 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) 7784 return TRUE; 7785 } 7786 return FALSE; 7787} 7788 7789static int32_t 7790e1000_polarity_reversal_workaround(struct e1000_hw *hw) 7791{ 7792 int32_t ret_val; 7793 uint16_t mii_status_reg; 7794 uint16_t i; 7795 7796 7797 /* Disable the transmitter on the PHY */ 7798 7799 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7800 if (ret_val) 7801 return ret_val; 7802 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 7803 if (ret_val) 7804 return ret_val; 7805 7806 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7807 if (ret_val) 7808 return ret_val; 7809 7810 /* This loop will early-out if the NO link condition has been met. */ 7811 for (i = PHY_FORCE_TIME; i > 0; i--) { 7812 /* Read the MII Status Register and wait for Link Status bit 7813 * to be clear. 7814 */ 7815 7816 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7817 if (ret_val) 7818 return ret_val; 7819 7820 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7821 if (ret_val) 7822 return ret_val; 7823 7824 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; 7825 mdelay(100); 7826 } 7827 7828 /* Recommended delay time after link has been lost */ 7829 mdelay(1000); 7830 7831 /* Now we will re-enable th transmitter on the PHY */ 7832 7833 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7834 if (ret_val) 7835 return ret_val; 7836 mdelay(50); 7837 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 7838 if (ret_val) 7839 return ret_val; 7840 mdelay(50); 7841 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 7842 if (ret_val) 7843 return ret_val; 7844 mdelay(50); 7845 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 7846 if (ret_val) 7847 return ret_val; 7848 7849 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7850 if (ret_val) 7851 return ret_val; 7852 7853 /* This loop will early-out if the link condition has been met. */ 7854 for (i = PHY_FORCE_TIME; i > 0; i--) { 7855 /* Read the MII Status Register and wait for Link Status bit 7856 * to be set. 7857 */ 7858 7859 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7860 if (ret_val) 7861 return ret_val; 7862 7863 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7864 if (ret_val) 7865 return ret_val; 7866 7867 if (mii_status_reg & MII_SR_LINK_STATUS) break; 7868 mdelay(100); 7869 } 7870 return E1000_SUCCESS; 7871} 7872 7873/*************************************************************************** 7874 * 7875 * Disables PCI-Express master access. 7876 * 7877 * hw: Struct containing variables accessed by shared code 7878 * 7879 * returns: - none. 7880 * 7881 ***************************************************************************/ 7882static void 7883e1000_set_pci_express_master_disable(struct e1000_hw *hw) 7884{ 7885 uint32_t ctrl; 7886 7887 DEBUGFUNC("e1000_set_pci_express_master_disable"); 7888 7889 if (hw->bus_type != e1000_bus_type_pci_express) 7890 return; 7891 7892 ctrl = E1000_READ_REG(hw, CTRL); 7893 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 7894 E1000_WRITE_REG(hw, CTRL, ctrl); 7895} 7896 7897/******************************************************************************* 7898 * 7899 * Disables PCI-Express master access and verifies there are no pending requests 7900 * 7901 * hw: Struct containing variables accessed by shared code 7902 * 7903 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 7904 * caused the master requests to be disabled. 7905 * E1000_SUCCESS master requests disabled. 7906 * 7907 ******************************************************************************/ 7908int32_t 7909e1000_disable_pciex_master(struct e1000_hw *hw) 7910{ 7911 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 7912 7913 DEBUGFUNC("e1000_disable_pciex_master"); 7914 7915 if (hw->bus_type != e1000_bus_type_pci_express) 7916 return E1000_SUCCESS; 7917 7918 e1000_set_pci_express_master_disable(hw); 7919 7920 while (timeout) { 7921 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 7922 break; 7923 else 7924 udelay(100); 7925 timeout--; 7926 } 7927 7928 if (!timeout) { 7929 DEBUGOUT("Master requests are pending.\n"); 7930 return -E1000_ERR_MASTER_REQUESTS_PENDING; 7931 } 7932 7933 return E1000_SUCCESS; 7934} 7935 7936/******************************************************************************* 7937 * 7938 * Check for EEPROM Auto Read bit done. 7939 * 7940 * hw: Struct containing variables accessed by shared code 7941 * 7942 * returns: - E1000_ERR_RESET if fail to reset MAC 7943 * E1000_SUCCESS at any other case. 7944 * 7945 ******************************************************************************/ 7946static int32_t 7947e1000_get_auto_rd_done(struct e1000_hw *hw) 7948{ 7949 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 7950 7951 DEBUGFUNC("e1000_get_auto_rd_done"); 7952 7953 switch (hw->mac_type) { 7954 default: 7955 msleep(5); 7956 break; 7957 case e1000_82571: 7958 case e1000_82572: 7959 case e1000_82573: 7960 case e1000_80003es2lan: 7961 case e1000_ich8lan: 7962 while (timeout) { 7963 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 7964 break; 7965 else msleep(1); 7966 timeout--; 7967 } 7968 7969 if (!timeout) { 7970 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); 7971 return -E1000_ERR_RESET; 7972 } 7973 break; 7974 } 7975 7976 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. 7977 * Need to wait for PHY configuration completion before accessing NVM 7978 * and PHY. */ 7979 if (hw->mac_type == e1000_82573) 7980 msleep(25); 7981 7982 return E1000_SUCCESS; 7983} 7984 7985/*************************************************************************** 7986 * Checks if the PHY configuration is done 7987 * 7988 * hw: Struct containing variables accessed by shared code 7989 * 7990 * returns: - E1000_ERR_RESET if fail to reset MAC 7991 * E1000_SUCCESS at any other case. 7992 * 7993 ***************************************************************************/ 7994static int32_t 7995e1000_get_phy_cfg_done(struct e1000_hw *hw) 7996{ 7997 int32_t timeout = PHY_CFG_TIMEOUT; 7998 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 7999 8000 DEBUGFUNC("e1000_get_phy_cfg_done"); 8001 8002 switch (hw->mac_type) { 8003 default: 8004 mdelay(10); 8005 break; 8006 case e1000_80003es2lan: 8007 /* Separate *_CFG_DONE_* bit for each port */ 8008 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 8009 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 8010 /* Fall Through */ 8011 case e1000_82571: 8012 case e1000_82572: 8013 while (timeout) { 8014 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 8015 break; 8016 else 8017 msleep(1); 8018 timeout--; 8019 } 8020 if (!timeout) { 8021 DEBUGOUT("MNG configuration cycle has not completed.\n"); 8022 return -E1000_ERR_RESET; 8023 } 8024 break; 8025 } 8026 8027 return E1000_SUCCESS; 8028} 8029 8030/*************************************************************************** 8031 * 8032 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 8033 * adapter or Eeprom access. 8034 * 8035 * hw: Struct containing variables accessed by shared code 8036 * 8037 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 8038 * E1000_SUCCESS at any other case. 8039 * 8040 ***************************************************************************/ 8041static int32_t 8042e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 8043{ 8044 int32_t timeout; 8045 uint32_t swsm; 8046 8047 DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); 8048 8049 if (!hw->eeprom_semaphore_present) 8050 return E1000_SUCCESS; 8051 8052 if (hw->mac_type == e1000_80003es2lan) { 8053 /* Get the SW semaphore. */ 8054 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 8055 return -E1000_ERR_EEPROM; 8056 } 8057 8058 /* Get the FW semaphore. */ 8059 timeout = hw->eeprom.word_size + 1; 8060 while (timeout) { 8061 swsm = E1000_READ_REG(hw, SWSM); 8062 swsm |= E1000_SWSM_SWESMBI; 8063 E1000_WRITE_REG(hw, SWSM, swsm); 8064 /* if we managed to set the bit we got the semaphore. */ 8065 swsm = E1000_READ_REG(hw, SWSM); 8066 if (swsm & E1000_SWSM_SWESMBI) 8067 break; 8068 8069 udelay(50); 8070 timeout--; 8071 } 8072 8073 if (!timeout) { 8074 /* Release semaphores */ 8075 e1000_put_hw_eeprom_semaphore(hw); 8076 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); 8077 return -E1000_ERR_EEPROM; 8078 } 8079 8080 return E1000_SUCCESS; 8081} 8082 8083/*************************************************************************** 8084 * This function clears HW semaphore bits. 8085 * 8086 * hw: Struct containing variables accessed by shared code 8087 * 8088 * returns: - None. 8089 * 8090 ***************************************************************************/ 8091static void 8092e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 8093{ 8094 uint32_t swsm; 8095 8096 DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); 8097 8098 if (!hw->eeprom_semaphore_present) 8099 return; 8100 8101 swsm = E1000_READ_REG(hw, SWSM); 8102 if (hw->mac_type == e1000_80003es2lan) { 8103 /* Release both semaphores. */ 8104 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 8105 } else 8106 swsm &= ~(E1000_SWSM_SWESMBI); 8107 E1000_WRITE_REG(hw, SWSM, swsm); 8108} 8109 8110/*************************************************************************** 8111 * 8112 * Obtaining software semaphore bit (SMBI) before resetting PHY. 8113 * 8114 * hw: Struct containing variables accessed by shared code 8115 * 8116 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 8117 * E1000_SUCCESS at any other case. 8118 * 8119 ***************************************************************************/ 8120static int32_t 8121e1000_get_software_semaphore(struct e1000_hw *hw) 8122{ 8123 int32_t timeout = hw->eeprom.word_size + 1; 8124 uint32_t swsm; 8125 8126 DEBUGFUNC("e1000_get_software_semaphore"); 8127 8128 if (hw->mac_type != e1000_80003es2lan) { 8129 return E1000_SUCCESS; 8130 } 8131 8132 while (timeout) { 8133 swsm = E1000_READ_REG(hw, SWSM); 8134 /* If SMBI bit cleared, it is now set and we hold the semaphore */ 8135 if (!(swsm & E1000_SWSM_SMBI)) 8136 break; 8137 mdelay(1); 8138 timeout--; 8139 } 8140 8141 if (!timeout) { 8142 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 8143 return -E1000_ERR_RESET; 8144 } 8145 8146 return E1000_SUCCESS; 8147} 8148 8149/*************************************************************************** 8150 * 8151 * Release semaphore bit (SMBI). 8152 * 8153 * hw: Struct containing variables accessed by shared code 8154 * 8155 ***************************************************************************/ 8156static void 8157e1000_release_software_semaphore(struct e1000_hw *hw) 8158{ 8159 uint32_t swsm; 8160 8161 DEBUGFUNC("e1000_release_software_semaphore"); 8162 8163 if (hw->mac_type != e1000_80003es2lan) { 8164 return; 8165 } 8166 8167 swsm = E1000_READ_REG(hw, SWSM); 8168 /* Release the SW semaphores.*/ 8169 swsm &= ~E1000_SWSM_SMBI; 8170 E1000_WRITE_REG(hw, SWSM, swsm); 8171} 8172 8173/****************************************************************************** 8174 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 8175 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 8176 * the caller to figure out how to deal with it. 8177 * 8178 * hw - Struct containing variables accessed by shared code 8179 * 8180 * returns: - E1000_BLK_PHY_RESET 8181 * E1000_SUCCESS 8182 * 8183 *****************************************************************************/ 8184int32_t 8185e1000_check_phy_reset_block(struct e1000_hw *hw) 8186{ 8187 uint32_t manc = 0; 8188 uint32_t fwsm = 0; 8189 8190 if (hw->mac_type == e1000_ich8lan) { 8191 fwsm = E1000_READ_REG(hw, FWSM); 8192 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 8193 : E1000_BLK_PHY_RESET; 8194 } 8195 8196 if (hw->mac_type > e1000_82547_rev_2) 8197 manc = E1000_READ_REG(hw, MANC); 8198 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 8199 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8200} 8201 8202static uint8_t 8203e1000_arc_subsystem_valid(struct e1000_hw *hw) 8204{ 8205 uint32_t fwsm; 8206 8207 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC 8208 * may not be provided a DMA clock when no manageability features are 8209 * enabled. We do not want to perform any reads/writes to these registers 8210 * if this is the case. We read FWSM to determine the manageability mode. 8211 */ 8212 switch (hw->mac_type) { 8213 case e1000_82571: 8214 case e1000_82572: 8215 case e1000_82573: 8216 case e1000_80003es2lan: 8217 fwsm = E1000_READ_REG(hw, FWSM); 8218 if ((fwsm & E1000_FWSM_MODE_MASK) != 0) 8219 return TRUE; 8220 break; 8221 case e1000_ich8lan: 8222 return TRUE; 8223 default: 8224 break; 8225 } 8226 return FALSE; 8227} 8228 8229 8230/****************************************************************************** 8231 * Configure PCI-Ex no-snoop 8232 * 8233 * hw - Struct containing variables accessed by shared code. 8234 * no_snoop - Bitmap of no-snoop events. 8235 * 8236 * returns: E1000_SUCCESS 8237 * 8238 *****************************************************************************/ 8239static int32_t 8240e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) 8241{ 8242 uint32_t gcr_reg = 0; 8243 8244 DEBUGFUNC("e1000_set_pci_ex_no_snoop"); 8245 8246 if (hw->bus_type == e1000_bus_type_unknown) 8247 e1000_get_bus_info(hw); 8248 8249 if (hw->bus_type != e1000_bus_type_pci_express) 8250 return E1000_SUCCESS; 8251 8252 if (no_snoop) { 8253 gcr_reg = E1000_READ_REG(hw, GCR); 8254 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 8255 gcr_reg |= no_snoop; 8256 E1000_WRITE_REG(hw, GCR, gcr_reg); 8257 } 8258 if (hw->mac_type == e1000_ich8lan) { 8259 uint32_t ctrl_ext; 8260 8261 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); 8262 8263 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 8264 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 8265 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 8266 } 8267 8268 return E1000_SUCCESS; 8269} 8270 8271/*************************************************************************** 8272 * 8273 * Get software semaphore FLAG bit (SWFLAG). 8274 * SWFLAG is used to synchronize the access to all shared resource between 8275 * SW, FW and HW. 8276 * 8277 * hw: Struct containing variables accessed by shared code 8278 * 8279 ***************************************************************************/ 8280static int32_t 8281e1000_get_software_flag(struct e1000_hw *hw) 8282{ 8283 int32_t timeout = PHY_CFG_TIMEOUT; 8284 uint32_t extcnf_ctrl; 8285 8286 DEBUGFUNC("e1000_get_software_flag"); 8287 8288 if (hw->mac_type == e1000_ich8lan) { 8289 while (timeout) { 8290 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8291 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 8292 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8293 8294 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8295 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 8296 break; 8297 mdelay(1); 8298 timeout--; 8299 } 8300 8301 if (!timeout) { 8302 DEBUGOUT("FW or HW locks the resource too long.\n"); 8303 return -E1000_ERR_CONFIG; 8304 } 8305 } 8306 8307 return E1000_SUCCESS; 8308} 8309 8310/*************************************************************************** 8311 * 8312 * Release software semaphore FLAG bit (SWFLAG). 8313 * SWFLAG is used to synchronize the access to all shared resource between 8314 * SW, FW and HW. 8315 * 8316 * hw: Struct containing variables accessed by shared code 8317 * 8318 ***************************************************************************/ 8319static void 8320e1000_release_software_flag(struct e1000_hw *hw) 8321{ 8322 uint32_t extcnf_ctrl; 8323 8324 DEBUGFUNC("e1000_release_software_flag"); 8325 8326 if (hw->mac_type == e1000_ich8lan) { 8327 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); 8328 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 8329 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8330 } 8331 8332 return; 8333} 8334 8335/****************************************************************************** 8336 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 8337 * register. 8338 * 8339 * hw - Struct containing variables accessed by shared code 8340 * offset - offset of word in the EEPROM to read 8341 * data - word read from the EEPROM 8342 * words - number of words to read 8343 *****************************************************************************/ 8344static int32_t 8345e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, 8346 uint16_t *data) 8347{ 8348 int32_t error = E1000_SUCCESS; 8349 uint32_t flash_bank = 0; 8350 uint32_t act_offset = 0; 8351 uint32_t bank_offset = 0; 8352 uint16_t word = 0; 8353 uint16_t i = 0; 8354 8355 /* We need to know which is the valid flash bank. In the event 8356 * that we didn't allocate eeprom_shadow_ram, we may not be 8357 * managing flash_bank. So it cannot be trusted and needs 8358 * to be updated with each read. 8359 */ 8360 /* Value of bit 22 corresponds to the flash bank we're on. */ 8361 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; 8362 8363 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ 8364 bank_offset = flash_bank * (hw->flash_bank_size * 2); 8365 8366 error = e1000_get_software_flag(hw); 8367 if (error != E1000_SUCCESS) 8368 return error; 8369 8370 for (i = 0; i < words; i++) { 8371 if (hw->eeprom_shadow_ram != NULL && 8372 hw->eeprom_shadow_ram[offset+i].modified == TRUE) { 8373 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 8374 } else { 8375 /* The NVM part needs a byte offset, hence * 2 */ 8376 act_offset = bank_offset + ((offset + i) * 2); 8377 error = e1000_read_ich8_word(hw, act_offset, &word); 8378 if (error != E1000_SUCCESS) 8379 break; 8380 data[i] = word; 8381 } 8382 } 8383 8384 e1000_release_software_flag(hw); 8385 8386 return error; 8387} 8388 8389/****************************************************************************** 8390 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 8391 * register. Actually, writes are written to the shadow ram cache in the hw 8392 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to 8393 * the NVM, which occurs when the NVM checksum is updated. 8394 * 8395 * hw - Struct containing variables accessed by shared code 8396 * offset - offset of word in the EEPROM to write 8397 * words - number of words to write 8398 * data - words to write to the EEPROM 8399 *****************************************************************************/ 8400static int32_t 8401e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, 8402 uint16_t *data) 8403{ 8404 uint32_t i = 0; 8405 int32_t error = E1000_SUCCESS; 8406 8407 error = e1000_get_software_flag(hw); 8408 if (error != E1000_SUCCESS) 8409 return error; 8410 8411 /* A driver can write to the NVM only if it has eeprom_shadow_ram 8412 * allocated. Subsequent reads to the modified words are read from 8413 * this cached structure as well. Writes will only go into this 8414 * cached structure unless it's followed by a call to 8415 * e1000_update_eeprom_checksum() where it will commit the changes 8416 * and clear the "modified" field. 8417 */ 8418 if (hw->eeprom_shadow_ram != NULL) { 8419 for (i = 0; i < words; i++) { 8420 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 8421 hw->eeprom_shadow_ram[offset+i].modified = TRUE; 8422 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; 8423 } else { 8424 error = -E1000_ERR_EEPROM; 8425 break; 8426 } 8427 } 8428 } else { 8429 /* Drivers have the option to not allocate eeprom_shadow_ram as long 8430 * as they don't perform any NVM writes. An attempt in doing so 8431 * will result in this error. 8432 */ 8433 error = -E1000_ERR_EEPROM; 8434 } 8435 8436 e1000_release_software_flag(hw); 8437 8438 return error; 8439} 8440 8441/****************************************************************************** 8442 * This function does initial flash setup so that a new read/write/erase cycle 8443 * can be started. 8444 * 8445 * hw - The pointer to the hw structure 8446 ****************************************************************************/ 8447static int32_t 8448e1000_ich8_cycle_init(struct e1000_hw *hw) 8449{ 8450 union ich8_hws_flash_status hsfsts; 8451 int32_t error = E1000_ERR_EEPROM; 8452 int32_t i = 0; 8453 8454 DEBUGFUNC("e1000_ich8_cycle_init"); 8455 8456 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8457 8458 /* May be check the Flash Des Valid bit in Hw status */ 8459 if (hsfsts.hsf_status.fldesvalid == 0) { 8460 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); 8461 return error; 8462 } 8463 8464 /* Clear FCERR in Hw status by writing 1 */ 8465 /* Clear DAEL in Hw status by writing a 1 */ 8466 hsfsts.hsf_status.flcerr = 1; 8467 hsfsts.hsf_status.dael = 1; 8468 8469 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 8470 8471 /* Either we should have a hardware SPI cycle in progress bit to check 8472 * against, in order to start a new cycle or FDONE bit should be changed 8473 * in the hardware so that it is 1 after harware reset, which can then be 8474 * used as an indication whether a cycle is in progress or has been 8475 * completed .. we should also have some software semaphore mechanism to 8476 * guard FDONE or the cycle in progress bit so that two threads access to 8477 * those bits can be sequentiallized or a way so that 2 threads dont 8478 * start the cycle at the same time */ 8479 8480 if (hsfsts.hsf_status.flcinprog == 0) { 8481 /* There is no cycle running at present, so we can start a cycle */ 8482 /* Begin by setting Flash Cycle Done. */ 8483 hsfsts.hsf_status.flcdone = 1; 8484 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 8485 error = E1000_SUCCESS; 8486 } else { 8487 /* otherwise poll for sometime so the current cycle has a chance 8488 * to end before giving up. */ 8489 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 8490 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8491 if (hsfsts.hsf_status.flcinprog == 0) { 8492 error = E1000_SUCCESS; 8493 break; 8494 } 8495 udelay(1); 8496 } 8497 if (error == E1000_SUCCESS) { 8498 /* Successful in waiting for previous cycle to timeout, 8499 * now set the Flash Cycle Done. */ 8500 hsfsts.hsf_status.flcdone = 1; 8501 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 8502 } else { 8503 DEBUGOUT("Flash controller busy, cannot get access"); 8504 } 8505 } 8506 return error; 8507} 8508 8509/****************************************************************************** 8510 * This function starts a flash cycle and waits for its completion 8511 * 8512 * hw - The pointer to the hw structure 8513 ****************************************************************************/ 8514static int32_t 8515e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) 8516{ 8517 union ich8_hws_flash_ctrl hsflctl; 8518 union ich8_hws_flash_status hsfsts; 8519 int32_t error = E1000_ERR_EEPROM; 8520 uint32_t i = 0; 8521 8522 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 8523 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 8524 hsflctl.hsf_ctrl.flcgo = 1; 8525 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 8526 8527 /* wait till FDONE bit is set to 1 */ 8528 do { 8529 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8530 if (hsfsts.hsf_status.flcdone == 1) 8531 break; 8532 udelay(1); 8533 i++; 8534 } while (i < timeout); 8535 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 8536 error = E1000_SUCCESS; 8537 } 8538 return error; 8539} 8540 8541/****************************************************************************** 8542 * Reads a byte or word from the NVM using the ICH8 flash access registers. 8543 * 8544 * hw - The pointer to the hw structure 8545 * index - The index of the byte or word to read. 8546 * size - Size of data to read, 1=byte 2=word 8547 * data - Pointer to the word to store the value read. 8548 *****************************************************************************/ 8549static int32_t 8550e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, 8551 uint32_t size, uint16_t* data) 8552{ 8553 union ich8_hws_flash_status hsfsts; 8554 union ich8_hws_flash_ctrl hsflctl; 8555 uint32_t flash_linear_address; 8556 uint32_t flash_data = 0; 8557 int32_t error = -E1000_ERR_EEPROM; 8558 int32_t count = 0; 8559 8560 DEBUGFUNC("e1000_read_ich8_data"); 8561 8562 if (size < 1 || size > 2 || data == 0x0 || 8563 index > ICH_FLASH_LINEAR_ADDR_MASK) 8564 return error; 8565 8566 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 8567 hw->flash_base_addr; 8568 8569 do { 8570 udelay(1); 8571 /* Steps */ 8572 error = e1000_ich8_cycle_init(hw); 8573 if (error != E1000_SUCCESS) 8574 break; 8575 8576 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 8577 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 8578 hsflctl.hsf_ctrl.fldbcount = size - 1; 8579 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 8580 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 8581 8582 /* Write the last 24 bits of index into Flash Linear address field in 8583 * Flash Address */ 8584 /* TODO: TBD maybe check the index against the size of flash */ 8585 8586 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); 8587 8588 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 8589 8590 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole 8591 * sequence a few more times, else read in (shift in) the Flash Data0, 8592 * the order is least significant byte first msb to lsb */ 8593 if (error == E1000_SUCCESS) { 8594 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); 8595 if (size == 1) { 8596 *data = (uint8_t)(flash_data & 0x000000FF); 8597 } else if (size == 2) { 8598 *data = (uint16_t)(flash_data & 0x0000FFFF); 8599 } 8600 break; 8601 } else { 8602 /* If we've gotten here, then things are probably completely hosed, 8603 * but if the error condition is detected, it won't hurt to give 8604 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 8605 */ 8606 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8607 if (hsfsts.hsf_status.flcerr == 1) { 8608 /* Repeat for some time before giving up. */ 8609 continue; 8610 } else if (hsfsts.hsf_status.flcdone == 0) { 8611 DEBUGOUT("Timeout error - flash cycle did not complete."); 8612 break; 8613 } 8614 } 8615 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 8616 8617 return error; 8618} 8619 8620/****************************************************************************** 8621 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 8622 * 8623 * hw - The pointer to the hw structure 8624 * index - The index of the byte/word to read. 8625 * size - Size of data to read, 1=byte 2=word 8626 * data - The byte(s) to write to the NVM. 8627 *****************************************************************************/ 8628static int32_t 8629e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, 8630 uint16_t data) 8631{ 8632 union ich8_hws_flash_status hsfsts; 8633 union ich8_hws_flash_ctrl hsflctl; 8634 uint32_t flash_linear_address; 8635 uint32_t flash_data = 0; 8636 int32_t error = -E1000_ERR_EEPROM; 8637 int32_t count = 0; 8638 8639 DEBUGFUNC("e1000_write_ich8_data"); 8640 8641 if (size < 1 || size > 2 || data > size * 0xff || 8642 index > ICH_FLASH_LINEAR_ADDR_MASK) 8643 return error; 8644 8645 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 8646 hw->flash_base_addr; 8647 8648 do { 8649 udelay(1); 8650 /* Steps */ 8651 error = e1000_ich8_cycle_init(hw); 8652 if (error != E1000_SUCCESS) 8653 break; 8654 8655 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 8656 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 8657 hsflctl.hsf_ctrl.fldbcount = size -1; 8658 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 8659 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 8660 8661 /* Write the last 24 bits of index into Flash Linear address field in 8662 * Flash Address */ 8663 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); 8664 8665 if (size == 1) 8666 flash_data = (uint32_t)data & 0x00FF; 8667 else 8668 flash_data = (uint32_t)data; 8669 8670 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 8671 8672 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole 8673 * sequence a few more times else done */ 8674 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 8675 if (error == E1000_SUCCESS) { 8676 break; 8677 } else { 8678 /* If we're here, then things are most likely completely hosed, 8679 * but if the error condition is detected, it won't hurt to give 8680 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 8681 */ 8682 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8683 if (hsfsts.hsf_status.flcerr == 1) { 8684 /* Repeat for some time before giving up. */ 8685 continue; 8686 } else if (hsfsts.hsf_status.flcdone == 0) { 8687 DEBUGOUT("Timeout error - flash cycle did not complete."); 8688 break; 8689 } 8690 } 8691 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 8692 8693 return error; 8694} 8695 8696/****************************************************************************** 8697 * Reads a single byte from the NVM using the ICH8 flash access registers. 8698 * 8699 * hw - pointer to e1000_hw structure 8700 * index - The index of the byte to read. 8701 * data - Pointer to a byte to store the value read. 8702 *****************************************************************************/ 8703static int32_t 8704e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) 8705{ 8706 int32_t status = E1000_SUCCESS; 8707 uint16_t word = 0; 8708 8709 status = e1000_read_ich8_data(hw, index, 1, &word); 8710 if (status == E1000_SUCCESS) { 8711 *data = (uint8_t)word; 8712 } 8713 8714 return status; 8715} 8716 8717/****************************************************************************** 8718 * Writes a single byte to the NVM using the ICH8 flash access registers. 8719 * Performs verification by reading back the value and then going through 8720 * a retry algorithm before giving up. 8721 * 8722 * hw - pointer to e1000_hw structure 8723 * index - The index of the byte to write. 8724 * byte - The byte to write to the NVM. 8725 *****************************************************************************/ 8726static int32_t 8727e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) 8728{ 8729 int32_t error = E1000_SUCCESS; 8730 int32_t program_retries = 0; 8731 8732 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 8733 8734 error = e1000_write_ich8_byte(hw, index, byte); 8735 8736 if (error != E1000_SUCCESS) { 8737 for (program_retries = 0; program_retries < 100; program_retries++) { 8738 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); 8739 error = e1000_write_ich8_byte(hw, index, byte); 8740 udelay(100); 8741 if (error == E1000_SUCCESS) 8742 break; 8743 } 8744 } 8745 8746 if (program_retries == 100) 8747 error = E1000_ERR_EEPROM; 8748 8749 return error; 8750} 8751 8752/****************************************************************************** 8753 * Writes a single byte to the NVM using the ICH8 flash access registers. 8754 * 8755 * hw - pointer to e1000_hw structure 8756 * index - The index of the byte to read. 8757 * data - The byte to write to the NVM. 8758 *****************************************************************************/ 8759static int32_t 8760e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) 8761{ 8762 int32_t status = E1000_SUCCESS; 8763 uint16_t word = (uint16_t)data; 8764 8765 status = e1000_write_ich8_data(hw, index, 1, word); 8766 8767 return status; 8768} 8769 8770/****************************************************************************** 8771 * Reads a word from the NVM using the ICH8 flash access registers. 8772 * 8773 * hw - pointer to e1000_hw structure 8774 * index - The starting byte index of the word to read. 8775 * data - Pointer to a word to store the value read. 8776 *****************************************************************************/ 8777static int32_t 8778e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) 8779{ 8780 int32_t status = E1000_SUCCESS; 8781 status = e1000_read_ich8_data(hw, index, 2, data); 8782 return status; 8783} 8784 8785/****************************************************************************** 8786 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 8787 * based. 8788 * 8789 * hw - pointer to e1000_hw structure 8790 * bank - 0 for first bank, 1 for second bank 8791 * 8792 * Note that this function may actually erase as much as 8 or 64 KBytes. The 8793 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 8794 * bank size may be 4, 8 or 64 KBytes 8795 *****************************************************************************/ 8796int32_t 8797e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) 8798{ 8799 union ich8_hws_flash_status hsfsts; 8800 union ich8_hws_flash_ctrl hsflctl; 8801 uint32_t flash_linear_address; 8802 int32_t count = 0; 8803 int32_t error = E1000_ERR_EEPROM; 8804 int32_t iteration; 8805 int32_t sub_sector_size = 0; 8806 int32_t bank_size; 8807 int32_t j = 0; 8808 int32_t error_flag = 0; 8809 8810 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8811 8812 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ 8813 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 8814 * consecutive sectors. The start index for the nth Hw sector can be 8815 * calculated as bank * 4096 + n * 256 8816 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 8817 * The start index for the nth Hw sector can be calculated 8818 * as bank * 4096 8819 * 10: The HW sector is 8K bytes 8820 * 11: The Hw sector size is 64K bytes */ 8821 if (hsfsts.hsf_status.berasesz == 0x0) { 8822 /* Hw sector size 256 */ 8823 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 8824 bank_size = ICH_FLASH_SECTOR_SIZE; 8825 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 8826 } else if (hsfsts.hsf_status.berasesz == 0x1) { 8827 bank_size = ICH_FLASH_SEG_SIZE_4K; 8828 iteration = 1; 8829 } else if (hsfsts.hsf_status.berasesz == 0x3) { 8830 bank_size = ICH_FLASH_SEG_SIZE_64K; 8831 iteration = 1; 8832 } else { 8833 return error; 8834 } 8835 8836 for (j = 0; j < iteration ; j++) { 8837 do { 8838 count++; 8839 /* Steps */ 8840 error = e1000_ich8_cycle_init(hw); 8841 if (error != E1000_SUCCESS) { 8842 error_flag = 1; 8843 break; 8844 } 8845 8846 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash 8847 * Control */ 8848 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 8849 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 8850 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 8851 8852 /* Write the last 24 bits of an index within the block into Flash 8853 * Linear address field in Flash Address. This probably needs to 8854 * be calculated here based off the on-chip erase sector size and 8855 * the software bank size (4, 8 or 64 KBytes) */ 8856 flash_linear_address = bank * bank_size + j * sub_sector_size; 8857 flash_linear_address += hw->flash_base_addr; 8858 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 8859 8860 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); 8861 8862 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 8863 /* Check if FCERR is set to 1. If 1, clear it and try the whole 8864 * sequence a few more times else Done */ 8865 if (error == E1000_SUCCESS) { 8866 break; 8867 } else { 8868 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8869 if (hsfsts.hsf_status.flcerr == 1) { 8870 /* repeat for some time before giving up */ 8871 continue; 8872 } else if (hsfsts.hsf_status.flcdone == 0) { 8873 error_flag = 1; 8874 break; 8875 } 8876 } 8877 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 8878 if (error_flag == 1) 8879 break; 8880 } 8881 if (error_flag != 1) 8882 error = E1000_SUCCESS; 8883 return error; 8884} 8885 8886static int32_t 8887e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, 8888 uint32_t cnf_base_addr, uint32_t cnf_size) 8889{ 8890 uint32_t ret_val = E1000_SUCCESS; 8891 uint16_t word_addr, reg_data, reg_addr; 8892 uint16_t i; 8893 8894 /* cnf_base_addr is in DWORD */ 8895 word_addr = (uint16_t)(cnf_base_addr << 1); 8896 8897 /* cnf_size is returned in size of dwords */ 8898 for (i = 0; i < cnf_size; i++) { 8899 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); 8900 if (ret_val) 8901 return ret_val; 8902 8903 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); 8904 if (ret_val) 8905 return ret_val; 8906 8907 ret_val = e1000_get_software_flag(hw); 8908 if (ret_val != E1000_SUCCESS) 8909 return ret_val; 8910 8911 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); 8912 8913 e1000_release_software_flag(hw); 8914 } 8915 8916 return ret_val; 8917} 8918 8919 8920/****************************************************************************** 8921 * This function initializes the PHY from the NVM on ICH8 platforms. This 8922 * is needed due to an issue where the NVM configuration is not properly 8923 * autoloaded after power transitions. Therefore, after each PHY reset, we 8924 * will load the configuration data out of the NVM manually. 8925 * 8926 * hw: Struct containing variables accessed by shared code 8927 *****************************************************************************/ 8928static int32_t 8929e1000_init_lcd_from_nvm(struct e1000_hw *hw) 8930{ 8931 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; 8932 8933 if (hw->phy_type != e1000_phy_igp_3) 8934 return E1000_SUCCESS; 8935 8936 /* Check if SW needs configure the PHY */ 8937 reg_data = E1000_READ_REG(hw, FEXTNVM); 8938 if (!(reg_data & FEXTNVM_SW_CONFIG)) 8939 return E1000_SUCCESS; 8940 8941 /* Wait for basic configuration completes before proceeding*/ 8942 loop = 0; 8943 do { 8944 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 8945 udelay(100); 8946 loop++; 8947 } while ((!reg_data) && (loop < 50)); 8948 8949 /* Clear the Init Done bit for the next init event */ 8950 reg_data = E1000_READ_REG(hw, STATUS); 8951 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 8952 E1000_WRITE_REG(hw, STATUS, reg_data); 8953 8954 /* Make sure HW does not configure LCD from PHY extended configuration 8955 before SW configuration */ 8956 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 8957 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 8958 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 8959 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 8960 cnf_size >>= 16; 8961 if (cnf_size) { 8962 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 8963 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 8964 /* cnf_base_addr is in DWORD */ 8965 cnf_base_addr >>= 16; 8966 8967 /* Configure LCD from extended configuration region. */ 8968 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, 8969 cnf_size); 8970 if (ret_val) 8971 return ret_val; 8972 } 8973 } 8974 8975 return E1000_SUCCESS; 8976} 8977