1/* 2 * drivers/net/big_sur_ge.h - Driver for PMC-Sierra Big Sur 3 * ethernet ports 4 * 5 * Copyright (C) 2003 PMC-Sierra Inc. 6 * Author : Manish Lachwani (lachwani@pmc-sierra.com) 7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 2 12 * of the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 * 23 */ 24 25#ifndef __BIG_SUR_GE_H__ 26#define __BIG_SUR_GE_H__ 27 28#include <linux/version.h> 29#include <linux/module.h> 30#include <linux/kernel.h> 31#include <linux/spinlock.h> 32#include <linux/types.h> 33 34#define BIG_SUR_DEVICE_NAME "big sur" 35#define BIG_SUR_DEVICE_DESC "Big Sur Ethernet 10/100 MAC" 36 37#define BIG_SUR_GE_BASE 0xbb000000 38 39#define BIG_SUR_GE_WRITE(ofs,data) *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) = data 40 41#define BIG_SUR_GE_READ(ofs) *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) 42 43/* Manish : Need to fix these defines later */ 44#define BIG_SUR_GE_EMAC_0_HIGHADDR 45#define BIG_SUR_GE_EMAC_0_BASEADDR 46#define BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID 1 47#define BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID 2 48#define BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID 3 49#define BIG_SUR_GE_EMAC_0_ERR_COUNT_EXIST 50#define BIG_SUR_GE_EMAC_0_DMA_PRESENT 51#define BIG_SUR_GE_EMAC_0_MII_EXIST 52#define BIG_SUR_GE_OPB_ETHERNET_0_BASEADDR 53#define BIG_SUR_GE_EMAC_0_DEVICE_ID 54#define BIG_SUR_GE_OPB_ETHERNET_0_ERR_COUNT_EXIST 55#define BIG_SUR_GE_OPB_ETHERNET_0_DMA_PRESENT 56#define BIG_SUR_GE_OPB_ETHERNET_0_MII_EXIST 57#define BIG_SUR_GE_OPB_ETHERNET_0_DEVICE_ID 58 59#define BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT 4UL 60/* IPIF specific defines */ 61#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */ 62#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */ 63#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */ 64#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */ 65#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */ 66#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ 67#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */ 68#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ 69#define XIIF_V123B_RESET_MASK 0xAUL 70#define XIIF_V123B_ERROR_MASK 0x1UL 71 72/* defines */ 73#define BIG_SUR_GE_UNICAST_OPTION 0x00000001 74#define BIG_SUR_GE_BROADCAST_OPTION 0x00000002 75#define BIG_SUR_GE_PROMISC_OPTION 0x00000004 76#define BIG_SUR_GE_FDUPLEX_OPTION 0x00000008 77#define BIG_SUR_GE_POLLED_OPTION 0x00000010 78#define BIG_SUR_GE_LOOPBACK_OPTION 0x00000020 79#define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080 80#define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100 81#define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200 82#define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400 83#define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800 84#define BIG_SUR_GE_STRIP_PAD_FCS_OPTION 0x00002000 85 86/* Not Supported */ 87#define BIG_SUR_GE_MULTICAST_OPTION 0x00000040 88#define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080 89#define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100 90#define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200 91#define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400 92#define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800 93#define BIG_SUR_GE_STRIP_PAD_OPTION 0x00001000 94#define BIG_SUR_GE_STRIP_FCS_OPTION 0x00002000 95 96 97/* Defaults for Interrupt Coalescing in the SG DMA Engine */ 98#define BIG_SUR_GE_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */ 99#define BIG_SUR_GE_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */ 100#define BIG_SUR_GE_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */ 101#define BIG_SUR_GE_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */ 102 103/* Direction */ 104#define BIG_SUR_GE_SEND 1 105#define BIG_SUR_GE_RECV 2 106 107/* SG DMA */ 108#define BIG_SUR_GE_SGDMA_NODELAY 0 /* start SG DMA immediately */ 109#define BIG_SUR_GE_SGDMA_DELAY 1 /* do not start SG DMA */ 110 111#define BIG_SUR_GE_CFG_NO_IPIF 0 /* Not supported by the driver */ 112#define BIG_SUR_GE_CFG_NO_DMA 1 /* No DMA */ 113#define BIG_SUR_GE_CFG_SIMPLE_DMA 2 /* Simple DMA */ 114#define BIG_SUR_GE_CFG_DMA_SG 3 /* DMA scatter gather */ 115 116#define BIG_SUR_GE_MAC_ADDR_SIZE 6 /* six-byte MAC address */ 117#define BIG_SUR_GE_MTU 1500 /* max size of Ethernet frame */ 118#define BIG_SUR_GE_HDR_SIZE 14 /* size of Ethernet header */ 119#define BIG_SUR_GE_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ 120#define BIG_SUR_GE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ 121#define BIG_SUR_GE_MAX_FRAME_SIZE \ 122 (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_SIZE + BIG_SUR_GE_TRL_SIZE) 123 124#define BIG_SUR_GE_MAX_VLAN_FRAME_SIZE \ 125 (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_VLAN_SIZE + BIG_SUR_GE_TRL_SIZE) 126 127/* Send and Receive buffers */ 128#define BIG_SUR_GE_MIN_RECV_BUFS 32 /* minimum # of recv buffers */ 129#define BIG_SUR_GE_DFT_RECV_BUFS 64 /* default # of recv buffers */ 130 131#define BIG_SUR_GE_MIN_SEND_BUFS 16 /* minimum # of send buffers */ 132#define BIG_SUR_GE_DFT_SEND_BUFS 32 /* default # of send buffers */ 133 134#define BIG_SUR_GE_MIN_BUFFERS (BIG_SUR_GE_MIN_RECV_BUFS + BIG_SUR_GE_MIN_SEND_BUFS) 135#define BIG_SUR_GE_DFT_BUFFERS (BIG_SUR_GE_DFT_RECV_BUFS + BIG_SUR_GE_DFT_SEND_BUFS) 136 137/* Send and Receive Descriptors */ 138#define BIG_SUR_GE_MIN_RECV_DESC 16 /* minimum # of recv descriptors */ 139#define BIG_SUR_GE_DFT_RECV_DESC 32 /* default # of recv descriptors */ 140 141#define BIG_SUR_GE_MIN_SEND_DESC 8 /* minimum # of send descriptors */ 142#define BIG_SUR_GE_DFT_SEND_DESC 16 /* default # of send descriptors */ 143 144/* FIFO Specific Defines */ 145#define BIG_SUR_GE_READ_FIFO_TYPE 0 /* a read FIFO */ 146#define BIG_SUR_GE_WRITE_FIFO_TYPE 1 /* a write FIFO */ 147#define BIG_SUR_GE_RESET_REG_OFFSET 0UL 148#define BIG_SUR_GE_MODULE_INFO_REG_OFFSET 0UL 149#define BIG_SUR_GE_COUNT_STATUS_REG_OFFSET 4UL 150#define BIG_SUR_GE_RESET_FIFO_MASK 0x0000000A 151#define BIG_SUR_GE_COUNT_MASK 0x0000FFFF 152#define BIG_SUR_GE_DEADLOCK_MASK 0x20000000 153#define BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK 0x40000000 154#define BIG_SUR_GE_EMPTY_FULL_MASK 0x80000000 155 156#define BIG_SUR_GE_FIFO_RESET(fifo) \ 157 BIG_SUR_GE_WRITE((fifo)->reg_base_addr + BIG_SUR_GE_RESET_REG_OFFSET, BIG_SUR_GE_RESET_FIFO_MASK) 158 159#define BIG_SUR_GE_GET_COUNT(fifo) \ 160 (BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 161 BIG_SUR_GE_COUNT_MASK) 162 163#define BIG_SUR_GE_IS_ALMOST_EMPTY(fifo) \ 164 (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 165 BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK) 166 167#define BIG_SUR_GE_IS_ALMOST_FULL(fifo) \ 168 (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 169 BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK) 170 171#define BIG_SUR_GE_IS_EMPTY(fifo) \ 172 (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 173 BIG_SUR_GE_EMPTY_FULL_MASK) 174 175#define BIG_SUR_GE_IS_FULL(fifo) \ 176 (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 177 BIG_SUR_GE_EMPTY_FULL_MASK) 178 179#define BIG_SUR_GE_IS_DEADLOCKED(fifo) \ 180 (BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 181 BIG_SUR_GE_DEADLOCK_MASK) 182 183/* Device Config */ 184typedef struct _big_sur_ge_config { 185 u16 device_id; 186 u32 base_address; 187 u32 has_counters; 188 u32 has_sg_dma; 189 u8 dma_config; 190 u32 has_mii; 191} big_sur_ge_config; 192 193#define BIG_SUR_GE_SIZE_IN_WORDS 10 194typedef unsigned long xbuf_descriptor[BIG_SUR_GE_SIZE_IN_WORDS]; 195 196/* Callback Functions */ 197typedef void (*big_sur_sg_handler) (void *callback, xbuf_descriptor *desc, u32 num_desc); 198typedef void (*big_sur_fifo_handler) (void *callback); 199typedef void (*big_sur_irq_handler) (void *instance); 200 201typedef struct _xdma_channel_tag { 202 u32 reg_base_address; 203 u32 base_address; 204 u32 ready; 205 xbuf_descriptor *put_ptr; 206 xbuf_descriptor *get_ptr; 207 xbuf_descriptor *commit_ptr; 208 xbuf_descriptor *last_ptr; 209 210 u32 total_desc_count; 211 u32 active_desc_count; 212} xdma_channel; 213 214typedef struct _packet_fifo { 215 u32 reg_base_addr; 216 u32 ready_status; 217 u32 data_base_address; 218} packet_fifo; 219 220 221/* Big Sur GE driver structure */ 222typedef struct _big_sur_ge { 223 u32 base_address; 224 u32 started; 225 u32 ready; 226 u32 polled; 227 u32 dma_sg; 228 229 u8 dma_config; 230 u32 has_mii; 231 u32 has_mcast_hash_table; 232 233 /* For the FIFO and simple DMA case only */ 234 packet_fifo recv_fifo; 235 packet_fifo send_fifo; 236 237 big_sur_fifo_handler big_sur_ge_fifo_recv_handler; 238 big_sur_fifo_handler big_sur_ge_fifo_send_handler; 239 240 void *fifo_send_ref; 241 void *fifo_recv_ref; 242 243 /* For SG DMA only */ 244 xdma_channel recv_channel; 245 xdma_channel send_channel; 246} big_sur_ge; 247 248/* Offset of the MAC registers from the IPIF base address */ 249#define BIG_SUR_GE_REG_OFFSET 0x1100UL 250 251/* 252 * Register offsets for the Ethernet MAC. Each register is 32 bits. 253 */ 254#define BIG_SUR_GE_EMIR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x0) /* EMAC Module ID */ 255#define BIG_SUR_GE_ECR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x4) /* MAC Control */ 256#define BIG_SUR_GE_IFGP_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x8) /* Interframe Gap */ 257#define BIG_SUR_GE_SAH_OFFSET (BIG_SUR_GE_REG_OFFSET + 0xC) /* Station addr, high */ 258#define BIG_SUR_GE_SAL_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x10) /* Station addr, low */ 259#define BIG_SUR_GE_MGTCR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x14) /* MII mgmt control */ 260#define BIG_SUR_GE_MGTDR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x18) /* MII mgmt data */ 261#define BIG_SUR_GE_RPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x1C) /* Rx packet length */ 262#define BIG_SUR_GE_TPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x20) /* Tx packet length */ 263#define BIG_SUR_GE_TSR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x24) /* Tx status */ 264#define BIG_SUR_GE_RMFC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x28) /* Rx missed frames */ 265#define BIG_SUR_GE_RCC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x2C) /* Rx collisions */ 266#define BIG_SUR_GE_RFCSEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x30) /* Rx FCS errors */ 267#define BIG_SUR_GE_RAEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x34) /* Rx alignment errors */ 268#define BIG_SUR_GE_TEDC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x38) /* Transmit excess 269 * deferral cnt */ 270/* 271 * Register offsets for the IPIF components 272 */ 273#define BIG_SUR_GE_ISR_OFFSET 0x20UL /* Interrupt status */ 274 275#define BIG_SUR_GE_DMA_OFFSET 0x2300UL 276#define BIG_SUR_GE_DMA_SEND_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x0) /* DMA send channel */ 277#define BIG_SUR_GE_DMA_RECV_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x40) /* DMA recv channel */ 278 279#define BIG_SUR_GE_PFIFO_OFFSET 0x2000UL 280#define BIG_SUR_GE_PFIFO_TXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x0) /* Tx registers */ 281#define BIG_SUR_GE_PFIFO_RXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x10) /* Rx registers */ 282#define BIG_SUR_GE_PFIFO_TXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x100) /* Tx keyhole */ 283#define BIG_SUR_GE_PFIFO_RXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x200) /* Rx keyhole */ 284 285/* 286 * EMAC Module Identification Register (EMIR) 287 */ 288#define BIG_SUR_GE_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */ 289#define BIG_SUR_GE_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */ 290 291/* 292 * EMAC Control Register (ECR) 293 */ 294#define BIG_SUR_GE_ECR_FULL_DUPLEX_MASK 0x80000000 /* Full duplex mode */ 295#define BIG_SUR_GE_ECR_XMIT_RESET_MASK 0x40000000 /* Reset transmitter */ 296#define BIG_SUR_GE_ECR_XMIT_ENABLE_MASK 0x20000000 /* Enable transmitter */ 297#define BIG_SUR_GE_ECR_RECV_RESET_MASK 0x10000000 /* Reset receiver */ 298#define BIG_SUR_GE_ECR_RECV_ENABLE_MASK 0x08000000 /* Enable receiver */ 299#define BIG_SUR_GE_ECR_PHY_ENABLE_MASK 0x04000000 /* Enable PHY */ 300#define BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK 0x02000000 /* Enable xmit pad insert */ 301#define BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK 0x01000000 /* Enable xmit FCS insert */ 302#define BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK 0x00800000 /* Enable xmit source addr insertion */ 303#define BIG_SUR_GE_ECR_XMIT_ERROR_INSERT_MASK 0x00400000 /* Insert xmit error */ 304#define BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000 /* Enable xmit source addr overwrite */ 305#define BIG_SUR_GE_ECR_LOOPBACK_MASK 0x00100000 /* Enable internal loopback */ 306#define BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK 0x00080000 /* Enable recv pad strip */ 307#define BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK 0x00040000 /* Enable recv FCS strip */ 308#define BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK 0x00080000 /* Enable recv pad/fcs strip */ 309#define BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK 0x00020000 /* Enable unicast addr */ 310#define BIG_SUR_GE_ECR_MULTI_ENABLE_MASK 0x00010000 /* Enable multicast addr */ 311#define BIG_SUR_GE_ECR_BROAD_ENABLE_MASK 0x00008000 /* Enable broadcast addr */ 312#define BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK 0x00004000 /* Enable promiscuous mode */ 313#define BIG_SUR_GE_ECR_RECV_ALL_MASK 0x00002000 /* Receive all frames */ 314#define BIG_SUR_GE_ECR_RESERVED2_MASK 0x00001000 /* Reserved */ 315#define BIG_SUR_GE_ECR_MULTI_HASH_ENABLE_MASK 0x00000800 /* Enable multicast hash */ 316#define BIG_SUR_GE_ECR_PAUSE_FRAME_MASK 0x00000400 /* Interpret pause frames */ 317#define BIG_SUR_GE_ECR_CLEAR_HASH_MASK 0x00000200 /* Clear hash table */ 318#define BIG_SUR_GE_ECR_ADD_HASH_ADDR_MASK 0x00000100 /* Add hash table address */ 319 320/* 321 * Interframe Gap Register (IFGR) 322 */ 323#define BIG_SUR_GE_IFGP_PART1_MASK 0xF8000000 /* Interframe Gap Part1 */ 324#define BIG_SUR_GE_IFGP_PART1_SHIFT 27 325#define BIG_SUR_GE_IFGP_PART2_MASK 0x07C00000 /* Interframe Gap Part2 */ 326#define BIG_SUR_GE_IFGP_PART2_SHIFT 22 327 328/* 329 * Station Address High Register (SAH) 330 */ 331#define BIG_SUR_GE_SAH_ADDR_MASK 0x0000FFFF /* Station address high bytes */ 332 333/* 334 * Station Address Low Register (SAL) 335 */ 336#define BIG_SUR_GE_SAL_ADDR_MASK 0xFFFFFFFF /* Station address low bytes */ 337 338/* 339 * MII Management Control Register (MGTCR) 340 */ 341#define BIG_SUR_GE_MGTCR_START_MASK 0x80000000 /* Start/Busy */ 342#define BIG_SUR_GE_MGTCR_RW_NOT_MASK 0x40000000 /* Read/Write Not (direction) */ 343#define BIG_SUR_GE_MGTCR_PHY_ADDR_MASK 0x3E000000 /* PHY address */ 344#define BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */ 345#define BIG_SUR_GE_MGTCR_REG_ADDR_MASK 0x01F00000 /* Register address */ 346#define BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */ 347#define BIG_SUR_GE_MGTCR_MII_ENABLE_MASK 0x00080000 /* Enable MII from EMAC */ 348#define BIG_SUR_GE_MGTCR_RD_ERROR_MASK 0x00040000 /* MII mgmt read error */ 349 350/* 351 * MII Management Data Register (MGTDR) 352 */ 353#define BIG_SUR_GE_MGTDR_DATA_MASK 0x0000FFFF /* MII data */ 354 355/* 356 * Receive Packet Length Register (RPLR) 357 */ 358#define BIG_SUR_GE_RPLR_LENGTH_MASK 0x0000FFFF /* Receive packet length */ 359 360/* 361 * Transmit Packet Length Register (TPLR) 362 */ 363#define BIG_SUR_GE_TPLR_LENGTH_MASK 0x0000FFFF /* Transmit packet length */ 364 365/* 366 * Transmit Status Register (TSR) 367 */ 368#define BIG_SUR_GE_TSR_EXCESS_DEFERRAL_MASK 0x80000000 /* Transmit excess deferral */ 369#define BIG_SUR_GE_TSR_FIFO_UNDERRUN_MASK 0x40000000 /* Packet FIFO underrun */ 370#define BIG_SUR_GE_TSR_ATTEMPTS_MASK 0x3E000000 /* Transmission attempts */ 371#define BIG_SUR_GE_TSR_LATE_COLLISION_MASK 0x01000000 /* Transmit late collision */ 372 373/* 374 * Receive Missed Frame Count (RMFC) 375 */ 376#define BIG_SUR_GE_RMFC_DATA_MASK 0x0000FFFF 377 378/* 379 * Receive Collision Count (RCC) 380 */ 381#define BIG_SUR_GE_RCC_DATA_MASK 0x0000FFFF 382/* 383 * Receive FCS Error Count (RFCSEC) 384 */ 385#define BIG_SUR_GE_RFCSEC_DATA_MASK 0x0000FFFF 386 387/* 388 * Receive Alignment Error Count (RALN) 389 */ 390#define BIG_SUR_GE_RAEC_DATA_MASK 0x0000FFFF 391 392/* 393 * Transmit Excess Deferral Count (TEDC) 394 */ 395#define BIG_SUR_GE_TEDC_DATA_MASK 0x0000FFFF 396 397/* 398 * EMAC Interrupt Registers (Status and Enable) masks. These registers are 399 * part of the IPIF IP Interrupt registers 400 */ 401#define BIG_SUR_GE_EIR_XMIT_DONE_MASK 0x00000001 /* Xmit complete */ 402#define BIG_SUR_GE_EIR_RECV_DONE_MASK 0x00000002 /* Recv complete */ 403#define BIG_SUR_GE_EIR_XMIT_ERROR_MASK 0x00000004 /* Xmit error */ 404#define BIG_SUR_GE_EIR_RECV_ERROR_MASK 0x00000008 /* Recv error */ 405#define BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010 /* Xmit status fifo empty */ 406#define BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020 /* Recv length fifo empty */ 407#define BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK 0x00000040 /* Xmit length fifo full */ 408#define BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK 0x00000080 /* Recv length fifo overrun */ 409#define BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK 0x00000100 /* Recv length fifo underrun */ 410#define BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK 0x00000200 /* Xmit status fifo overrun */ 411#define BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400 /* Transmit status fifo underrun */ 412#define BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK 0x00000800 /* Transmit length fifo overrun */ 413#define BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000 /* Transmit length fifo underrun */ 414#define BIG_SUR_GE_EIR_XMIT_PAUSE_MASK 0x00002000 /* Transmit pause pkt received */ 415#define BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK 0x00004000 /* Receive data fifo overrun */ 416#define BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK 0x00008000 /* Receive missed frame error */ 417#define BIG_SUR_GE_EIR_RECV_COLLISION_MASK 0x00010000 /* Receive collision error */ 418#define BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK 0x00020000 /* Receive FCS error */ 419#define BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK 0x00040000 /* Receive length field error */ 420#define BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK 0x00080000 /* Receive short frame error */ 421#define BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK 0x00100000 /* Receive long frame error */ 422#define BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK 0x00200000 /* Receive alignment error */ 423 424#define BIG_SUR_GE_READ_REG(base_addr, reg_offset) \ 425 BIG_SUR_GE_READ(base_addr + reg_offset) 426 427#define BIG_SUR_GE_WRITE_REG(base_addr, reg_offset, data) \ 428 BIG_SUR_GE_WRITE(base_addr + reg_offset, data) 429 430#define BIG_SUR_GE_CONTROL_REG(base_addr, mask) \ 431 BIG_SUR_GE_WRITE(base_addr + BIG_SUR_GE_ECR_OFFSET, mask) 432 433/* Set the MAC Address */ 434#define big_sur_ge_set_mac(base_addr, address) \ 435{ \ 436 u32 mac_addr; \ 437 \ 438 mac_addr = ((address[0] << 8) | (address[1]); \ 439 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAH_OFFSET, mac_address); \ 440 \ 441 mac_addr = ((address[2] << 24) | (address[3] << 16) | \ 442 (address[4] << 8) | address[5]); \ 443 \ 444 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAL_OFFSET, mac_address); \ 445 \ 446} 447 448/* Enable the MAC unit */ 449#define big_sur_ge_mac_enable(base_address) \ 450{ \ 451 u32 control; \ 452 control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \ 453 control &= ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | BIG_SUR_GE_ECR_RECV_RESET_MASK); \ 454 control |= (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \ 455 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ 456} 457 458/* Disable the MAC unit */ 459#define big_sur_ge_mac_disable(base_address) \ 460{ \ 461 u32 control; \ 462 control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \ 463 control &= ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \ 464 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ 465} 466 467/* Check if the Tx is done */ 468#define big_sur_ge_tx_done(base_address) \ 469 (BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_XMIT_DONE_MASK) 470 471 472/* Check if Rx FIFO is empty */ 473#define big_sur_ge_rx_empty(base_address) \ 474 (!(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_RECV_DONE_MASK)) 475 476/* Reset the MAC PHY */ 477#define big_sur_ge_reset_phy(base_address) \ 478{ \ 479 u32 control; \ 480 control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \ 481 control &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK); \ 482 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ 483 control |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK; \ 484 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ 485} 486 487/* DMA SG defines */ 488#define BIG_SUR_GE_CONTROL_LAST_BD_MASK 0x02000000 489#define BIG_SUR_GE_STATUS_LAST_BD_MASK 0x10000000 490#define BIG_SUR_GE_RST_REG_OFFSET 0 /* reset register */ 491#define BIG_SUR_GE_MI_REG_OFFSET 0 /* module information register */ 492#define BIG_SUR_GE_DMAC_REG_OFFSET 4 /* DMA control register */ 493#define BIG_SUR_GE_SA_REG_OFFSET 8 /* source address register */ 494#define BIG_SUR_GE_DA_REG_OFFSET 12 /* destination address register */ 495#define BIG_SUR_GE_LEN_REG_OFFSET 16 /* length register */ 496#define BIG_SUR_GE_DMAS_REG_OFFSET 20 /* DMA status register */ 497#define BIG_SUR_GE_BDA_REG_OFFSET 24 /* buffer descriptor address register */ 498#define BIG_SUR_GE_SWCR_REG_OFFSET 28 /* software control register */ 499#define BIG_SUR_GE_UPC_REG_OFFSET 32 /* unserviced packet count register */ 500#define BIG_SUR_GE_PCT_REG_OFFSET 36 /* packet count threshold register */ 501#define BIG_SUR_GE_PWB_REG_OFFSET 40 /* packet wait bound register */ 502#define BIG_SUR_GE_IS_REG_OFFSET 44 /* interrupt status register */ 503#define BIG_SUR_GE_IE_REG_OFFSET 48 /* interrupt enable register */ 504 505#define BIG_SUR_GE_RESET_MASK 0x0000000A 506 507/* Buffer Descriptor Control */ 508 509#define BIG_SUR_GE_DEVICE_STATUS_OFFSET 0 510#define BIG_SUR_GE_CONTROL_OFFSET 1 511#define BIG_SUR_GE_SOURCE_OFFSET 2 512#define BIG_SUR_GE_DESTINATION_OFFSET 3 513#define BIG_SUR_GE_LENGTH_OFFSET 4 514#define BIG_SUR_GE_STATUS_OFFSET 5 515#define BIG_SUR_GE_NEXT_PTR_OFFSET 6 516#define BIG_SUR_GE_ID_OFFSET 7 517#define BIG_SUR_GE_FLAGS_OFFSET 8 518#define BIG_SUR_GE_RQSTED_LENGTH_OFFSET 9 519 520#define BIG_SUR_GE_FLAGS_LOCKED_MASK 1 521 522#define xbuf_descriptor_init(base) \ 523{ \ 524 (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = 0); \ 525 (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = 0); \ 526 (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = 0); \ 527 (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = 0); \ 528 (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = 0); \ 529 (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = 0); \ 530 (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = 0); \ 531 (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = 0); \ 532 (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = 0); \ 533 (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = 0); \ 534} 535 536#define xbuf_descriptor_GetControl(base) \ 537 (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET)) 538 539#define xbuf_descriptor_SetControl(base, Control) \ 540 (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = (u32)Control) 541 542#define xbuf_descriptor_IsLastControl(base) \ 543 (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) & \ 544 BIG_SUR_GE_CONTROL_LAST_BD_MASK) 545 546#define xbuf_descriptor_SetLast(base) \ 547 (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) |= BIG_SUR_GECONTROL_LAST_BD_MASK) 548 549#define xbuf_descriptor_GetSrcAddress(base) \ 550 ((u32 *)(*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET))) 551 552#define xbuf_descriptor_SetSrcAddress(base, Source) \ 553 (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = (u32)Source) 554 555#define xbuf_descriptor_GetDestAddress(base) \ 556 ((u32 *)(*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET))) 557 558#define xbuf_descriptor_SetDestAddress(base, Destination) \ 559 (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = (u32)Destination) 560 561#define xbuf_descriptor_GetLength(base) \ 562 (u32)(*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) - \ 563 *((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET)) 564 565#define xbuf_descriptor_SetLength(base, Length) \ 566{ \ 567 (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = (u32)(Length)); \ 568 (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = (u32)(Length));\ 569} 570 571#define xbuf_descriptor_GetStatus(base) \ 572 (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET)) 573 574#define xbuf_descriptor_SetStatus(base, Status) \ 575 (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = (u32)Status) 576 577#define xbuf_descriptor_IsLastStatus(base) \ 578 (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) & \ 579 BIG_SUR_GE_STATUS_LAST_BD_MASK) 580 581#define xbuf_descriptor_GetDeviceStatus(base) \ 582 ((u32)(*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET))) 583 584#define xbuf_descriptor_SetDeviceStatus(base, Status) \ 585 (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = (u32)Status) 586 587#define xbuf_descriptor_GetNextPtr(base) \ 588 (xbuf_descriptor *)(*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET)) 589 590#define xbuf_descriptor_SetNextPtr(base, NextPtr) \ 591 (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = (u32)NextPtr) 592 593#define xbuf_descriptor_GetId(base) \ 594 (u32)(*((u32 *)base + BIG_SUR_GE_ID_OFFSET)) 595 596#define xbuf_descriptor_SetId(base, Id) \ 597 (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = (u32)Id) 598 599#define xbuf_descriptor_GetFlags(base) \ 600 (u32)(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET)) 601 602#define xbuf_descriptor_SetFlags(base, Flags) \ 603 (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = (u32)Flags) 604 605#define xbuf_descriptor_Lock(base) \ 606 (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) |= BIG_SUR_GE_FLAGS_LOCKED_MASK) 607 608#define xbuf_descriptor_Unlock(base) \ 609 (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) &= ~BIG_SUR_GE_FLAGS_LOCKED_MASK) 610 611#define xbuf_descriptor_IsLocked(base) \ 612 (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) & BIG_SUR_GE_FLAGS_LOCKED_MASK) 613 614#define BIG_SUR_GE_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */ 615#define BIG_SUR_GE_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */ 616#define BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */ 617#define BIG_SUR_GE_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */ 618#define BIG_SUR_GE_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */ 619#define BIG_SUR_GE_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */ 620#define BIG_SUR_GE_DMACR_LAST_BD_MASK BIG_SUR_GE_CONTROL_LAST_BD_MASK /* last buffer */ 621#define BIG_SUR_GE_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */ 622#define BIG_SUR_GE_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */ 623#define BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */ 624#define BIG_SUR_GE_DMASR_LAST_BD_MASK BIG_SUR_GE_STATUS_LAST_BD_MASK /* last buffer */ 625#define BIG_SUR_GE_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */ 626#define BIG_SUR_GE_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */ 627#define BIG_SUR_GE_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */ 628#define BIG_SUR_GE_IXR_PKT_DONE_MASK 0x4UL /* packet done */ 629#define BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */ 630#define BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */ 631#define BIG_SUR_GE_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable 632 acknowledge occurred */ 633#define BIG_SUR_GEIXR_SG_END_MASK 0x40UL /* last buffer descriptor 634 disabled scatter gather */ 635#define BIG_SUR_GEIXR_BD_MASK 0x80UL /* buffer descriptor done */ 636 637/* BD control */ 638#define BIG_SUR_GE_DFT_SEND_BD_MASK (BIG_SUR_GEDMACR_SOURCE_INCR_MASK | \ 639 BIG_SUR_GEDMACR_DEST_LOCAL_MASK) 640#define BIG_SUR_GE_DFT_RECV_BD_MASK (BIG_SUR_GEDMACR_DEST_INCR_MASK | \ 641 BIG_SUR_GEDMACR_SOURCE_LOCAL_MASK) 642 643/* Interrupts */ 644#define BIG_SUR_GE_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */ 645#define BIG_SUR_GE_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */ 646#define BIG_SUR_GE_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */ 647#define BIG_SUR_GE_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */ 648#define BIG_SUR_GE_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */ 649 650#define BIG_SUR_GE_IPIF_DMA_DFT_MASK (BIG_SUR_GE_IPIF_SEND_DMA_MASK | \ 651 BIG_SUR_GE_IPIF_RECV_DMA_MASK | \ 652 BIG_SUR_GE_IPIF_EMAC_MASK | \ 653 BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \ 654 BIG_SUR_GE_IPIF_RECV_FIFO_MASK) 655 656#define BIG_SUR_GE_IPIF_FIFO_DFT_MASK (BIG_SUR_GE_IPIF_EMAC_MASK | \ 657 BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \ 658 BIG_SUR_GE_IPIF_RECV_FIFO_MASK) 659 660#define BIG_SUR_GE_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */ 661#define BIG_SUR_GE_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */ 662#define BIG_SUR_GE_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */ 663#define BIG_SUR_GE_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */ 664 665/* a mask for all transmit interrupts, used in polled mode */ 666#define BIG_SUR_GE_EIR_XMIT_ALL_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \ 667 BIG_SUR_GE_EIR_XMIT_ERROR_MASK | \ 668 BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK | \ 669 BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) 670 671/* a mask for all receive interrupts, used in polled mode */ 672#define BIG_SUR_GE_EIR_RECV_ALL_MASK (BIG_SUR_GE_EIR_RECV_DONE_MASK | \ 673 BIG_SUR_GE_EIR_RECV_ERROR_MASK | \ 674 BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK | \ 675 BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | \ 676 BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | \ 677 BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | \ 678 BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | \ 679 BIG_SUR_GE_EIR_RECV_COLLISION_MASK | \ 680 BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | \ 681 BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | \ 682 BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | \ 683 BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | \ 684 BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK) 685 686/* a default interrupt mask for scatter-gather DMA operation */ 687#define BIG_SUR_GE_EIR_DFT_SG_MASK (BIG_SUR_GE_EIR_RECV_ERROR_MASK | \ 688 BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | \ 689 BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | \ 690 BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK | \ 691 BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK | \ 692 BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK | \ 693 BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK | \ 694 BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | \ 695 BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | \ 696 BIG_SUR_GE_EIR_RECV_COLLISION_MASK | \ 697 BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | \ 698 BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | \ 699 BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | \ 700 BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | \ 701 BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK) 702 703/* a default interrupt mask for non-DMA operation (direct FIFOs) */ 704#define BIG_SUR_GE_EIR_DFT_FIFO_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \ 705 BIG_SUR_GE_EIR_RECV_DONE_MASK | \ 706 BIG_SUR_GE_EIR_DFT_SG_MASK) 707 708#define BIG_SUR_GE_DMA_SG_INTR_MASK (BIG_SUR_GEIXR_DMA_ERROR_MASK | \ 709 BIG_SUR_GEIXR_PKT_THRESHOLD_MASK | \ 710 BIG_SUR_GEIXR_PKT_WAIT_BOUND_MASK | \ 711 BIG_SUR_GEIXR_SG_END_MASK) 712 713#endif 714