1/* 2 * linux/drivers/mmc/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 */ 11 12/* 13 * PCI registers 14 */ 15 16#define PCI_SDHCI_IFPIO 0x00 17#define PCI_SDHCI_IFDMA 0x01 18#define PCI_SDHCI_IFVENDOR 0x02 19 20#define PCI_SLOT_INFO 0x40 /* 8 bits */ 21#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 22#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 23 24/* 25 * Controller registers 26 */ 27 28#define SDHCI_DMA_ADDRESS 0x00 29 30#define SDHCI_BLOCK_SIZE 0x04 31#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33#define SDHCI_BLOCK_COUNT 0x06 34 35#define SDHCI_ARGUMENT 0x08 36 37#define SDHCI_TRANSFER_MODE 0x0C 38#define SDHCI_TRNS_DMA 0x01 39#define SDHCI_TRNS_BLK_CNT_EN 0x02 40#define SDHCI_TRNS_ACMD12 0x04 41#define SDHCI_TRNS_READ 0x10 42#define SDHCI_TRNS_MULTI 0x20 43 44#define SDHCI_COMMAND 0x0E 45#define SDHCI_CMD_RESP_MASK 0x03 46#define SDHCI_CMD_CRC 0x08 47#define SDHCI_CMD_INDEX 0x10 48#define SDHCI_CMD_DATA 0x20 49 50#define SDHCI_CMD_RESP_NONE 0x00 51#define SDHCI_CMD_RESP_LONG 0x01 52#define SDHCI_CMD_RESP_SHORT 0x02 53#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 54 55#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 56 57#define SDHCI_RESPONSE 0x10 58 59#define SDHCI_BUFFER 0x20 60 61#define SDHCI_PRESENT_STATE 0x24 62#define SDHCI_CMD_INHIBIT 0x00000001 63#define SDHCI_DATA_INHIBIT 0x00000002 64#define SDHCI_DOING_WRITE 0x00000100 65#define SDHCI_DOING_READ 0x00000200 66#define SDHCI_SPACE_AVAILABLE 0x00000400 67#define SDHCI_DATA_AVAILABLE 0x00000800 68#define SDHCI_CARD_PRESENT 0x00010000 69#define SDHCI_WRITE_PROTECT 0x00080000 70 71#define SDHCI_HOST_CONTROL 0x28 72#define SDHCI_CTRL_LED 0x01 73#define SDHCI_CTRL_4BITBUS 0x02 74#define SDHCI_CTRL_HISPD 0x04 75 76#define SDHCI_POWER_CONTROL 0x29 77#define SDHCI_POWER_ON 0x01 78#define SDHCI_POWER_180 0x0A 79#define SDHCI_POWER_300 0x0C 80#define SDHCI_POWER_330 0x0E 81 82#define SDHCI_BLOCK_GAP_CONTROL 0x2A 83 84#define SDHCI_WALK_UP_CONTROL 0x2B 85 86#define SDHCI_CLOCK_CONTROL 0x2C 87#define SDHCI_DIVIDER_SHIFT 8 88#define SDHCI_CLOCK_CARD_EN 0x0004 89#define SDHCI_CLOCK_INT_STABLE 0x0002 90#define SDHCI_CLOCK_INT_EN 0x0001 91 92#define SDHCI_TIMEOUT_CONTROL 0x2E 93 94#define SDHCI_SOFTWARE_RESET 0x2F 95#define SDHCI_RESET_ALL 0x01 96#define SDHCI_RESET_CMD 0x02 97#define SDHCI_RESET_DATA 0x04 98 99#define SDHCI_INT_STATUS 0x30 100#define SDHCI_INT_ENABLE 0x34 101#define SDHCI_SIGNAL_ENABLE 0x38 102#define SDHCI_INT_RESPONSE 0x00000001 103#define SDHCI_INT_DATA_END 0x00000002 104#define SDHCI_INT_DMA_END 0x00000008 105#define SDHCI_INT_SPACE_AVAIL 0x00000010 106#define SDHCI_INT_DATA_AVAIL 0x00000020 107#define SDHCI_INT_CARD_INSERT 0x00000040 108#define SDHCI_INT_CARD_REMOVE 0x00000080 109#define SDHCI_INT_CARD_INT 0x00000100 110#define SDHCI_INT_TIMEOUT 0x00010000 111#define SDHCI_INT_CRC 0x00020000 112#define SDHCI_INT_END_BIT 0x00040000 113#define SDHCI_INT_INDEX 0x00080000 114#define SDHCI_INT_DATA_TIMEOUT 0x00100000 115#define SDHCI_INT_DATA_CRC 0x00200000 116#define SDHCI_INT_DATA_END_BIT 0x00400000 117#define SDHCI_INT_BUS_POWER 0x00800000 118#define SDHCI_INT_ACMD12ERR 0x01000000 119 120#define SDHCI_INT_NORMAL_MASK 0x00007FFF 121#define SDHCI_INT_ERROR_MASK 0xFFFF8000 122 123#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 124 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 125#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 126 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 127 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 128 SDHCI_INT_DATA_END_BIT) 129 130#define SDHCI_ACMD12_ERR 0x3C 131 132/* 3E-3F reserved */ 133 134#define SDHCI_CAPABILITIES 0x40 135#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 136#define SDHCI_TIMEOUT_CLK_SHIFT 0 137#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 138#define SDHCI_CLOCK_BASE_MASK 0x00003F00 139#define SDHCI_CLOCK_BASE_SHIFT 8 140#define SDHCI_MAX_BLOCK_MASK 0x00030000 141#define SDHCI_MAX_BLOCK_SHIFT 16 142#define SDHCI_CAN_DO_HISPD 0x00200000 143#define SDHCI_CAN_DO_DMA 0x00400000 144#define SDHCI_CAN_VDD_330 0x01000000 145#define SDHCI_CAN_VDD_300 0x02000000 146#define SDHCI_CAN_VDD_180 0x04000000 147 148/* 44-47 reserved for more caps */ 149 150#define SDHCI_MAX_CURRENT 0x48 151 152/* 4C-4F reserved for more max current */ 153 154/* 50-FB reserved */ 155 156#define SDHCI_SLOT_INT_STATUS 0xFC 157 158#define SDHCI_HOST_VERSION 0xFE 159#define SDHCI_VENDOR_VER_MASK 0xFF00 160#define SDHCI_VENDOR_VER_SHIFT 8 161#define SDHCI_SPEC_VER_MASK 0x00FF 162#define SDHCI_SPEC_VER_SHIFT 0 163 164struct sdhci_chip; 165 166struct sdhci_host { 167 struct sdhci_chip *chip; 168 struct mmc_host *mmc; /* MMC structure */ 169 170 spinlock_t lock; /* Mutex */ 171 172 int flags; /* Host attributes */ 173#define SDHCI_USE_DMA (1<<0) 174 175 unsigned int max_clk; /* Max possible freq (MHz) */ 176 unsigned int timeout_clk; /* Timeout freq (KHz) */ 177 178 unsigned int clock; /* Current clock (MHz) */ 179 unsigned short power; /* Current voltage */ 180 181 struct mmc_request *mrq; /* Current request */ 182 struct mmc_command *cmd; /* Current command */ 183 struct mmc_data *data; /* Current data request */ 184 185 struct scatterlist *cur_sg; /* We're working on this */ 186 int num_sg; /* Entries left */ 187 int offset; /* Offset into current sg */ 188 int remain; /* Bytes left in current */ 189 190 char slot_descr[20]; /* Name for reservations */ 191 192 int irq; /* Device IRQ */ 193 int bar; /* PCI BAR index */ 194 unsigned long addr; /* Bus address */ 195 void __iomem * ioaddr; /* Mapped address */ 196 197 struct tasklet_struct card_tasklet; /* Tasklet structures */ 198 struct tasklet_struct finish_tasklet; 199 200 struct timer_list timer; /* Timer for timeouts */ 201}; 202 203struct sdhci_chip { 204 struct pci_dev *pdev; 205 206 unsigned long quirks; 207 208 int num_slots; /* Slots on controller */ 209 struct sdhci_host *hosts[0]; /* Pointers to hosts */ 210}; 211