1/*
2 * Zoran ZR36050 basic configuration functions - header file
3 *
4 * Copyright (C) 2001 Wolfgang Scherr <scherr@net4you.at>
5 *
6 * $Id: zr36050.h,v 1.1.1.1 2007/08/03 18:52:41 Exp $
7 *
8 * ------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 * ------------------------------------------------------------------------
25 */
26
27#ifndef ZR36050_H
28#define ZR36050_H
29
30#include "videocodec.h"
31
32/* data stored for each zoran jpeg codec chip */
33struct zr36050 {
34	char name[32];
35	int num;
36	/* io datastructure */
37	struct videocodec *codec;
38	// last coder status
39	__u8 status1;
40	// actual coder setup
41	int mode;
42
43	__u16 width;
44	__u16 height;
45
46	__u16 bitrate_ctrl;
47
48	__u32 total_code_vol;
49	__u32 real_code_vol;
50	__u16 max_block_vol;
51
52	__u8 h_samp_ratio[8];
53	__u8 v_samp_ratio[8];
54	__u16 scalefact;
55	__u16 dri;
56
57	/* com/app marker */
58	struct jpeg_com_marker com;
59	struct jpeg_app_marker app;
60};
61
62/* zr36050 register addresses */
63#define ZR050_GO                  0x000
64#define ZR050_HARDWARE            0x002
65#define ZR050_MODE                0x003
66#define ZR050_OPTIONS             0x004
67#define ZR050_MBCV                0x005
68#define ZR050_MARKERS_EN          0x006
69#define ZR050_INT_REQ_0           0x007
70#define ZR050_INT_REQ_1           0x008
71#define ZR050_TCV_NET_HI          0x009
72#define ZR050_TCV_NET_MH          0x00a
73#define ZR050_TCV_NET_ML          0x00b
74#define ZR050_TCV_NET_LO          0x00c
75#define ZR050_TCV_DATA_HI         0x00d
76#define ZR050_TCV_DATA_MH         0x00e
77#define ZR050_TCV_DATA_ML         0x00f
78#define ZR050_TCV_DATA_LO         0x010
79#define ZR050_SF_HI               0x011
80#define ZR050_SF_LO               0x012
81#define ZR050_AF_HI               0x013
82#define ZR050_AF_M                0x014
83#define ZR050_AF_LO               0x015
84#define ZR050_ACV_HI              0x016
85#define ZR050_ACV_MH              0x017
86#define ZR050_ACV_ML              0x018
87#define ZR050_ACV_LO              0x019
88#define ZR050_ACT_HI              0x01a
89#define ZR050_ACT_MH              0x01b
90#define ZR050_ACT_ML              0x01c
91#define ZR050_ACT_LO              0x01d
92#define ZR050_ACV_TRUN_HI         0x01e
93#define ZR050_ACV_TRUN_MH         0x01f
94#define ZR050_ACV_TRUN_ML         0x020
95#define ZR050_ACV_TRUN_LO         0x021
96#define ZR050_STATUS_0            0x02e
97#define ZR050_STATUS_1            0x02f
98
99#define ZR050_SOF_IDX             0x040
100#define ZR050_SOS1_IDX            0x07a
101#define ZR050_SOS2_IDX            0x08a
102#define ZR050_SOS3_IDX            0x09a
103#define ZR050_SOS4_IDX            0x0aa
104#define ZR050_DRI_IDX             0x0c0
105#define ZR050_DNL_IDX             0x0c6
106#define ZR050_DQT_IDX             0x0cc
107#define ZR050_DHT_IDX             0x1d4
108#define ZR050_APP_IDX             0x380
109#define ZR050_COM_IDX             0x3c0
110
111/* zr36050 hardware register bits */
112
113#define ZR050_HW_BSWD                0x80
114#define ZR050_HW_MSTR                0x40
115#define ZR050_HW_DMA                 0x20
116#define ZR050_HW_CFIS_1_CLK          0x00
117#define ZR050_HW_CFIS_2_CLK          0x04
118#define ZR050_HW_CFIS_3_CLK          0x08
119#define ZR050_HW_CFIS_4_CLK          0x0C
120#define ZR050_HW_CFIS_5_CLK          0x10
121#define ZR050_HW_CFIS_6_CLK          0x14
122#define ZR050_HW_CFIS_7_CLK          0x18
123#define ZR050_HW_CFIS_8_CLK          0x1C
124#define ZR050_HW_BELE                0x01
125
126/* zr36050 mode register bits */
127
128#define ZR050_MO_COMP                0x80
129#define ZR050_MO_COMP                0x80
130#define ZR050_MO_ATP                 0x40
131#define ZR050_MO_PASS2               0x20
132#define ZR050_MO_TLM                 0x10
133#define ZR050_MO_DCONLY              0x08
134#define ZR050_MO_BRC                 0x04
135
136#define ZR050_MO_ATP                 0x40
137#define ZR050_MO_PASS2               0x20
138#define ZR050_MO_TLM                 0x10
139#define ZR050_MO_DCONLY              0x08
140
141/* zr36050 option register bits */
142
143#define ZR050_OP_NSCN_1              0x00
144#define ZR050_OP_NSCN_2              0x20
145#define ZR050_OP_NSCN_3              0x40
146#define ZR050_OP_NSCN_4              0x60
147#define ZR050_OP_NSCN_5              0x80
148#define ZR050_OP_NSCN_6              0xA0
149#define ZR050_OP_NSCN_7              0xC0
150#define ZR050_OP_NSCN_8              0xE0
151#define ZR050_OP_OVF                 0x10
152
153
154/* zr36050 markers-enable register bits */
155
156#define ZR050_ME_APP                 0x80
157#define ZR050_ME_COM                 0x40
158#define ZR050_ME_DRI                 0x20
159#define ZR050_ME_DQT                 0x10
160#define ZR050_ME_DHT                 0x08
161#define ZR050_ME_DNL                 0x04
162#define ZR050_ME_DQTI                0x02
163#define ZR050_ME_DHTI                0x01
164
165/* zr36050 status0/1 register bit masks */
166
167#define ZR050_ST_RST_MASK            0x20
168#define ZR050_ST_SOF_MASK            0x02
169#define ZR050_ST_SOS_MASK            0x02
170#define ZR050_ST_DATRDY_MASK         0x80
171#define ZR050_ST_MRKDET_MASK         0x40
172#define ZR050_ST_RFM_MASK            0x10
173#define ZR050_ST_RFD_MASK            0x08
174#define ZR050_ST_END_MASK            0x04
175#define ZR050_ST_TCVOVF_MASK         0x02
176#define ZR050_ST_DATOVF_MASK         0x01
177
178/* pixel component idx */
179
180#define ZR050_Y_COMPONENT         0
181#define ZR050_U_COMPONENT         1
182#define ZR050_V_COMPONENT         2
183
184#endif				/*fndef ZR36050_H */
185