1/* 2 Driver for VES1893 and VES1993 QPSK Demodulators 3 4 Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de> 5 Copyright (C) 2001 Ronny Strutz <3des@elitedvb.de> 6 Copyright (C) 2002 Dennis Noermann <dennis.noermann@noernet.de> 7 Copyright (C) 2002-2003 Andreas Oberritter <obi@linuxtv.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 24*/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/string.h> 30#include <linux/slab.h> 31#include <linux/delay.h> 32 33#include "dvb_frontend.h" 34#include "ves1x93.h" 35 36 37struct ves1x93_state { 38 struct i2c_adapter* i2c; 39 /* configuration settings */ 40 const struct ves1x93_config* config; 41 struct dvb_frontend frontend; 42 43 /* previous uncorrected block counter */ 44 fe_spectral_inversion_t inversion; 45 u8 *init_1x93_tab; 46 u8 *init_1x93_wtab; 47 u8 tab_size; 48 u8 demod_type; 49}; 50 51static int debug = 0; 52#define dprintk if (debug) printk 53 54#define DEMOD_VES1893 0 55#define DEMOD_VES1993 1 56 57static u8 init_1893_tab [] = { 58 0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4, 59 0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00, 60 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 61 0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00, 62 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 63 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 64 0x00, 0x55, 0x00, 0x00, 0x7f, 0x00 65}; 66 67static u8 init_1993_tab [] = { 68 0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c, 69 0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00, 70 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 71 0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10, 72 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 73 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 74 0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 75 0x00, 0x00, 0x0e, 0x80, 0x00 76}; 77 78static u8 init_1893_wtab[] = 79{ 80 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0, 81 0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1, 82 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0, 83 1,1,1,0,1,1 84}; 85 86static u8 init_1993_wtab[] = 87{ 88 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0, 89 0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1, 90 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0, 91 1,1,1,0,1,1,1,1, 1,1,1,1,1 92}; 93 94static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data) 95{ 96 u8 buf [] = { 0x00, reg, data }; 97 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 }; 98 int err; 99 100 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 101 dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __FUNCTION__, err, reg, data); 102 return -EREMOTEIO; 103 } 104 105 return 0; 106} 107 108static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg) 109{ 110 int ret; 111 u8 b0 [] = { 0x00, reg }; 112 u8 b1 [] = { 0 }; 113 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, 114 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 115 116 ret = i2c_transfer (state->i2c, msg, 2); 117 118 if (ret != 2) return ret; 119 120 return b1[0]; 121} 122 123static int ves1x93_clr_bit (struct ves1x93_state* state) 124{ 125 msleep(10); 126 ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe); 127 ves1x93_writereg (state, 0, state->init_1x93_tab[0]); 128 msleep(50); 129 return 0; 130} 131 132static int ves1x93_set_inversion (struct ves1x93_state* state, fe_spectral_inversion_t inversion) 133{ 134 u8 val; 135 136 /* 137 * inversion on/off are interchanged because i and q seem to 138 * be swapped on the hardware 139 */ 140 141 switch (inversion) { 142 case INVERSION_OFF: 143 val = 0xc0; 144 break; 145 case INVERSION_ON: 146 val = 0x80; 147 break; 148 case INVERSION_AUTO: 149 val = 0x00; 150 break; 151 default: 152 return -EINVAL; 153 } 154 155 return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val); 156} 157 158static int ves1x93_set_fec (struct ves1x93_state* state, fe_code_rate_t fec) 159{ 160 if (fec == FEC_AUTO) 161 return ves1x93_writereg (state, 0x0d, 0x08); 162 else if (fec < FEC_1_2 || fec > FEC_8_9) 163 return -EINVAL; 164 else 165 return ves1x93_writereg (state, 0x0d, fec - FEC_1_2); 166} 167 168static fe_code_rate_t ves1x93_get_fec (struct ves1x93_state* state) 169{ 170 return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7); 171} 172 173static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate) 174{ 175 u32 BDR; 176 u32 ratio; 177 u8 ADCONF, FCONF, FNR, AGCR; 178 u32 BDRI; 179 u32 tmp; 180 u32 FIN; 181 182 dprintk("%s: srate == %d\n", __FUNCTION__, (unsigned int) srate); 183 184 if (srate > state->config->xin/2) 185 srate = state->config->xin/2; 186 187 if (srate < 500000) 188 srate = 500000; 189 190#define MUL (1UL<<26) 191 192 FIN = (state->config->xin + 6000) >> 4; 193 194 tmp = srate << 6; 195 ratio = tmp / FIN; 196 197 tmp = (tmp % FIN) << 8; 198 ratio = (ratio << 8) + tmp / FIN; 199 200 tmp = (tmp % FIN) << 8; 201 ratio = (ratio << 8) + tmp / FIN; 202 203 FNR = 0xff; 204 205 if (ratio < MUL/3) FNR = 0; 206 if (ratio < (MUL*11)/50) FNR = 1; 207 if (ratio < MUL/6) FNR = 2; 208 if (ratio < MUL/9) FNR = 3; 209 if (ratio < MUL/12) FNR = 4; 210 if (ratio < (MUL*11)/200) FNR = 5; 211 if (ratio < MUL/24) FNR = 6; 212 if (ratio < (MUL*27)/1000) FNR = 7; 213 if (ratio < MUL/48) FNR = 8; 214 if (ratio < (MUL*137)/10000) FNR = 9; 215 216 if (FNR == 0xff) { 217 ADCONF = 0x89; 218 FCONF = 0x80; 219 FNR = 0; 220 } else { 221 ADCONF = 0x81; 222 FCONF = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5); 223 /*FCONF = 0x80 | ((FNR & 0x01) << 5) | (((FNR > 1) & 0x03) << 3) | ((FNR >> 1) & 0x07);*/ 224 } 225 226 BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1; 227 BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1; 228 229 dprintk("FNR= %d\n", FNR); 230 dprintk("ratio= %08x\n", (unsigned int) ratio); 231 dprintk("BDR= %08x\n", (unsigned int) BDR); 232 dprintk("BDRI= %02x\n", (unsigned int) BDRI); 233 234 if (BDRI > 0xff) 235 BDRI = 0xff; 236 237 ves1x93_writereg (state, 0x06, 0xff & BDR); 238 ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8)); 239 ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16)); 240 241 ves1x93_writereg (state, 0x09, BDRI); 242 ves1x93_writereg (state, 0x20, ADCONF); 243 ves1x93_writereg (state, 0x21, FCONF); 244 245 AGCR = state->init_1x93_tab[0x05]; 246 if (state->config->invert_pwm) 247 AGCR |= 0x20; 248 249 if (srate < 6000000) 250 AGCR |= 0x80; 251 else 252 AGCR &= ~0x80; 253 254 ves1x93_writereg (state, 0x05, AGCR); 255 256 /* ves1993 hates this, will lose lock */ 257 if (state->demod_type != DEMOD_VES1993) 258 ves1x93_clr_bit (state); 259 260 return 0; 261} 262 263static int ves1x93_init (struct dvb_frontend* fe) 264{ 265 struct ves1x93_state* state = fe->demodulator_priv; 266 int i; 267 int val; 268 269 dprintk("%s: init chip\n", __FUNCTION__); 270 271 for (i = 0; i < state->tab_size; i++) { 272 if (state->init_1x93_wtab[i]) { 273 val = state->init_1x93_tab[i]; 274 275 if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */ 276 ves1x93_writereg (state, i, val); 277 } 278 } 279 280 return 0; 281} 282 283static int ves1x93_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage) 284{ 285 struct ves1x93_state* state = fe->demodulator_priv; 286 287 switch (voltage) { 288 case SEC_VOLTAGE_13: 289 return ves1x93_writereg (state, 0x1f, 0x20); 290 case SEC_VOLTAGE_18: 291 return ves1x93_writereg (state, 0x1f, 0x30); 292 case SEC_VOLTAGE_OFF: 293 return ves1x93_writereg (state, 0x1f, 0x00); 294 default: 295 return -EINVAL; 296 } 297} 298 299static int ves1x93_read_status(struct dvb_frontend* fe, fe_status_t* status) 300{ 301 struct ves1x93_state* state = fe->demodulator_priv; 302 303 u8 sync = ves1x93_readreg (state, 0x0e); 304 305 /* 306 * The ves1893 sometimes returns sync values that make no sense, 307 * because, e.g., the SIGNAL bit is 0, while some of the higher 308 * bits are 1 (and how can there be a CARRIER w/o a SIGNAL?). 309 * Tests showed that the VITERBI and SYNC bits are returned 310 * reliably, while the SIGNAL and CARRIER bits ar sometimes wrong. 311 * If such a case occurs, we read the value again, until we get a 312 * valid value. 313 */ 314 int maxtry = 10; /* just for safety - let's not get stuck here */ 315 while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) { 316 msleep(10); 317 sync = ves1x93_readreg (state, 0x0e); 318 } 319 320 *status = 0; 321 322 if (sync & 1) 323 *status |= FE_HAS_SIGNAL; 324 325 if (sync & 2) 326 *status |= FE_HAS_CARRIER; 327 328 if (sync & 4) 329 *status |= FE_HAS_VITERBI; 330 331 if (sync & 8) 332 *status |= FE_HAS_SYNC; 333 334 if ((sync & 0x1f) == 0x1f) 335 *status |= FE_HAS_LOCK; 336 337 return 0; 338} 339 340static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber) 341{ 342 struct ves1x93_state* state = fe->demodulator_priv; 343 344 *ber = ves1x93_readreg (state, 0x15); 345 *ber |= (ves1x93_readreg (state, 0x16) << 8); 346 *ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16); 347 *ber *= 10; 348 349 return 0; 350} 351 352static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength) 353{ 354 struct ves1x93_state* state = fe->demodulator_priv; 355 356 u8 signal = ~ves1x93_readreg (state, 0x0b); 357 *strength = (signal << 8) | signal; 358 359 return 0; 360} 361 362static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr) 363{ 364 struct ves1x93_state* state = fe->demodulator_priv; 365 366 u8 _snr = ~ves1x93_readreg (state, 0x1c); 367 *snr = (_snr << 8) | _snr; 368 369 return 0; 370} 371 372static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 373{ 374 struct ves1x93_state* state = fe->demodulator_priv; 375 376 *ucblocks = ves1x93_readreg (state, 0x18) & 0x7f; 377 378 if (*ucblocks == 0x7f) 379 *ucblocks = 0xffffffff; /* counter overflow... */ 380 381 ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */ 382 ves1x93_writereg (state, 0x18, 0x80); /* dto. */ 383 384 return 0; 385} 386 387static int ves1x93_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 388{ 389 struct ves1x93_state* state = fe->demodulator_priv; 390 391 if (fe->ops.tuner_ops.set_params) { 392 fe->ops.tuner_ops.set_params(fe, p); 393 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 394 } 395 ves1x93_set_inversion (state, p->inversion); 396 ves1x93_set_fec (state, p->u.qpsk.fec_inner); 397 ves1x93_set_symbolrate (state, p->u.qpsk.symbol_rate); 398 state->inversion = p->inversion; 399 400 return 0; 401} 402 403static int ves1x93_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 404{ 405 struct ves1x93_state* state = fe->demodulator_priv; 406 int afc; 407 408 afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2; 409 afc = (afc * (int)(p->u.qpsk.symbol_rate/1000/8))/16; 410 411 p->frequency -= afc; 412 413 /* 414 * inversion indicator is only valid 415 * if auto inversion was used 416 */ 417 if (state->inversion == INVERSION_AUTO) 418 p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ? 419 INVERSION_OFF : INVERSION_ON; 420 p->u.qpsk.fec_inner = ves1x93_get_fec (state); 421 422 return 0; 423} 424 425static int ves1x93_sleep(struct dvb_frontend* fe) 426{ 427 struct ves1x93_state* state = fe->demodulator_priv; 428 429 return ves1x93_writereg (state, 0x00, 0x08); 430} 431 432static void ves1x93_release(struct dvb_frontend* fe) 433{ 434 struct ves1x93_state* state = fe->demodulator_priv; 435 kfree(state); 436} 437 438static int ves1x93_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) 439{ 440 struct ves1x93_state* state = fe->demodulator_priv; 441 442 if (enable) { 443 return ves1x93_writereg(state, 0x00, 0x11); 444 } else { 445 return ves1x93_writereg(state, 0x00, 0x01); 446 } 447} 448 449static struct dvb_frontend_ops ves1x93_ops; 450 451struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config, 452 struct i2c_adapter* i2c) 453{ 454 struct ves1x93_state* state = NULL; 455 u8 identity; 456 457 /* allocate memory for the internal state */ 458 state = kmalloc(sizeof(struct ves1x93_state), GFP_KERNEL); 459 if (state == NULL) goto error; 460 461 /* setup the state */ 462 state->config = config; 463 state->i2c = i2c; 464 state->inversion = INVERSION_OFF; 465 466 /* check if the demod is there + identify it */ 467 identity = ves1x93_readreg(state, 0x1e); 468 switch (identity) { 469 case 0xdc: /* VES1893A rev1 */ 470 printk("ves1x93: Detected ves1893a rev1\n"); 471 state->demod_type = DEMOD_VES1893; 472 state->init_1x93_tab = init_1893_tab; 473 state->init_1x93_wtab = init_1893_wtab; 474 state->tab_size = sizeof(init_1893_tab); 475 break; 476 477 case 0xdd: /* VES1893A rev2 */ 478 printk("ves1x93: Detected ves1893a rev2\n"); 479 state->demod_type = DEMOD_VES1893; 480 state->init_1x93_tab = init_1893_tab; 481 state->init_1x93_wtab = init_1893_wtab; 482 state->tab_size = sizeof(init_1893_tab); 483 break; 484 485 case 0xde: /* VES1993 */ 486 printk("ves1x93: Detected ves1993\n"); 487 state->demod_type = DEMOD_VES1993; 488 state->init_1x93_tab = init_1993_tab; 489 state->init_1x93_wtab = init_1993_wtab; 490 state->tab_size = sizeof(init_1993_tab); 491 break; 492 493 default: 494 goto error; 495 } 496 497 /* create dvb_frontend */ 498 memcpy(&state->frontend.ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops)); 499 state->frontend.demodulator_priv = state; 500 return &state->frontend; 501 502error: 503 kfree(state); 504 return NULL; 505} 506 507static struct dvb_frontend_ops ves1x93_ops = { 508 509 .info = { 510 .name = "VLSI VES1x93 DVB-S", 511 .type = FE_QPSK, 512 .frequency_min = 950000, 513 .frequency_max = 2150000, 514 .frequency_stepsize = 125, /* kHz for QPSK frontends */ 515 .frequency_tolerance = 29500, 516 .symbol_rate_min = 1000000, 517 .symbol_rate_max = 45000000, 518 /* .symbol_rate_tolerance = ???,*/ 519 .caps = FE_CAN_INVERSION_AUTO | 520 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 521 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 522 FE_CAN_QPSK 523 }, 524 525 .release = ves1x93_release, 526 527 .init = ves1x93_init, 528 .sleep = ves1x93_sleep, 529 .i2c_gate_ctrl = ves1x93_i2c_gate_ctrl, 530 531 .set_frontend = ves1x93_set_frontend, 532 .get_frontend = ves1x93_get_frontend, 533 534 .read_status = ves1x93_read_status, 535 .read_ber = ves1x93_read_ber, 536 .read_signal_strength = ves1x93_read_signal_strength, 537 .read_snr = ves1x93_read_snr, 538 .read_ucblocks = ves1x93_read_ucblocks, 539 540 .set_voltage = ves1x93_set_voltage, 541}; 542 543module_param(debug, int, 0644); 544 545MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver"); 546MODULE_AUTHOR("Ralph Metzler"); 547MODULE_LICENSE("GPL"); 548 549EXPORT_SYMBOL(ves1x93_attach); 550