1/* 2 Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver 3 4 Copyright (C) 2005 Steven Toth <stoth@hauppauge.com> 5 6 Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21*/ 22 23#include <linux/slab.h> 24#include <linux/kernel.h> 25#include <linux/module.h> 26#include <linux/moduleparam.h> 27#include <linux/init.h> 28 29#include "dvb_frontend.h" 30#include "cx24123.h" 31 32#define XTAL 10111000 33 34static int force_band; 35static int debug; 36#define dprintk(args...) \ 37 do { \ 38 if (debug) printk (KERN_DEBUG "cx24123: " args); \ 39 } while (0) 40 41struct cx24123_state 42{ 43 struct i2c_adapter* i2c; 44 const struct cx24123_config* config; 45 46 struct dvb_frontend frontend; 47 48 /* Some PLL specifics for tuning */ 49 u32 VCAarg; 50 u32 VGAarg; 51 u32 bandselectarg; 52 u32 pllarg; 53 u32 FILTune; 54 55 /* The Demod/Tuner can't easily provide these, we cache them */ 56 u32 currentfreq; 57 u32 currentsymbolrate; 58}; 59 60/* Various tuner defaults need to be established for a given symbol rate Sps */ 61static struct 62{ 63 u32 symbolrate_low; 64 u32 symbolrate_high; 65 u32 VCAprogdata; 66 u32 VGAprogdata; 67 u32 FILTune; 68} cx24123_AGC_vals[] = 69{ 70 { 71 .symbolrate_low = 1000000, 72 .symbolrate_high = 4999999, 73 /* the specs recommend other values for VGA offsets, 74 but tests show they are wrong */ 75 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, 76 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, 77 .FILTune = 0x27f /* 0.41 V */ 78 }, 79 { 80 .symbolrate_low = 5000000, 81 .symbolrate_high = 14999999, 82 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, 83 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, 84 .FILTune = 0x317 /* 0.90 V */ 85 }, 86 { 87 .symbolrate_low = 15000000, 88 .symbolrate_high = 45000000, 89 .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, 90 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, 91 .FILTune = 0x145 /* 2.70 V */ 92 }, 93}; 94 95static struct 96{ 97 u32 freq_low; 98 u32 freq_high; 99 u32 VCOdivider; 100 u32 progdata; 101} cx24123_bandselect_vals[] = 102{ 103 /* band 1 */ 104 { 105 .freq_low = 950000, 106 .freq_high = 1074999, 107 .VCOdivider = 4, 108 .progdata = (0 << 19) | (0 << 9) | 0x40, 109 }, 110 111 /* band 2 */ 112 { 113 .freq_low = 1075000, 114 .freq_high = 1177999, 115 .VCOdivider = 4, 116 .progdata = (0 << 19) | (0 << 9) | 0x80, 117 }, 118 119 /* band 3 */ 120 { 121 .freq_low = 1178000, 122 .freq_high = 1295999, 123 .VCOdivider = 2, 124 .progdata = (0 << 19) | (1 << 9) | 0x01, 125 }, 126 127 /* band 4 */ 128 { 129 .freq_low = 1296000, 130 .freq_high = 1431999, 131 .VCOdivider = 2, 132 .progdata = (0 << 19) | (1 << 9) | 0x02, 133 }, 134 135 /* band 5 */ 136 { 137 .freq_low = 1432000, 138 .freq_high = 1575999, 139 .VCOdivider = 2, 140 .progdata = (0 << 19) | (1 << 9) | 0x04, 141 }, 142 143 /* band 6 */ 144 { 145 .freq_low = 1576000, 146 .freq_high = 1717999, 147 .VCOdivider = 2, 148 .progdata = (0 << 19) | (1 << 9) | 0x08, 149 }, 150 151 /* band 7 */ 152 { 153 .freq_low = 1718000, 154 .freq_high = 1855999, 155 .VCOdivider = 2, 156 .progdata = (0 << 19) | (1 << 9) | 0x10, 157 }, 158 159 /* band 8 */ 160 { 161 .freq_low = 1856000, 162 .freq_high = 2035999, 163 .VCOdivider = 2, 164 .progdata = (0 << 19) | (1 << 9) | 0x20, 165 }, 166 167 /* band 9 */ 168 { 169 .freq_low = 2036000, 170 .freq_high = 2150000, 171 .VCOdivider = 2, 172 .progdata = (0 << 19) | (1 << 9) | 0x40, 173 }, 174}; 175 176static struct { 177 u8 reg; 178 u8 data; 179} cx24123_regdata[] = 180{ 181 {0x00, 0x03}, /* Reset system */ 182 {0x00, 0x00}, /* Clear reset */ 183 {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ 184 {0x04, 0x10}, /* MPEG */ 185 {0x05, 0x04}, /* MPEG */ 186 {0x06, 0x31}, /* MPEG (default) */ 187 {0x0b, 0x00}, /* Freq search start point (default) */ 188 {0x0c, 0x00}, /* Demodulator sample gain (default) */ 189 {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */ 190 {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ 191 {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ 192 {0x10, 0x01}, /* Default search inversion, no repeat (default) */ 193 {0x16, 0x00}, /* Enable reading of frequency */ 194 {0x17, 0x01}, /* Enable EsNO Ready Counter */ 195 {0x1c, 0x80}, /* Enable error counter */ 196 {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ 197 {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ 198 {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ 199 {0x29, 0x00}, /* DiSEqC LNB_DC off */ 200 {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ 201 {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ 202 {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ 203 {0x2d, 0x00}, 204 {0x2e, 0x00}, 205 {0x2f, 0x00}, 206 {0x30, 0x00}, 207 {0x31, 0x00}, 208 {0x32, 0x8c}, /* DiSEqC Parameters (default) */ 209 {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ 210 {0x34, 0x00}, 211 {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ 212 {0x36, 0x02}, /* DiSEqC Parameters (default) */ 213 {0x37, 0x3a}, /* DiSEqC Parameters (default) */ 214 {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ 215 {0x44, 0x00}, /* Constellation (default) */ 216 {0x45, 0x00}, /* Symbol count (default) */ 217 {0x46, 0x0d}, /* Symbol rate estimator on (default) */ 218 {0x56, 0xc1}, /* Error Counter = Viterbi BER */ 219 {0x57, 0xff}, /* Error Counter Window (default) */ 220 {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */ 221 {0x67, 0x83}, /* Non-DCII symbol clock */ 222}; 223 224static int cx24123_writereg(struct cx24123_state* state, int reg, int data) 225{ 226 u8 buf[] = { reg, data }; 227 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; 228 int err; 229 230 if (debug>1) 231 printk("cx24123: %s: write reg 0x%02x, value 0x%02x\n", 232 __FUNCTION__,reg, data); 233 234 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { 235 printk("%s: writereg error(err == %i, reg == 0x%02x," 236 " data == 0x%02x)\n", __FUNCTION__, err, reg, data); 237 return -EREMOTEIO; 238 } 239 240 return 0; 241} 242 243static int cx24123_readreg(struct cx24123_state* state, u8 reg) 244{ 245 int ret; 246 u8 b0[] = { reg }; 247 u8 b1[] = { 0 }; 248 struct i2c_msg msg[] = { 249 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, 250 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } 251 }; 252 253 ret = i2c_transfer(state->i2c, msg, 2); 254 255 if (ret != 2) { 256 printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret); 257 return ret; 258 } 259 260 if (debug>1) 261 printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret); 262 263 return b1[0]; 264} 265 266static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion) 267{ 268 u8 nom_reg = cx24123_readreg(state, 0x0e); 269 u8 auto_reg = cx24123_readreg(state, 0x10); 270 271 switch (inversion) { 272 case INVERSION_OFF: 273 dprintk("%s: inversion off\n",__FUNCTION__); 274 cx24123_writereg(state, 0x0e, nom_reg & ~0x80); 275 cx24123_writereg(state, 0x10, auto_reg | 0x80); 276 break; 277 case INVERSION_ON: 278 dprintk("%s: inversion on\n",__FUNCTION__); 279 cx24123_writereg(state, 0x0e, nom_reg | 0x80); 280 cx24123_writereg(state, 0x10, auto_reg | 0x80); 281 break; 282 case INVERSION_AUTO: 283 dprintk("%s: inversion auto\n",__FUNCTION__); 284 cx24123_writereg(state, 0x10, auto_reg & ~0x80); 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 return 0; 291} 292 293static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion) 294{ 295 u8 val; 296 297 val = cx24123_readreg(state, 0x1b) >> 7; 298 299 if (val == 0) { 300 dprintk("%s: read inversion off\n",__FUNCTION__); 301 *inversion = INVERSION_OFF; 302 } else { 303 dprintk("%s: read inversion on\n",__FUNCTION__); 304 *inversion = INVERSION_ON; 305 } 306 307 return 0; 308} 309 310static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec) 311{ 312 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; 313 314 if ( (fec < FEC_NONE) || (fec > FEC_AUTO) ) 315 fec = FEC_AUTO; 316 317 /* Set the soft decision threshold */ 318 if(fec == FEC_1_2) 319 cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) | 0x01); 320 else 321 cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) & ~0x01); 322 323 switch (fec) { 324 case FEC_1_2: 325 dprintk("%s: set FEC to 1/2\n",__FUNCTION__); 326 cx24123_writereg(state, 0x0e, nom_reg | 0x01); 327 cx24123_writereg(state, 0x0f, 0x02); 328 break; 329 case FEC_2_3: 330 dprintk("%s: set FEC to 2/3\n",__FUNCTION__); 331 cx24123_writereg(state, 0x0e, nom_reg | 0x02); 332 cx24123_writereg(state, 0x0f, 0x04); 333 break; 334 case FEC_3_4: 335 dprintk("%s: set FEC to 3/4\n",__FUNCTION__); 336 cx24123_writereg(state, 0x0e, nom_reg | 0x03); 337 cx24123_writereg(state, 0x0f, 0x08); 338 break; 339 case FEC_4_5: 340 dprintk("%s: set FEC to 4/5\n",__FUNCTION__); 341 cx24123_writereg(state, 0x0e, nom_reg | 0x04); 342 cx24123_writereg(state, 0x0f, 0x10); 343 break; 344 case FEC_5_6: 345 dprintk("%s: set FEC to 5/6\n",__FUNCTION__); 346 cx24123_writereg(state, 0x0e, nom_reg | 0x05); 347 cx24123_writereg(state, 0x0f, 0x20); 348 break; 349 case FEC_6_7: 350 dprintk("%s: set FEC to 6/7\n",__FUNCTION__); 351 cx24123_writereg(state, 0x0e, nom_reg | 0x06); 352 cx24123_writereg(state, 0x0f, 0x40); 353 break; 354 case FEC_7_8: 355 dprintk("%s: set FEC to 7/8\n",__FUNCTION__); 356 cx24123_writereg(state, 0x0e, nom_reg | 0x07); 357 cx24123_writereg(state, 0x0f, 0x80); 358 break; 359 case FEC_AUTO: 360 dprintk("%s: set FEC to auto\n",__FUNCTION__); 361 cx24123_writereg(state, 0x0f, 0xfe); 362 break; 363 default: 364 return -EOPNOTSUPP; 365 } 366 367 return 0; 368} 369 370static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec) 371{ 372 int ret; 373 374 ret = cx24123_readreg (state, 0x1b); 375 if (ret < 0) 376 return ret; 377 ret = ret & 0x07; 378 379 switch (ret) { 380 case 1: 381 *fec = FEC_1_2; 382 break; 383 case 2: 384 *fec = FEC_2_3; 385 break; 386 case 3: 387 *fec = FEC_3_4; 388 break; 389 case 4: 390 *fec = FEC_4_5; 391 break; 392 case 5: 393 *fec = FEC_5_6; 394 break; 395 case 6: 396 *fec = FEC_6_7; 397 break; 398 case 7: 399 *fec = FEC_7_8; 400 break; 401 default: 402 /* this can happen when there's no lock */ 403 *fec = FEC_NONE; 404 } 405 406 return 0; 407} 408 409/* Approximation of closest integer of log2(a/b). It actually gives the 410 lowest integer i such that 2^i >= round(a/b) */ 411static u32 cx24123_int_log2(u32 a, u32 b) 412{ 413 u32 exp, nearest = 0; 414 u32 div = a / b; 415 if(a % b >= b / 2) ++div; 416 if(div < (1 << 31)) 417 { 418 for(exp = 1; div > exp; nearest++) 419 exp += exp; 420 } 421 return nearest; 422} 423 424static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate) 425{ 426 u32 tmp, sample_rate, ratio, sample_gain; 427 u8 pll_mult; 428 429 /* check if symbol rate is within limits */ 430 if ((srate > state->frontend.ops.info.symbol_rate_max) || 431 (srate < state->frontend.ops.info.symbol_rate_min)) 432 return -EOPNOTSUPP;; 433 434 /* choose the sampling rate high enough for the required operation, 435 while optimizing the power consumed by the demodulator */ 436 if (srate < (XTAL*2)/2) 437 pll_mult = 2; 438 else if (srate < (XTAL*3)/2) 439 pll_mult = 3; 440 else if (srate < (XTAL*4)/2) 441 pll_mult = 4; 442 else if (srate < (XTAL*5)/2) 443 pll_mult = 5; 444 else if (srate < (XTAL*6)/2) 445 pll_mult = 6; 446 else if (srate < (XTAL*7)/2) 447 pll_mult = 7; 448 else if (srate < (XTAL*8)/2) 449 pll_mult = 8; 450 else 451 pll_mult = 9; 452 453 454 sample_rate = pll_mult * XTAL; 455 456 /* 457 SYSSymbolRate[21:0] = (srate << 23) / sample_rate 458 459 We have to use 32 bit unsigned arithmetic without precision loss. 460 The maximum srate is 45000000 or 0x02AEA540. This number has 461 only 6 clear bits on top, hence we can shift it left only 6 bits 462 at a time. Borrowed from cx24110.c 463 */ 464 465 tmp = srate << 6; 466 ratio = tmp / sample_rate; 467 468 tmp = (tmp % sample_rate) << 6; 469 ratio = (ratio << 6) + (tmp / sample_rate); 470 471 tmp = (tmp % sample_rate) << 6; 472 ratio = (ratio << 6) + (tmp / sample_rate); 473 474 tmp = (tmp % sample_rate) << 5; 475 ratio = (ratio << 5) + (tmp / sample_rate); 476 477 478 cx24123_writereg(state, 0x01, pll_mult * 6); 479 480 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f ); 481 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff ); 482 cx24123_writereg(state, 0x0a, (ratio ) & 0xff ); 483 484 /* also set the demodulator sample gain */ 485 sample_gain = cx24123_int_log2(sample_rate, srate); 486 tmp = cx24123_readreg(state, 0x0c) & ~0xe0; 487 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); 488 489 dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain); 490 491 return 0; 492} 493 494/* 495 * Based on the required frequency and symbolrate, the tuner AGC has to be configured 496 * and the correct band selected. Calculate those values 497 */ 498static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 499{ 500 struct cx24123_state *state = fe->demodulator_priv; 501 u32 ndiv = 0, adiv = 0, vco_div = 0; 502 int i = 0; 503 int pump = 2; 504 int band = 0; 505 int num_bands = ARRAY_SIZE(cx24123_bandselect_vals); 506 507 /* Defaults for low freq, low rate */ 508 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; 509 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; 510 state->bandselectarg = cx24123_bandselect_vals[0].progdata; 511 vco_div = cx24123_bandselect_vals[0].VCOdivider; 512 513 /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */ 514 for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) 515 { 516 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) && 517 (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) { 518 state->VCAarg = cx24123_AGC_vals[i].VCAprogdata; 519 state->VGAarg = cx24123_AGC_vals[i].VGAprogdata; 520 state->FILTune = cx24123_AGC_vals[i].FILTune; 521 } 522 } 523 524 /* determine the band to use */ 525 if(force_band < 1 || force_band > num_bands) 526 { 527 for (i = 0; i < num_bands; i++) 528 { 529 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) && 530 (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) 531 band = i; 532 } 533 } 534 else 535 band = force_band - 1; 536 537 state->bandselectarg = cx24123_bandselect_vals[band].progdata; 538 vco_div = cx24123_bandselect_vals[band].VCOdivider; 539 540 /* determine the charge pump current */ 541 if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 ) 542 pump = 0x01; 543 else 544 pump = 0x02; 545 546 /* Determine the N/A dividers for the requested lband freq (in kHz). */ 547 /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */ 548 ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff; 549 adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f; 550 551 if (adiv == 0 && ndiv > 0) 552 ndiv--; 553 554 /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */ 555 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv; 556 557 return 0; 558} 559 560/* 561 * Tuner data is 21 bits long, must be left-aligned in data. 562 * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip. 563 */ 564static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data) 565{ 566 struct cx24123_state *state = fe->demodulator_priv; 567 unsigned long timeout; 568 569 dprintk("%s: pll writereg called, data=0x%08x\n",__FUNCTION__,data); 570 571 /* align the 21 bytes into to bit23 boundary */ 572 data = data << 3; 573 574 /* Reset the demod pll word length to 0x15 bits */ 575 cx24123_writereg(state, 0x21, 0x15); 576 577 /* write the msb 8 bits, wait for the send to be completed */ 578 timeout = jiffies + msecs_to_jiffies(40); 579 cx24123_writereg(state, 0x22, (data >> 16) & 0xff); 580 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { 581 if (time_after(jiffies, timeout)) { 582 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); 583 return -EREMOTEIO; 584 } 585 msleep(10); 586 } 587 588 /* send another 8 bytes, wait for the send to be completed */ 589 timeout = jiffies + msecs_to_jiffies(40); 590 cx24123_writereg(state, 0x22, (data>>8) & 0xff ); 591 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { 592 if (time_after(jiffies, timeout)) { 593 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); 594 return -EREMOTEIO; 595 } 596 msleep(10); 597 } 598 599 /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */ 600 timeout = jiffies + msecs_to_jiffies(40); 601 cx24123_writereg(state, 0x22, (data) & 0xff ); 602 while ((cx24123_readreg(state, 0x20) & 0x80)) { 603 if (time_after(jiffies, timeout)) { 604 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); 605 return -EREMOTEIO; 606 } 607 msleep(10); 608 } 609 610 /* Trigger the demod to configure the tuner */ 611 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); 612 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); 613 614 return 0; 615} 616 617static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 618{ 619 struct cx24123_state *state = fe->demodulator_priv; 620 u8 val; 621 622 dprintk("frequency=%i\n", p->frequency); 623 624 if (cx24123_pll_calculate(fe, p) != 0) { 625 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__); 626 return -EINVAL; 627 } 628 629 /* Write the new VCO/VGA */ 630 cx24123_pll_writereg(fe, p, state->VCAarg); 631 cx24123_pll_writereg(fe, p, state->VGAarg); 632 633 /* Write the new bandselect and pll args */ 634 cx24123_pll_writereg(fe, p, state->bandselectarg); 635 cx24123_pll_writereg(fe, p, state->pllarg); 636 637 /* set the FILTUNE voltage */ 638 val = cx24123_readreg(state, 0x28) & ~0x3; 639 cx24123_writereg(state, 0x27, state->FILTune >> 2); 640 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); 641 642 dprintk("%s: pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg, 643 state->bandselectarg,state->pllarg); 644 645 return 0; 646} 647 648static int cx24123_initfe(struct dvb_frontend* fe) 649{ 650 struct cx24123_state *state = fe->demodulator_priv; 651 int i; 652 653 dprintk("%s: init frontend\n",__FUNCTION__); 654 655 /* Configure the demod to a good set of defaults */ 656 for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++) 657 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data); 658 659 /* Set the LNB polarity */ 660 if(state->config->lnb_polarity) 661 cx24123_writereg(state, 0x32, cx24123_readreg(state, 0x32) | 0x02); 662 663 return 0; 664} 665 666static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage) 667{ 668 struct cx24123_state *state = fe->demodulator_priv; 669 u8 val; 670 671 val = cx24123_readreg(state, 0x29) & ~0x40; 672 673 switch (voltage) { 674 case SEC_VOLTAGE_13: 675 dprintk("%s: setting voltage 13V\n", __FUNCTION__); 676 return cx24123_writereg(state, 0x29, val & 0x7f); 677 case SEC_VOLTAGE_18: 678 dprintk("%s: setting voltage 18V\n", __FUNCTION__); 679 return cx24123_writereg(state, 0x29, val | 0x80); 680 case SEC_VOLTAGE_OFF: 681 /* already handled in cx88-dvb */ 682 return 0; 683 default: 684 return -EINVAL; 685 }; 686 687 return 0; 688} 689 690/* wait for diseqc queue to become ready (or timeout) */ 691static void cx24123_wait_for_diseqc(struct cx24123_state *state) 692{ 693 unsigned long timeout = jiffies + msecs_to_jiffies(200); 694 while (!(cx24123_readreg(state, 0x29) & 0x40)) { 695 if(time_after(jiffies, timeout)) { 696 printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__); 697 break; 698 } 699 msleep(10); 700 } 701} 702 703static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd) 704{ 705 struct cx24123_state *state = fe->demodulator_priv; 706 int i, val, tone; 707 708 dprintk("%s:\n",__FUNCTION__); 709 710 /* stop continuous tone if enabled */ 711 tone = cx24123_readreg(state, 0x29); 712 if (tone & 0x10) 713 cx24123_writereg(state, 0x29, tone & ~0x50); 714 715 /* wait for diseqc queue ready */ 716 cx24123_wait_for_diseqc(state); 717 718 /* select tone mode */ 719 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); 720 721 for (i = 0; i < cmd->msg_len; i++) 722 cx24123_writereg(state, 0x2C + i, cmd->msg[i]); 723 724 val = cx24123_readreg(state, 0x29); 725 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3)); 726 727 /* wait for diseqc message to finish sending */ 728 cx24123_wait_for_diseqc(state); 729 730 /* restart continuous tone if enabled */ 731 if (tone & 0x10) { 732 cx24123_writereg(state, 0x29, tone & ~0x40); 733 } 734 735 return 0; 736} 737 738static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) 739{ 740 struct cx24123_state *state = fe->demodulator_priv; 741 int val, tone; 742 743 dprintk("%s:\n", __FUNCTION__); 744 745 /* stop continuous tone if enabled */ 746 tone = cx24123_readreg(state, 0x29); 747 if (tone & 0x10) 748 cx24123_writereg(state, 0x29, tone & ~0x50); 749 750 /* wait for diseqc queue ready */ 751 cx24123_wait_for_diseqc(state); 752 753 /* select tone mode */ 754 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); 755 msleep(30); 756 val = cx24123_readreg(state, 0x29); 757 if (burst == SEC_MINI_A) 758 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); 759 else if (burst == SEC_MINI_B) 760 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); 761 else 762 return -EINVAL; 763 764 cx24123_wait_for_diseqc(state); 765 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); 766 767 /* restart continuous tone if enabled */ 768 if (tone & 0x10) { 769 cx24123_writereg(state, 0x29, tone & ~0x40); 770 } 771 return 0; 772} 773 774static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status) 775{ 776 struct cx24123_state *state = fe->demodulator_priv; 777 778 int sync = cx24123_readreg(state, 0x14); 779 int lock = cx24123_readreg(state, 0x20); 780 781 *status = 0; 782 if (lock & 0x01) 783 *status |= FE_HAS_SIGNAL; 784 if (sync & 0x02) 785 *status |= FE_HAS_CARRIER; /* Phase locked */ 786 if (sync & 0x04) 787 *status |= FE_HAS_VITERBI; 788 789 /* Reed-Solomon Status */ 790 if (sync & 0x08) 791 *status |= FE_HAS_SYNC; 792 if (sync & 0x80) 793 *status |= FE_HAS_LOCK; /*Full Sync */ 794 795 return 0; 796} 797 798/* 799 * Configured to return the measurement of errors in blocks, because no UCBLOCKS value 800 * is available, so this value doubles up to satisfy both measurements 801 */ 802static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber) 803{ 804 struct cx24123_state *state = fe->demodulator_priv; 805 806 /* The true bit error rate is this value divided by 807 the window size (set as 256 * 255) */ 808 *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | 809 (cx24123_readreg(state, 0x1d) << 8 | 810 cx24123_readreg(state, 0x1e)); 811 812 dprintk("%s: BER = %d\n",__FUNCTION__,*ber); 813 814 return 0; 815} 816 817static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength) 818{ 819 struct cx24123_state *state = fe->demodulator_priv; 820 821 *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */ 822 823 dprintk("%s: Signal strength = %d\n",__FUNCTION__,*signal_strength); 824 825 return 0; 826} 827 828static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr) 829{ 830 struct cx24123_state *state = fe->demodulator_priv; 831 832 /* Inverted raw Es/N0 count, totally bogus but better than the 833 BER threshold. */ 834 *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | 835 (u16)cx24123_readreg(state, 0x19)); 836 837 dprintk("%s: read S/N index = %d\n",__FUNCTION__,*snr); 838 839 return 0; 840} 841 842static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 843{ 844 struct cx24123_state *state = fe->demodulator_priv; 845 846 dprintk("%s: set_frontend\n",__FUNCTION__); 847 848 if (state->config->set_ts_params) 849 state->config->set_ts_params(fe, 0); 850 851 state->currentfreq=p->frequency; 852 state->currentsymbolrate = p->u.qpsk.symbol_rate; 853 854 cx24123_set_inversion(state, p->inversion); 855 cx24123_set_fec(state, p->u.qpsk.fec_inner); 856 cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate); 857 cx24123_pll_tune(fe, p); 858 859 /* Enable automatic aquisition and reset cycle */ 860 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); 861 cx24123_writereg(state, 0x00, 0x10); 862 cx24123_writereg(state, 0x00, 0); 863 864 return 0; 865} 866 867static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 868{ 869 struct cx24123_state *state = fe->demodulator_priv; 870 871 dprintk("%s: get_frontend\n",__FUNCTION__); 872 873 if (cx24123_get_inversion(state, &p->inversion) != 0) { 874 printk("%s: Failed to get inversion status\n",__FUNCTION__); 875 return -EREMOTEIO; 876 } 877 if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) { 878 printk("%s: Failed to get fec status\n",__FUNCTION__); 879 return -EREMOTEIO; 880 } 881 p->frequency = state->currentfreq; 882 p->u.qpsk.symbol_rate = state->currentsymbolrate; 883 884 return 0; 885} 886 887static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) 888{ 889 struct cx24123_state *state = fe->demodulator_priv; 890 u8 val; 891 892 /* wait for diseqc queue ready */ 893 cx24123_wait_for_diseqc(state); 894 895 val = cx24123_readreg(state, 0x29) & ~0x40; 896 897 switch (tone) { 898 case SEC_TONE_ON: 899 dprintk("%s: setting tone on\n", __FUNCTION__); 900 return cx24123_writereg(state, 0x29, val | 0x10); 901 case SEC_TONE_OFF: 902 dprintk("%s: setting tone off\n",__FUNCTION__); 903 return cx24123_writereg(state, 0x29, val & 0xef); 904 default: 905 printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone); 906 return -EINVAL; 907 } 908 909 return 0; 910} 911 912static int cx24123_tune(struct dvb_frontend* fe, 913 struct dvb_frontend_parameters* params, 914 unsigned int mode_flags, 915 int *delay, 916 fe_status_t *status) 917{ 918 int retval = 0; 919 920 if (params != NULL) 921 retval = cx24123_set_frontend(fe, params); 922 923 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 924 cx24123_read_status(fe, status); 925 *delay = HZ/10; 926 927 return retval; 928} 929 930static int cx24123_get_algo(struct dvb_frontend *fe) 931{ 932 return 1; //FE_ALGO_HW 933} 934 935static void cx24123_release(struct dvb_frontend* fe) 936{ 937 struct cx24123_state* state = fe->demodulator_priv; 938 dprintk("%s\n",__FUNCTION__); 939 kfree(state); 940} 941 942static struct dvb_frontend_ops cx24123_ops; 943 944struct dvb_frontend* cx24123_attach(const struct cx24123_config* config, 945 struct i2c_adapter* i2c) 946{ 947 struct cx24123_state* state = NULL; 948 int ret; 949 950 dprintk("%s\n",__FUNCTION__); 951 952 /* allocate memory for the internal state */ 953 state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL); 954 if (state == NULL) { 955 printk("Unable to kmalloc\n"); 956 goto error; 957 } 958 959 /* setup the state */ 960 state->config = config; 961 state->i2c = i2c; 962 state->VCAarg = 0; 963 state->VGAarg = 0; 964 state->bandselectarg = 0; 965 state->pllarg = 0; 966 state->currentfreq = 0; 967 state->currentsymbolrate = 0; 968 969 /* check if the demod is there */ 970 ret = cx24123_readreg(state, 0x00); 971 if ((ret != 0xd1) && (ret != 0xe1)) { 972 printk("Version != d1 or e1\n"); 973 goto error; 974 } 975 976 /* create dvb_frontend */ 977 memcpy(&state->frontend.ops, &cx24123_ops, sizeof(struct dvb_frontend_ops)); 978 state->frontend.demodulator_priv = state; 979 return &state->frontend; 980 981error: 982 kfree(state); 983 984 return NULL; 985} 986 987static struct dvb_frontend_ops cx24123_ops = { 988 989 .info = { 990 .name = "Conexant CX24123/CX24109", 991 .type = FE_QPSK, 992 .frequency_min = 950000, 993 .frequency_max = 2150000, 994 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 995 .frequency_tolerance = 5000, 996 .symbol_rate_min = 1000000, 997 .symbol_rate_max = 45000000, 998 .caps = FE_CAN_INVERSION_AUTO | 999 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1000 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | 1001 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1002 FE_CAN_QPSK | FE_CAN_RECOVER 1003 }, 1004 1005 .release = cx24123_release, 1006 1007 .init = cx24123_initfe, 1008 .set_frontend = cx24123_set_frontend, 1009 .get_frontend = cx24123_get_frontend, 1010 .read_status = cx24123_read_status, 1011 .read_ber = cx24123_read_ber, 1012 .read_signal_strength = cx24123_read_signal_strength, 1013 .read_snr = cx24123_read_snr, 1014 .diseqc_send_master_cmd = cx24123_send_diseqc_msg, 1015 .diseqc_send_burst = cx24123_diseqc_send_burst, 1016 .set_tone = cx24123_set_tone, 1017 .set_voltage = cx24123_set_voltage, 1018 .tune = cx24123_tune, 1019 .get_frontend_algo = cx24123_get_algo, 1020}; 1021 1022module_param(debug, int, 0644); 1023MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 1024 1025module_param(force_band, int, 0644); 1026MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off)."); 1027 1028MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware"); 1029MODULE_AUTHOR("Steven Toth"); 1030MODULE_LICENSE("GPL"); 1031 1032EXPORT_SYMBOL(cx24123_attach); 1033