1/* 2 * Copyright (c) 2006 QLogic, Inc. All rights reserved. 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34/* 35 * This file contains all of the code that is specific to the InfiniPath 36 * HT chip. 37 */ 38 39#include <linux/pci.h> 40#include <linux/delay.h> 41#include <linux/htirq.h> 42 43#include "ipath_kernel.h" 44#include "ipath_registers.h" 45 46static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64); 47 48 49/* 50 * This lists the InfiniPath registers, in the actual chip layout. 51 * This structure should never be directly accessed. 52 * 53 * The names are in InterCap form because they're taken straight from 54 * the chip specification. Since they're only used in this file, they 55 * don't pollute the rest of the source. 56*/ 57 58struct _infinipath_do_not_use_kernel_regs { 59 unsigned long long Revision; 60 unsigned long long Control; 61 unsigned long long PageAlign; 62 unsigned long long PortCnt; 63 unsigned long long DebugPortSelect; 64 unsigned long long DebugPort; 65 unsigned long long SendRegBase; 66 unsigned long long UserRegBase; 67 unsigned long long CounterRegBase; 68 unsigned long long Scratch; 69 unsigned long long ReservedMisc1; 70 unsigned long long InterruptConfig; 71 unsigned long long IntBlocked; 72 unsigned long long IntMask; 73 unsigned long long IntStatus; 74 unsigned long long IntClear; 75 unsigned long long ErrorMask; 76 unsigned long long ErrorStatus; 77 unsigned long long ErrorClear; 78 unsigned long long HwErrMask; 79 unsigned long long HwErrStatus; 80 unsigned long long HwErrClear; 81 unsigned long long HwDiagCtrl; 82 unsigned long long MDIO; 83 unsigned long long IBCStatus; 84 unsigned long long IBCCtrl; 85 unsigned long long ExtStatus; 86 unsigned long long ExtCtrl; 87 unsigned long long GPIOOut; 88 unsigned long long GPIOMask; 89 unsigned long long GPIOStatus; 90 unsigned long long GPIOClear; 91 unsigned long long RcvCtrl; 92 unsigned long long RcvBTHQP; 93 unsigned long long RcvHdrSize; 94 unsigned long long RcvHdrCnt; 95 unsigned long long RcvHdrEntSize; 96 unsigned long long RcvTIDBase; 97 unsigned long long RcvTIDCnt; 98 unsigned long long RcvEgrBase; 99 unsigned long long RcvEgrCnt; 100 unsigned long long RcvBufBase; 101 unsigned long long RcvBufSize; 102 unsigned long long RxIntMemBase; 103 unsigned long long RxIntMemSize; 104 unsigned long long RcvPartitionKey; 105 unsigned long long ReservedRcv[10]; 106 unsigned long long SendCtrl; 107 unsigned long long SendPIOBufBase; 108 unsigned long long SendPIOSize; 109 unsigned long long SendPIOBufCnt; 110 unsigned long long SendPIOAvailAddr; 111 unsigned long long TxIntMemBase; 112 unsigned long long TxIntMemSize; 113 unsigned long long ReservedSend[9]; 114 unsigned long long SendBufferError; 115 unsigned long long SendBufferErrorCONT1; 116 unsigned long long SendBufferErrorCONT2; 117 unsigned long long SendBufferErrorCONT3; 118 unsigned long long ReservedSBE[4]; 119 unsigned long long RcvHdrAddr0; 120 unsigned long long RcvHdrAddr1; 121 unsigned long long RcvHdrAddr2; 122 unsigned long long RcvHdrAddr3; 123 unsigned long long RcvHdrAddr4; 124 unsigned long long RcvHdrAddr5; 125 unsigned long long RcvHdrAddr6; 126 unsigned long long RcvHdrAddr7; 127 unsigned long long RcvHdrAddr8; 128 unsigned long long ReservedRHA[7]; 129 unsigned long long RcvHdrTailAddr0; 130 unsigned long long RcvHdrTailAddr1; 131 unsigned long long RcvHdrTailAddr2; 132 unsigned long long RcvHdrTailAddr3; 133 unsigned long long RcvHdrTailAddr4; 134 unsigned long long RcvHdrTailAddr5; 135 unsigned long long RcvHdrTailAddr6; 136 unsigned long long RcvHdrTailAddr7; 137 unsigned long long RcvHdrTailAddr8; 138 unsigned long long ReservedRHTA[7]; 139 unsigned long long Sync; /* Software only */ 140 unsigned long long Dump; /* Software only */ 141 unsigned long long SimVer; /* Software only */ 142 unsigned long long ReservedSW[5]; 143 unsigned long long SerdesConfig0; 144 unsigned long long SerdesConfig1; 145 unsigned long long SerdesStatus; 146 unsigned long long XGXSConfig; 147 unsigned long long ReservedSW2[4]; 148}; 149 150#define IPATH_KREG_OFFSET(field) (offsetof(struct \ 151 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64)) 152#define IPATH_CREG_OFFSET(field) (offsetof( \ 153 struct infinipath_counters, field) / sizeof(u64)) 154 155static const struct ipath_kregs ipath_ht_kregs = { 156 .kr_control = IPATH_KREG_OFFSET(Control), 157 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase), 158 .kr_debugport = IPATH_KREG_OFFSET(DebugPort), 159 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect), 160 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear), 161 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask), 162 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus), 163 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl), 164 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus), 165 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear), 166 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask), 167 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut), 168 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus), 169 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl), 170 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear), 171 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask), 172 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus), 173 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl), 174 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus), 175 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked), 176 .kr_intclear = IPATH_KREG_OFFSET(IntClear), 177 .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig), 178 .kr_intmask = IPATH_KREG_OFFSET(IntMask), 179 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus), 180 .kr_mdio = IPATH_KREG_OFFSET(MDIO), 181 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign), 182 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey), 183 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt), 184 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP), 185 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase), 186 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize), 187 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl), 188 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase), 189 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt), 190 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt), 191 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize), 192 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize), 193 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase), 194 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize), 195 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase), 196 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt), 197 .kr_revision = IPATH_KREG_OFFSET(Revision), 198 .kr_scratch = IPATH_KREG_OFFSET(Scratch), 199 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError), 200 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl), 201 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr), 202 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase), 203 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt), 204 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize), 205 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase), 206 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase), 207 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize), 208 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase), 209 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0), 210 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1), 211 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus), 212 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig), 213 /* 214 * These should not be used directly via ipath_write_kreg64(), 215 * use them with ipath_write_kreg64_port(), 216 */ 217 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0), 218 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0) 219}; 220 221static const struct ipath_cregs ipath_ht_cregs = { 222 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt), 223 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt), 224 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt), 225 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt), 226 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt), 227 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt), 228 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt), 229 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt), 230 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt), 231 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt), 232 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt), 233 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt), 234 /* calc from Reg_CounterRegBase + offset */ 235 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt), 236 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt), 237 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt), 238 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt), 239 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt), 240 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt), 241 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt), 242 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt), 243 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt), 244 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt), 245 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt), 246 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt), 247 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt), 248 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt), 249 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt), 250 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt), 251 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt), 252 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt), 253 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt), 254 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt), 255 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt) 256}; 257 258/* kr_intstatus, kr_intclear, kr_intmask bits */ 259#define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1) 260#define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1) 261 262/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */ 263#define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0 264#define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL 265#define INFINIPATH_HWE_HTCLNKABYTE0CRCERR 0x0000000000800000ULL 266#define INFINIPATH_HWE_HTCLNKABYTE1CRCERR 0x0000000001000000ULL 267#define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR 0x0000000002000000ULL 268#define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR 0x0000000004000000ULL 269#define INFINIPATH_HWE_HTCMISCERR4 0x0000000008000000ULL 270#define INFINIPATH_HWE_HTCMISCERR5 0x0000000010000000ULL 271#define INFINIPATH_HWE_HTCMISCERR6 0x0000000020000000ULL 272#define INFINIPATH_HWE_HTCMISCERR7 0x0000000040000000ULL 273#define INFINIPATH_HWE_HTCBUSTREQPARITYERR 0x0000000080000000ULL 274#define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL 275#define INFINIPATH_HWE_HTCBUSIREQPARITYERR 0x0000000200000000ULL 276#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL 277#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL 278#define INFINIPATH_HWE_HTBPLL_FBSLIP 0x0200000000000000ULL 279#define INFINIPATH_HWE_HTBPLL_RFSLIP 0x0400000000000000ULL 280#define INFINIPATH_HWE_HTAPLL_FBSLIP 0x0800000000000000ULL 281#define INFINIPATH_HWE_HTAPLL_RFSLIP 0x1000000000000000ULL 282#define INFINIPATH_HWE_SERDESPLLFAILED 0x2000000000000000ULL 283 284/* kr_extstatus bits */ 285#define INFINIPATH_EXTS_FREQSEL 0x2 286#define INFINIPATH_EXTS_SERDESSEL 0x4 287#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000 288#define INFINIPATH_EXTS_MEMBIST_CORRECT 0x0000000000008000 289 290 291/* TID entries (memory), HT-only */ 292#define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */ 293#define INFINIPATH_RT_VALID 0x8000000000000000ULL 294#define INFINIPATH_RT_ADDR_SHIFT 0 295#define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL 296#define INFINIPATH_RT_BUFSIZE_SHIFT 48 297 298/* 299 * masks and bits that are different in different chips, or present only 300 * in one 301 */ 302static const ipath_err_t infinipath_hwe_htcmemparityerr_mask = 303 INFINIPATH_HWE_HTCMEMPARITYERR_MASK; 304static const ipath_err_t infinipath_hwe_htcmemparityerr_shift = 305 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT; 306 307static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr = 308 INFINIPATH_HWE_HTCLNKABYTE0CRCERR; 309static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr = 310 INFINIPATH_HWE_HTCLNKABYTE1CRCERR; 311static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr = 312 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR; 313static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr = 314 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR; 315 316#define _IPATH_GPIO_SDA_NUM 1 317#define _IPATH_GPIO_SCL_NUM 0 318 319#define IPATH_GPIO_SDA \ 320 (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT)) 321#define IPATH_GPIO_SCL \ 322 (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT)) 323 324/* keep the code below somewhat more readonable; not used elsewhere */ 325#define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \ 326 infinipath_hwe_htclnkabyte1crcerr) 327#define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr | \ 328 infinipath_hwe_htclnkbbyte1crcerr) 329#define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \ 330 infinipath_hwe_htclnkbbyte0crcerr) 331#define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr | \ 332 infinipath_hwe_htclnkbbyte1crcerr) 333 334static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs, 335 char *msg, size_t msgl) 336{ 337 char bitsmsg[64]; 338 ipath_err_t crcbits = hwerrs & 339 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS); 340 /* don't check if 8bit HT */ 341 if (dd->ipath_flags & IPATH_8BIT_IN_HT0) 342 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr; 343 /* don't check if 8bit HT */ 344 if (dd->ipath_flags & IPATH_8BIT_IN_HT1) 345 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr; 346 /* 347 * we'll want to ignore link errors on link that is 348 * not in use, if any. For now, complain about both 349 */ 350 if (crcbits) { 351 u16 ctrl0, ctrl1; 352 snprintf(bitsmsg, sizeof bitsmsg, 353 "[HT%s lane %s CRC (%llx); powercycle to completely clear]", 354 !(crcbits & _IPATH_HTLINK1_CRCBITS) ? 355 "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS) 356 ? "1 (B)" : "0+1 (A+B)"), 357 !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0" 358 : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" : 359 "0+1"), (unsigned long long) crcbits); 360 strlcat(msg, bitsmsg, msgl); 361 362 /* 363 * print extra info for debugging. slave/primary 364 * config word 4, 8 (link control 0, 1) 365 */ 366 367 if (pci_read_config_word(dd->pcidev, 368 dd->ipath_ht_slave_off + 0x4, 369 &ctrl0)) 370 dev_info(&dd->pcidev->dev, "Couldn't read " 371 "linkctrl0 of slave/primary " 372 "config block\n"); 373 else if (!(ctrl0 & 1 << 6)) 374 /* not if EOC bit set */ 375 ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0, 376 ((ctrl0 >> 8) & 7) ? " CRC" : "", 377 ((ctrl0 >> 4) & 1) ? "linkfail" : 378 ""); 379 if (pci_read_config_word(dd->pcidev, 380 dd->ipath_ht_slave_off + 0x8, 381 &ctrl1)) 382 dev_info(&dd->pcidev->dev, "Couldn't read " 383 "linkctrl1 of slave/primary " 384 "config block\n"); 385 else if (!(ctrl1 & 1 << 6)) 386 /* not if EOC bit set */ 387 ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1, 388 ((ctrl1 >> 8) & 7) ? " CRC" : "", 389 ((ctrl1 >> 4) & 1) ? "linkfail" : 390 ""); 391 392 /* disable until driver reloaded */ 393 dd->ipath_hwerrmask &= ~crcbits; 394 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 395 dd->ipath_hwerrmask); 396 ipath_dbg("HT crc errs: %s\n", msg); 397 } else 398 ipath_dbg("ignoring HT crc errors 0x%llx, " 399 "not in use\n", (unsigned long long) 400 (hwerrs & (_IPATH_HTLINK0_CRCBITS | 401 _IPATH_HTLINK1_CRCBITS))); 402} 403 404/* 6110 specific hardware errors... */ 405static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = { 406 INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"), 407 INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"), 408 INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"), 409 INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"), 410 INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"), 411 INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"), 412 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"), 413 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"), 414}; 415 416#define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \ 417 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \ 418 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) 419#define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \ 420 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) 421 422static int ipath_ht_txe_recover(struct ipath_devdata *); 423 424/** 425 * ipath_ht_handle_hwerrors - display hardware errors. 426 * @dd: the infinipath device 427 * @msg: the output buffer 428 * @msgl: the size of the output buffer 429 * 430 * Use same msg buffer as regular errors to avoid excessive stack 431 * use. Most hardware errors are catastrophic, but for right now, 432 * we'll print them and continue. We reuse the same message buffer as 433 * ipath_handle_errors() to avoid excessive stack usage. 434 */ 435static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg, 436 size_t msgl) 437{ 438 ipath_err_t hwerrs; 439 u32 bits, ctrl; 440 int isfatal = 0; 441 char bitsmsg[64]; 442 443 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus); 444 445 if (!hwerrs) { 446 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n"); 447 /* 448 * better than printing cofusing messages 449 * This seems to be related to clearing the crc error, or 450 * the pll error during init. 451 */ 452 goto bail; 453 } else if (hwerrs == -1LL) { 454 ipath_dev_err(dd, "Read of hardware error status failed " 455 "(all bits set); ignoring\n"); 456 goto bail; 457 } 458 ipath_stats.sps_hwerrs++; 459 460 /* Always clear the error status register, except MEMBISTFAIL, 461 * regardless of whether we continue or stop using the chip. 462 * We want that set so we know it failed, even across driver reload. 463 * We'll still ignore it in the hwerrmask. We do this partly for 464 * diagnostics, but also for support */ 465 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 466 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED); 467 468 hwerrs &= dd->ipath_hwerrmask; 469 470 /* 471 * make sure we get this much out, unless told to be quiet, 472 * it's a parity error we may recover from, 473 * or it's occurred within the last 5 seconds 474 */ 475 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY | 476 RXE_EAGER_PARITY)) || 477 (ipath_debug & __IPATH_VERBDBG)) 478 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx " 479 "(cleared)\n", (unsigned long long) hwerrs); 480 dd->ipath_lasthwerror |= hwerrs; 481 482 if (hwerrs & ~dd->ipath_hwe_bitsextant) 483 ipath_dev_err(dd, "hwerror interrupt with unknown errors " 484 "%llx set\n", (unsigned long long) 485 (hwerrs & ~dd->ipath_hwe_bitsextant)); 486 487 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control); 488 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) { 489 /* 490 * parity errors in send memory are recoverable, 491 * just cancel the send (if indicated in * sendbuffererror), 492 * count the occurrence, unfreeze (if no other handled 493 * hardware error bits are set), and continue. They can 494 * occur if a processor speculative read is done to the PIO 495 * buffer while we are sending a packet, for example. 496 */ 497 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd)) 498 hwerrs &= ~TXE_PIO_PARITY; 499 if (hwerrs & RXE_EAGER_PARITY) 500 ipath_dev_err(dd, "RXE parity, Eager TID error is not " 501 "recoverable\n"); 502 if (!hwerrs) { 503 ipath_dbg("Clearing freezemode on ignored or " 504 "recovered hardware error\n"); 505 ctrl &= ~INFINIPATH_C_FREEZEMODE; 506 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 507 ctrl); 508 } 509 } 510 511 *msg = '\0'; 512 513 /* 514 * may someday want to decode into which bits are which 515 * functional area for parity errors, etc. 516 */ 517 if (hwerrs & (infinipath_hwe_htcmemparityerr_mask 518 << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) { 519 bits = (u32) ((hwerrs >> 520 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) & 521 INFINIPATH_HWE_HTCMEMPARITYERR_MASK); 522 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ", 523 bits); 524 strlcat(msg, bitsmsg, msgl); 525 } 526 527 ipath_format_hwerrors(hwerrs, 528 ipath_6110_hwerror_msgs, 529 sizeof(ipath_6110_hwerror_msgs) / 530 sizeof(ipath_6110_hwerror_msgs[0]), 531 msg, msgl); 532 533 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS)) 534 hwerr_crcbits(dd, hwerrs, msg, msgl); 535 536 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) { 537 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]", 538 msgl); 539 /* ignore from now on, so disable until driver reloaded */ 540 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED; 541 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 542 dd->ipath_hwerrmask); 543 } 544#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \ 545 INFINIPATH_HWE_COREPLL_RFSLIP | \ 546 INFINIPATH_HWE_HTBPLL_FBSLIP | \ 547 INFINIPATH_HWE_HTBPLL_RFSLIP | \ 548 INFINIPATH_HWE_HTAPLL_FBSLIP | \ 549 INFINIPATH_HWE_HTAPLL_RFSLIP) 550 551 if (hwerrs & _IPATH_PLL_FAIL) { 552 snprintf(bitsmsg, sizeof bitsmsg, 553 "[PLL failed (%llx), InfiniPath hardware unusable]", 554 (unsigned long long) (hwerrs & _IPATH_PLL_FAIL)); 555 strlcat(msg, bitsmsg, msgl); 556 /* ignore from now on, so disable until driver reloaded */ 557 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL); 558 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 559 dd->ipath_hwerrmask); 560 } 561 562 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) { 563 /* 564 * If it occurs, it is left masked since the eternal 565 * interface is unused 566 */ 567 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED; 568 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 569 dd->ipath_hwerrmask); 570 } 571 572 if (hwerrs) { 573 /* 574 * if any set that we aren't ignoring; only 575 * make the complaint once, in case it's stuck 576 * or recurring, and we get here multiple 577 * times. 578 * force link down, so switch knows, and 579 * LEDs are turned off 580 */ 581 if (dd->ipath_flags & IPATH_INITTED) { 582 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN); 583 ipath_setup_ht_setextled(dd, 584 INFINIPATH_IBCS_L_STATE_DOWN, 585 INFINIPATH_IBCS_LT_STATE_DISABLED); 586 ipath_dev_err(dd, "Fatal Hardware Error (freeze " 587 "mode), no longer usable, SN %.16s\n", 588 dd->ipath_serial); 589 isfatal = 1; 590 } 591 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 592 /* mark as having had error */ 593 *dd->ipath_statusp |= IPATH_STATUS_HWERROR; 594 /* 595 * mark as not usable, at a minimum until driver 596 * is reloaded, probably until reboot, since no 597 * other reset is possible. 598 */ 599 dd->ipath_flags &= ~IPATH_INITTED; 600 } 601 else 602 *msg = 0; /* recovered from all of them */ 603 if (*msg) 604 ipath_dev_err(dd, "%s hardware error\n", msg); 605 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) 606 /* 607 * for status file; if no trailing brace is copied, 608 * we'll know it was truncated. 609 */ 610 snprintf(dd->ipath_freezemsg, 611 dd->ipath_freezelen, "{%s}", msg); 612 613bail:; 614} 615 616/** 617 * ipath_ht_boardname - fill in the board name 618 * @dd: the infinipath device 619 * @name: the output buffer 620 * @namelen: the size of the output buffer 621 * 622 * fill in the board name, based on the board revision register 623 */ 624static int ipath_ht_boardname(struct ipath_devdata *dd, char *name, 625 size_t namelen) 626{ 627 char *n = NULL; 628 u8 boardrev = dd->ipath_boardrev; 629 int ret; 630 631 switch (boardrev) { 632 case 4: /* Ponderosa is one of the bringup boards */ 633 n = "Ponderosa"; 634 break; 635 case 5: 636 /* 637 * original production board; two production levels, with 638 * different serial number ranges. See ipath_ht_early_init() for 639 * case where we enable IPATH_GPIO_INTR for later serial # range. 640 */ 641 n = "InfiniPath_QHT7040"; 642 break; 643 case 6: 644 n = "OEM_Board_3"; 645 break; 646 case 7: 647 /* small form factor production board */ 648 n = "InfiniPath_QHT7140"; 649 break; 650 case 8: 651 n = "LS/X-1"; 652 break; 653 case 9: /* Comstock bringup test board */ 654 n = "Comstock"; 655 break; 656 case 10: 657 n = "OEM_Board_2"; 658 break; 659 case 11: 660 n = "InfiniPath_HT-470"; /* obsoleted */ 661 break; 662 case 12: 663 n = "OEM_Board_4"; 664 break; 665 default: /* don't know, just print the number */ 666 ipath_dev_err(dd, "Don't yet know about board " 667 "with ID %u\n", boardrev); 668 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u", 669 boardrev); 670 break; 671 } 672 if (n) 673 snprintf(name, namelen, "%s", n); 674 675 if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 || 676 dd->ipath_minrev > 3)) { 677 /* 678 * This version of the driver only supports Rev 3.2 and 3.3 679 */ 680 ipath_dev_err(dd, 681 "Unsupported InfiniPath hardware revision %u.%u!\n", 682 dd->ipath_majrev, dd->ipath_minrev); 683 ret = 1; 684 goto bail; 685 } 686 /* 687 * pkt/word counters are 32 bit, and therefore wrap fast enough 688 * that we snapshot them from a timer, and maintain 64 bit shadow 689 * copies 690 */ 691 dd->ipath_flags |= IPATH_32BITCOUNTERS; 692 if (dd->ipath_htspeed != 800) 693 ipath_dev_err(dd, 694 "Incorrectly configured for HT @ %uMHz\n", 695 dd->ipath_htspeed); 696 if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 || 697 dd->ipath_boardrev == 6) 698 dd->ipath_flags |= IPATH_GPIO_INTR; 699 else 700 dd->ipath_flags |= IPATH_POLL_RX_INTR; 701 if (dd->ipath_boardrev == 8) { /* LS/X-1 */ 702 u64 val; 703 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus); 704 if (val & INFINIPATH_EXTS_SERDESSEL) { 705 /* 706 * hardware disabled 707 * 708 * This means that the chip is hardware disabled, 709 * and will not be able to bring up the link, 710 * in any case. We special case this and abort 711 * early, to avoid later messages. We also set 712 * the DISABLED status bit 713 */ 714 ipath_dbg("Unit %u is hardware-disabled\n", 715 dd->ipath_unit); 716 *dd->ipath_statusp |= IPATH_STATUS_DISABLED; 717 /* this value is handled differently */ 718 ret = 2; 719 goto bail; 720 } 721 } 722 ret = 0; 723 724bail: 725 return ret; 726} 727 728static void ipath_check_htlink(struct ipath_devdata *dd) 729{ 730 u8 linkerr, link_off, i; 731 732 for (i = 0; i < 2; i++) { 733 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd; 734 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr)) 735 dev_info(&dd->pcidev->dev, "Couldn't read " 736 "linkerror%d of HT slave/primary block\n", 737 i); 738 else if (linkerr & 0xf0) { 739 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, " 740 "clearing\n", linkerr >> 4, i); 741 /* 742 * writing the linkerr bits that are set should 743 * clear them 744 */ 745 if (pci_write_config_byte(dd->pcidev, link_off, 746 linkerr)) 747 ipath_dbg("Failed write to clear HT " 748 "linkerror%d\n", i); 749 if (pci_read_config_byte(dd->pcidev, link_off, 750 &linkerr)) 751 dev_info(&dd->pcidev->dev, 752 "Couldn't reread linkerror%d of " 753 "HT slave/primary block\n", i); 754 else if (linkerr & 0xf0) 755 dev_info(&dd->pcidev->dev, 756 "HT linkerror%d bits 0x%x " 757 "couldn't be cleared\n", 758 i, linkerr >> 4); 759 } 760 } 761} 762 763static int ipath_setup_ht_reset(struct ipath_devdata *dd) 764{ 765 ipath_dbg("No reset possible for this InfiniPath hardware\n"); 766 return 0; 767} 768 769#define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */ 770#define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */ 771 772/* 773 * Bits 13-15 of command==0 is slave/primary block. Clear any HT CRC 774 * errors. We only bother to do this at load time, because it's OK if 775 * it happened before we were loaded (first time after boot/reset), 776 * but any time after that, it's fatal anyway. Also need to not check 777 * for for upper byte errors if we are in 8 bit mode, so figure out 778 * our width. For now, at least, also complain if it's 8 bit. 779 */ 780static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev, 781 int pos, u8 cap_type) 782{ 783 u8 linkwidth = 0, linkerr, link_a_b_off, link_off; 784 u16 linkctrl = 0; 785 int i; 786 787 dd->ipath_ht_slave_off = pos; 788 /* command word, master_host bit */ 789 /* master host || slave */ 790 if ((cap_type >> 2) & 1) 791 link_a_b_off = 4; 792 else 793 link_a_b_off = 0; 794 ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n", 795 link_a_b_off ? 1 : 0, 796 link_a_b_off ? 'B' : 'A'); 797 798 link_a_b_off += pos; 799 800 /* 801 * check both link control registers; clear both HT CRC sets if 802 * necessary. 803 */ 804 for (i = 0; i < 2; i++) { 805 link_off = pos + i * 4 + 0x4; 806 if (pci_read_config_word(pdev, link_off, &linkctrl)) 807 ipath_dev_err(dd, "Couldn't read HT link control%d " 808 "register\n", i); 809 else if (linkctrl & (0xf << 8)) { 810 ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error " 811 "bits %x\n", i, linkctrl & (0xf << 8)); 812 /* 813 * now write them back to clear the error. 814 */ 815 pci_write_config_byte(pdev, link_off, 816 linkctrl & (0xf << 8)); 817 } 818 } 819 820 /* 821 * As with HT CRC bits, same for protocol errors that might occur 822 * during boot. 823 */ 824 for (i = 0; i < 2; i++) { 825 link_off = pos + i * 4 + 0xd; 826 if (pci_read_config_byte(pdev, link_off, &linkerr)) 827 dev_info(&pdev->dev, "Couldn't read linkerror%d " 828 "of HT slave/primary block\n", i); 829 else if (linkerr & 0xf0) { 830 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, " 831 "clearing\n", linkerr >> 4, i); 832 /* 833 * writing the linkerr bits that are set will clear 834 * them 835 */ 836 if (pci_write_config_byte 837 (pdev, link_off, linkerr)) 838 ipath_dbg("Failed write to clear HT " 839 "linkerror%d\n", i); 840 if (pci_read_config_byte(pdev, link_off, &linkerr)) 841 dev_info(&pdev->dev, "Couldn't reread " 842 "linkerror%d of HT slave/primary " 843 "block\n", i); 844 else if (linkerr & 0xf0) 845 dev_info(&pdev->dev, "HT linkerror%d bits " 846 "0x%x couldn't be cleared\n", 847 i, linkerr >> 4); 848 } 849 } 850 851 /* 852 * this is just for our link to the host, not devices connected 853 * through tunnel. 854 */ 855 856 if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth)) 857 ipath_dev_err(dd, "Couldn't read HT link width " 858 "config register\n"); 859 else { 860 u32 width; 861 switch (linkwidth & 7) { 862 case 5: 863 width = 4; 864 break; 865 case 4: 866 width = 2; 867 break; 868 case 3: 869 width = 32; 870 break; 871 case 1: 872 width = 16; 873 break; 874 case 0: 875 default: /* if wrong, assume 8 bit */ 876 width = 8; 877 break; 878 } 879 880 dd->ipath_htwidth = width; 881 882 if (linkwidth != 0x11) { 883 ipath_dev_err(dd, "Not configured for 16 bit HT " 884 "(%x)\n", linkwidth); 885 if (!(linkwidth & 0xf)) { 886 ipath_dbg("Will ignore HT lane1 errors\n"); 887 dd->ipath_flags |= IPATH_8BIT_IN_HT0; 888 } 889 } 890 } 891 892 /* 893 * this is just for our link to the host, not devices connected 894 * through tunnel. 895 */ 896 if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth)) 897 ipath_dev_err(dd, "Couldn't read HT link frequency " 898 "config register\n"); 899 else { 900 u32 speed; 901 switch (linkwidth & 0xf) { 902 case 6: 903 speed = 1000; 904 break; 905 case 5: 906 speed = 800; 907 break; 908 case 4: 909 speed = 600; 910 break; 911 case 3: 912 speed = 500; 913 break; 914 case 2: 915 speed = 400; 916 break; 917 case 1: 918 speed = 300; 919 break; 920 default: 921 /* 922 * assume reserved and vendor-specific are 200... 923 */ 924 case 0: 925 speed = 200; 926 break; 927 } 928 dd->ipath_htspeed = speed; 929 } 930} 931 932static int ipath_ht_intconfig(struct ipath_devdata *dd) 933{ 934 int ret; 935 936 if (dd->ipath_intconfig) { 937 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig, 938 dd->ipath_intconfig); /* interrupt address */ 939 ret = 0; 940 } else { 941 ipath_dev_err(dd, "No interrupts enabled, couldn't setup " 942 "interrupt address\n"); 943 ret = -EINVAL; 944 } 945 946 return ret; 947} 948 949static void ipath_ht_irq_update(struct pci_dev *dev, int irq, 950 struct ht_irq_msg *msg) 951{ 952 struct ipath_devdata *dd = pci_get_drvdata(dev); 953 u64 prev_intconfig = dd->ipath_intconfig; 954 955 dd->ipath_intconfig = msg->address_lo; 956 dd->ipath_intconfig |= ((u64) msg->address_hi) << 32; 957 958 /* 959 * If the previous value of dd->ipath_intconfig is zero, we're 960 * getting configured for the first time, and must not program the 961 * intconfig register here (it will be programmed later, when the 962 * hardware is ready). Otherwise, we should. 963 */ 964 if (prev_intconfig) 965 ipath_ht_intconfig(dd); 966} 967 968/** 969 * ipath_setup_ht_config - setup the interruptconfig register 970 * @dd: the infinipath device 971 * @pdev: the PCI device 972 * 973 * setup the interruptconfig register from the HT config info. 974 * Also clear CRC errors in HT linkcontrol, if necessary. 975 * This is done only for the real hardware. It is done before 976 * chip address space is initted, so can't touch infinipath registers 977 */ 978static int ipath_setup_ht_config(struct ipath_devdata *dd, 979 struct pci_dev *pdev) 980{ 981 int pos, ret; 982 983 ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update); 984 if (ret < 0) { 985 ipath_dev_err(dd, "Couldn't create interrupt handler: " 986 "err %d\n", ret); 987 goto bail; 988 } 989 dd->ipath_irq = ret; 990 ret = 0; 991 992 /* 993 * Handle clearing CRC errors in linkctrl register if necessary. We 994 * do this early, before we ever enable errors or hardware errors, 995 * mostly to avoid causing the chip to enter freeze mode. 996 */ 997 pos = pci_find_capability(pdev, PCI_CAP_ID_HT); 998 if (!pos) { 999 ipath_dev_err(dd, "Couldn't find HyperTransport " 1000 "capability; no interrupts\n"); 1001 ret = -ENODEV; 1002 goto bail; 1003 } 1004 do { 1005 u8 cap_type; 1006 1007 /* the HT capability type byte is 3 bytes after the 1008 * capability byte. 1009 */ 1010 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) { 1011 dev_info(&pdev->dev, "Couldn't read config " 1012 "command @ %d\n", pos); 1013 continue; 1014 } 1015 if (!(cap_type & 0xE0)) 1016 slave_or_pri_blk(dd, pdev, pos, cap_type); 1017 } while ((pos = pci_find_next_capability(pdev, pos, 1018 PCI_CAP_ID_HT))); 1019 1020bail: 1021 return ret; 1022} 1023 1024/** 1025 * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff 1026 * @dd: the infinipath device 1027 * 1028 * Called during driver unload. 1029 * This is currently a nop for the HT chip, not for all chips 1030 */ 1031static void ipath_setup_ht_cleanup(struct ipath_devdata *dd) 1032{ 1033} 1034 1035/** 1036 * ipath_setup_ht_setextled - set the state of the two external LEDs 1037 * @dd: the infinipath device 1038 * @lst: the L state 1039 * @ltst: the LT state 1040 * 1041 * Set the state of the two external LEDs, to indicate physical and 1042 * logical state of IB link. For this chip (at least with recommended 1043 * board pinouts), LED1 is Green (physical state), and LED2 is Yellow 1044 * (logical state) 1045 * 1046 * Note: We try to match the Mellanox HCA LED behavior as best 1047 * we can. Green indicates physical link state is OK (something is 1048 * plugged in, and we can train). 1049 * Amber indicates the link is logically up (ACTIVE). 1050 * Mellanox further blinks the amber LED to indicate data packet 1051 * activity, but we have no hardware support for that, so it would 1052 * require waking up every 10-20 msecs and checking the counters 1053 * on the chip, and then turning the LED off if appropriate. That's 1054 * visible overhead, so not something we will do. 1055 * 1056 */ 1057static void ipath_setup_ht_setextled(struct ipath_devdata *dd, 1058 u64 lst, u64 ltst) 1059{ 1060 u64 extctl; 1061 1062 /* the diags use the LED to indicate diag info, so we leave 1063 * the external LED alone when the diags are running */ 1064 if (ipath_diag_inuse) 1065 return; 1066 1067 /* 1068 * start by setting both LED control bits to off, then turn 1069 * on the appropriate bit(s). 1070 */ 1071 if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */ 1072 /* 1073 * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF 1074 * is inverted, because it is normally used to indicate 1075 * a hardware fault at reset, if there were errors 1076 */ 1077 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON) 1078 | INFINIPATH_EXTC_LEDGBLERR_OFF; 1079 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP) 1080 extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF; 1081 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE) 1082 extctl |= INFINIPATH_EXTC_LEDGBLOK_ON; 1083 } 1084 else { 1085 extctl = dd->ipath_extctrl & 1086 ~(INFINIPATH_EXTC_LED1PRIPORT_ON | 1087 INFINIPATH_EXTC_LED2PRIPORT_ON); 1088 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP) 1089 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON; 1090 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE) 1091 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON; 1092 } 1093 dd->ipath_extctrl = extctl; 1094 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl); 1095} 1096 1097static void ipath_init_ht_variables(struct ipath_devdata *dd) 1098{ 1099 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM; 1100 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM; 1101 dd->ipath_gpio_sda = IPATH_GPIO_SDA; 1102 dd->ipath_gpio_scl = IPATH_GPIO_SCL; 1103 1104 dd->ipath_i_bitsextant = 1105 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) | 1106 (INFINIPATH_I_RCVAVAIL_MASK << 1107 INFINIPATH_I_RCVAVAIL_SHIFT) | 1108 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT | 1109 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO; 1110 1111 dd->ipath_e_bitsextant = 1112 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC | 1113 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN | 1114 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN | 1115 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR | 1116 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP | 1117 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION | 1118 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL | 1119 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN | 1120 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK | 1121 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN | 1122 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN | 1123 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT | 1124 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | 1125 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED | 1126 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET | 1127 INFINIPATH_E_HARDWARE; 1128 1129 dd->ipath_hwe_bitsextant = 1130 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK << 1131 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) | 1132 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK << 1133 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) | 1134 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK << 1135 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) | 1136 INFINIPATH_HWE_HTCLNKABYTE0CRCERR | 1137 INFINIPATH_HWE_HTCLNKABYTE1CRCERR | 1138 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR | 1139 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR | 1140 INFINIPATH_HWE_HTCMISCERR4 | 1141 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 | 1142 INFINIPATH_HWE_HTCMISCERR7 | 1143 INFINIPATH_HWE_HTCBUSTREQPARITYERR | 1144 INFINIPATH_HWE_HTCBUSTRESPPARITYERR | 1145 INFINIPATH_HWE_HTCBUSIREQPARITYERR | 1146 INFINIPATH_HWE_RXDSYNCMEMPARITYERR | 1147 INFINIPATH_HWE_MEMBISTFAILED | 1148 INFINIPATH_HWE_COREPLL_FBSLIP | 1149 INFINIPATH_HWE_COREPLL_RFSLIP | 1150 INFINIPATH_HWE_HTBPLL_FBSLIP | 1151 INFINIPATH_HWE_HTBPLL_RFSLIP | 1152 INFINIPATH_HWE_HTAPLL_FBSLIP | 1153 INFINIPATH_HWE_HTAPLL_RFSLIP | 1154 INFINIPATH_HWE_SERDESPLLFAILED | 1155 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR | 1156 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR; 1157 1158 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK; 1159 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK; 1160} 1161 1162/** 1163 * ipath_ht_init_hwerrors - enable hardware errors 1164 * @dd: the infinipath device 1165 * 1166 * now that we have finished initializing everything that might reasonably 1167 * cause a hardware error, and cleared those errors bits as they occur, 1168 * we can enable hardware errors in the mask (potentially enabling 1169 * freeze mode), and enable hardware errors as errors (along with 1170 * everything else) in errormask 1171 */ 1172static void ipath_ht_init_hwerrors(struct ipath_devdata *dd) 1173{ 1174 ipath_err_t val; 1175 u64 extsval; 1176 1177 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus); 1178 1179 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST)) 1180 ipath_dev_err(dd, "MemBIST did not complete!\n"); 1181 if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT) 1182 ipath_dbg("MemBIST corrected\n"); 1183 1184 ipath_check_htlink(dd); 1185 1186 /* barring bugs, all hwerrors become interrupts, which can */ 1187 val = -1LL; 1188 /* don't look at crc lane1 if 8 bit */ 1189 if (dd->ipath_flags & IPATH_8BIT_IN_HT0) 1190 val &= ~infinipath_hwe_htclnkabyte1crcerr; 1191 /* don't look at crc lane1 if 8 bit */ 1192 if (dd->ipath_flags & IPATH_8BIT_IN_HT1) 1193 val &= ~infinipath_hwe_htclnkbbyte1crcerr; 1194 1195 /* 1196 * disable RXDSYNCMEMPARITY because external serdes is unused, 1197 * and therefore the logic will never be used or initialized, 1198 * and uninitialized state will normally result in this error 1199 * being asserted. Similarly for the external serdess pll 1200 * lock signal. 1201 */ 1202 val &= ~(INFINIPATH_HWE_SERDESPLLFAILED | 1203 INFINIPATH_HWE_RXDSYNCMEMPARITYERR); 1204 1205 /* 1206 * Disable MISCERR4 because of an inversion in the HT core 1207 * logic checking for errors that cause this bit to be set. 1208 * The errata can also cause the protocol error bit to be set 1209 * in the HT config space linkerror register(s). 1210 */ 1211 val &= ~INFINIPATH_HWE_HTCMISCERR4; 1212 1213 /* 1214 * PLL ignored because MDIO interface has a logic problem 1215 * for reads, on Comstock and Ponderosa. BRINGUP 1216 */ 1217 if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9) 1218 val &= ~INFINIPATH_HWE_SERDESPLLFAILED; 1219 dd->ipath_hwerrmask = val; 1220} 1221 1222/** 1223 * ipath_ht_bringup_serdes - bring up the serdes 1224 * @dd: the infinipath device 1225 */ 1226static int ipath_ht_bringup_serdes(struct ipath_devdata *dd) 1227{ 1228 u64 val, config1; 1229 int ret = 0, change = 0; 1230 1231 ipath_dbg("Trying to bringup serdes\n"); 1232 1233 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) & 1234 INFINIPATH_HWE_SERDESPLLFAILED) 1235 { 1236 ipath_dbg("At start, serdes PLL failed bit set in " 1237 "hwerrstatus, clearing and continuing\n"); 1238 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 1239 INFINIPATH_HWE_SERDESPLLFAILED); 1240 } 1241 1242 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); 1243 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1); 1244 1245 ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx " 1246 "config1=%llx, sstatus=%llx xgxs %llx\n", 1247 (unsigned long long) val, (unsigned long long) config1, 1248 (unsigned long long) 1249 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus), 1250 (unsigned long long) 1251 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); 1252 1253 /* force reset on */ 1254 val |= INFINIPATH_SERDC0_RESET_PLL 1255 /* | INFINIPATH_SERDC0_RESET_MASK */ 1256 ; 1257 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); 1258 udelay(15); /* need pll reset set at least for a bit */ 1259 1260 if (val & INFINIPATH_SERDC0_RESET_PLL) { 1261 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL; 1262 /* set lane resets, and tx idle, during pll reset */ 1263 val2 |= INFINIPATH_SERDC0_RESET_MASK | 1264 INFINIPATH_SERDC0_TXIDLE; 1265 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing " 1266 "%llx)\n", (unsigned long long) val2); 1267 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, 1268 val2); 1269 /* 1270 * be sure chip saw it 1271 */ 1272 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 1273 /* 1274 * need pll reset clear at least 11 usec before lane 1275 * resets cleared; give it a few more 1276 */ 1277 udelay(15); 1278 val = val2; /* for check below */ 1279 } 1280 1281 if (val & (INFINIPATH_SERDC0_RESET_PLL | 1282 INFINIPATH_SERDC0_RESET_MASK | 1283 INFINIPATH_SERDC0_TXIDLE)) { 1284 val &= ~(INFINIPATH_SERDC0_RESET_PLL | 1285 INFINIPATH_SERDC0_RESET_MASK | 1286 INFINIPATH_SERDC0_TXIDLE); 1287 /* clear them */ 1288 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, 1289 val); 1290 } 1291 1292 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); 1293 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) & 1294 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) { 1295 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK << 1296 INFINIPATH_XGXS_MDIOADDR_SHIFT); 1297 /* 1298 * we use address 3 1299 */ 1300 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT; 1301 change = 1; 1302 } 1303 if (val & INFINIPATH_XGXS_RESET) { 1304 /* normally true after boot */ 1305 val &= ~INFINIPATH_XGXS_RESET; 1306 change = 1; 1307 } 1308 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) & 1309 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) { 1310 /* need to compensate for Tx inversion in partner */ 1311 val &= ~(INFINIPATH_XGXS_RX_POL_MASK << 1312 INFINIPATH_XGXS_RX_POL_SHIFT); 1313 val |= dd->ipath_rx_pol_inv << 1314 INFINIPATH_XGXS_RX_POL_SHIFT; 1315 change = 1; 1316 } 1317 if (change) 1318 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val); 1319 1320 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); 1321 1322 /* clear current and de-emphasis bits */ 1323 config1 &= ~0x0ffffffff00ULL; 1324 /* set current to 20ma */ 1325 config1 |= 0x00000000000ULL; 1326 /* set de-emphasis to -5.68dB */ 1327 config1 |= 0x0cccc000000ULL; 1328 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1); 1329 1330 ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx " 1331 "config1=%llx, sstatus=%llx xgxs %llx\n", 1332 (unsigned long long) val, (unsigned long long) config1, 1333 (unsigned long long) 1334 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus), 1335 (unsigned long long) 1336 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); 1337 1338 if (!ipath_waitfor_mdio_cmdready(dd)) { 1339 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio, 1340 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31, 1341 IPATH_MDIO_CTRL_XGXS_REG_8, 1342 0)); 1343 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio, 1344 IPATH_MDIO_DATAVALID, &val)) 1345 ipath_dbg("Never got MDIO data for XGXS status " 1346 "read\n"); 1347 else 1348 ipath_cdbg(VERBOSE, "MDIO Read reg8, " 1349 "'bank' 31 %x\n", (u32) val); 1350 } else 1351 ipath_dbg("Never got MDIO cmdready for XGXS status read\n"); 1352 1353 return ret; /* for now, say we always succeeded */ 1354} 1355 1356/** 1357 * ipath_ht_quiet_serdes - set serdes to txidle 1358 * @dd: the infinipath device 1359 * driver is being unloaded 1360 */ 1361static void ipath_ht_quiet_serdes(struct ipath_devdata *dd) 1362{ 1363 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); 1364 1365 val |= INFINIPATH_SERDC0_TXIDLE; 1366 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n", 1367 (unsigned long long) val); 1368 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); 1369} 1370 1371/** 1372 * ipath_pe_put_tid - write a TID in chip 1373 * @dd: the infinipath device 1374 * @tidptr: pointer to the expected TID (in chip) to udpate 1375 * @tidtype: 0 for eager, 1 for expected 1376 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing 1377 * 1378 * This exists as a separate routine to allow for special locking etc. 1379 * It's used for both the full cleanup on exit, as well as the normal 1380 * setup and teardown. 1381 */ 1382static void ipath_ht_put_tid(struct ipath_devdata *dd, 1383 u64 __iomem *tidptr, u32 type, 1384 unsigned long pa) 1385{ 1386 if (!dd->ipath_kregbase) 1387 return; 1388 1389 if (pa != dd->ipath_tidinvalid) { 1390 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) { 1391 dev_info(&dd->pcidev->dev, 1392 "physaddr %lx has more than " 1393 "40 bits, using only 40!!!\n", pa); 1394 pa &= INFINIPATH_RT_ADDR_MASK; 1395 } 1396 if (type == 0) 1397 pa |= dd->ipath_tidtemplate; 1398 else { 1399 /* in words (fixed, full page). */ 1400 u64 lenvalid = PAGE_SIZE >> 2; 1401 lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT; 1402 pa |= lenvalid | INFINIPATH_RT_VALID; 1403 } 1404 } 1405 writeq(pa, tidptr); 1406} 1407 1408 1409/** 1410 * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager 1411 * @dd: the infinipath device 1412 * @port: the port 1413 * 1414 * Used from ipath_close(), and at chip initialization. 1415 */ 1416static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port) 1417{ 1418 u64 __iomem *tidbase; 1419 int i; 1420 1421 if (!dd->ipath_kregbase) 1422 return; 1423 1424 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port); 1425 1426 /* 1427 * need to invalidate all of the expected TID entries for this 1428 * port, so we don't have valid entries that might somehow get 1429 * used (early in next use of this port, or through some bug) 1430 */ 1431 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) + 1432 dd->ipath_rcvtidbase + 1433 port * dd->ipath_rcvtidcnt * 1434 sizeof(*tidbase)); 1435 for (i = 0; i < dd->ipath_rcvtidcnt; i++) 1436 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid); 1437 1438 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) + 1439 dd->ipath_rcvegrbase + 1440 port * dd->ipath_rcvegrcnt * 1441 sizeof(*tidbase)); 1442 1443 for (i = 0; i < dd->ipath_rcvegrcnt; i++) 1444 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid); 1445} 1446 1447/** 1448 * ipath_ht_tidtemplate - setup constants for TID updates 1449 * @dd: the infinipath device 1450 * 1451 * We setup stuff that we use a lot, to avoid calculating each time 1452 */ 1453static void ipath_ht_tidtemplate(struct ipath_devdata *dd) 1454{ 1455 dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2; 1456 dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT; 1457 dd->ipath_tidtemplate |= INFINIPATH_RT_VALID; 1458 1459 dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) << 1460 INFINIPATH_RT_BUFSIZE_SHIFT; 1461} 1462 1463static int ipath_ht_early_init(struct ipath_devdata *dd) 1464{ 1465 u32 __iomem *piobuf; 1466 u32 pioincr, val32; 1467 int i; 1468 1469 /* 1470 * one cache line; long IB headers will spill over into received 1471 * buffer 1472 */ 1473 dd->ipath_rcvhdrentsize = 16; 1474 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE; 1475 1476 /* 1477 * For HT, we allocate a somewhat overly large eager buffer, 1478 * such that we can guarantee that we can receive the largest 1479 * packet that we can send out. To truly support a 4KB MTU, 1480 * we need to bump this to a large value. To date, other than 1481 * testing, we have never encountered an HCA that can really 1482 * send 4KB MTU packets, so we do not handle that (we'll get 1483 * errors interrupts if we ever see one). 1484 */ 1485 dd->ipath_rcvegrbufsize = dd->ipath_piosize2k; 1486 1487 /* 1488 * the min() check here is currently a nop, but it may not 1489 * always be, depending on just how we do ipath_rcvegrbufsize 1490 */ 1491 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k, 1492 dd->ipath_rcvegrbufsize); 1493 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen; 1494 ipath_ht_tidtemplate(dd); 1495 1496 /* 1497 * zero all the TID entries at startup. We do this for sanity, 1498 * in case of a previous driver crash of some kind, and also 1499 * because the chip powers up with these memories in an unknown 1500 * state. Use portcnt, not cfgports, since this is for the 1501 * full chip, not for current (possibly different) configuration 1502 * value. 1503 * Chip Errata bug 6447 1504 */ 1505 for (val32 = 0; val32 < dd->ipath_portcnt; val32++) 1506 ipath_ht_clear_tids(dd, val32); 1507 1508 /* 1509 * write the pbc of each buffer, to be sure it's initialized, then 1510 * cancel all the buffers, and also abort any packets that might 1511 * have been in flight for some reason (the latter is for driver 1512 * unload/reload, but isn't a bad idea at first init). PIO send 1513 * isn't enabled at this point, so there is no danger of sending 1514 * these out on the wire. 1515 * Chip Errata bug 6610 1516 */ 1517 piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) + 1518 dd->ipath_piobufbase); 1519 pioincr = dd->ipath_palign / sizeof(*piobuf); 1520 for (i = 0; i < dd->ipath_piobcnt2k; i++) { 1521 /* 1522 * reasonable word count, just to init pbc 1523 */ 1524 writel(16, piobuf); 1525 piobuf += pioincr; 1526 } 1527 /* 1528 * self-clearing 1529 */ 1530 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 1531 INFINIPATH_S_ABORT); 1532 1533 ipath_get_eeprom_info(dd); 1534 if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' && 1535 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') { 1536 /* 1537 * Later production QHT7040 has same changes as QHT7140, so 1538 * can use GPIO interrupts. They have serial #'s starting 1539 * with 128, rather than 112. 1540 */ 1541 dd->ipath_flags |= IPATH_GPIO_INTR; 1542 dd->ipath_flags &= ~IPATH_POLL_RX_INTR; 1543 } 1544 return 0; 1545} 1546 1547 1548static int ipath_ht_txe_recover(struct ipath_devdata *dd) 1549{ 1550 int cnt = ++ipath_stats.sps_txeparity; 1551 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) { 1552 if (cnt == IPATH_MAX_PARITY_ATTEMPTS) 1553 ipath_dev_err(dd, 1554 "Too many attempts to recover from " 1555 "TXE parity, giving up\n"); 1556 return 0; 1557 } 1558 dev_info(&dd->pcidev->dev, 1559 "Recovering from TXE PIO parity error\n"); 1560 ipath_disarm_senderrbufs(dd, 1); 1561 return 1; 1562} 1563 1564 1565/** 1566 * ipath_init_ht_get_base_info - set chip-specific flags for user code 1567 * @dd: the infinipath device 1568 * @kbase: ipath_base_info pointer 1569 * 1570 * We set the PCIE flag because the lower bandwidth on PCIe vs 1571 * HyperTransport can affect some user packet algorithms. 1572 */ 1573static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase) 1574{ 1575 struct ipath_base_info *kinfo = kbase; 1576 1577 kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT | 1578 IPATH_RUNTIME_RCVHDR_COPY; 1579 1580 return 0; 1581} 1582 1583static void ipath_ht_free_irq(struct ipath_devdata *dd) 1584{ 1585 free_irq(dd->ipath_irq, dd); 1586 ht_destroy_irq(dd->ipath_irq); 1587 dd->ipath_irq = 0; 1588 dd->ipath_intconfig = 0; 1589} 1590 1591/** 1592 * ipath_init_iba6110_funcs - set up the chip-specific function pointers 1593 * @dd: the infinipath device 1594 * 1595 * This is global, and is called directly at init to set up the 1596 * chip-specific function pointers for later use. 1597 */ 1598void ipath_init_iba6110_funcs(struct ipath_devdata *dd) 1599{ 1600 dd->ipath_f_intrsetup = ipath_ht_intconfig; 1601 dd->ipath_f_bus = ipath_setup_ht_config; 1602 dd->ipath_f_reset = ipath_setup_ht_reset; 1603 dd->ipath_f_get_boardname = ipath_ht_boardname; 1604 dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors; 1605 dd->ipath_f_early_init = ipath_ht_early_init; 1606 dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors; 1607 dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes; 1608 dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes; 1609 dd->ipath_f_clear_tids = ipath_ht_clear_tids; 1610 dd->ipath_f_put_tid = ipath_ht_put_tid; 1611 dd->ipath_f_cleanup = ipath_setup_ht_cleanup; 1612 dd->ipath_f_setextled = ipath_setup_ht_setextled; 1613 dd->ipath_f_get_base_info = ipath_ht_get_base_info; 1614 dd->ipath_f_free_irq = ipath_ht_free_irq; 1615 1616 /* 1617 * initialize chip-specific variables 1618 */ 1619 dd->ipath_f_tidtemplate = ipath_ht_tidtemplate; 1620 1621 /* 1622 * setup the register offsets, since they are different for each 1623 * chip 1624 */ 1625 dd->ipath_kregs = &ipath_ht_kregs; 1626 dd->ipath_cregs = &ipath_ht_cregs; 1627 1628 /* 1629 * do very early init that is needed before ipath_f_bus is 1630 * called 1631 */ 1632 ipath_init_ht_variables(dd); 1633} 1634