1/* 2 * (C) Copyright 2003-2004 3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk. 4 5 * This is a combined i2c adapter and algorithm driver for the 6 * MPC107/Tsi107 PowerPC northbridge and processors that include 7 * the same I2C unit (8240, 8245, 85xx). 8 * 9 * Release 0.8 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/sched.h> 19#include <linux/init.h> 20#include <linux/platform_device.h> 21 22#include <asm/io.h> 23#include <linux/fsl_devices.h> 24#include <linux/i2c.h> 25#include <linux/interrupt.h> 26#include <linux/delay.h> 27 28#define MPC_I2C_ADDR 0x00 29#define MPC_I2C_FDR 0x04 30#define MPC_I2C_CR 0x08 31#define MPC_I2C_SR 0x0c 32#define MPC_I2C_DR 0x10 33#define MPC_I2C_DFSRR 0x14 34#define MPC_I2C_REGION 0x20 35 36#define CCR_MEN 0x80 37#define CCR_MIEN 0x40 38#define CCR_MSTA 0x20 39#define CCR_MTX 0x10 40#define CCR_TXAK 0x08 41#define CCR_RSTA 0x04 42 43#define CSR_MCF 0x80 44#define CSR_MAAS 0x40 45#define CSR_MBB 0x20 46#define CSR_MAL 0x10 47#define CSR_SRW 0x04 48#define CSR_MIF 0x02 49#define CSR_RXAK 0x01 50 51struct mpc_i2c { 52 void __iomem *base; 53 u32 interrupt; 54 wait_queue_head_t queue; 55 struct i2c_adapter adap; 56 int irq; 57 u32 flags; 58}; 59 60static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x) 61{ 62 writeb(x, i2c->base + MPC_I2C_CR); 63} 64 65static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) 66{ 67 struct mpc_i2c *i2c = dev_id; 68 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) { 69 /* Read again to allow register to stabilise */ 70 i2c->interrupt = readb(i2c->base + MPC_I2C_SR); 71 writeb(0, i2c->base + MPC_I2C_SR); 72 wake_up_interruptible(&i2c->queue); 73 } 74 return IRQ_HANDLED; 75} 76 77static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) 78{ 79 unsigned long orig_jiffies = jiffies; 80 u32 x; 81 int result = 0; 82 83 if (i2c->irq == 0) 84 { 85 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) { 86 schedule(); 87 if (time_after(jiffies, orig_jiffies + timeout)) { 88 pr_debug("I2C: timeout\n"); 89 result = -EIO; 90 break; 91 } 92 } 93 x = readb(i2c->base + MPC_I2C_SR); 94 writeb(0, i2c->base + MPC_I2C_SR); 95 } else { 96 /* Interrupt mode */ 97 result = wait_event_interruptible_timeout(i2c->queue, 98 (i2c->interrupt & CSR_MIF), timeout * HZ); 99 100 if (unlikely(result < 0)) 101 pr_debug("I2C: wait interrupted\n"); 102 else if (unlikely(!(i2c->interrupt & CSR_MIF))) { 103 pr_debug("I2C: wait timeout\n"); 104 result = -ETIMEDOUT; 105 } 106 107 x = i2c->interrupt; 108 i2c->interrupt = 0; 109 } 110 111 if (result < 0) 112 return result; 113 114 if (!(x & CSR_MCF)) { 115 pr_debug("I2C: unfinished\n"); 116 return -EIO; 117 } 118 119 if (x & CSR_MAL) { 120 pr_debug("I2C: MAL\n"); 121 return -EIO; 122 } 123 124 if (writing && (x & CSR_RXAK)) { 125 pr_debug("I2C: No RXAK\n"); 126 /* generate stop */ 127 writeccr(i2c, CCR_MEN); 128 return -EIO; 129 } 130 return 0; 131} 132 133static void mpc_i2c_setclock(struct mpc_i2c *i2c) 134{ 135 /* Set clock and filters */ 136 if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) { 137 writeb(0x31, i2c->base + MPC_I2C_FDR); 138 writeb(0x10, i2c->base + MPC_I2C_DFSRR); 139 } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200) 140 writeb(0x3f, i2c->base + MPC_I2C_FDR); 141 else 142 writel(0x1031, i2c->base + MPC_I2C_FDR); 143} 144 145static void mpc_i2c_start(struct mpc_i2c *i2c) 146{ 147 /* Clear arbitration */ 148 writeb(0, i2c->base + MPC_I2C_SR); 149 /* Start with MEN */ 150 writeccr(i2c, CCR_MEN); 151} 152 153static void mpc_i2c_stop(struct mpc_i2c *i2c) 154{ 155 writeccr(i2c, CCR_MEN); 156} 157 158static int mpc_write(struct mpc_i2c *i2c, int target, 159 const u8 * data, int length, int restart) 160{ 161 int i; 162 unsigned timeout = i2c->adap.timeout; 163 u32 flags = restart ? CCR_RSTA : 0; 164 165 /* Start with MEN */ 166 if (!restart) 167 writeccr(i2c, CCR_MEN); 168 /* Start as master */ 169 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 170 /* Write target byte */ 171 writeb((target << 1), i2c->base + MPC_I2C_DR); 172 173 if (i2c_wait(i2c, timeout, 1) < 0) 174 return -1; 175 176 for (i = 0; i < length; i++) { 177 /* Write data byte */ 178 writeb(data[i], i2c->base + MPC_I2C_DR); 179 180 if (i2c_wait(i2c, timeout, 1) < 0) 181 return -1; 182 } 183 184 return 0; 185} 186 187static int mpc_read(struct mpc_i2c *i2c, int target, 188 u8 * data, int length, int restart) 189{ 190 unsigned timeout = i2c->adap.timeout; 191 int i; 192 u32 flags = restart ? CCR_RSTA : 0; 193 194 /* Start with MEN */ 195 if (!restart) 196 writeccr(i2c, CCR_MEN); 197 /* Switch to read - restart */ 198 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 199 /* Write target address byte - this time with the read flag set */ 200 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR); 201 202 if (i2c_wait(i2c, timeout, 1) < 0) 203 return -1; 204 205 if (length) { 206 if (length == 1) 207 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); 208 else 209 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA); 210 /* Dummy read */ 211 readb(i2c->base + MPC_I2C_DR); 212 } 213 214 for (i = 0; i < length; i++) { 215 if (i2c_wait(i2c, timeout, 0) < 0) 216 return -1; 217 218 /* Generate txack on next to last byte */ 219 if (i == length - 2) 220 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); 221 /* Generate stop on last byte */ 222 if (i == length - 1) 223 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK); 224 data[i] = readb(i2c->base + MPC_I2C_DR); 225 } 226 227 return length; 228} 229 230static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 231{ 232 struct i2c_msg *pmsg; 233 int i; 234 int ret = 0; 235 unsigned long orig_jiffies = jiffies; 236 struct mpc_i2c *i2c = i2c_get_adapdata(adap); 237 238 mpc_i2c_start(i2c); 239 240 /* Allow bus up to 1s to become not busy */ 241 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { 242 if (signal_pending(current)) { 243 pr_debug("I2C: Interrupted\n"); 244 return -EINTR; 245 } 246 if (time_after(jiffies, orig_jiffies + HZ)) { 247 pr_debug("I2C: timeout\n"); 248 return -EIO; 249 } 250 schedule(); 251 } 252 253 for (i = 0; ret >= 0 && i < num; i++) { 254 pmsg = &msgs[i]; 255 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n", 256 pmsg->flags & I2C_M_RD ? "read" : "write", 257 pmsg->len, pmsg->addr, i + 1, num); 258 if (pmsg->flags & I2C_M_RD) 259 ret = 260 mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); 261 else 262 ret = 263 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); 264 } 265 mpc_i2c_stop(i2c); 266 return (ret < 0) ? ret : num; 267} 268 269static u32 mpc_functionality(struct i2c_adapter *adap) 270{ 271 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 272} 273 274static const struct i2c_algorithm mpc_algo = { 275 .master_xfer = mpc_xfer, 276 .functionality = mpc_functionality, 277}; 278 279static struct i2c_adapter mpc_ops = { 280 .owner = THIS_MODULE, 281 .name = "MPC adapter", 282 .id = I2C_HW_MPC107, 283 .algo = &mpc_algo, 284 .class = I2C_CLASS_HWMON, 285 .timeout = 1, 286 .retries = 1 287}; 288 289static int fsl_i2c_probe(struct platform_device *pdev) 290{ 291 int result = 0; 292 struct mpc_i2c *i2c; 293 struct fsl_i2c_platform_data *pdata; 294 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 295 296 pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data; 297 298 if (!(i2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) { 299 return -ENOMEM; 300 } 301 302 i2c->irq = platform_get_irq(pdev, 0); 303 if (i2c->irq < 0) { 304 result = -ENXIO; 305 goto fail_get_irq; 306 } 307 i2c->flags = pdata->device_flags; 308 init_waitqueue_head(&i2c->queue); 309 310 i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION); 311 312 if (!i2c->base) { 313 printk(KERN_ERR "i2c-mpc - failed to map controller\n"); 314 result = -ENOMEM; 315 goto fail_map; 316 } 317 318 if (i2c->irq != 0) 319 if ((result = request_irq(i2c->irq, mpc_i2c_isr, 320 IRQF_SHARED, "i2c-mpc", i2c)) < 0) { 321 printk(KERN_ERR 322 "i2c-mpc - failed to attach interrupt\n"); 323 goto fail_irq; 324 } 325 326 mpc_i2c_setclock(i2c); 327 platform_set_drvdata(pdev, i2c); 328 329 i2c->adap = mpc_ops; 330 i2c_set_adapdata(&i2c->adap, i2c); 331 i2c->adap.dev.parent = &pdev->dev; 332 if ((result = i2c_add_adapter(&i2c->adap)) < 0) { 333 printk(KERN_ERR "i2c-mpc - failed to add adapter\n"); 334 goto fail_add; 335 } 336 337 return result; 338 339 fail_add: 340 if (i2c->irq != 0) 341 free_irq(i2c->irq, NULL); 342 fail_irq: 343 iounmap(i2c->base); 344 fail_map: 345 fail_get_irq: 346 kfree(i2c); 347 return result; 348}; 349 350static int fsl_i2c_remove(struct platform_device *pdev) 351{ 352 struct mpc_i2c *i2c = platform_get_drvdata(pdev); 353 354 i2c_del_adapter(&i2c->adap); 355 platform_set_drvdata(pdev, NULL); 356 357 if (i2c->irq != 0) 358 free_irq(i2c->irq, i2c); 359 360 iounmap(i2c->base); 361 kfree(i2c); 362 return 0; 363}; 364 365/* Structure for a device driver */ 366static struct platform_driver fsl_i2c_driver = { 367 .probe = fsl_i2c_probe, 368 .remove = fsl_i2c_remove, 369 .driver = { 370 .owner = THIS_MODULE, 371 .name = "fsl-i2c", 372 }, 373}; 374 375static int __init fsl_i2c_init(void) 376{ 377 return platform_driver_register(&fsl_i2c_driver); 378} 379 380static void __exit fsl_i2c_exit(void) 381{ 382 platform_driver_unregister(&fsl_i2c_driver); 383} 384 385module_init(fsl_i2c_init); 386module_exit(fsl_i2c_exit); 387 388MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); 389MODULE_DESCRIPTION 390 ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors"); 391MODULE_LICENSE("GPL"); 392