1/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- 2 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Jeff Hartmann <jhartmann@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 * 31 * Rewritten by: 32 * Gareth Hughes <gareth@valinux.com> 33 */ 34 35#ifndef __MGA_DRM_H__ 36#define __MGA_DRM_H__ 37 38/* WARNING: If you change any of these defines, make sure to change the 39 * defines in the Xserver file (mga_sarea.h) 40 */ 41 42#ifndef __MGA_SAREA_DEFINES__ 43#define __MGA_SAREA_DEFINES__ 44 45/* WARP pipe flags 46 */ 47#define MGA_F 0x1 /* fog */ 48#define MGA_A 0x2 /* alpha */ 49#define MGA_S 0x4 /* specular */ 50#define MGA_T2 0x8 /* multitexture */ 51 52#define MGA_WARP_TGZ 0 53#define MGA_WARP_TGZF (MGA_F) 54#define MGA_WARP_TGZA (MGA_A) 55#define MGA_WARP_TGZAF (MGA_F|MGA_A) 56#define MGA_WARP_TGZS (MGA_S) 57#define MGA_WARP_TGZSF (MGA_S|MGA_F) 58#define MGA_WARP_TGZSA (MGA_S|MGA_A) 59#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) 60#define MGA_WARP_T2GZ (MGA_T2) 61#define MGA_WARP_T2GZF (MGA_T2|MGA_F) 62#define MGA_WARP_T2GZA (MGA_T2|MGA_A) 63#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) 64#define MGA_WARP_T2GZS (MGA_T2|MGA_S) 65#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) 66#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) 67#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) 68 69#define MGA_MAX_G200_PIPES 8 /* no multitex */ 70#define MGA_MAX_G400_PIPES 16 71#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES 72#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ 73 74#define MGA_CARD_TYPE_G200 1 75#define MGA_CARD_TYPE_G400 2 76#define MGA_CARD_TYPE_G450 3 /* not currently used */ 77#define MGA_CARD_TYPE_G550 4 78 79#define MGA_FRONT 0x1 80#define MGA_BACK 0x2 81#define MGA_DEPTH 0x4 82 83/* What needs to be changed for the current vertex dma buffer? 84 */ 85#define MGA_UPLOAD_CONTEXT 0x1 86#define MGA_UPLOAD_TEX0 0x2 87#define MGA_UPLOAD_TEX1 0x4 88#define MGA_UPLOAD_PIPE 0x8 89#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ 90#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ 91#define MGA_UPLOAD_2D 0x40 92#define MGA_WAIT_AGE 0x80 /* handled client-side */ 93#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ 94 95/* 32 buffers of 64k each, total 2 meg. 96 */ 97#define MGA_BUFFER_SIZE (1 << 16) 98#define MGA_NUM_BUFFERS 128 99 100/* Keep these small for testing. 101 */ 102#define MGA_NR_SAREA_CLIPRECTS 8 103 104/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 105 * regions, subject to a minimum region size of (1<<16) == 64k. 106 * 107 * Clients may subdivide regions internally, but when sharing between 108 * clients, the region size is the minimum granularity. 109 */ 110 111#define MGA_CARD_HEAP 0 112#define MGA_AGP_HEAP 1 113#define MGA_NR_TEX_HEAPS 2 114#define MGA_NR_TEX_REGIONS 16 115#define MGA_LOG_MIN_TEX_REGION_SIZE 16 116 117#define DRM_MGA_IDLE_RETRY 2048 118 119#endif /* __MGA_SAREA_DEFINES__ */ 120 121/* Setup registers for 3D context 122 */ 123typedef struct { 124 unsigned int dstorg; 125 unsigned int maccess; 126 unsigned int plnwt; 127 unsigned int dwgctl; 128 unsigned int alphactrl; 129 unsigned int fogcolor; 130 unsigned int wflag; 131 unsigned int tdualstage0; 132 unsigned int tdualstage1; 133 unsigned int fcol; 134 unsigned int stencil; 135 unsigned int stencilctl; 136} drm_mga_context_regs_t; 137 138/* Setup registers for 2D, X server 139 */ 140typedef struct { 141 unsigned int pitch; 142} drm_mga_server_regs_t; 143 144/* Setup registers for each texture unit 145 */ 146typedef struct { 147 unsigned int texctl; 148 unsigned int texctl2; 149 unsigned int texfilter; 150 unsigned int texbordercol; 151 unsigned int texorg; 152 unsigned int texwidth; 153 unsigned int texheight; 154 unsigned int texorg1; 155 unsigned int texorg2; 156 unsigned int texorg3; 157 unsigned int texorg4; 158} drm_mga_texture_regs_t; 159 160/* General aging mechanism 161 */ 162typedef struct { 163 unsigned int head; /* Position of head pointer */ 164 unsigned int wrap; /* Primary DMA wrap count */ 165} drm_mga_age_t; 166 167typedef struct _drm_mga_sarea { 168 /* The channel for communication of state information to the kernel 169 * on firing a vertex dma buffer. 170 */ 171 drm_mga_context_regs_t context_state; 172 drm_mga_server_regs_t server_state; 173 drm_mga_texture_regs_t tex_state[2]; 174 unsigned int warp_pipe; 175 unsigned int dirty; 176 unsigned int vertsize; 177 178 /* The current cliprects, or a subset thereof. 179 */ 180 drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; 181 unsigned int nbox; 182 183 /* Information about the most recently used 3d drawable. The 184 * client fills in the req_* fields, the server fills in the 185 * exported_ fields and puts the cliprects into boxes, above. 186 * 187 * The client clears the exported_drawable field before 188 * clobbering the boxes data. 189 */ 190 unsigned int req_drawable; /* the X drawable id */ 191 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ 192 193 unsigned int exported_drawable; 194 unsigned int exported_index; 195 unsigned int exported_stamp; 196 unsigned int exported_buffers; 197 unsigned int exported_nfront; 198 unsigned int exported_nback; 199 int exported_back_x, exported_front_x, exported_w; 200 int exported_back_y, exported_front_y, exported_h; 201 drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; 202 203 /* Counters for aging textures and for client-side throttling. 204 */ 205 unsigned int status[4]; 206 unsigned int last_wrap; 207 208 drm_mga_age_t last_frame; 209 unsigned int last_enqueue; /* last time a buffer was enqueued */ 210 unsigned int last_dispatch; /* age of the most recently dispatched buffer */ 211 unsigned int last_quiescent; /* */ 212 213 /* LRU lists for texture memory in agp space and on the card. 214 */ 215 drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; 216 unsigned int texAge[MGA_NR_TEX_HEAPS]; 217 218 /* Mechanism to validate card state. 219 */ 220 int ctxOwner; 221} drm_mga_sarea_t; 222 223/* MGA specific ioctls 224 * The device specific ioctl range is 0x40 to 0x79. 225 */ 226#define DRM_MGA_INIT 0x00 227#define DRM_MGA_FLUSH 0x01 228#define DRM_MGA_RESET 0x02 229#define DRM_MGA_SWAP 0x03 230#define DRM_MGA_CLEAR 0x04 231#define DRM_MGA_VERTEX 0x05 232#define DRM_MGA_INDICES 0x06 233#define DRM_MGA_ILOAD 0x07 234#define DRM_MGA_BLIT 0x08 235#define DRM_MGA_GETPARAM 0x09 236 237/* 3.2: 238 * ioctls for operating on fences. 239 */ 240#define DRM_MGA_SET_FENCE 0x0a 241#define DRM_MGA_WAIT_FENCE 0x0b 242#define DRM_MGA_DMA_BOOTSTRAP 0x0c 243 244#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) 245#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) 246#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) 247#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) 248#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) 249#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) 250#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) 251#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) 252#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) 253#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) 254#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t) 255#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t) 256#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) 257 258typedef struct _drm_mga_warp_index { 259 int installed; 260 unsigned long phys_addr; 261 int size; 262} drm_mga_warp_index_t; 263 264typedef struct drm_mga_init { 265 enum { 266 MGA_INIT_DMA = 0x01, 267 MGA_CLEANUP_DMA = 0x02 268 } func; 269 270 unsigned long sarea_priv_offset; 271 272 int chipset; 273 int sgram; 274 275 unsigned int maccess; 276 277 unsigned int fb_cpp; 278 unsigned int front_offset, front_pitch; 279 unsigned int back_offset, back_pitch; 280 281 unsigned int depth_cpp; 282 unsigned int depth_offset, depth_pitch; 283 284 unsigned int texture_offset[MGA_NR_TEX_HEAPS]; 285 unsigned int texture_size[MGA_NR_TEX_HEAPS]; 286 287 unsigned long fb_offset; 288 unsigned long mmio_offset; 289 unsigned long status_offset; 290 unsigned long warp_offset; 291 unsigned long primary_offset; 292 unsigned long buffers_offset; 293} drm_mga_init_t; 294 295typedef struct drm_mga_dma_bootstrap { 296 /** 297 * \name AGP texture region 298 * 299 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will 300 * be filled in with the actual AGP texture settings. 301 * 302 * \warning 303 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode 304 * is zero, it means that PCI memory (most likely through the use of 305 * an IOMMU) is being used for "AGP" textures. 306 */ 307 /*@{ */ 308 unsigned long texture_handle; /**< Handle used to map AGP textures. */ 309 uint32_t texture_size; /**< Size of the AGP texture region. */ 310 /*@} */ 311 312 /** 313 * Requested size of the primary DMA region. 314 * 315 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 316 * filled in with the actual AGP mode. If AGP was not available 317 */ 318 uint32_t primary_size; 319 320 /** 321 * Requested number of secondary DMA buffers. 322 * 323 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 324 * filled in with the actual number of secondary DMA buffers 325 * allocated. Particularly when PCI DMA is used, this may be 326 * (subtantially) less than the number requested. 327 */ 328 uint32_t secondary_bin_count; 329 330 /** 331 * Requested size of each secondary DMA buffer. 332 * 333 * While the kernel \b is free to reduce 334 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed 335 * to reduce dma_mga_dma_bootstrap::secondary_bin_size. 336 */ 337 uint32_t secondary_bin_size; 338 339 /** 340 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, 341 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is 342 * zero, it means that PCI DMA should be used, even if AGP is 343 * possible. 344 * 345 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 346 * filled in with the actual AGP mode. If AGP was not available 347 * (i.e., PCI DMA was used), this value will be zero. 348 */ 349 uint32_t agp_mode; 350 351 /** 352 * Desired AGP GART size, measured in megabytes. 353 */ 354 uint8_t agp_size; 355} drm_mga_dma_bootstrap_t; 356 357typedef struct drm_mga_clear { 358 unsigned int flags; 359 unsigned int clear_color; 360 unsigned int clear_depth; 361 unsigned int color_mask; 362 unsigned int depth_mask; 363} drm_mga_clear_t; 364 365typedef struct drm_mga_vertex { 366 int idx; /* buffer to queue */ 367 int used; /* bytes in use */ 368 int discard; /* client finished with buffer? */ 369} drm_mga_vertex_t; 370 371typedef struct drm_mga_indices { 372 int idx; /* buffer to queue */ 373 unsigned int start; 374 unsigned int end; 375 int discard; /* client finished with buffer? */ 376} drm_mga_indices_t; 377 378typedef struct drm_mga_iload { 379 int idx; 380 unsigned int dstorg; 381 unsigned int length; 382} drm_mga_iload_t; 383 384typedef struct _drm_mga_blit { 385 unsigned int planemask; 386 unsigned int srcorg; 387 unsigned int dstorg; 388 int src_pitch, dst_pitch; 389 int delta_sx, delta_sy; 390 int delta_dx, delta_dy; 391 int height, ydir; /* flip image vertically */ 392 int source_pitch, dest_pitch; 393} drm_mga_blit_t; 394 395/* 3.1: An ioctl to get parameters that aren't available to the 3d 396 * client any other way. 397 */ 398#define MGA_PARAM_IRQ_NR 1 399 400/* 3.2: Query the actual card type. The DDX only distinguishes between 401 * G200 chips and non-G200 chips, which it calls G400. It turns out that 402 * there are some very sublte differences between the G4x0 chips and the G550 403 * chips. Using this parameter query, a client-side driver can detect the 404 * difference between a G4x0 and a G550. 405 */ 406#define MGA_PARAM_CARD_TYPE 2 407 408typedef struct drm_mga_getparam { 409 int param; 410 void __user *value; 411} drm_mga_getparam_t; 412 413#endif 414