1/* 2 * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of 3 * the "Intel 460GTX Chipset Software Developer's Manual": 4 * http://developer.intel.com/design/itanium/downloads/24870401s.htm 5 */ 6/* 7 * 460GX support by Chris Ahna <christopher.j.ahna@intel.com> 8 * Clean up & simplification by David Mosberger-Tang <davidm@hpl.hp.com> 9 */ 10#include <linux/module.h> 11#include <linux/pci.h> 12#include <linux/init.h> 13#include <linux/string.h> 14#include <linux/slab.h> 15#include <linux/agp_backend.h> 16 17#include "agp.h" 18 19#define INTEL_I460_BAPBASE 0x98 20#define INTEL_I460_GXBCTL 0xa0 21#define INTEL_I460_AGPSIZ 0xa2 22#define INTEL_I460_ATTBASE 0xfe200000 23#define INTEL_I460_GATT_VALID (1UL << 24) 24#define INTEL_I460_GATT_COHERENT (1UL << 25) 25 26/* 27 * The i460 can operate with large (4MB) pages, but there is no sane way to support this 28 * within the current kernel/DRM environment, so we disable the relevant code for now. 29 * See also comments in ia64_alloc_page()... 30 */ 31#define I460_LARGE_IO_PAGES 0 32 33#if I460_LARGE_IO_PAGES 34# define I460_IO_PAGE_SHIFT i460.io_page_shift 35#else 36# define I460_IO_PAGE_SHIFT 12 37#endif 38 39#define I460_IOPAGES_PER_KPAGE (PAGE_SIZE >> I460_IO_PAGE_SHIFT) 40#define I460_KPAGES_PER_IOPAGE (1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT)) 41#define I460_SRAM_IO_DISABLE (1 << 4) 42#define I460_BAPBASE_ENABLE (1 << 3) 43#define I460_AGPSIZ_MASK 0x7 44#define I460_4M_PS (1 << 1) 45 46/* Control bits for Out-Of-GART coherency and Burst Write Combining */ 47#define I460_GXBCTL_OOG (1UL << 0) 48#define I460_GXBCTL_BWC (1UL << 2) 49 50/* 51 * gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the 52 * gatt_table and gatt_table_real pointers a "void *"... 53 */ 54#define RD_GATT(index) readl((u32 *) i460.gatt + (index)) 55#define WR_GATT(index, val) writel((val), (u32 *) i460.gatt + (index)) 56/* 57 * The 460 spec says we have to read the last location written to make sure that all 58 * writes have taken effect 59 */ 60#define WR_FLUSH_GATT(index) RD_GATT(index) 61 62#define log2(x) ffz(~(x)) 63 64static struct { 65 void *gatt; /* ioremap'd GATT area */ 66 67 /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */ 68 u8 io_page_shift; 69 70 /* BIOS configures chipset to one of 2 possible apbase values: */ 71 u8 dynamic_apbase; 72 73 /* structure for tracking partial use of 4MB GART pages: */ 74 struct lp_desc { 75 unsigned long *alloced_map; /* bitmap of kernel-pages in use */ 76 int refcount; /* number of kernel pages using the large page */ 77 u64 paddr; /* physical address of large page */ 78 } *lp_desc; 79} i460; 80 81static const struct aper_size_info_8 i460_sizes[3] = 82{ 83 /* 84 * The 32GB aperture is only available with a 4M GART page size. Due to the 85 * dynamic GART page size, we can't figure out page_order or num_entries until 86 * runtime. 87 */ 88 {32768, 0, 0, 4}, 89 {1024, 0, 0, 2}, 90 {256, 0, 0, 1} 91}; 92 93static struct gatt_mask i460_masks[] = 94{ 95 { 96 .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT, 97 .type = 0 98 } 99}; 100 101static int i460_fetch_size (void) 102{ 103 int i; 104 u8 temp; 105 struct aper_size_info_8 *values; 106 107 /* Determine the GART page size */ 108 pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp); 109 i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12; 110 pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift); 111 112 if (i460.io_page_shift != I460_IO_PAGE_SHIFT) { 113 printk(KERN_ERR PFX 114 "I/O (GART) page-size %luKB doesn't match expected " 115 "size %luKB\n", 116 1UL << (i460.io_page_shift - 10), 117 1UL << (I460_IO_PAGE_SHIFT)); 118 return 0; 119 } 120 121 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 122 123 pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp); 124 125 /* Exit now if the IO drivers for the GART SRAMS are turned off */ 126 if (temp & I460_SRAM_IO_DISABLE) { 127 printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n"); 128 printk(KERN_ERR PFX "AGPGART operation not possible\n"); 129 return 0; 130 } 131 132 /* Make sure we don't try to create an 2 ^ 23 entry GATT */ 133 if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) { 134 printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n"); 135 return 0; 136 } 137 138 /* Determine the proper APBASE register */ 139 if (temp & I460_BAPBASE_ENABLE) 140 i460.dynamic_apbase = INTEL_I460_BAPBASE; 141 else 142 i460.dynamic_apbase = AGP_APBASE; 143 144 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 145 /* 146 * Dynamically calculate the proper num_entries and page_order values for 147 * the define aperture sizes. Take care not to shift off the end of 148 * values[i].size. 149 */ 150 values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12); 151 values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT); 152 } 153 154 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 155 /* Neglect control bits when matching up size_value */ 156 if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) { 157 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 158 agp_bridge->aperture_size_idx = i; 159 return values[i].size; 160 } 161 } 162 163 return 0; 164} 165 166/* There isn't anything to do here since 460 has no GART TLB. */ 167static void i460_tlb_flush (struct agp_memory *mem) 168{ 169 return; 170} 171 172/* 173 * This utility function is needed to prevent corruption of the control bits 174 * which are stored along with the aperture size in 460's AGPSIZ register 175 */ 176static void i460_write_agpsiz (u8 size_value) 177{ 178 u8 temp; 179 180 pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp); 181 pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, 182 ((temp & ~I460_AGPSIZ_MASK) | size_value)); 183} 184 185static void i460_cleanup (void) 186{ 187 struct aper_size_info_8 *previous_size; 188 189 previous_size = A_SIZE_8(agp_bridge->previous_size); 190 i460_write_agpsiz(previous_size->size_value); 191 192 if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) 193 kfree(i460.lp_desc); 194} 195 196static int i460_configure (void) 197{ 198 union { 199 u32 small[2]; 200 u64 large; 201 } temp; 202 size_t size; 203 u8 scratch; 204 struct aper_size_info_8 *current_size; 205 206 temp.large = 0; 207 208 current_size = A_SIZE_8(agp_bridge->current_size); 209 i460_write_agpsiz(current_size->size_value); 210 211 /* 212 * Do the necessary rigmarole to read all eight bytes of APBASE. 213 * This has to be done since the AGP aperture can be above 4GB on 214 * 460 based systems. 215 */ 216 pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0])); 217 pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1])); 218 219 /* Clear BAR control bits */ 220 agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1); 221 222 pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch); 223 pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, 224 (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC); 225 226 /* 227 * Initialize partial allocation trackers if a GART page is bigger than a kernel 228 * page. 229 */ 230 if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) { 231 size = current_size->num_entries * sizeof(i460.lp_desc[0]); 232 i460.lp_desc = kzalloc(size, GFP_KERNEL); 233 if (!i460.lp_desc) 234 return -ENOMEM; 235 } 236 return 0; 237} 238 239static int i460_create_gatt_table (struct agp_bridge_data *bridge) 240{ 241 int page_order, num_entries, i; 242 void *temp; 243 244 /* 245 * Load up the fixed address of the GART SRAMS which hold our GATT table. 246 */ 247 temp = agp_bridge->current_size; 248 page_order = A_SIZE_8(temp)->page_order; 249 num_entries = A_SIZE_8(temp)->num_entries; 250 251 i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order); 252 253 /* These are no good, the should be removed from the agp_bridge strucure... */ 254 agp_bridge->gatt_table_real = NULL; 255 agp_bridge->gatt_table = NULL; 256 agp_bridge->gatt_bus_addr = 0; 257 258 for (i = 0; i < num_entries; ++i) 259 WR_GATT(i, 0); 260 WR_FLUSH_GATT(i - 1); 261 return 0; 262} 263 264static int i460_free_gatt_table (struct agp_bridge_data *bridge) 265{ 266 int num_entries, i; 267 void *temp; 268 269 temp = agp_bridge->current_size; 270 271 num_entries = A_SIZE_8(temp)->num_entries; 272 273 for (i = 0; i < num_entries; ++i) 274 WR_GATT(i, 0); 275 WR_FLUSH_GATT(num_entries - 1); 276 277 iounmap(i460.gatt); 278 return 0; 279} 280 281/* 282 * The following functions are called when the I/O (GART) page size is smaller than 283 * PAGE_SIZE. 284 */ 285 286static int i460_insert_memory_small_io_page (struct agp_memory *mem, 287 off_t pg_start, int type) 288{ 289 unsigned long paddr, io_pg_start, io_page_size; 290 int i, j, k, num_entries; 291 void *temp; 292 293 pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n", 294 mem, pg_start, type, mem->memory[0]); 295 296 if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES) 297 return -EINVAL; 298 299 io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start; 300 301 temp = agp_bridge->current_size; 302 num_entries = A_SIZE_8(temp)->num_entries; 303 304 if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) { 305 printk(KERN_ERR PFX "Looks like we're out of AGP memory\n"); 306 return -EINVAL; 307 } 308 309 j = io_pg_start; 310 while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) { 311 if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) { 312 pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n", 313 j, RD_GATT(j)); 314 return -EBUSY; 315 } 316 j++; 317 } 318 319 io_page_size = 1UL << I460_IO_PAGE_SHIFT; 320 for (i = 0, j = io_pg_start; i < mem->page_count; i++) { 321 paddr = mem->memory[i]; 322 for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size) 323 WR_GATT(j, agp_bridge->driver->mask_memory(agp_bridge, 324 paddr, mem->type)); 325 } 326 WR_FLUSH_GATT(j - 1); 327 return 0; 328} 329 330static int i460_remove_memory_small_io_page(struct agp_memory *mem, 331 off_t pg_start, int type) 332{ 333 int i; 334 335 pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n", 336 mem, pg_start, type); 337 338 pg_start = I460_IOPAGES_PER_KPAGE * pg_start; 339 340 for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++) 341 WR_GATT(i, 0); 342 WR_FLUSH_GATT(i - 1); 343 return 0; 344} 345 346#if I460_LARGE_IO_PAGES 347 348 349static int i460_alloc_large_page (struct lp_desc *lp) 350{ 351 unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT; 352 size_t map_size; 353 void *lpage; 354 355 lpage = (void *) __get_free_pages(GFP_KERNEL, order); 356 if (!lpage) { 357 printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n"); 358 return -ENOMEM; 359 } 360 361 map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8; 362 lp->alloced_map = kzalloc(map_size, GFP_KERNEL); 363 if (!lp->alloced_map) { 364 free_pages((unsigned long) lpage, order); 365 printk(KERN_ERR PFX "Out of memory, we're in trouble...\n"); 366 return -ENOMEM; 367 } 368 369 lp->paddr = virt_to_gart(lpage); 370 lp->refcount = 0; 371 atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp); 372 return 0; 373} 374 375static void i460_free_large_page (struct lp_desc *lp) 376{ 377 kfree(lp->alloced_map); 378 lp->alloced_map = NULL; 379 380 free_pages((unsigned long) gart_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT); 381 atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp); 382} 383 384static int i460_insert_memory_large_io_page (struct agp_memory *mem, 385 off_t pg_start, int type) 386{ 387 int i, start_offset, end_offset, idx, pg, num_entries; 388 struct lp_desc *start, *end, *lp; 389 void *temp; 390 391 if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES) 392 return -EINVAL; 393 394 temp = agp_bridge->current_size; 395 num_entries = A_SIZE_8(temp)->num_entries; 396 397 /* Figure out what pg_start means in terms of our large GART pages */ 398 start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE]; 399 end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE]; 400 start_offset = pg_start % I460_KPAGES_PER_IOPAGE; 401 end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE; 402 403 if (end > i460.lp_desc + num_entries) { 404 printk(KERN_ERR PFX "Looks like we're out of AGP memory\n"); 405 return -EINVAL; 406 } 407 408 /* Check if the requested region of the aperture is free */ 409 for (lp = start; lp <= end; ++lp) { 410 if (!lp->alloced_map) 411 continue; /* OK, the entire large page is available... */ 412 413 for (idx = ((lp == start) ? start_offset : 0); 414 idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); 415 idx++) 416 { 417 if (test_bit(idx, lp->alloced_map)) 418 return -EBUSY; 419 } 420 } 421 422 for (lp = start, i = 0; lp <= end; ++lp) { 423 if (!lp->alloced_map) { 424 /* Allocate new GART pages... */ 425 if (i460_alloc_large_page(lp) < 0) 426 return -ENOMEM; 427 pg = lp - i460.lp_desc; 428 WR_GATT(pg, agp_bridge->driver->mask_memory(agp_bridge, 429 lp->paddr, 0)); 430 WR_FLUSH_GATT(pg); 431 } 432 433 for (idx = ((lp == start) ? start_offset : 0); 434 idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); 435 idx++, i++) 436 { 437 mem->memory[i] = lp->paddr + idx*PAGE_SIZE; 438 __set_bit(idx, lp->alloced_map); 439 ++lp->refcount; 440 } 441 } 442 return 0; 443} 444 445static int i460_remove_memory_large_io_page (struct agp_memory *mem, 446 off_t pg_start, int type) 447{ 448 int i, pg, start_offset, end_offset, idx, num_entries; 449 struct lp_desc *start, *end, *lp; 450 void *temp; 451 452 temp = agp_bridge->driver->current_size; 453 num_entries = A_SIZE_8(temp)->num_entries; 454 455 /* Figure out what pg_start means in terms of our large GART pages */ 456 start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE]; 457 end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE]; 458 start_offset = pg_start % I460_KPAGES_PER_IOPAGE; 459 end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE; 460 461 for (i = 0, lp = start; lp <= end; ++lp) { 462 for (idx = ((lp == start) ? start_offset : 0); 463 idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); 464 idx++, i++) 465 { 466 mem->memory[i] = 0; 467 __clear_bit(idx, lp->alloced_map); 468 --lp->refcount; 469 } 470 471 /* Free GART pages if they are unused */ 472 if (lp->refcount == 0) { 473 pg = lp - i460.lp_desc; 474 WR_GATT(pg, 0); 475 WR_FLUSH_GATT(pg); 476 i460_free_large_page(lp); 477 } 478 } 479 return 0; 480} 481 482/* Wrapper routines to call the approriate {small_io_page,large_io_page} function */ 483 484static int i460_insert_memory (struct agp_memory *mem, 485 off_t pg_start, int type) 486{ 487 if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) 488 return i460_insert_memory_small_io_page(mem, pg_start, type); 489 else 490 return i460_insert_memory_large_io_page(mem, pg_start, type); 491} 492 493static int i460_remove_memory (struct agp_memory *mem, 494 off_t pg_start, int type) 495{ 496 if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) 497 return i460_remove_memory_small_io_page(mem, pg_start, type); 498 else 499 return i460_remove_memory_large_io_page(mem, pg_start, type); 500} 501 502/* 503 * If the I/O (GART) page size is bigger than the kernel page size, we don't want to 504 * allocate memory until we know where it is to be bound in the aperture (a 505 * multi-kernel-page alloc might fit inside of an already allocated GART page). 506 * 507 * Let's just hope nobody counts on the allocated AGP memory being there before bind time 508 * (I don't think current drivers do)... 509 */ 510static void *i460_alloc_page (struct agp_bridge_data *bridge) 511{ 512 void *page; 513 514 if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) { 515 page = agp_generic_alloc_page(agp_bridge); 516 global_flush_tlb(); 517 } else 518 /* Returning NULL would cause problems */ 519 /* AK: really dubious code. */ 520 page = (void *)~0UL; 521 return page; 522} 523 524static void i460_destroy_page (void *page) 525{ 526 if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) { 527 agp_generic_destroy_page(page); 528 global_flush_tlb(); 529 } 530} 531 532#endif /* I460_LARGE_IO_PAGES */ 533 534static unsigned long i460_mask_memory (struct agp_bridge_data *bridge, 535 unsigned long addr, int type) 536{ 537 /* Make sure the returned address is a valid GATT entry */ 538 return bridge->driver->masks[0].mask 539 | (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xfffff000) >> 12); 540} 541 542const struct agp_bridge_driver intel_i460_driver = { 543 .owner = THIS_MODULE, 544 .aperture_sizes = i460_sizes, 545 .size_type = U8_APER_SIZE, 546 .num_aperture_sizes = 3, 547 .configure = i460_configure, 548 .fetch_size = i460_fetch_size, 549 .cleanup = i460_cleanup, 550 .tlb_flush = i460_tlb_flush, 551 .mask_memory = i460_mask_memory, 552 .masks = i460_masks, 553 .agp_enable = agp_generic_enable, 554 .cache_flush = global_cache_flush, 555 .create_gatt_table = i460_create_gatt_table, 556 .free_gatt_table = i460_free_gatt_table, 557#if I460_LARGE_IO_PAGES 558 .insert_memory = i460_insert_memory, 559 .remove_memory = i460_remove_memory, 560 .agp_alloc_page = i460_alloc_page, 561 .agp_destroy_page = i460_destroy_page, 562#else 563 .insert_memory = i460_insert_memory_small_io_page, 564 .remove_memory = i460_remove_memory_small_io_page, 565 .agp_alloc_page = agp_generic_alloc_page, 566 .agp_destroy_page = agp_generic_destroy_page, 567#endif 568 .alloc_by_type = agp_generic_alloc_by_type, 569 .free_by_type = agp_generic_free_by_type, 570 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 571 .cant_use_aperture = 1, 572}; 573 574static int __devinit agp_intel_i460_probe(struct pci_dev *pdev, 575 const struct pci_device_id *ent) 576{ 577 struct agp_bridge_data *bridge; 578 u8 cap_ptr; 579 580 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 581 if (!cap_ptr) 582 return -ENODEV; 583 584 bridge = agp_alloc_bridge(); 585 if (!bridge) 586 return -ENOMEM; 587 588 bridge->driver = &intel_i460_driver; 589 bridge->dev = pdev; 590 bridge->capndx = cap_ptr; 591 592 printk(KERN_INFO PFX "Detected Intel 460GX chipset\n"); 593 594 pci_set_drvdata(pdev, bridge); 595 return agp_add_bridge(bridge); 596} 597 598static void __devexit agp_intel_i460_remove(struct pci_dev *pdev) 599{ 600 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 601 602 agp_remove_bridge(bridge); 603 agp_put_bridge(bridge); 604} 605 606static struct pci_device_id agp_intel_i460_pci_table[] = { 607 { 608 .class = (PCI_CLASS_BRIDGE_HOST << 8), 609 .class_mask = ~0, 610 .vendor = PCI_VENDOR_ID_INTEL, 611 .device = PCI_DEVICE_ID_INTEL_84460GX, 612 .subvendor = PCI_ANY_ID, 613 .subdevice = PCI_ANY_ID, 614 }, 615 { } 616}; 617 618MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table); 619 620static struct pci_driver agp_intel_i460_pci_driver = { 621 .name = "agpgart-intel-i460", 622 .id_table = agp_intel_i460_pci_table, 623 .probe = agp_intel_i460_probe, 624 .remove = __devexit_p(agp_intel_i460_remove), 625}; 626 627static int __init agp_intel_i460_init(void) 628{ 629 if (agp_off) 630 return -EINVAL; 631 return pci_register_driver(&agp_intel_i460_pci_driver); 632} 633 634static void __exit agp_intel_i460_cleanup(void) 635{ 636 pci_unregister_driver(&agp_intel_i460_pci_driver); 637} 638 639module_init(agp_intel_i460_init); 640module_exit(agp_intel_i460_cleanup); 641 642MODULE_AUTHOR("Chris Ahna <Christopher.J.Ahna@intel.com>"); 643MODULE_LICENSE("GPL and additional rights"); 644