1/******************************************************************* 2 * ident "$Id: idt77252.c,v 1.1.1.1 2007-08-03 18:52:26 $" 3 * 4 * $Author: rnuti $ 5 * $Date: 2007-08-03 18:52:26 $ 6 * 7 * Copyright (c) 2000 ATecoM GmbH 8 * 9 * The author may be reached at ecd@atecom.com. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 *******************************************************************/ 32static char const rcsid[] = 33"$Id: idt77252.c,v 1.1.1.1 2007-08-03 18:52:26 $"; 34 35 36#include <linux/module.h> 37#include <linux/pci.h> 38#include <linux/poison.h> 39#include <linux/skbuff.h> 40#include <linux/kernel.h> 41#include <linux/vmalloc.h> 42#include <linux/netdevice.h> 43#include <linux/atmdev.h> 44#include <linux/atm.h> 45#include <linux/delay.h> 46#include <linux/init.h> 47#include <linux/bitops.h> 48#include <linux/wait.h> 49#include <linux/jiffies.h> 50#include <linux/mutex.h> 51 52#include <asm/io.h> 53#include <asm/uaccess.h> 54#include <asm/atomic.h> 55#include <asm/byteorder.h> 56 57#ifdef CONFIG_ATM_IDT77252_USE_SUNI 58#include "suni.h" 59#endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 60 61 62#include "idt77252.h" 63#include "idt77252_tables.h" 64 65static unsigned int vpibits = 1; 66 67 68#define CONFIG_ATM_IDT77252_SEND_IDLE 1 69 70 71/* 72 * Debug HACKs. 73 */ 74#define DEBUG_MODULE 1 75#undef HAVE_EEPROM /* does not work, yet. */ 76 77#ifdef CONFIG_ATM_IDT77252_DEBUG 78static unsigned long debug = DBG_GENERAL; 79#endif 80 81 82#define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 83 84 85/* 86 * SCQ Handling. 87 */ 88static struct scq_info *alloc_scq(struct idt77252_dev *, int); 89static void free_scq(struct idt77252_dev *, struct scq_info *); 90static int queue_skb(struct idt77252_dev *, struct vc_map *, 91 struct sk_buff *, int oam); 92static void drain_scq(struct idt77252_dev *, struct vc_map *); 93static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 94static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 95 96/* 97 * FBQ Handling. 98 */ 99static int push_rx_skb(struct idt77252_dev *, 100 struct sk_buff *, int queue); 101static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 102static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 103static void recycle_rx_pool_skb(struct idt77252_dev *, 104 struct rx_pool *); 105static void add_rx_skb(struct idt77252_dev *, int queue, 106 unsigned int size, unsigned int count); 107 108/* 109 * RSQ Handling. 110 */ 111static int init_rsq(struct idt77252_dev *); 112static void deinit_rsq(struct idt77252_dev *); 113static void idt77252_rx(struct idt77252_dev *); 114 115/* 116 * TSQ handling. 117 */ 118static int init_tsq(struct idt77252_dev *); 119static void deinit_tsq(struct idt77252_dev *); 120static void idt77252_tx(struct idt77252_dev *); 121 122 123/* 124 * ATM Interface. 125 */ 126static void idt77252_dev_close(struct atm_dev *dev); 127static int idt77252_open(struct atm_vcc *vcc); 128static void idt77252_close(struct atm_vcc *vcc); 129static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 130static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 131 int flags); 132static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 133 unsigned long addr); 134static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 135static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 136 int flags); 137static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 138 char *page); 139static void idt77252_softint(struct work_struct *work); 140 141 142static struct atmdev_ops idt77252_ops = 143{ 144 .dev_close = idt77252_dev_close, 145 .open = idt77252_open, 146 .close = idt77252_close, 147 .send = idt77252_send, 148 .send_oam = idt77252_send_oam, 149 .phy_put = idt77252_phy_put, 150 .phy_get = idt77252_phy_get, 151 .change_qos = idt77252_change_qos, 152 .proc_read = idt77252_proc_read, 153 .owner = THIS_MODULE 154}; 155 156static struct idt77252_dev *idt77252_chain = NULL; 157static unsigned int idt77252_sram_write_errors = 0; 158 159/*****************************************************************************/ 160/* */ 161/* I/O and Utility Bus */ 162/* */ 163/*****************************************************************************/ 164 165static void 166waitfor_idle(struct idt77252_dev *card) 167{ 168 u32 stat; 169 170 stat = readl(SAR_REG_STAT); 171 while (stat & SAR_STAT_CMDBZ) 172 stat = readl(SAR_REG_STAT); 173} 174 175static u32 176read_sram(struct idt77252_dev *card, unsigned long addr) 177{ 178 unsigned long flags; 179 u32 value; 180 181 spin_lock_irqsave(&card->cmd_lock, flags); 182 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 183 waitfor_idle(card); 184 value = readl(SAR_REG_DR0); 185 spin_unlock_irqrestore(&card->cmd_lock, flags); 186 return value; 187} 188 189static void 190write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 191{ 192 unsigned long flags; 193 194 if ((idt77252_sram_write_errors == 0) && 195 (((addr > card->tst[0] + card->tst_size - 2) && 196 (addr < card->tst[0] + card->tst_size)) || 197 ((addr > card->tst[1] + card->tst_size - 2) && 198 (addr < card->tst[1] + card->tst_size)))) { 199 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 200 card->name, addr, value); 201 } 202 203 spin_lock_irqsave(&card->cmd_lock, flags); 204 writel(value, SAR_REG_DR0); 205 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 206 waitfor_idle(card); 207 spin_unlock_irqrestore(&card->cmd_lock, flags); 208} 209 210static u8 211read_utility(void *dev, unsigned long ubus_addr) 212{ 213 struct idt77252_dev *card = dev; 214 unsigned long flags; 215 u8 value; 216 217 if (!card) { 218 printk("Error: No such device.\n"); 219 return -1; 220 } 221 222 spin_lock_irqsave(&card->cmd_lock, flags); 223 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 224 waitfor_idle(card); 225 value = readl(SAR_REG_DR0); 226 spin_unlock_irqrestore(&card->cmd_lock, flags); 227 return value; 228} 229 230static void 231write_utility(void *dev, unsigned long ubus_addr, u8 value) 232{ 233 struct idt77252_dev *card = dev; 234 unsigned long flags; 235 236 if (!card) { 237 printk("Error: No such device.\n"); 238 return; 239 } 240 241 spin_lock_irqsave(&card->cmd_lock, flags); 242 writel((u32) value, SAR_REG_DR0); 243 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 244 waitfor_idle(card); 245 spin_unlock_irqrestore(&card->cmd_lock, flags); 246} 247 248#ifdef HAVE_EEPROM 249static u32 rdsrtab[] = 250{ 251 SAR_GP_EECS | SAR_GP_EESCLK, 252 0, 253 SAR_GP_EESCLK, /* 0 */ 254 0, 255 SAR_GP_EESCLK, /* 0 */ 256 0, 257 SAR_GP_EESCLK, /* 0 */ 258 0, 259 SAR_GP_EESCLK, /* 0 */ 260 0, 261 SAR_GP_EESCLK, /* 0 */ 262 SAR_GP_EEDO, 263 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 264 0, 265 SAR_GP_EESCLK, /* 0 */ 266 SAR_GP_EEDO, 267 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 268}; 269 270static u32 wrentab[] = 271{ 272 SAR_GP_EECS | SAR_GP_EESCLK, 273 0, 274 SAR_GP_EESCLK, /* 0 */ 275 0, 276 SAR_GP_EESCLK, /* 0 */ 277 0, 278 SAR_GP_EESCLK, /* 0 */ 279 0, 280 SAR_GP_EESCLK, /* 0 */ 281 SAR_GP_EEDO, 282 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 283 SAR_GP_EEDO, 284 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 285 0, 286 SAR_GP_EESCLK, /* 0 */ 287 0, 288 SAR_GP_EESCLK /* 0 */ 289}; 290 291static u32 rdtab[] = 292{ 293 SAR_GP_EECS | SAR_GP_EESCLK, 294 0, 295 SAR_GP_EESCLK, /* 0 */ 296 0, 297 SAR_GP_EESCLK, /* 0 */ 298 0, 299 SAR_GP_EESCLK, /* 0 */ 300 0, 301 SAR_GP_EESCLK, /* 0 */ 302 0, 303 SAR_GP_EESCLK, /* 0 */ 304 0, 305 SAR_GP_EESCLK, /* 0 */ 306 SAR_GP_EEDO, 307 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 308 SAR_GP_EEDO, 309 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 310}; 311 312static u32 wrtab[] = 313{ 314 SAR_GP_EECS | SAR_GP_EESCLK, 315 0, 316 SAR_GP_EESCLK, /* 0 */ 317 0, 318 SAR_GP_EESCLK, /* 0 */ 319 0, 320 SAR_GP_EESCLK, /* 0 */ 321 0, 322 SAR_GP_EESCLK, /* 0 */ 323 0, 324 SAR_GP_EESCLK, /* 0 */ 325 0, 326 SAR_GP_EESCLK, /* 0 */ 327 SAR_GP_EEDO, 328 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 329 0, 330 SAR_GP_EESCLK /* 0 */ 331}; 332 333static u32 clktab[] = 334{ 335 0, 336 SAR_GP_EESCLK, 337 0, 338 SAR_GP_EESCLK, 339 0, 340 SAR_GP_EESCLK, 341 0, 342 SAR_GP_EESCLK, 343 0, 344 SAR_GP_EESCLK, 345 0, 346 SAR_GP_EESCLK, 347 0, 348 SAR_GP_EESCLK, 349 0, 350 SAR_GP_EESCLK, 351 0 352}; 353 354static u32 355idt77252_read_gp(struct idt77252_dev *card) 356{ 357 u32 gp; 358 359 gp = readl(SAR_REG_GP); 360 return gp; 361} 362 363static void 364idt77252_write_gp(struct idt77252_dev *card, u32 value) 365{ 366 unsigned long flags; 367 368 369 spin_lock_irqsave(&card->cmd_lock, flags); 370 waitfor_idle(card); 371 writel(value, SAR_REG_GP); 372 spin_unlock_irqrestore(&card->cmd_lock, flags); 373} 374 375static u8 376idt77252_eeprom_read_status(struct idt77252_dev *card) 377{ 378 u8 byte; 379 u32 gp; 380 int i, j; 381 382 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 383 384 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 385 idt77252_write_gp(card, gp | rdsrtab[i]); 386 udelay(5); 387 } 388 idt77252_write_gp(card, gp | SAR_GP_EECS); 389 udelay(5); 390 391 byte = 0; 392 for (i = 0, j = 0; i < 8; i++) { 393 byte <<= 1; 394 395 idt77252_write_gp(card, gp | clktab[j++]); 396 udelay(5); 397 398 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 399 400 idt77252_write_gp(card, gp | clktab[j++]); 401 udelay(5); 402 } 403 idt77252_write_gp(card, gp | SAR_GP_EECS); 404 udelay(5); 405 406 return byte; 407} 408 409static u8 410idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 411{ 412 u8 byte; 413 u32 gp; 414 int i, j; 415 416 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 417 418 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 419 idt77252_write_gp(card, gp | rdtab[i]); 420 udelay(5); 421 } 422 idt77252_write_gp(card, gp | SAR_GP_EECS); 423 udelay(5); 424 425 for (i = 0, j = 0; i < 8; i++) { 426 idt77252_write_gp(card, gp | clktab[j++] | 427 (offset & 1 ? SAR_GP_EEDO : 0)); 428 udelay(5); 429 430 idt77252_write_gp(card, gp | clktab[j++] | 431 (offset & 1 ? SAR_GP_EEDO : 0)); 432 udelay(5); 433 434 offset >>= 1; 435 } 436 idt77252_write_gp(card, gp | SAR_GP_EECS); 437 udelay(5); 438 439 byte = 0; 440 for (i = 0, j = 0; i < 8; i++) { 441 byte <<= 1; 442 443 idt77252_write_gp(card, gp | clktab[j++]); 444 udelay(5); 445 446 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 447 448 idt77252_write_gp(card, gp | clktab[j++]); 449 udelay(5); 450 } 451 idt77252_write_gp(card, gp | SAR_GP_EECS); 452 udelay(5); 453 454 return byte; 455} 456 457static void 458idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 459{ 460 u32 gp; 461 int i, j; 462 463 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 464 465 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 466 idt77252_write_gp(card, gp | wrentab[i]); 467 udelay(5); 468 } 469 idt77252_write_gp(card, gp | SAR_GP_EECS); 470 udelay(5); 471 472 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 473 idt77252_write_gp(card, gp | wrtab[i]); 474 udelay(5); 475 } 476 idt77252_write_gp(card, gp | SAR_GP_EECS); 477 udelay(5); 478 479 for (i = 0, j = 0; i < 8; i++) { 480 idt77252_write_gp(card, gp | clktab[j++] | 481 (offset & 1 ? SAR_GP_EEDO : 0)); 482 udelay(5); 483 484 idt77252_write_gp(card, gp | clktab[j++] | 485 (offset & 1 ? SAR_GP_EEDO : 0)); 486 udelay(5); 487 488 offset >>= 1; 489 } 490 idt77252_write_gp(card, gp | SAR_GP_EECS); 491 udelay(5); 492 493 for (i = 0, j = 0; i < 8; i++) { 494 idt77252_write_gp(card, gp | clktab[j++] | 495 (data & 1 ? SAR_GP_EEDO : 0)); 496 udelay(5); 497 498 idt77252_write_gp(card, gp | clktab[j++] | 499 (data & 1 ? SAR_GP_EEDO : 0)); 500 udelay(5); 501 502 data >>= 1; 503 } 504 idt77252_write_gp(card, gp | SAR_GP_EECS); 505 udelay(5); 506} 507 508static void 509idt77252_eeprom_init(struct idt77252_dev *card) 510{ 511 u32 gp; 512 513 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 514 515 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 516 udelay(5); 517 idt77252_write_gp(card, gp | SAR_GP_EECS); 518 udelay(5); 519 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 520 udelay(5); 521 idt77252_write_gp(card, gp | SAR_GP_EECS); 522 udelay(5); 523} 524#endif /* HAVE_EEPROM */ 525 526 527#ifdef CONFIG_ATM_IDT77252_DEBUG 528static void 529dump_tct(struct idt77252_dev *card, int index) 530{ 531 unsigned long tct; 532 int i; 533 534 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 535 536 printk("%s: TCT %x:", card->name, index); 537 for (i = 0; i < 8; i++) { 538 printk(" %08x", read_sram(card, tct + i)); 539 } 540 printk("\n"); 541} 542 543static void 544idt77252_tx_dump(struct idt77252_dev *card) 545{ 546 struct atm_vcc *vcc; 547 struct vc_map *vc; 548 int i; 549 550 printk("%s\n", __FUNCTION__); 551 for (i = 0; i < card->tct_size; i++) { 552 vc = card->vcs[i]; 553 if (!vc) 554 continue; 555 556 vcc = NULL; 557 if (vc->rx_vcc) 558 vcc = vc->rx_vcc; 559 else if (vc->tx_vcc) 560 vcc = vc->tx_vcc; 561 562 if (!vcc) 563 continue; 564 565 printk("%s: Connection %d:\n", card->name, vc->index); 566 dump_tct(card, vc->index); 567 } 568} 569#endif 570 571 572/*****************************************************************************/ 573/* */ 574/* SCQ Handling */ 575/* */ 576/*****************************************************************************/ 577 578static int 579sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 580{ 581 struct sb_pool *pool = &card->sbpool[queue]; 582 int index; 583 584 index = pool->index; 585 while (pool->skb[index]) { 586 index = (index + 1) & FBQ_MASK; 587 if (index == pool->index) 588 return -ENOBUFS; 589 } 590 591 pool->skb[index] = skb; 592 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 593 594 pool->index = (index + 1) & FBQ_MASK; 595 return 0; 596} 597 598static void 599sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 600{ 601 unsigned int queue, index; 602 u32 handle; 603 604 handle = IDT77252_PRV_POOL(skb); 605 606 queue = POOL_QUEUE(handle); 607 if (queue > 3) 608 return; 609 610 index = POOL_INDEX(handle); 611 if (index > FBQ_SIZE - 1) 612 return; 613 614 card->sbpool[queue].skb[index] = NULL; 615} 616 617static struct sk_buff * 618sb_pool_skb(struct idt77252_dev *card, u32 handle) 619{ 620 unsigned int queue, index; 621 622 queue = POOL_QUEUE(handle); 623 if (queue > 3) 624 return NULL; 625 626 index = POOL_INDEX(handle); 627 if (index > FBQ_SIZE - 1) 628 return NULL; 629 630 return card->sbpool[queue].skb[index]; 631} 632 633static struct scq_info * 634alloc_scq(struct idt77252_dev *card, int class) 635{ 636 struct scq_info *scq; 637 638 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 639 if (!scq) 640 return NULL; 641 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 642 &scq->paddr); 643 if (scq->base == NULL) { 644 kfree(scq); 645 return NULL; 646 } 647 memset(scq->base, 0, SCQ_SIZE); 648 649 scq->next = scq->base; 650 scq->last = scq->base + (SCQ_ENTRIES - 1); 651 atomic_set(&scq->used, 0); 652 653 spin_lock_init(&scq->lock); 654 spin_lock_init(&scq->skblock); 655 656 skb_queue_head_init(&scq->transmit); 657 skb_queue_head_init(&scq->pending); 658 659 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 660 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 661 662 return scq; 663} 664 665static void 666free_scq(struct idt77252_dev *card, struct scq_info *scq) 667{ 668 struct sk_buff *skb; 669 struct atm_vcc *vcc; 670 671 pci_free_consistent(card->pcidev, SCQ_SIZE, 672 scq->base, scq->paddr); 673 674 while ((skb = skb_dequeue(&scq->transmit))) { 675 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 676 skb->len, PCI_DMA_TODEVICE); 677 678 vcc = ATM_SKB(skb)->vcc; 679 if (vcc->pop) 680 vcc->pop(vcc, skb); 681 else 682 dev_kfree_skb(skb); 683 } 684 685 while ((skb = skb_dequeue(&scq->pending))) { 686 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 687 skb->len, PCI_DMA_TODEVICE); 688 689 vcc = ATM_SKB(skb)->vcc; 690 if (vcc->pop) 691 vcc->pop(vcc, skb); 692 else 693 dev_kfree_skb(skb); 694 } 695 696 kfree(scq); 697} 698 699 700static int 701push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 702{ 703 struct scq_info *scq = vc->scq; 704 unsigned long flags; 705 struct scqe *tbd; 706 int entries; 707 708 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 709 710 atomic_inc(&scq->used); 711 entries = atomic_read(&scq->used); 712 if (entries > (SCQ_ENTRIES - 1)) { 713 atomic_dec(&scq->used); 714 goto out; 715 } 716 717 skb_queue_tail(&scq->transmit, skb); 718 719 spin_lock_irqsave(&vc->lock, flags); 720 if (vc->estimator) { 721 struct atm_vcc *vcc = vc->tx_vcc; 722 struct sock *sk = sk_atm(vcc); 723 724 vc->estimator->cells += (skb->len + 47) / 48; 725 if (atomic_read(&sk->sk_wmem_alloc) > 726 (sk->sk_sndbuf >> 1)) { 727 u32 cps = vc->estimator->maxcps; 728 729 vc->estimator->cps = cps; 730 vc->estimator->avcps = cps << 5; 731 if (vc->lacr < vc->init_er) { 732 vc->lacr = vc->init_er; 733 writel(TCMDQ_LACR | (vc->lacr << 16) | 734 vc->index, SAR_REG_TCMDQ); 735 } 736 } 737 } 738 spin_unlock_irqrestore(&vc->lock, flags); 739 740 tbd = &IDT77252_PRV_TBD(skb); 741 742 spin_lock_irqsave(&scq->lock, flags); 743 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 744 SAR_TBD_TSIF | SAR_TBD_GTSI); 745 scq->next->word_2 = cpu_to_le32(tbd->word_2); 746 scq->next->word_3 = cpu_to_le32(tbd->word_3); 747 scq->next->word_4 = cpu_to_le32(tbd->word_4); 748 749 if (scq->next == scq->last) 750 scq->next = scq->base; 751 else 752 scq->next++; 753 754 write_sram(card, scq->scd, 755 scq->paddr + 756 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 757 spin_unlock_irqrestore(&scq->lock, flags); 758 759 scq->trans_start = jiffies; 760 761 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 762 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 763 SAR_REG_TCMDQ); 764 } 765 766 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 767 768 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 769 card->name, atomic_read(&scq->used), 770 read_sram(card, scq->scd + 1), scq->next); 771 772 return 0; 773 774out: 775 if (time_after(jiffies, scq->trans_start + HZ)) { 776 printk("%s: Error pushing TBD for %d.%d\n", 777 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 778#ifdef CONFIG_ATM_IDT77252_DEBUG 779 idt77252_tx_dump(card); 780#endif 781 scq->trans_start = jiffies; 782 } 783 784 return -ENOBUFS; 785} 786 787 788static void 789drain_scq(struct idt77252_dev *card, struct vc_map *vc) 790{ 791 struct scq_info *scq = vc->scq; 792 struct sk_buff *skb; 793 struct atm_vcc *vcc; 794 795 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 796 card->name, atomic_read(&scq->used), scq->next); 797 798 skb = skb_dequeue(&scq->transmit); 799 if (skb) { 800 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 801 802 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 803 skb->len, PCI_DMA_TODEVICE); 804 805 vcc = ATM_SKB(skb)->vcc; 806 807 if (vcc->pop) 808 vcc->pop(vcc, skb); 809 else 810 dev_kfree_skb(skb); 811 812 atomic_inc(&vcc->stats->tx); 813 } 814 815 atomic_dec(&scq->used); 816 817 spin_lock(&scq->skblock); 818 while ((skb = skb_dequeue(&scq->pending))) { 819 if (push_on_scq(card, vc, skb)) { 820 skb_queue_head(&vc->scq->pending, skb); 821 break; 822 } 823 } 824 spin_unlock(&scq->skblock); 825} 826 827static int 828queue_skb(struct idt77252_dev *card, struct vc_map *vc, 829 struct sk_buff *skb, int oam) 830{ 831 struct atm_vcc *vcc; 832 struct scqe *tbd; 833 unsigned long flags; 834 int error; 835 int aal; 836 837 if (skb->len == 0) { 838 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 839 return -EINVAL; 840 } 841 842 TXPRINTK("%s: Sending %d bytes of data.\n", 843 card->name, skb->len); 844 845 tbd = &IDT77252_PRV_TBD(skb); 846 vcc = ATM_SKB(skb)->vcc; 847 848 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 849 skb->len, PCI_DMA_TODEVICE); 850 851 error = -EINVAL; 852 853 if (oam) { 854 if (skb->len != 52) 855 goto errout; 856 857 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 858 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 859 tbd->word_3 = 0x00000000; 860 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 861 (skb->data[2] << 8) | (skb->data[3] << 0); 862 863 if (test_bit(VCF_RSV, &vc->flags)) 864 vc = card->vcs[0]; 865 866 goto done; 867 } 868 869 if (test_bit(VCF_RSV, &vc->flags)) { 870 printk("%s: Trying to transmit on reserved VC\n", card->name); 871 goto errout; 872 } 873 874 aal = vcc->qos.aal; 875 876 switch (aal) { 877 case ATM_AAL0: 878 case ATM_AAL34: 879 if (skb->len > 52) 880 goto errout; 881 882 if (aal == ATM_AAL0) 883 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 884 ATM_CELL_PAYLOAD; 885 else 886 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 887 ATM_CELL_PAYLOAD; 888 889 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 890 tbd->word_3 = 0x00000000; 891 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 892 (skb->data[2] << 8) | (skb->data[3] << 0); 893 break; 894 895 case ATM_AAL5: 896 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 897 tbd->word_2 = IDT77252_PRV_PADDR(skb); 898 tbd->word_3 = skb->len; 899 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 900 (vcc->vci << SAR_TBD_VCI_SHIFT); 901 break; 902 903 case ATM_AAL1: 904 case ATM_AAL2: 905 default: 906 printk("%s: Traffic type not supported.\n", card->name); 907 error = -EPROTONOSUPPORT; 908 goto errout; 909 } 910 911done: 912 spin_lock_irqsave(&vc->scq->skblock, flags); 913 skb_queue_tail(&vc->scq->pending, skb); 914 915 while ((skb = skb_dequeue(&vc->scq->pending))) { 916 if (push_on_scq(card, vc, skb)) { 917 skb_queue_head(&vc->scq->pending, skb); 918 break; 919 } 920 } 921 spin_unlock_irqrestore(&vc->scq->skblock, flags); 922 923 return 0; 924 925errout: 926 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 927 skb->len, PCI_DMA_TODEVICE); 928 return error; 929} 930 931static unsigned long 932get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 933{ 934 int i; 935 936 for (i = 0; i < card->scd_size; i++) { 937 if (!card->scd2vc[i]) { 938 card->scd2vc[i] = vc; 939 vc->scd_index = i; 940 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 941 } 942 } 943 return 0; 944} 945 946static void 947fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 948{ 949 write_sram(card, scq->scd, scq->paddr); 950 write_sram(card, scq->scd + 1, 0x00000000); 951 write_sram(card, scq->scd + 2, 0xffffffff); 952 write_sram(card, scq->scd + 3, 0x00000000); 953} 954 955static void 956clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 957{ 958 return; 959} 960 961/*****************************************************************************/ 962/* */ 963/* RSQ Handling */ 964/* */ 965/*****************************************************************************/ 966 967static int 968init_rsq(struct idt77252_dev *card) 969{ 970 struct rsq_entry *rsqe; 971 972 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 973 &card->rsq.paddr); 974 if (card->rsq.base == NULL) { 975 printk("%s: can't allocate RSQ.\n", card->name); 976 return -1; 977 } 978 memset(card->rsq.base, 0, RSQSIZE); 979 980 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 981 card->rsq.next = card->rsq.last; 982 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 983 rsqe->word_4 = 0; 984 985 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 986 SAR_REG_RSQH); 987 writel(card->rsq.paddr, SAR_REG_RSQB); 988 989 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 990 (unsigned long) card->rsq.base, 991 readl(SAR_REG_RSQB)); 992 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 993 card->name, 994 readl(SAR_REG_RSQH), 995 readl(SAR_REG_RSQB), 996 readl(SAR_REG_RSQT)); 997 998 return 0; 999} 1000 1001static void 1002deinit_rsq(struct idt77252_dev *card) 1003{ 1004 pci_free_consistent(card->pcidev, RSQSIZE, 1005 card->rsq.base, card->rsq.paddr); 1006} 1007 1008static void 1009dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1010{ 1011 struct atm_vcc *vcc; 1012 struct sk_buff *skb; 1013 struct rx_pool *rpp; 1014 struct vc_map *vc; 1015 u32 header, vpi, vci; 1016 u32 stat; 1017 int i; 1018 1019 stat = le32_to_cpu(rsqe->word_4); 1020 1021 if (stat & SAR_RSQE_IDLE) { 1022 RXPRINTK("%s: message about inactive connection.\n", 1023 card->name); 1024 return; 1025 } 1026 1027 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1028 if (skb == NULL) { 1029 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1030 card->name, __FUNCTION__, 1031 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1032 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1033 return; 1034 } 1035 1036 header = le32_to_cpu(rsqe->word_1); 1037 vpi = (header >> 16) & 0x00ff; 1038 vci = (header >> 0) & 0xffff; 1039 1040 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1041 card->name, vpi, vci, skb, skb->data); 1042 1043 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1044 printk("%s: SDU received for out-of-range vc %u.%u\n", 1045 card->name, vpi, vci); 1046 recycle_rx_skb(card, skb); 1047 return; 1048 } 1049 1050 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1051 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1052 printk("%s: SDU received on non RX vc %u.%u\n", 1053 card->name, vpi, vci); 1054 recycle_rx_skb(card, skb); 1055 return; 1056 } 1057 1058 vcc = vc->rx_vcc; 1059 1060 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1061 skb_end_pointer(skb) - skb->data, 1062 PCI_DMA_FROMDEVICE); 1063 1064 if ((vcc->qos.aal == ATM_AAL0) || 1065 (vcc->qos.aal == ATM_AAL34)) { 1066 struct sk_buff *sb; 1067 unsigned char *cell; 1068 u32 aal0; 1069 1070 cell = skb->data; 1071 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1072 if ((sb = dev_alloc_skb(64)) == NULL) { 1073 printk("%s: Can't allocate buffers for aal0.\n", 1074 card->name); 1075 atomic_add(i, &vcc->stats->rx_drop); 1076 break; 1077 } 1078 if (!atm_charge(vcc, sb->truesize)) { 1079 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1080 card->name); 1081 atomic_add(i - 1, &vcc->stats->rx_drop); 1082 dev_kfree_skb(sb); 1083 break; 1084 } 1085 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1086 (vci << ATM_HDR_VCI_SHIFT); 1087 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1088 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1089 1090 *((u32 *) sb->data) = aal0; 1091 skb_put(sb, sizeof(u32)); 1092 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1093 cell, ATM_CELL_PAYLOAD); 1094 1095 ATM_SKB(sb)->vcc = vcc; 1096 __net_timestamp(sb); 1097 vcc->push(vcc, sb); 1098 atomic_inc(&vcc->stats->rx); 1099 1100 cell += ATM_CELL_PAYLOAD; 1101 } 1102 1103 recycle_rx_skb(card, skb); 1104 return; 1105 } 1106 if (vcc->qos.aal != ATM_AAL5) { 1107 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1108 card->name, vcc->qos.aal); 1109 recycle_rx_skb(card, skb); 1110 return; 1111 } 1112 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1113 1114 rpp = &vc->rcv.rx_pool; 1115 1116 rpp->len += skb->len; 1117 if (!rpp->count++) 1118 rpp->first = skb; 1119 *rpp->last = skb; 1120 rpp->last = &skb->next; 1121 1122 if (stat & SAR_RSQE_EPDU) { 1123 unsigned char *l1l2; 1124 unsigned int len; 1125 1126 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1127 1128 len = (l1l2[0] << 8) | l1l2[1]; 1129 len = len ? len : 0x10000; 1130 1131 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1132 1133 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1134 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1135 "(CDC: %08x)\n", 1136 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1137 recycle_rx_pool_skb(card, rpp); 1138 atomic_inc(&vcc->stats->rx_err); 1139 return; 1140 } 1141 if (stat & SAR_RSQE_CRC) { 1142 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1143 recycle_rx_pool_skb(card, rpp); 1144 atomic_inc(&vcc->stats->rx_err); 1145 return; 1146 } 1147 if (rpp->count > 1) { 1148 struct sk_buff *sb; 1149 1150 skb = dev_alloc_skb(rpp->len); 1151 if (!skb) { 1152 RXPRINTK("%s: Can't alloc RX skb.\n", 1153 card->name); 1154 recycle_rx_pool_skb(card, rpp); 1155 atomic_inc(&vcc->stats->rx_err); 1156 return; 1157 } 1158 if (!atm_charge(vcc, skb->truesize)) { 1159 recycle_rx_pool_skb(card, rpp); 1160 dev_kfree_skb(skb); 1161 return; 1162 } 1163 sb = rpp->first; 1164 for (i = 0; i < rpp->count; i++) { 1165 memcpy(skb_put(skb, sb->len), 1166 sb->data, sb->len); 1167 sb = sb->next; 1168 } 1169 1170 recycle_rx_pool_skb(card, rpp); 1171 1172 skb_trim(skb, len); 1173 ATM_SKB(skb)->vcc = vcc; 1174 __net_timestamp(skb); 1175 1176 vcc->push(vcc, skb); 1177 atomic_inc(&vcc->stats->rx); 1178 1179 return; 1180 } 1181 1182 skb->next = NULL; 1183 flush_rx_pool(card, rpp); 1184 1185 if (!atm_charge(vcc, skb->truesize)) { 1186 recycle_rx_skb(card, skb); 1187 return; 1188 } 1189 1190 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1191 skb_end_pointer(skb) - skb->data, 1192 PCI_DMA_FROMDEVICE); 1193 sb_pool_remove(card, skb); 1194 1195 skb_trim(skb, len); 1196 ATM_SKB(skb)->vcc = vcc; 1197 __net_timestamp(skb); 1198 1199 vcc->push(vcc, skb); 1200 atomic_inc(&vcc->stats->rx); 1201 1202 if (skb->truesize > SAR_FB_SIZE_3) 1203 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1204 else if (skb->truesize > SAR_FB_SIZE_2) 1205 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1206 else if (skb->truesize > SAR_FB_SIZE_1) 1207 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1208 else 1209 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1210 return; 1211 } 1212} 1213 1214static void 1215idt77252_rx(struct idt77252_dev *card) 1216{ 1217 struct rsq_entry *rsqe; 1218 1219 if (card->rsq.next == card->rsq.last) 1220 rsqe = card->rsq.base; 1221 else 1222 rsqe = card->rsq.next + 1; 1223 1224 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1225 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1226 return; 1227 } 1228 1229 do { 1230 dequeue_rx(card, rsqe); 1231 rsqe->word_4 = 0; 1232 card->rsq.next = rsqe; 1233 if (card->rsq.next == card->rsq.last) 1234 rsqe = card->rsq.base; 1235 else 1236 rsqe = card->rsq.next + 1; 1237 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1238 1239 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1240 SAR_REG_RSQH); 1241} 1242 1243static void 1244idt77252_rx_raw(struct idt77252_dev *card) 1245{ 1246 struct sk_buff *queue; 1247 u32 head, tail; 1248 struct atm_vcc *vcc; 1249 struct vc_map *vc; 1250 struct sk_buff *sb; 1251 1252 if (card->raw_cell_head == NULL) { 1253 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1254 card->raw_cell_head = sb_pool_skb(card, handle); 1255 } 1256 1257 queue = card->raw_cell_head; 1258 if (!queue) 1259 return; 1260 1261 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1262 tail = readl(SAR_REG_RAWCT); 1263 1264 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1265 skb_end_pointer(queue) - queue->head - 16, 1266 PCI_DMA_FROMDEVICE); 1267 1268 while (head != tail) { 1269 unsigned int vpi, vci, pti; 1270 u32 header; 1271 1272 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1273 1274 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1275 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1276 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; 1277 1278#ifdef CONFIG_ATM_IDT77252_DEBUG 1279 if (debug & DBG_RAW_CELL) { 1280 int i; 1281 1282 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1283 card->name, (header >> 28) & 0x000f, 1284 (header >> 20) & 0x00ff, 1285 (header >> 4) & 0xffff, 1286 (header >> 1) & 0x0007, 1287 (header >> 0) & 0x0001); 1288 for (i = 16; i < 64; i++) 1289 printk(" %02x", queue->data[i]); 1290 printk("\n"); 1291 } 1292#endif 1293 1294 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1295 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1296 card->name, vpi, vci); 1297 goto drop; 1298 } 1299 1300 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1301 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1302 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1303 card->name, vpi, vci); 1304 goto drop; 1305 } 1306 1307 vcc = vc->rx_vcc; 1308 1309 if (vcc->qos.aal != ATM_AAL0) { 1310 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1311 card->name, vpi, vci); 1312 atomic_inc(&vcc->stats->rx_drop); 1313 goto drop; 1314 } 1315 1316 if ((sb = dev_alloc_skb(64)) == NULL) { 1317 printk("%s: Can't allocate buffers for AAL0.\n", 1318 card->name); 1319 atomic_inc(&vcc->stats->rx_err); 1320 goto drop; 1321 } 1322 1323 if (!atm_charge(vcc, sb->truesize)) { 1324 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1325 card->name); 1326 dev_kfree_skb(sb); 1327 goto drop; 1328 } 1329 1330 *((u32 *) sb->data) = header; 1331 skb_put(sb, sizeof(u32)); 1332 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1333 ATM_CELL_PAYLOAD); 1334 1335 ATM_SKB(sb)->vcc = vcc; 1336 __net_timestamp(sb); 1337 vcc->push(vcc, sb); 1338 atomic_inc(&vcc->stats->rx); 1339 1340drop: 1341 skb_pull(queue, 64); 1342 1343 head = IDT77252_PRV_PADDR(queue) 1344 + (queue->data - queue->head - 16); 1345 1346 if (queue->len < 128) { 1347 struct sk_buff *next; 1348 u32 handle; 1349 1350 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1351 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1352 1353 next = sb_pool_skb(card, handle); 1354 recycle_rx_skb(card, queue); 1355 1356 if (next) { 1357 card->raw_cell_head = next; 1358 queue = card->raw_cell_head; 1359 pci_dma_sync_single_for_cpu(card->pcidev, 1360 IDT77252_PRV_PADDR(queue), 1361 (skb_end_pointer(queue) - 1362 queue->data), 1363 PCI_DMA_FROMDEVICE); 1364 } else { 1365 card->raw_cell_head = NULL; 1366 printk("%s: raw cell queue overrun\n", 1367 card->name); 1368 break; 1369 } 1370 } 1371 } 1372} 1373 1374 1375/*****************************************************************************/ 1376/* */ 1377/* TSQ Handling */ 1378/* */ 1379/*****************************************************************************/ 1380 1381static int 1382init_tsq(struct idt77252_dev *card) 1383{ 1384 struct tsq_entry *tsqe; 1385 1386 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1387 &card->tsq.paddr); 1388 if (card->tsq.base == NULL) { 1389 printk("%s: can't allocate TSQ.\n", card->name); 1390 return -1; 1391 } 1392 memset(card->tsq.base, 0, TSQSIZE); 1393 1394 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1395 card->tsq.next = card->tsq.last; 1396 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1397 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1398 1399 writel(card->tsq.paddr, SAR_REG_TSQB); 1400 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1401 SAR_REG_TSQH); 1402 1403 return 0; 1404} 1405 1406static void 1407deinit_tsq(struct idt77252_dev *card) 1408{ 1409 pci_free_consistent(card->pcidev, TSQSIZE, 1410 card->tsq.base, card->tsq.paddr); 1411} 1412 1413static void 1414idt77252_tx(struct idt77252_dev *card) 1415{ 1416 struct tsq_entry *tsqe; 1417 unsigned int vpi, vci; 1418 struct vc_map *vc; 1419 u32 conn, stat; 1420 1421 if (card->tsq.next == card->tsq.last) 1422 tsqe = card->tsq.base; 1423 else 1424 tsqe = card->tsq.next + 1; 1425 1426 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1427 card->tsq.base, card->tsq.next, card->tsq.last); 1428 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1429 readl(SAR_REG_TSQB), 1430 readl(SAR_REG_TSQT), 1431 readl(SAR_REG_TSQH)); 1432 1433 stat = le32_to_cpu(tsqe->word_2); 1434 1435 if (stat & SAR_TSQE_INVALID) 1436 return; 1437 1438 do { 1439 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1440 le32_to_cpu(tsqe->word_1), 1441 le32_to_cpu(tsqe->word_2)); 1442 1443 switch (stat & SAR_TSQE_TYPE) { 1444 case SAR_TSQE_TYPE_TIMER: 1445 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1446 break; 1447 1448 case SAR_TSQE_TYPE_IDLE: 1449 1450 conn = le32_to_cpu(tsqe->word_1); 1451 1452 if (SAR_TSQE_TAG(stat) == 0x10) { 1453#ifdef NOTDEF 1454 printk("%s: Connection %d halted.\n", 1455 card->name, 1456 le32_to_cpu(tsqe->word_1) & 0x1fff); 1457#endif 1458 break; 1459 } 1460 1461 vc = card->vcs[conn & 0x1fff]; 1462 if (!vc) { 1463 printk("%s: could not find VC from conn %d\n", 1464 card->name, conn & 0x1fff); 1465 break; 1466 } 1467 1468 printk("%s: Connection %d IDLE.\n", 1469 card->name, vc->index); 1470 1471 set_bit(VCF_IDLE, &vc->flags); 1472 break; 1473 1474 case SAR_TSQE_TYPE_TSR: 1475 1476 conn = le32_to_cpu(tsqe->word_1); 1477 1478 vc = card->vcs[conn & 0x1fff]; 1479 if (!vc) { 1480 printk("%s: no VC at index %d\n", 1481 card->name, 1482 le32_to_cpu(tsqe->word_1) & 0x1fff); 1483 break; 1484 } 1485 1486 drain_scq(card, vc); 1487 break; 1488 1489 case SAR_TSQE_TYPE_TBD_COMP: 1490 1491 conn = le32_to_cpu(tsqe->word_1); 1492 1493 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1494 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1495 1496 if (vpi >= (1 << card->vpibits) || 1497 vci >= (1 << card->vcibits)) { 1498 printk("%s: TBD complete: " 1499 "out of range VPI.VCI %u.%u\n", 1500 card->name, vpi, vci); 1501 break; 1502 } 1503 1504 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1505 if (!vc) { 1506 printk("%s: TBD complete: " 1507 "no VC at VPI.VCI %u.%u\n", 1508 card->name, vpi, vci); 1509 break; 1510 } 1511 1512 drain_scq(card, vc); 1513 break; 1514 } 1515 1516 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1517 1518 card->tsq.next = tsqe; 1519 if (card->tsq.next == card->tsq.last) 1520 tsqe = card->tsq.base; 1521 else 1522 tsqe = card->tsq.next + 1; 1523 1524 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1525 card->tsq.base, card->tsq.next, card->tsq.last); 1526 1527 stat = le32_to_cpu(tsqe->word_2); 1528 1529 } while (!(stat & SAR_TSQE_INVALID)); 1530 1531 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1532 SAR_REG_TSQH); 1533 1534 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1535 card->index, readl(SAR_REG_TSQH), 1536 readl(SAR_REG_TSQT), card->tsq.next); 1537} 1538 1539 1540static void 1541tst_timer(unsigned long data) 1542{ 1543 struct idt77252_dev *card = (struct idt77252_dev *)data; 1544 unsigned long base, idle, jump; 1545 unsigned long flags; 1546 u32 pc; 1547 int e; 1548 1549 spin_lock_irqsave(&card->tst_lock, flags); 1550 1551 base = card->tst[card->tst_index]; 1552 idle = card->tst[card->tst_index ^ 1]; 1553 1554 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1555 jump = base + card->tst_size - 2; 1556 1557 pc = readl(SAR_REG_NOW) >> 2; 1558 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1559 mod_timer(&card->tst_timer, jiffies + 1); 1560 goto out; 1561 } 1562 1563 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1564 1565 card->tst_index ^= 1; 1566 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1567 1568 base = card->tst[card->tst_index]; 1569 idle = card->tst[card->tst_index ^ 1]; 1570 1571 for (e = 0; e < card->tst_size - 2; e++) { 1572 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1573 write_sram(card, idle + e, 1574 card->soft_tst[e].tste & TSTE_MASK); 1575 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1576 } 1577 } 1578 } 1579 1580 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1581 1582 for (e = 0; e < card->tst_size - 2; e++) { 1583 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1584 write_sram(card, idle + e, 1585 card->soft_tst[e].tste & TSTE_MASK); 1586 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1587 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1588 } 1589 } 1590 1591 jump = base + card->tst_size - 2; 1592 1593 write_sram(card, jump, TSTE_OPC_NULL); 1594 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1595 1596 mod_timer(&card->tst_timer, jiffies + 1); 1597 } 1598 1599out: 1600 spin_unlock_irqrestore(&card->tst_lock, flags); 1601} 1602 1603static int 1604__fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1605 int n, unsigned int opc) 1606{ 1607 unsigned long cl, avail; 1608 unsigned long idle; 1609 int e, r; 1610 u32 data; 1611 1612 avail = card->tst_size - 2; 1613 for (e = 0; e < avail; e++) { 1614 if (card->soft_tst[e].vc == NULL) 1615 break; 1616 } 1617 if (e >= avail) { 1618 printk("%s: No free TST entries found\n", card->name); 1619 return -1; 1620 } 1621 1622 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1623 card->name, vc ? vc->index : -1, e); 1624 1625 r = n; 1626 cl = avail; 1627 data = opc & TSTE_OPC_MASK; 1628 if (vc && (opc != TSTE_OPC_NULL)) 1629 data = opc | vc->index; 1630 1631 idle = card->tst[card->tst_index ^ 1]; 1632 1633 /* 1634 * Fill Soft TST. 1635 */ 1636 while (r > 0) { 1637 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1638 if (vc) 1639 card->soft_tst[e].vc = vc; 1640 else 1641 card->soft_tst[e].vc = (void *)-1; 1642 1643 card->soft_tst[e].tste = data; 1644 if (timer_pending(&card->tst_timer)) 1645 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1646 else { 1647 write_sram(card, idle + e, data); 1648 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1649 } 1650 1651 cl -= card->tst_size; 1652 r--; 1653 } 1654 1655 if (++e == avail) 1656 e = 0; 1657 cl += n; 1658 } 1659 1660 return 0; 1661} 1662 1663static int 1664fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1665{ 1666 unsigned long flags; 1667 int res; 1668 1669 spin_lock_irqsave(&card->tst_lock, flags); 1670 1671 res = __fill_tst(card, vc, n, opc); 1672 1673 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1674 if (!timer_pending(&card->tst_timer)) 1675 mod_timer(&card->tst_timer, jiffies + 1); 1676 1677 spin_unlock_irqrestore(&card->tst_lock, flags); 1678 return res; 1679} 1680 1681static int 1682__clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1683{ 1684 unsigned long idle; 1685 int e; 1686 1687 idle = card->tst[card->tst_index ^ 1]; 1688 1689 for (e = 0; e < card->tst_size - 2; e++) { 1690 if (card->soft_tst[e].vc == vc) { 1691 card->soft_tst[e].vc = NULL; 1692 1693 card->soft_tst[e].tste = TSTE_OPC_VAR; 1694 if (timer_pending(&card->tst_timer)) 1695 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1696 else { 1697 write_sram(card, idle + e, TSTE_OPC_VAR); 1698 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1699 } 1700 } 1701 } 1702 1703 return 0; 1704} 1705 1706static int 1707clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1708{ 1709 unsigned long flags; 1710 int res; 1711 1712 spin_lock_irqsave(&card->tst_lock, flags); 1713 1714 res = __clear_tst(card, vc); 1715 1716 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1717 if (!timer_pending(&card->tst_timer)) 1718 mod_timer(&card->tst_timer, jiffies + 1); 1719 1720 spin_unlock_irqrestore(&card->tst_lock, flags); 1721 return res; 1722} 1723 1724static int 1725change_tst(struct idt77252_dev *card, struct vc_map *vc, 1726 int n, unsigned int opc) 1727{ 1728 unsigned long flags; 1729 int res; 1730 1731 spin_lock_irqsave(&card->tst_lock, flags); 1732 1733 __clear_tst(card, vc); 1734 res = __fill_tst(card, vc, n, opc); 1735 1736 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1737 if (!timer_pending(&card->tst_timer)) 1738 mod_timer(&card->tst_timer, jiffies + 1); 1739 1740 spin_unlock_irqrestore(&card->tst_lock, flags); 1741 return res; 1742} 1743 1744 1745static int 1746set_tct(struct idt77252_dev *card, struct vc_map *vc) 1747{ 1748 unsigned long tct; 1749 1750 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1751 1752 switch (vc->class) { 1753 case SCHED_CBR: 1754 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1755 card->name, tct, vc->scq->scd); 1756 1757 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1758 write_sram(card, tct + 1, 0); 1759 write_sram(card, tct + 2, 0); 1760 write_sram(card, tct + 3, 0); 1761 write_sram(card, tct + 4, 0); 1762 write_sram(card, tct + 5, 0); 1763 write_sram(card, tct + 6, 0); 1764 write_sram(card, tct + 7, 0); 1765 break; 1766 1767 case SCHED_UBR: 1768 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1769 card->name, tct, vc->scq->scd); 1770 1771 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1772 write_sram(card, tct + 1, 0); 1773 write_sram(card, tct + 2, TCT_TSIF); 1774 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1775 write_sram(card, tct + 4, 0); 1776 write_sram(card, tct + 5, vc->init_er); 1777 write_sram(card, tct + 6, 0); 1778 write_sram(card, tct + 7, TCT_FLAG_UBR); 1779 break; 1780 1781 case SCHED_VBR: 1782 case SCHED_ABR: 1783 default: 1784 return -ENOSYS; 1785 } 1786 1787 return 0; 1788} 1789 1790/*****************************************************************************/ 1791/* */ 1792/* FBQ Handling */ 1793/* */ 1794/*****************************************************************************/ 1795 1796static __inline__ int 1797idt77252_fbq_level(struct idt77252_dev *card, int queue) 1798{ 1799 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1800} 1801 1802static __inline__ int 1803idt77252_fbq_full(struct idt77252_dev *card, int queue) 1804{ 1805 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1806} 1807 1808static int 1809push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1810{ 1811 unsigned long flags; 1812 u32 handle; 1813 u32 addr; 1814 1815 skb->data = skb->head; 1816 skb_reset_tail_pointer(skb); 1817 skb->len = 0; 1818 1819 skb_reserve(skb, 16); 1820 1821 switch (queue) { 1822 case 0: 1823 skb_put(skb, SAR_FB_SIZE_0); 1824 break; 1825 case 1: 1826 skb_put(skb, SAR_FB_SIZE_1); 1827 break; 1828 case 2: 1829 skb_put(skb, SAR_FB_SIZE_2); 1830 break; 1831 case 3: 1832 skb_put(skb, SAR_FB_SIZE_3); 1833 break; 1834 default: 1835 return -1; 1836 } 1837 1838 if (idt77252_fbq_full(card, queue)) 1839 return -1; 1840 1841 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1842 1843 handle = IDT77252_PRV_POOL(skb); 1844 addr = IDT77252_PRV_PADDR(skb); 1845 1846 spin_lock_irqsave(&card->cmd_lock, flags); 1847 writel(handle, card->fbq[queue]); 1848 writel(addr, card->fbq[queue]); 1849 spin_unlock_irqrestore(&card->cmd_lock, flags); 1850 1851 return 0; 1852} 1853 1854static void 1855add_rx_skb(struct idt77252_dev *card, int queue, 1856 unsigned int size, unsigned int count) 1857{ 1858 struct sk_buff *skb; 1859 dma_addr_t paddr; 1860 u32 handle; 1861 1862 while (count--) { 1863 skb = dev_alloc_skb(size); 1864 if (!skb) 1865 return; 1866 1867 if (sb_pool_add(card, skb, queue)) { 1868 printk("%s: SB POOL full\n", __FUNCTION__); 1869 goto outfree; 1870 } 1871 1872 paddr = pci_map_single(card->pcidev, skb->data, 1873 skb_end_pointer(skb) - skb->data, 1874 PCI_DMA_FROMDEVICE); 1875 IDT77252_PRV_PADDR(skb) = paddr; 1876 1877 if (push_rx_skb(card, skb, queue)) { 1878 printk("%s: FB QUEUE full\n", __FUNCTION__); 1879 goto outunmap; 1880 } 1881 } 1882 1883 return; 1884 1885outunmap: 1886 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1887 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE); 1888 1889 handle = IDT77252_PRV_POOL(skb); 1890 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1891 1892outfree: 1893 dev_kfree_skb(skb); 1894} 1895 1896 1897static void 1898recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1899{ 1900 u32 handle = IDT77252_PRV_POOL(skb); 1901 int err; 1902 1903 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1904 skb_end_pointer(skb) - skb->data, 1905 PCI_DMA_FROMDEVICE); 1906 1907 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1908 if (err) { 1909 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1910 skb_end_pointer(skb) - skb->data, 1911 PCI_DMA_FROMDEVICE); 1912 sb_pool_remove(card, skb); 1913 dev_kfree_skb(skb); 1914 } 1915} 1916 1917static void 1918flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1919{ 1920 rpp->len = 0; 1921 rpp->count = 0; 1922 rpp->first = NULL; 1923 rpp->last = &rpp->first; 1924} 1925 1926static void 1927recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1928{ 1929 struct sk_buff *skb, *next; 1930 int i; 1931 1932 skb = rpp->first; 1933 for (i = 0; i < rpp->count; i++) { 1934 next = skb->next; 1935 skb->next = NULL; 1936 recycle_rx_skb(card, skb); 1937 skb = next; 1938 } 1939 flush_rx_pool(card, rpp); 1940} 1941 1942/*****************************************************************************/ 1943/* */ 1944/* ATM Interface */ 1945/* */ 1946/*****************************************************************************/ 1947 1948static void 1949idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1950{ 1951 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1952} 1953 1954static unsigned char 1955idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1956{ 1957 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1958} 1959 1960static inline int 1961idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1962{ 1963 struct atm_dev *dev = vcc->dev; 1964 struct idt77252_dev *card = dev->dev_data; 1965 struct vc_map *vc = vcc->dev_data; 1966 int err; 1967 1968 if (vc == NULL) { 1969 printk("%s: NULL connection in send().\n", card->name); 1970 atomic_inc(&vcc->stats->tx_err); 1971 dev_kfree_skb(skb); 1972 return -EINVAL; 1973 } 1974 if (!test_bit(VCF_TX, &vc->flags)) { 1975 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1976 atomic_inc(&vcc->stats->tx_err); 1977 dev_kfree_skb(skb); 1978 return -EINVAL; 1979 } 1980 1981 switch (vcc->qos.aal) { 1982 case ATM_AAL0: 1983 case ATM_AAL1: 1984 case ATM_AAL5: 1985 break; 1986 default: 1987 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1988 atomic_inc(&vcc->stats->tx_err); 1989 dev_kfree_skb(skb); 1990 return -EINVAL; 1991 } 1992 1993 if (skb_shinfo(skb)->nr_frags != 0) { 1994 printk("%s: No scatter-gather yet.\n", card->name); 1995 atomic_inc(&vcc->stats->tx_err); 1996 dev_kfree_skb(skb); 1997 return -EINVAL; 1998 } 1999 ATM_SKB(skb)->vcc = vcc; 2000 2001 err = queue_skb(card, vc, skb, oam); 2002 if (err) { 2003 atomic_inc(&vcc->stats->tx_err); 2004 dev_kfree_skb(skb); 2005 return err; 2006 } 2007 2008 return 0; 2009} 2010 2011int 2012idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 2013{ 2014 return idt77252_send_skb(vcc, skb, 0); 2015} 2016 2017static int 2018idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2019{ 2020 struct atm_dev *dev = vcc->dev; 2021 struct idt77252_dev *card = dev->dev_data; 2022 struct sk_buff *skb; 2023 2024 skb = dev_alloc_skb(64); 2025 if (!skb) { 2026 printk("%s: Out of memory in send_oam().\n", card->name); 2027 atomic_inc(&vcc->stats->tx_err); 2028 return -ENOMEM; 2029 } 2030 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2031 2032 memcpy(skb_put(skb, 52), cell, 52); 2033 2034 return idt77252_send_skb(vcc, skb, 1); 2035} 2036 2037static __inline__ unsigned int 2038idt77252_fls(unsigned int x) 2039{ 2040 int r = 1; 2041 2042 if (x == 0) 2043 return 0; 2044 if (x & 0xffff0000) { 2045 x >>= 16; 2046 r += 16; 2047 } 2048 if (x & 0xff00) { 2049 x >>= 8; 2050 r += 8; 2051 } 2052 if (x & 0xf0) { 2053 x >>= 4; 2054 r += 4; 2055 } 2056 if (x & 0xc) { 2057 x >>= 2; 2058 r += 2; 2059 } 2060 if (x & 0x2) 2061 r += 1; 2062 return r; 2063} 2064 2065static u16 2066idt77252_int_to_atmfp(unsigned int rate) 2067{ 2068 u16 m, e; 2069 2070 if (rate == 0) 2071 return 0; 2072 e = idt77252_fls(rate) - 1; 2073 if (e < 9) 2074 m = (rate - (1 << e)) << (9 - e); 2075 else if (e == 9) 2076 m = (rate - (1 << e)); 2077 else /* e > 9 */ 2078 m = (rate - (1 << e)) >> (e - 9); 2079 return 0x4000 | (e << 9) | m; 2080} 2081 2082static u8 2083idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2084{ 2085 u16 afp; 2086 2087 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2088 if (pcr < 0) 2089 return rate_to_log[(afp >> 5) & 0x1ff]; 2090 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2091} 2092 2093static void 2094idt77252_est_timer(unsigned long data) 2095{ 2096 struct vc_map *vc = (struct vc_map *)data; 2097 struct idt77252_dev *card = vc->card; 2098 struct rate_estimator *est; 2099 unsigned long flags; 2100 u32 rate, cps; 2101 u64 ncells; 2102 u8 lacr; 2103 2104 spin_lock_irqsave(&vc->lock, flags); 2105 est = vc->estimator; 2106 if (!est) 2107 goto out; 2108 2109 ncells = est->cells; 2110 2111 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2112 est->last_cells = ncells; 2113 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2114 est->cps = (est->avcps + 0x1f) >> 5; 2115 2116 cps = est->cps; 2117 if (cps < (est->maxcps >> 4)) 2118 cps = est->maxcps >> 4; 2119 2120 lacr = idt77252_rate_logindex(card, cps); 2121 if (lacr > vc->max_er) 2122 lacr = vc->max_er; 2123 2124 if (lacr != vc->lacr) { 2125 vc->lacr = lacr; 2126 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2127 } 2128 2129 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2130 add_timer(&est->timer); 2131 2132out: 2133 spin_unlock_irqrestore(&vc->lock, flags); 2134} 2135 2136static struct rate_estimator * 2137idt77252_init_est(struct vc_map *vc, int pcr) 2138{ 2139 struct rate_estimator *est; 2140 2141 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2142 if (!est) 2143 return NULL; 2144 est->maxcps = pcr < 0 ? -pcr : pcr; 2145 est->cps = est->maxcps; 2146 est->avcps = est->cps << 5; 2147 2148 est->interval = 2; 2149 est->ewma_log = 2; 2150 init_timer(&est->timer); 2151 est->timer.data = (unsigned long)vc; 2152 est->timer.function = idt77252_est_timer; 2153 2154 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2155 add_timer(&est->timer); 2156 2157 return est; 2158} 2159 2160static int 2161idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2162 struct atm_vcc *vcc, struct atm_qos *qos) 2163{ 2164 int tst_free, tst_used, tst_entries; 2165 unsigned long tmpl, modl; 2166 int tcr, tcra; 2167 2168 if ((qos->txtp.max_pcr == 0) && 2169 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2170 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2171 card->name); 2172 return -EINVAL; 2173 } 2174 2175 tst_used = 0; 2176 tst_free = card->tst_free; 2177 if (test_bit(VCF_TX, &vc->flags)) 2178 tst_used = vc->ntste; 2179 tst_free += tst_used; 2180 2181 tcr = atm_pcr_goal(&qos->txtp); 2182 tcra = tcr >= 0 ? tcr : -tcr; 2183 2184 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2185 2186 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2187 modl = tmpl % (unsigned long)card->utopia_pcr; 2188 2189 tst_entries = (int) (tmpl / card->utopia_pcr); 2190 if (tcr > 0) { 2191 if (modl > 0) 2192 tst_entries++; 2193 } else if (tcr == 0) { 2194 tst_entries = tst_free - SAR_TST_RESERVED; 2195 if (tst_entries <= 0) { 2196 printk("%s: no CBR bandwidth free.\n", card->name); 2197 return -ENOSR; 2198 } 2199 } 2200 2201 if (tst_entries == 0) { 2202 printk("%s: selected CBR bandwidth < granularity.\n", 2203 card->name); 2204 return -EINVAL; 2205 } 2206 2207 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2208 printk("%s: not enough CBR bandwidth free.\n", card->name); 2209 return -ENOSR; 2210 } 2211 2212 vc->ntste = tst_entries; 2213 2214 card->tst_free = tst_free - tst_entries; 2215 if (test_bit(VCF_TX, &vc->flags)) { 2216 if (tst_used == tst_entries) 2217 return 0; 2218 2219 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2220 card->name, tst_used, tst_entries); 2221 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2222 return 0; 2223 } 2224 2225 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2226 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2227 return 0; 2228} 2229 2230static int 2231idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2232 struct atm_vcc *vcc, struct atm_qos *qos) 2233{ 2234 unsigned long flags; 2235 int tcr; 2236 2237 spin_lock_irqsave(&vc->lock, flags); 2238 if (vc->estimator) { 2239 del_timer(&vc->estimator->timer); 2240 kfree(vc->estimator); 2241 vc->estimator = NULL; 2242 } 2243 spin_unlock_irqrestore(&vc->lock, flags); 2244 2245 tcr = atm_pcr_goal(&qos->txtp); 2246 if (tcr == 0) 2247 tcr = card->link_pcr; 2248 2249 vc->estimator = idt77252_init_est(vc, tcr); 2250 2251 vc->class = SCHED_UBR; 2252 vc->init_er = idt77252_rate_logindex(card, tcr); 2253 vc->lacr = vc->init_er; 2254 if (tcr < 0) 2255 vc->max_er = vc->init_er; 2256 else 2257 vc->max_er = 0xff; 2258 2259 return 0; 2260} 2261 2262static int 2263idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2264 struct atm_vcc *vcc, struct atm_qos *qos) 2265{ 2266 int error; 2267 2268 if (test_bit(VCF_TX, &vc->flags)) 2269 return -EBUSY; 2270 2271 switch (qos->txtp.traffic_class) { 2272 case ATM_CBR: 2273 vc->class = SCHED_CBR; 2274 break; 2275 2276 case ATM_UBR: 2277 vc->class = SCHED_UBR; 2278 break; 2279 2280 case ATM_VBR: 2281 case ATM_ABR: 2282 default: 2283 return -EPROTONOSUPPORT; 2284 } 2285 2286 vc->scq = alloc_scq(card, vc->class); 2287 if (!vc->scq) { 2288 printk("%s: can't get SCQ.\n", card->name); 2289 return -ENOMEM; 2290 } 2291 2292 vc->scq->scd = get_free_scd(card, vc); 2293 if (vc->scq->scd == 0) { 2294 printk("%s: no SCD available.\n", card->name); 2295 free_scq(card, vc->scq); 2296 return -ENOMEM; 2297 } 2298 2299 fill_scd(card, vc->scq, vc->class); 2300 2301 if (set_tct(card, vc)) { 2302 printk("%s: class %d not supported.\n", 2303 card->name, qos->txtp.traffic_class); 2304 2305 card->scd2vc[vc->scd_index] = NULL; 2306 free_scq(card, vc->scq); 2307 return -EPROTONOSUPPORT; 2308 } 2309 2310 switch (vc->class) { 2311 case SCHED_CBR: 2312 error = idt77252_init_cbr(card, vc, vcc, qos); 2313 if (error) { 2314 card->scd2vc[vc->scd_index] = NULL; 2315 free_scq(card, vc->scq); 2316 return error; 2317 } 2318 2319 clear_bit(VCF_IDLE, &vc->flags); 2320 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2321 break; 2322 2323 case SCHED_UBR: 2324 error = idt77252_init_ubr(card, vc, vcc, qos); 2325 if (error) { 2326 card->scd2vc[vc->scd_index] = NULL; 2327 free_scq(card, vc->scq); 2328 return error; 2329 } 2330 2331 set_bit(VCF_IDLE, &vc->flags); 2332 break; 2333 } 2334 2335 vc->tx_vcc = vcc; 2336 set_bit(VCF_TX, &vc->flags); 2337 return 0; 2338} 2339 2340static int 2341idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2342 struct atm_vcc *vcc, struct atm_qos *qos) 2343{ 2344 unsigned long flags; 2345 unsigned long addr; 2346 u32 rcte = 0; 2347 2348 if (test_bit(VCF_RX, &vc->flags)) 2349 return -EBUSY; 2350 2351 vc->rx_vcc = vcc; 2352 set_bit(VCF_RX, &vc->flags); 2353 2354 if ((vcc->vci == 3) || (vcc->vci == 4)) 2355 return 0; 2356 2357 flush_rx_pool(card, &vc->rcv.rx_pool); 2358 2359 rcte |= SAR_RCTE_CONNECTOPEN; 2360 rcte |= SAR_RCTE_RAWCELLINTEN; 2361 2362 switch (qos->aal) { 2363 case ATM_AAL0: 2364 rcte |= SAR_RCTE_RCQ; 2365 break; 2366 case ATM_AAL1: 2367 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2368 break; 2369 case ATM_AAL34: 2370 rcte |= SAR_RCTE_AAL34; 2371 break; 2372 case ATM_AAL5: 2373 rcte |= SAR_RCTE_AAL5; 2374 break; 2375 default: 2376 rcte |= SAR_RCTE_RCQ; 2377 break; 2378 } 2379 2380 if (qos->aal != ATM_AAL5) 2381 rcte |= SAR_RCTE_FBP_1; 2382 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2383 rcte |= SAR_RCTE_FBP_3; 2384 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2385 rcte |= SAR_RCTE_FBP_2; 2386 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2387 rcte |= SAR_RCTE_FBP_1; 2388 else 2389 rcte |= SAR_RCTE_FBP_01; 2390 2391 addr = card->rct_base + (vc->index << 2); 2392 2393 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2394 write_sram(card, addr, rcte); 2395 2396 spin_lock_irqsave(&card->cmd_lock, flags); 2397 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2398 waitfor_idle(card); 2399 spin_unlock_irqrestore(&card->cmd_lock, flags); 2400 2401 return 0; 2402} 2403 2404static int 2405idt77252_open(struct atm_vcc *vcc) 2406{ 2407 struct atm_dev *dev = vcc->dev; 2408 struct idt77252_dev *card = dev->dev_data; 2409 struct vc_map *vc; 2410 unsigned int index; 2411 unsigned int inuse; 2412 int error; 2413 int vci = vcc->vci; 2414 short vpi = vcc->vpi; 2415 2416 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2417 return 0; 2418 2419 if (vpi >= (1 << card->vpibits)) { 2420 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2421 return -EINVAL; 2422 } 2423 2424 if (vci >= (1 << card->vcibits)) { 2425 printk("%s: unsupported VCI: %d\n", card->name, vci); 2426 return -EINVAL; 2427 } 2428 2429 set_bit(ATM_VF_ADDR, &vcc->flags); 2430 2431 mutex_lock(&card->mutex); 2432 2433 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2434 2435 switch (vcc->qos.aal) { 2436 case ATM_AAL0: 2437 case ATM_AAL1: 2438 case ATM_AAL5: 2439 break; 2440 default: 2441 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2442 mutex_unlock(&card->mutex); 2443 return -EPROTONOSUPPORT; 2444 } 2445 2446 index = VPCI2VC(card, vpi, vci); 2447 if (!card->vcs[index]) { 2448 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2449 if (!card->vcs[index]) { 2450 printk("%s: can't alloc vc in open()\n", card->name); 2451 mutex_unlock(&card->mutex); 2452 return -ENOMEM; 2453 } 2454 card->vcs[index]->card = card; 2455 card->vcs[index]->index = index; 2456 2457 spin_lock_init(&card->vcs[index]->lock); 2458 } 2459 vc = card->vcs[index]; 2460 2461 vcc->dev_data = vc; 2462 2463 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2464 card->name, vc->index, vcc->vpi, vcc->vci, 2465 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2466 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2467 vcc->qos.rxtp.max_sdu); 2468 2469 inuse = 0; 2470 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2471 test_bit(VCF_TX, &vc->flags)) 2472 inuse = 1; 2473 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2474 test_bit(VCF_RX, &vc->flags)) 2475 inuse += 2; 2476 2477 if (inuse) { 2478 printk("%s: %s vci already in use.\n", card->name, 2479 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2480 mutex_unlock(&card->mutex); 2481 return -EADDRINUSE; 2482 } 2483 2484 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2485 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2486 if (error) { 2487 mutex_unlock(&card->mutex); 2488 return error; 2489 } 2490 } 2491 2492 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2493 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2494 if (error) { 2495 mutex_unlock(&card->mutex); 2496 return error; 2497 } 2498 } 2499 2500 set_bit(ATM_VF_READY, &vcc->flags); 2501 2502 mutex_unlock(&card->mutex); 2503 return 0; 2504} 2505 2506static void 2507idt77252_close(struct atm_vcc *vcc) 2508{ 2509 struct atm_dev *dev = vcc->dev; 2510 struct idt77252_dev *card = dev->dev_data; 2511 struct vc_map *vc = vcc->dev_data; 2512 unsigned long flags; 2513 unsigned long addr; 2514 unsigned long timeout; 2515 2516 mutex_lock(&card->mutex); 2517 2518 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2519 card->name, vc->index, vcc->vpi, vcc->vci); 2520 2521 clear_bit(ATM_VF_READY, &vcc->flags); 2522 2523 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2524 2525 spin_lock_irqsave(&vc->lock, flags); 2526 clear_bit(VCF_RX, &vc->flags); 2527 vc->rx_vcc = NULL; 2528 spin_unlock_irqrestore(&vc->lock, flags); 2529 2530 if ((vcc->vci == 3) || (vcc->vci == 4)) 2531 goto done; 2532 2533 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2534 2535 spin_lock_irqsave(&card->cmd_lock, flags); 2536 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2537 waitfor_idle(card); 2538 spin_unlock_irqrestore(&card->cmd_lock, flags); 2539 2540 if (vc->rcv.rx_pool.count) { 2541 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2542 card->name); 2543 2544 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2545 } 2546 } 2547 2548done: 2549 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2550 2551 spin_lock_irqsave(&vc->lock, flags); 2552 clear_bit(VCF_TX, &vc->flags); 2553 clear_bit(VCF_IDLE, &vc->flags); 2554 clear_bit(VCF_RSV, &vc->flags); 2555 vc->tx_vcc = NULL; 2556 2557 if (vc->estimator) { 2558 del_timer(&vc->estimator->timer); 2559 kfree(vc->estimator); 2560 vc->estimator = NULL; 2561 } 2562 spin_unlock_irqrestore(&vc->lock, flags); 2563 2564 timeout = 5 * 1000; 2565 while (atomic_read(&vc->scq->used) > 0) { 2566 timeout = msleep_interruptible(timeout); 2567 if (!timeout) 2568 break; 2569 } 2570 if (!timeout) 2571 printk("%s: SCQ drain timeout: %u used\n", 2572 card->name, atomic_read(&vc->scq->used)); 2573 2574 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2575 clear_scd(card, vc->scq, vc->class); 2576 2577 if (vc->class == SCHED_CBR) { 2578 clear_tst(card, vc); 2579 card->tst_free += vc->ntste; 2580 vc->ntste = 0; 2581 } 2582 2583 card->scd2vc[vc->scd_index] = NULL; 2584 free_scq(card, vc->scq); 2585 } 2586 2587 mutex_unlock(&card->mutex); 2588} 2589 2590static int 2591idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2592{ 2593 struct atm_dev *dev = vcc->dev; 2594 struct idt77252_dev *card = dev->dev_data; 2595 struct vc_map *vc = vcc->dev_data; 2596 int error = 0; 2597 2598 mutex_lock(&card->mutex); 2599 2600 if (qos->txtp.traffic_class != ATM_NONE) { 2601 if (!test_bit(VCF_TX, &vc->flags)) { 2602 error = idt77252_init_tx(card, vc, vcc, qos); 2603 if (error) 2604 goto out; 2605 } else { 2606 switch (qos->txtp.traffic_class) { 2607 case ATM_CBR: 2608 error = idt77252_init_cbr(card, vc, vcc, qos); 2609 if (error) 2610 goto out; 2611 break; 2612 2613 case ATM_UBR: 2614 error = idt77252_init_ubr(card, vc, vcc, qos); 2615 if (error) 2616 goto out; 2617 2618 if (!test_bit(VCF_IDLE, &vc->flags)) { 2619 writel(TCMDQ_LACR | (vc->lacr << 16) | 2620 vc->index, SAR_REG_TCMDQ); 2621 } 2622 break; 2623 2624 case ATM_VBR: 2625 case ATM_ABR: 2626 error = -EOPNOTSUPP; 2627 goto out; 2628 } 2629 } 2630 } 2631 2632 if ((qos->rxtp.traffic_class != ATM_NONE) && 2633 !test_bit(VCF_RX, &vc->flags)) { 2634 error = idt77252_init_rx(card, vc, vcc, qos); 2635 if (error) 2636 goto out; 2637 } 2638 2639 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2640 2641 set_bit(ATM_VF_HASQOS, &vcc->flags); 2642 2643out: 2644 mutex_unlock(&card->mutex); 2645 return error; 2646} 2647 2648static int 2649idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2650{ 2651 struct idt77252_dev *card = dev->dev_data; 2652 int i, left; 2653 2654 left = (int) *pos; 2655 if (!left--) 2656 return sprintf(page, "IDT77252 Interrupts:\n"); 2657 if (!left--) 2658 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2659 if (!left--) 2660 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2661 if (!left--) 2662 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2663 if (!left--) 2664 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2665 if (!left--) 2666 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2667 if (!left--) 2668 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2669 if (!left--) 2670 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2671 if (!left--) 2672 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2673 if (!left--) 2674 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2675 if (!left--) 2676 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2677 if (!left--) 2678 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2679 if (!left--) 2680 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2681 if (!left--) 2682 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2683 if (!left--) 2684 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2685 2686 for (i = 0; i < card->tct_size; i++) { 2687 unsigned long tct; 2688 struct atm_vcc *vcc; 2689 struct vc_map *vc; 2690 char *p; 2691 2692 vc = card->vcs[i]; 2693 if (!vc) 2694 continue; 2695 2696 vcc = NULL; 2697 if (vc->tx_vcc) 2698 vcc = vc->tx_vcc; 2699 if (!vcc) 2700 continue; 2701 if (left--) 2702 continue; 2703 2704 p = page; 2705 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2706 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2707 2708 for (i = 0; i < 8; i++) 2709 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2710 p += sprintf(p, "\n"); 2711 return p - page; 2712 } 2713 return 0; 2714} 2715 2716/*****************************************************************************/ 2717/* */ 2718/* Interrupt handler */ 2719/* */ 2720/*****************************************************************************/ 2721 2722static void 2723idt77252_collect_stat(struct idt77252_dev *card) 2724{ 2725 u32 cdc, vpec, icc; 2726 2727 cdc = readl(SAR_REG_CDC); 2728 vpec = readl(SAR_REG_VPEC); 2729 icc = readl(SAR_REG_ICC); 2730 2731#ifdef NOTDEF 2732 printk("%s:", card->name); 2733 2734 if (cdc & 0x7f0000) { 2735 char *s = ""; 2736 2737 printk(" ["); 2738 if (cdc & (1 << 22)) { 2739 printk("%sRM ID", s); 2740 s = " | "; 2741 } 2742 if (cdc & (1 << 21)) { 2743 printk("%sCON TAB", s); 2744 s = " | "; 2745 } 2746 if (cdc & (1 << 20)) { 2747 printk("%sNO FB", s); 2748 s = " | "; 2749 } 2750 if (cdc & (1 << 19)) { 2751 printk("%sOAM CRC", s); 2752 s = " | "; 2753 } 2754 if (cdc & (1 << 18)) { 2755 printk("%sRM CRC", s); 2756 s = " | "; 2757 } 2758 if (cdc & (1 << 17)) { 2759 printk("%sRM FIFO", s); 2760 s = " | "; 2761 } 2762 if (cdc & (1 << 16)) { 2763 printk("%sRX FIFO", s); 2764 s = " | "; 2765 } 2766 printk("]"); 2767 } 2768 2769 printk(" CDC %04x, VPEC %04x, ICC: %04x\n", 2770 cdc & 0xffff, vpec & 0xffff, icc & 0xffff); 2771#endif 2772} 2773 2774static irqreturn_t 2775idt77252_interrupt(int irq, void *dev_id) 2776{ 2777 struct idt77252_dev *card = dev_id; 2778 u32 stat; 2779 2780 stat = readl(SAR_REG_STAT) & 0xffff; 2781 if (!stat) /* no interrupt for us */ 2782 return IRQ_NONE; 2783 2784 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2785 printk("%s: Re-entering irq_handler()\n", card->name); 2786 goto out; 2787 } 2788 2789 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2790 2791 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2792 INTPRINTK("%s: TSIF\n", card->name); 2793 card->irqstat[15]++; 2794 idt77252_tx(card); 2795 } 2796 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2797 INTPRINTK("%s: TXICP\n", card->name); 2798 card->irqstat[14]++; 2799#ifdef CONFIG_ATM_IDT77252_DEBUG 2800 idt77252_tx_dump(card); 2801#endif 2802 } 2803 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2804 INTPRINTK("%s: TSQF\n", card->name); 2805 card->irqstat[12]++; 2806 idt77252_tx(card); 2807 } 2808 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2809 INTPRINTK("%s: TMROF\n", card->name); 2810 card->irqstat[11]++; 2811 idt77252_collect_stat(card); 2812 } 2813 2814 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2815 INTPRINTK("%s: EPDU\n", card->name); 2816 card->irqstat[5]++; 2817 idt77252_rx(card); 2818 } 2819 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2820 INTPRINTK("%s: RSQAF\n", card->name); 2821 card->irqstat[1]++; 2822 idt77252_rx(card); 2823 } 2824 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2825 INTPRINTK("%s: RSQF\n", card->name); 2826 card->irqstat[6]++; 2827 idt77252_rx(card); 2828 } 2829 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2830 INTPRINTK("%s: RAWCF\n", card->name); 2831 card->irqstat[4]++; 2832 idt77252_rx_raw(card); 2833 } 2834 2835 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2836 INTPRINTK("%s: PHYI", card->name); 2837 card->irqstat[10]++; 2838 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2839 card->atmdev->phy->interrupt(card->atmdev); 2840 } 2841 2842 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2843 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2844 2845 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2846 2847 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2848 2849 if (stat & SAR_STAT_FBQ0A) 2850 card->irqstat[2]++; 2851 if (stat & SAR_STAT_FBQ1A) 2852 card->irqstat[3]++; 2853 if (stat & SAR_STAT_FBQ2A) 2854 card->irqstat[7]++; 2855 if (stat & SAR_STAT_FBQ3A) 2856 card->irqstat[8]++; 2857 2858 schedule_work(&card->tqueue); 2859 } 2860 2861out: 2862 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2863 return IRQ_HANDLED; 2864} 2865 2866static void 2867idt77252_softint(struct work_struct *work) 2868{ 2869 struct idt77252_dev *card = 2870 container_of(work, struct idt77252_dev, tqueue); 2871 u32 stat; 2872 int done; 2873 2874 for (done = 1; ; done = 1) { 2875 stat = readl(SAR_REG_STAT) >> 16; 2876 2877 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2878 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2879 done = 0; 2880 } 2881 2882 stat >>= 4; 2883 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2884 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2885 done = 0; 2886 } 2887 2888 stat >>= 4; 2889 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2890 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2891 done = 0; 2892 } 2893 2894 stat >>= 4; 2895 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2896 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2897 done = 0; 2898 } 2899 2900 if (done) 2901 break; 2902 } 2903 2904 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2905} 2906 2907 2908static int 2909open_card_oam(struct idt77252_dev *card) 2910{ 2911 unsigned long flags; 2912 unsigned long addr; 2913 struct vc_map *vc; 2914 int vpi, vci; 2915 int index; 2916 u32 rcte; 2917 2918 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2919 for (vci = 3; vci < 5; vci++) { 2920 index = VPCI2VC(card, vpi, vci); 2921 2922 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2923 if (!vc) { 2924 printk("%s: can't alloc vc\n", card->name); 2925 return -ENOMEM; 2926 } 2927 vc->index = index; 2928 card->vcs[index] = vc; 2929 2930 flush_rx_pool(card, &vc->rcv.rx_pool); 2931 2932 rcte = SAR_RCTE_CONNECTOPEN | 2933 SAR_RCTE_RAWCELLINTEN | 2934 SAR_RCTE_RCQ | 2935 SAR_RCTE_FBP_1; 2936 2937 addr = card->rct_base + (vc->index << 2); 2938 write_sram(card, addr, rcte); 2939 2940 spin_lock_irqsave(&card->cmd_lock, flags); 2941 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2942 SAR_REG_CMD); 2943 waitfor_idle(card); 2944 spin_unlock_irqrestore(&card->cmd_lock, flags); 2945 } 2946 } 2947 2948 return 0; 2949} 2950 2951static void 2952close_card_oam(struct idt77252_dev *card) 2953{ 2954 unsigned long flags; 2955 unsigned long addr; 2956 struct vc_map *vc; 2957 int vpi, vci; 2958 int index; 2959 2960 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2961 for (vci = 3; vci < 5; vci++) { 2962 index = VPCI2VC(card, vpi, vci); 2963 vc = card->vcs[index]; 2964 2965 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2966 2967 spin_lock_irqsave(&card->cmd_lock, flags); 2968 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2969 SAR_REG_CMD); 2970 waitfor_idle(card); 2971 spin_unlock_irqrestore(&card->cmd_lock, flags); 2972 2973 if (vc->rcv.rx_pool.count) { 2974 DPRINTK("%s: closing a VC " 2975 "with pending rx buffers.\n", 2976 card->name); 2977 2978 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2979 } 2980 } 2981 } 2982} 2983 2984static int 2985open_card_ubr0(struct idt77252_dev *card) 2986{ 2987 struct vc_map *vc; 2988 2989 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2990 if (!vc) { 2991 printk("%s: can't alloc vc\n", card->name); 2992 return -ENOMEM; 2993 } 2994 card->vcs[0] = vc; 2995 vc->class = SCHED_UBR0; 2996 2997 vc->scq = alloc_scq(card, vc->class); 2998 if (!vc->scq) { 2999 printk("%s: can't get SCQ.\n", card->name); 3000 return -ENOMEM; 3001 } 3002 3003 card->scd2vc[0] = vc; 3004 vc->scd_index = 0; 3005 vc->scq->scd = card->scd_base; 3006 3007 fill_scd(card, vc->scq, vc->class); 3008 3009 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 3010 write_sram(card, card->tct_base + 1, 0); 3011 write_sram(card, card->tct_base + 2, 0); 3012 write_sram(card, card->tct_base + 3, 0); 3013 write_sram(card, card->tct_base + 4, 0); 3014 write_sram(card, card->tct_base + 5, 0); 3015 write_sram(card, card->tct_base + 6, 0); 3016 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 3017 3018 clear_bit(VCF_IDLE, &vc->flags); 3019 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 3020 return 0; 3021} 3022 3023static int 3024idt77252_dev_open(struct idt77252_dev *card) 3025{ 3026 u32 conf; 3027 3028 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3029 printk("%s: SAR not yet initialized.\n", card->name); 3030 return -1; 3031 } 3032 3033 conf = SAR_CFG_RXPTH| /* enable receive path */ 3034 SAR_RX_DELAY | /* interrupt on complete PDU */ 3035 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3036 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3037 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3038 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3039 SAR_CFG_TXEN | /* transmit operation enable */ 3040 SAR_CFG_TXINT | /* interrupt on transmit status */ 3041 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 3042 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 3043 SAR_CFG_PHYIE /* enable PHY interrupts */ 3044 ; 3045 3046#ifdef CONFIG_ATM_IDT77252_RCV_ALL 3047 /* Test RAW cell receive. */ 3048 conf |= SAR_CFG_VPECA; 3049#endif 3050 3051 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3052 3053 if (open_card_oam(card)) { 3054 printk("%s: Error initializing OAM.\n", card->name); 3055 return -1; 3056 } 3057 3058 if (open_card_ubr0(card)) { 3059 printk("%s: Error initializing UBR0.\n", card->name); 3060 return -1; 3061 } 3062 3063 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3064 return 0; 3065} 3066 3067void 3068idt77252_dev_close(struct atm_dev *dev) 3069{ 3070 struct idt77252_dev *card = dev->dev_data; 3071 u32 conf; 3072 3073 close_card_oam(card); 3074 3075 conf = SAR_CFG_RXPTH | /* enable receive path */ 3076 SAR_RX_DELAY | /* interrupt on complete PDU */ 3077 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3078 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3079 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3080 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3081 SAR_CFG_TXEN | /* transmit operation enable */ 3082 SAR_CFG_TXINT | /* interrupt on transmit status */ 3083 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3084 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3085 ; 3086 3087 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3088 3089 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3090} 3091 3092 3093/*****************************************************************************/ 3094/* */ 3095/* Initialisation and Deinitialization of IDT77252 */ 3096/* */ 3097/*****************************************************************************/ 3098 3099 3100static void 3101deinit_card(struct idt77252_dev *card) 3102{ 3103 struct sk_buff *skb; 3104 int i, j; 3105 3106 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3107 printk("%s: SAR not yet initialized.\n", card->name); 3108 return; 3109 } 3110 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3111 3112 writel(0, SAR_REG_CFG); 3113 3114 if (card->atmdev) 3115 atm_dev_deregister(card->atmdev); 3116 3117 for (i = 0; i < 4; i++) { 3118 for (j = 0; j < FBQ_SIZE; j++) { 3119 skb = card->sbpool[i].skb[j]; 3120 if (skb) { 3121 pci_unmap_single(card->pcidev, 3122 IDT77252_PRV_PADDR(skb), 3123 (skb_end_pointer(skb) - 3124 skb->data), 3125 PCI_DMA_FROMDEVICE); 3126 card->sbpool[i].skb[j] = NULL; 3127 dev_kfree_skb(skb); 3128 } 3129 } 3130 } 3131 3132 vfree(card->soft_tst); 3133 3134 vfree(card->scd2vc); 3135 3136 vfree(card->vcs); 3137 3138 if (card->raw_cell_hnd) { 3139 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3140 card->raw_cell_hnd, card->raw_cell_paddr); 3141 } 3142 3143 if (card->rsq.base) { 3144 DIPRINTK("%s: Release RSQ ...\n", card->name); 3145 deinit_rsq(card); 3146 } 3147 3148 if (card->tsq.base) { 3149 DIPRINTK("%s: Release TSQ ...\n", card->name); 3150 deinit_tsq(card); 3151 } 3152 3153 DIPRINTK("idt77252: Release IRQ.\n"); 3154 free_irq(card->pcidev->irq, card); 3155 3156 for (i = 0; i < 4; i++) { 3157 if (card->fbq[i]) 3158 iounmap(card->fbq[i]); 3159 } 3160 3161 if (card->membase) 3162 iounmap(card->membase); 3163 3164 clear_bit(IDT77252_BIT_INIT, &card->flags); 3165 DIPRINTK("%s: Card deinitialized.\n", card->name); 3166} 3167 3168 3169static int __devinit 3170init_sram(struct idt77252_dev *card) 3171{ 3172 int i; 3173 3174 for (i = 0; i < card->sramsize; i += 4) 3175 write_sram(card, (i >> 2), 0); 3176 3177 /* set SRAM layout for THIS card */ 3178 if (card->sramsize == (512 * 1024)) { 3179 card->tct_base = SAR_SRAM_TCT_128_BASE; 3180 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3181 / SAR_SRAM_TCT_SIZE; 3182 card->rct_base = SAR_SRAM_RCT_128_BASE; 3183 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3184 / SAR_SRAM_RCT_SIZE; 3185 card->rt_base = SAR_SRAM_RT_128_BASE; 3186 card->scd_base = SAR_SRAM_SCD_128_BASE; 3187 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3188 / SAR_SRAM_SCD_SIZE; 3189 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3190 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3191 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3192 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3193 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3194 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3195 card->fifo_size = SAR_RXFD_SIZE_32K; 3196 } else { 3197 card->tct_base = SAR_SRAM_TCT_32_BASE; 3198 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3199 / SAR_SRAM_TCT_SIZE; 3200 card->rct_base = SAR_SRAM_RCT_32_BASE; 3201 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3202 / SAR_SRAM_RCT_SIZE; 3203 card->rt_base = SAR_SRAM_RT_32_BASE; 3204 card->scd_base = SAR_SRAM_SCD_32_BASE; 3205 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3206 / SAR_SRAM_SCD_SIZE; 3207 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3208 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3209 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3210 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3211 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3212 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3213 card->fifo_size = SAR_RXFD_SIZE_4K; 3214 } 3215 3216 /* Initialize TCT */ 3217 for (i = 0; i < card->tct_size; i++) { 3218 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3219 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3220 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3221 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3222 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3223 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3224 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3225 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3226 } 3227 3228 /* Initialize RCT */ 3229 for (i = 0; i < card->rct_size; i++) { 3230 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3231 (u32) SAR_RCTE_RAWCELLINTEN); 3232 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3233 (u32) 0); 3234 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3235 (u32) 0); 3236 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3237 (u32) 0xffffffff); 3238 } 3239 3240 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3241 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3242 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3243 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3244 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3245 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3246 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3247 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3248 3249 /* Initialize rate table */ 3250 for (i = 0; i < 256; i++) { 3251 write_sram(card, card->rt_base + i, log_to_rate[i]); 3252 } 3253 3254 for (i = 0; i < 128; i++) { 3255 unsigned int tmp; 3256 3257 tmp = rate_to_log[(i << 2) + 0] << 0; 3258 tmp |= rate_to_log[(i << 2) + 1] << 8; 3259 tmp |= rate_to_log[(i << 2) + 2] << 16; 3260 tmp |= rate_to_log[(i << 2) + 3] << 24; 3261 write_sram(card, card->rt_base + 256 + i, tmp); 3262 } 3263 3264 3265 IPRINTK("%s: initialize rate table ...\n", card->name); 3266 writel(card->rt_base << 2, SAR_REG_RTBL); 3267 3268 /* Initialize TSTs */ 3269 IPRINTK("%s: initialize TST ...\n", card->name); 3270 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3271 3272 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3273 write_sram(card, i, TSTE_OPC_VAR); 3274 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3275 idt77252_sram_write_errors = 1; 3276 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3277 idt77252_sram_write_errors = 0; 3278 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3279 write_sram(card, i, TSTE_OPC_VAR); 3280 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3281 idt77252_sram_write_errors = 1; 3282 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3283 idt77252_sram_write_errors = 0; 3284 3285 card->tst_index = 0; 3286 writel(card->tst[0] << 2, SAR_REG_TSTB); 3287 3288 /* Initialize ABRSTD and Receive FIFO */ 3289 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3290 writel(card->abrst_size | (card->abrst_base << 2), 3291 SAR_REG_ABRSTD); 3292 3293 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3294 writel(card->fifo_size | (card->fifo_base << 2), 3295 SAR_REG_RXFD); 3296 3297 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3298 return 0; 3299} 3300 3301static int __devinit 3302init_card(struct atm_dev *dev) 3303{ 3304 struct idt77252_dev *card = dev->dev_data; 3305 struct pci_dev *pcidev = card->pcidev; 3306 unsigned long tmpl, modl; 3307 unsigned int linkrate, rsvdcr; 3308 unsigned int tst_entries; 3309 struct net_device *tmp; 3310 char tname[10]; 3311 3312 u32 size; 3313 u_char pci_byte; 3314 u32 conf; 3315 int i, k; 3316 3317 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3318 printk("Error: SAR already initialized.\n"); 3319 return -1; 3320 } 3321 3322/*****************************************************************/ 3323/* P C I C O N F I G U R A T I O N */ 3324/*****************************************************************/ 3325 3326 /* Set PCI Retry-Timeout and TRDY timeout */ 3327 IPRINTK("%s: Checking PCI retries.\n", card->name); 3328 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3329 printk("%s: can't read PCI retry timeout.\n", card->name); 3330 deinit_card(card); 3331 return -1; 3332 } 3333 if (pci_byte != 0) { 3334 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3335 card->name, pci_byte); 3336 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3337 printk("%s: can't set PCI retry timeout.\n", 3338 card->name); 3339 deinit_card(card); 3340 return -1; 3341 } 3342 } 3343 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3344 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3345 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3346 deinit_card(card); 3347 return -1; 3348 } 3349 if (pci_byte != 0) { 3350 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3351 card->name, pci_byte); 3352 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3353 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3354 deinit_card(card); 3355 return -1; 3356 } 3357 } 3358 /* Reset Timer register */ 3359 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3360 printk("%s: resetting timer overflow.\n", card->name); 3361 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3362 } 3363 IPRINTK("%s: Request IRQ ... ", card->name); 3364 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED, 3365 card->name, card) != 0) { 3366 printk("%s: can't allocate IRQ.\n", card->name); 3367 deinit_card(card); 3368 return -1; 3369 } 3370 IPRINTK("got %d.\n", pcidev->irq); 3371 3372/*****************************************************************/ 3373/* C H E C K A N D I N I T S R A M */ 3374/*****************************************************************/ 3375 3376 IPRINTK("%s: Initializing SRAM\n", card->name); 3377 3378 /* preset size of connecton table, so that init_sram() knows about it */ 3379 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3380 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3381 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3382#ifndef CONFIG_ATM_IDT77252_SEND_IDLE 3383 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3384#endif 3385 0; 3386 3387 if (card->sramsize == (512 * 1024)) 3388 conf |= SAR_CFG_CNTBL_1k; 3389 else 3390 conf |= SAR_CFG_CNTBL_512; 3391 3392 switch (vpibits) { 3393 case 0: 3394 conf |= SAR_CFG_VPVCS_0; 3395 break; 3396 default: 3397 case 1: 3398 conf |= SAR_CFG_VPVCS_1; 3399 break; 3400 case 2: 3401 conf |= SAR_CFG_VPVCS_2; 3402 break; 3403 case 8: 3404 conf |= SAR_CFG_VPVCS_8; 3405 break; 3406 } 3407 3408 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3409 3410 if (init_sram(card) < 0) 3411 return -1; 3412 3413/********************************************************************/ 3414/* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3415/********************************************************************/ 3416 /* Initialize TSQ */ 3417 if (0 != init_tsq(card)) { 3418 deinit_card(card); 3419 return -1; 3420 } 3421 /* Initialize RSQ */ 3422 if (0 != init_rsq(card)) { 3423 deinit_card(card); 3424 return -1; 3425 } 3426 3427 card->vpibits = vpibits; 3428 if (card->sramsize == (512 * 1024)) { 3429 card->vcibits = 10 - card->vpibits; 3430 } else { 3431 card->vcibits = 9 - card->vpibits; 3432 } 3433 3434 card->vcimask = 0; 3435 for (k = 0, i = 1; k < card->vcibits; k++) { 3436 card->vcimask |= i; 3437 i <<= 1; 3438 } 3439 3440 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3441 writel(0, SAR_REG_VPM); 3442 3443 /* Little Endian Order */ 3444 writel(0, SAR_REG_GP); 3445 3446 /* Initialize RAW Cell Handle Register */ 3447 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3448 &card->raw_cell_paddr); 3449 if (!card->raw_cell_hnd) { 3450 printk("%s: memory allocation failure.\n", card->name); 3451 deinit_card(card); 3452 return -1; 3453 } 3454 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3455 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3456 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3457 card->raw_cell_hnd); 3458 3459 size = sizeof(struct vc_map *) * card->tct_size; 3460 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3461 if (NULL == (card->vcs = vmalloc(size))) { 3462 printk("%s: memory allocation failure.\n", card->name); 3463 deinit_card(card); 3464 return -1; 3465 } 3466 memset(card->vcs, 0, size); 3467 3468 size = sizeof(struct vc_map *) * card->scd_size; 3469 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3470 card->name, size); 3471 if (NULL == (card->scd2vc = vmalloc(size))) { 3472 printk("%s: memory allocation failure.\n", card->name); 3473 deinit_card(card); 3474 return -1; 3475 } 3476 memset(card->scd2vc, 0, size); 3477 3478 size = sizeof(struct tst_info) * (card->tst_size - 2); 3479 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3480 card->name, size); 3481 if (NULL == (card->soft_tst = vmalloc(size))) { 3482 printk("%s: memory allocation failure.\n", card->name); 3483 deinit_card(card); 3484 return -1; 3485 } 3486 for (i = 0; i < card->tst_size - 2; i++) { 3487 card->soft_tst[i].tste = TSTE_OPC_VAR; 3488 card->soft_tst[i].vc = NULL; 3489 } 3490 3491 if (dev->phy == NULL) { 3492 printk("%s: No LT device defined.\n", card->name); 3493 deinit_card(card); 3494 return -1; 3495 } 3496 if (dev->phy->ioctl == NULL) { 3497 printk("%s: LT had no IOCTL funtion defined.\n", card->name); 3498 deinit_card(card); 3499 return -1; 3500 } 3501 3502#ifdef CONFIG_ATM_IDT77252_USE_SUNI 3503 /* 3504 * this is a jhs hack to get around special functionality in the 3505 * phy driver for the atecom hardware; the functionality doesn't 3506 * exist in the linux atm suni driver 3507 * 3508 * it isn't the right way to do things, but as the guy from NIST 3509 * said, talking about their measurement of the fine structure 3510 * constant, "it's good enough for government work." 3511 */ 3512 linkrate = 149760000; 3513#endif 3514 3515 card->link_pcr = (linkrate / 8 / 53); 3516 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3517 card->name, linkrate, card->link_pcr); 3518 3519#ifdef CONFIG_ATM_IDT77252_SEND_IDLE 3520 card->utopia_pcr = card->link_pcr; 3521#else 3522 card->utopia_pcr = (160000000 / 8 / 54); 3523#endif 3524 3525 rsvdcr = 0; 3526 if (card->utopia_pcr > card->link_pcr) 3527 rsvdcr = card->utopia_pcr - card->link_pcr; 3528 3529 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3530 modl = tmpl % (unsigned long)card->utopia_pcr; 3531 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3532 if (modl) 3533 tst_entries++; 3534 card->tst_free -= tst_entries; 3535 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3536 3537#ifdef HAVE_EEPROM 3538 idt77252_eeprom_init(card); 3539 printk("%s: EEPROM: %02x:", card->name, 3540 idt77252_eeprom_read_status(card)); 3541 3542 for (i = 0; i < 0x80; i++) { 3543 printk(" %02x", 3544 idt77252_eeprom_read_byte(card, i) 3545 ); 3546 } 3547 printk("\n"); 3548#endif /* HAVE_EEPROM */ 3549 3550 sprintf(tname, "eth%d", card->index); 3551 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */ 3552 if (tmp) { 3553 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3554 3555 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n", 3556 card->name, card->atmdev->esi[0], card->atmdev->esi[1], 3557 card->atmdev->esi[2], card->atmdev->esi[3], 3558 card->atmdev->esi[4], card->atmdev->esi[5]); 3559 } 3560 3561 /* Set Maximum Deficit Count for now. */ 3562 writel(0xffff, SAR_REG_MDFCT); 3563 3564 set_bit(IDT77252_BIT_INIT, &card->flags); 3565 3566 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3567 return 0; 3568} 3569 3570 3571/*****************************************************************************/ 3572/* */ 3573/* Probing of IDT77252 ABR SAR */ 3574/* */ 3575/*****************************************************************************/ 3576 3577 3578static int __devinit 3579idt77252_preset(struct idt77252_dev *card) 3580{ 3581 u16 pci_command; 3582 3583/*****************************************************************/ 3584/* P C I C O N F I G U R A T I O N */ 3585/*****************************************************************/ 3586 3587 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3588 card->name); 3589 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3590 printk("%s: can't read PCI_COMMAND.\n", card->name); 3591 deinit_card(card); 3592 return -1; 3593 } 3594 if (!(pci_command & PCI_COMMAND_IO)) { 3595 printk("%s: PCI_COMMAND: %04x (???)\n", 3596 card->name, pci_command); 3597 deinit_card(card); 3598 return (-1); 3599 } 3600 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3601 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3602 printk("%s: can't write PCI_COMMAND.\n", card->name); 3603 deinit_card(card); 3604 return -1; 3605 } 3606/*****************************************************************/ 3607/* G E N E R I C R E S E T */ 3608/*****************************************************************/ 3609 3610 /* Software reset */ 3611 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3612 mdelay(1); 3613 writel(0, SAR_REG_CFG); 3614 3615 IPRINTK("%s: Software resetted.\n", card->name); 3616 return 0; 3617} 3618 3619 3620static unsigned long __devinit 3621probe_sram(struct idt77252_dev *card) 3622{ 3623 u32 data, addr; 3624 3625 writel(0, SAR_REG_DR0); 3626 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3627 3628 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3629 writel(ATM_POISON, SAR_REG_DR0); 3630 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3631 3632 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3633 data = readl(SAR_REG_DR0); 3634 3635 if (data != 0) 3636 break; 3637 } 3638 3639 return addr * sizeof(u32); 3640} 3641 3642static int __devinit 3643idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3644{ 3645 static struct idt77252_dev **last = &idt77252_chain; 3646 static int index = 0; 3647 3648 unsigned long membase, srambase; 3649 struct idt77252_dev *card; 3650 struct atm_dev *dev; 3651 ushort revision = 0; 3652 int i, err; 3653 3654 3655 if ((err = pci_enable_device(pcidev))) { 3656 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3657 return err; 3658 } 3659 3660 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) { 3661 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index); 3662 err = -ENODEV; 3663 goto err_out_disable_pdev; 3664 } 3665 3666 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3667 if (!card) { 3668 printk("idt77252-%d: can't allocate private data\n", index); 3669 err = -ENOMEM; 3670 goto err_out_disable_pdev; 3671 } 3672 card->revision = revision; 3673 card->index = index; 3674 card->pcidev = pcidev; 3675 sprintf(card->name, "idt77252-%d", card->index); 3676 3677 INIT_WORK(&card->tqueue, idt77252_softint); 3678 3679 membase = pci_resource_start(pcidev, 1); 3680 srambase = pci_resource_start(pcidev, 2); 3681 3682 mutex_init(&card->mutex); 3683 spin_lock_init(&card->cmd_lock); 3684 spin_lock_init(&card->tst_lock); 3685 3686 init_timer(&card->tst_timer); 3687 card->tst_timer.data = (unsigned long)card; 3688 card->tst_timer.function = tst_timer; 3689 3690 /* Do the I/O remapping... */ 3691 card->membase = ioremap(membase, 1024); 3692 if (!card->membase) { 3693 printk("%s: can't ioremap() membase\n", card->name); 3694 err = -EIO; 3695 goto err_out_free_card; 3696 } 3697 3698 if (idt77252_preset(card)) { 3699 printk("%s: preset failed\n", card->name); 3700 err = -EIO; 3701 goto err_out_iounmap; 3702 } 3703 3704 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL); 3705 if (!dev) { 3706 printk("%s: can't register atm device\n", card->name); 3707 err = -EIO; 3708 goto err_out_iounmap; 3709 } 3710 dev->dev_data = card; 3711 card->atmdev = dev; 3712 3713#ifdef CONFIG_ATM_IDT77252_USE_SUNI 3714 suni_init(dev); 3715 if (!dev->phy) { 3716 printk("%s: can't init SUNI\n", card->name); 3717 err = -EIO; 3718 goto err_out_deinit_card; 3719 } 3720#endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3721 3722 card->sramsize = probe_sram(card); 3723 3724 for (i = 0; i < 4; i++) { 3725 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3726 if (!card->fbq[i]) { 3727 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3728 err = -EIO; 3729 goto err_out_deinit_card; 3730 } 3731 } 3732 3733 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3734 card->name, ((revision > 1) && (revision < 25)) ? 3735 'A' + revision - 1 : '?', membase, srambase, 3736 card->sramsize / 1024); 3737 3738 if (init_card(dev)) { 3739 printk("%s: init_card failed\n", card->name); 3740 err = -EIO; 3741 goto err_out_deinit_card; 3742 } 3743 3744 dev->ci_range.vpi_bits = card->vpibits; 3745 dev->ci_range.vci_bits = card->vcibits; 3746 dev->link_rate = card->link_pcr; 3747 3748 if (dev->phy->start) 3749 dev->phy->start(dev); 3750 3751 if (idt77252_dev_open(card)) { 3752 printk("%s: dev_open failed\n", card->name); 3753 err = -EIO; 3754 goto err_out_stop; 3755 } 3756 3757 *last = card; 3758 last = &card->next; 3759 index++; 3760 3761 return 0; 3762 3763err_out_stop: 3764 if (dev->phy->stop) 3765 dev->phy->stop(dev); 3766 3767err_out_deinit_card: 3768 deinit_card(card); 3769 3770err_out_iounmap: 3771 iounmap(card->membase); 3772 3773err_out_free_card: 3774 kfree(card); 3775 3776err_out_disable_pdev: 3777 pci_disable_device(pcidev); 3778 return err; 3779} 3780 3781static struct pci_device_id idt77252_pci_tbl[] = 3782{ 3783 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252, 3784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 3785 { 0, } 3786}; 3787 3788MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3789 3790static struct pci_driver idt77252_driver = { 3791 .name = "idt77252", 3792 .id_table = idt77252_pci_tbl, 3793 .probe = idt77252_init_one, 3794}; 3795 3796static int __init idt77252_init(void) 3797{ 3798 struct sk_buff *skb; 3799 3800 printk("%s: at %p\n", __FUNCTION__, idt77252_init); 3801 3802 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3803 sizeof(struct idt77252_skb_prv)) { 3804 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3805 __FUNCTION__, (unsigned long) sizeof(skb->cb), 3806 (unsigned long) sizeof(struct atm_skb_data) + 3807 sizeof(struct idt77252_skb_prv)); 3808 return -EIO; 3809 } 3810 3811 return pci_register_driver(&idt77252_driver); 3812} 3813 3814static void __exit idt77252_exit(void) 3815{ 3816 struct idt77252_dev *card; 3817 struct atm_dev *dev; 3818 3819 pci_unregister_driver(&idt77252_driver); 3820 3821 while (idt77252_chain) { 3822 card = idt77252_chain; 3823 dev = card->atmdev; 3824 idt77252_chain = card->next; 3825 3826 if (dev->phy->stop) 3827 dev->phy->stop(dev); 3828 deinit_card(card); 3829 pci_disable_device(card->pcidev); 3830 kfree(card); 3831 } 3832 3833 DIPRINTK("idt77252: finished cleanup-module().\n"); 3834} 3835 3836module_init(idt77252_init); 3837module_exit(idt77252_exit); 3838 3839MODULE_LICENSE("GPL"); 3840 3841module_param(vpibits, uint, 0); 3842MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3843#ifdef CONFIG_ATM_IDT77252_DEBUG 3844module_param(debug, ulong, 0644); 3845MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3846#endif 3847 3848MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3849MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3850