1/* 2 Madge Ambassador ATM Adapter driver. 3 Copyright (C) 1995-1999 Madge Networks Ltd. 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian 20 system and in the file COPYING in the Linux kernel source. 21*/ 22 23#ifndef AMBASSADOR_H 24#define AMBASSADOR_H 25 26 27#ifdef CONFIG_ATM_AMBASSADOR_DEBUG 28#define DEBUG_AMBASSADOR 29#endif 30 31#define DEV_LABEL "amb" 32 33#ifndef PCI_VENDOR_ID_MADGE 34#define PCI_VENDOR_ID_MADGE 0x10B6 35#endif 36#ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR 37#define PCI_DEVICE_ID_MADGE_AMBASSADOR 0x1001 38#endif 39#ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR_BAD 40#define PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD 0x1002 41#endif 42 43// diagnostic output 44 45#define PRINTK(severity,format,args...) \ 46 printk(severity DEV_LABEL ": " format "\n" , ## args) 47 48#ifdef DEBUG_AMBASSADOR 49 50#define DBG_ERR 0x0001 51#define DBG_WARN 0x0002 52#define DBG_INFO 0x0004 53#define DBG_INIT 0x0008 54#define DBG_LOAD 0x0010 55#define DBG_VCC 0x0020 56#define DBG_QOS 0x0040 57#define DBG_CMD 0x0080 58#define DBG_TX 0x0100 59#define DBG_RX 0x0200 60#define DBG_SKB 0x0400 61#define DBG_POOL 0x0800 62#define DBG_IRQ 0x1000 63#define DBG_FLOW 0x2000 64#define DBG_REGS 0x4000 65#define DBG_DATA 0x8000 66#define DBG_MASK 0xffff 67 68/* the ## prevents the annoying double expansion of the macro arguments */ 69/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */ 70#define PRINTDB(bits,format,args...) \ 71 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 ) 72#define PRINTDM(bits,format,args...) \ 73 ( (debug & (bits)) ? printk (format , ## args) : 1 ) 74#define PRINTDE(bits,format,args...) \ 75 ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 ) 76#define PRINTD(bits,format,args...) \ 77 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 ) 78 79#else 80 81#define PRINTD(bits,format,args...) 82#define PRINTDB(bits,format,args...) 83#define PRINTDM(bits,format,args...) 84#define PRINTDE(bits,format,args...) 85 86#endif 87 88#define PRINTDD(bits,format,args...) 89#define PRINTDDB(sec,fmt,args...) 90#define PRINTDDM(sec,fmt,args...) 91#define PRINTDDE(sec,fmt,args...) 92 93// tunable values (?) 94 95/* MUST be powers of two -- why ? */ 96#define COM_Q_ENTRIES 8 97#define TX_Q_ENTRIES 32 98#define RX_Q_ENTRIES 64 99 100// fixed values 101 102// guessing 103#define AMB_EXTENT 0x80 104 105// Minimum allowed size for an Ambassador queue 106#define MIN_QUEUE_SIZE 2 107 108// Ambassador microcode allows 1 to 4 pools, we use 4 (simpler) 109#define NUM_RX_POOLS 4 110 111// minimum RX buffers required to cope with replenishing delay 112#define MIN_RX_BUFFERS 1 113 114// minimum PCI latency we will tolerate (32 IS TOO SMALL) 115#define MIN_PCI_LATENCY 64 // 255 116 117// VCs supported by card (VPI always 0) 118#define NUM_VPI_BITS 0 119#define NUM_VCI_BITS 10 120#define NUM_VCS 1024 121 122/* The status field bits defined so far. */ 123#define RX_ERR 0x8000 // always present if there is an error (hmm) 124#define CRC_ERR 0x4000 // AAL5 CRC error 125#define LEN_ERR 0x2000 // overlength frame 126#define ABORT_ERR 0x1000 // zero length field in received frame 127#define UNUSED_ERR 0x0800 // buffer returned unused 128 129// Adaptor commands 130 131#define SRB_OPEN_VC 0 132/* par_0: dwordswap(VC_number) */ 133/* par_1: dwordswap(flags<<16) or wordswap(flags)*/ 134/* flags: */ 135 136/* LANE: 0x0004 */ 137/* NOT_UBR: 0x0008 */ 138/* ABR: 0x0010 */ 139 140/* RxPool0: 0x0000 */ 141/* RxPool1: 0x0020 */ 142/* RxPool2: 0x0040 */ 143/* RxPool3: 0x0060 */ 144 145/* par_2: dwordswap(fp_rate<<16) or wordswap(fp_rate) */ 146 147#define SRB_CLOSE_VC 1 148/* par_0: dwordswap(VC_number) */ 149 150#define SRB_GET_BIA 2 151/* returns */ 152/* par_0: dwordswap(half BIA) */ 153/* par_1: dwordswap(half BIA) */ 154 155#define SRB_GET_SUNI_STATS 3 156/* par_0: dwordswap(physical_host_address) */ 157 158#define SRB_SET_BITS_8 4 159#define SRB_SET_BITS_16 5 160#define SRB_SET_BITS_32 6 161#define SRB_CLEAR_BITS_8 7 162#define SRB_CLEAR_BITS_16 8 163#define SRB_CLEAR_BITS_32 9 164/* par_0: dwordswap(ATMizer address) */ 165/* par_1: dwordswap(mask) */ 166 167#define SRB_SET_8 10 168#define SRB_SET_16 11 169#define SRB_SET_32 12 170/* par_0: dwordswap(ATMizer address) */ 171/* par_1: dwordswap(data) */ 172 173#define SRB_GET_32 13 174/* par_0: dwordswap(ATMizer address) */ 175/* returns */ 176/* par_1: dwordswap(ATMizer data) */ 177 178#define SRB_GET_VERSION 14 179/* returns */ 180/* par_0: dwordswap(Major Version) */ 181/* par_1: dwordswap(Minor Version) */ 182 183#define SRB_FLUSH_BUFFER_Q 15 184/* Only flags to define which buffer pool; all others must be zero */ 185/* par_0: dwordswap(flags<<16) or wordswap(flags)*/ 186 187#define SRB_GET_DMA_SPEEDS 16 188/* returns */ 189/* par_0: dwordswap(Read speed (bytes/sec)) */ 190/* par_1: dwordswap(Write speed (bytes/sec)) */ 191 192#define SRB_MODIFY_VC_RATE 17 193/* par_0: dwordswap(VC_number) */ 194/* par_1: dwordswap(fp_rate<<16) or wordswap(fp_rate) */ 195 196#define SRB_MODIFY_VC_FLAGS 18 197/* par_0: dwordswap(VC_number) */ 198/* par_1: dwordswap(flags<<16) or wordswap(flags)*/ 199 200/* flags: */ 201 202/* LANE: 0x0004 */ 203/* NOT_UBR: 0x0008 */ 204/* ABR: 0x0010 */ 205 206/* RxPool0: 0x0000 */ 207/* RxPool1: 0x0020 */ 208/* RxPool2: 0x0040 */ 209/* RxPool3: 0x0060 */ 210 211#define SRB_RATE_SHIFT 16 212#define SRB_POOL_SHIFT (SRB_FLAGS_SHIFT+5) 213#define SRB_FLAGS_SHIFT 16 214 215#define SRB_STOP_TASKING 19 216#define SRB_START_TASKING 20 217#define SRB_SHUT_DOWN 21 218#define MAX_SRB 21 219 220#define SRB_COMPLETE 0xffffffff 221 222#define TX_FRAME 0x80000000 223 224// number of types of SRB MUST be a power of two -- why? 225#define NUM_OF_SRB 32 226 227// number of bits of period info for rate 228#define MAX_RATE_BITS 6 229 230#define TX_UBR 0x0000 231#define TX_UBR_CAPPED 0x0008 232#define TX_ABR 0x0018 233#define TX_FRAME_NOTCAP 0x0000 234#define TX_FRAME_CAPPED 0x8000 235 236#define FP_155_RATE 0x24b1 237#define FP_25_RATE 0x1f9d 238 239/* #define VERSION_NUMBER 0x01000000 // initial release */ 240/* #define VERSION_NUMBER 0x01010000 // fixed startup probs PLX MB0 not cleared */ 241/* #define VERSION_NUMBER 0x01020000 // changed SUNI reset timings; allowed r/w onchip */ 242 243/* #define VERSION_NUMBER 0x01030000 // clear local doorbell int reg on reset */ 244/* remove race conditions on basic interface */ 245/* indicate to the host that diagnostics */ 246/* have finished; if failed, how and what */ 247/* failed */ 248/* fix host memory test to fix PLX bug */ 249/* allow flash upgrade and BIA upgrade directly */ 250/* */ 251#define VERSION_NUMBER 0x01050025 /* Jason's first hacked version. */ 252/* Change in download algorithm */ 253 254#define DMA_VALID 0xb728e149 /* completely random */ 255 256#define FLASH_BASE 0xa0c00000 257#define FLASH_SIZE 0x00020000 /* 128K */ 258#define BIA_BASE (FLASH_BASE+0x0001c000) /* Flash Sector 7 */ 259#define BIA_ADDRESS ((void *)0xa0c1c000) 260#define PLX_BASE 0xe0000000 261 262typedef enum { 263 host_memory_test = 1, 264 read_adapter_memory, 265 write_adapter_memory, 266 adapter_start, 267 get_version_number, 268 interrupt_host, 269 flash_erase_sector, 270 adap_download_block = 0x20, 271 adap_erase_flash, 272 adap_run_in_iram, 273 adap_end_download 274} loader_command; 275 276#define BAD_COMMAND (-1) 277#define COMMAND_IN_PROGRESS 1 278#define COMMAND_PASSED_TEST 2 279#define COMMAND_FAILED_TEST 3 280#define COMMAND_READ_DATA_OK 4 281#define COMMAND_READ_BAD_ADDRESS 5 282#define COMMAND_WRITE_DATA_OK 6 283#define COMMAND_WRITE_BAD_ADDRESS 7 284#define COMMAND_WRITE_FLASH_FAILURE 8 285#define COMMAND_COMPLETE 9 286#define COMMAND_FLASH_ERASE_FAILURE 10 287#define COMMAND_WRITE_BAD_DATA 11 288 289/* bit fields for mailbox[0] return values */ 290 291#define GPINT_TST_FAILURE 0x00000001 292#define SUNI_DATA_PATTERN_FAILURE 0x00000002 293#define SUNI_DATA_BITS_FAILURE 0x00000004 294#define SUNI_UTOPIA_FAILURE 0x00000008 295#define SUNI_FIFO_FAILURE 0x00000010 296#define SRAM_FAILURE 0x00000020 297#define SELF_TEST_FAILURE 0x0000003f 298 299/* mailbox[1] = 0 in progress, -1 on completion */ 300/* mailbox[2] = current test 00 00 test(8 bit) phase(8 bit) */ 301/* mailbox[3] = last failure, 00 00 test(8 bit) phase(8 bit) */ 302/* mailbox[4],mailbox[5],mailbox[6] random failure values */ 303 304/* PLX/etc. memory map including command structure */ 305 306/* These registers may also be memory mapped in PCI memory */ 307 308#define UNUSED_LOADER_MAILBOXES 6 309 310typedef struct { 311 u32 stuff[16]; 312 union { 313 struct { 314 u32 result; 315 u32 ready; 316 u32 stuff[UNUSED_LOADER_MAILBOXES]; 317 } loader; 318 struct { 319 u32 cmd_address; 320 u32 tx_address; 321 u32 rx_address[NUM_RX_POOLS]; 322 u32 gen_counter; 323 u32 spare; 324 } adapter; 325 } mb; 326 u32 doorbell; 327 u32 interrupt; 328 u32 interrupt_control; 329 u32 reset_control; 330} amb_mem; 331 332/* RESET bit, IRQ (card to host) and doorbell (host to card) enable bits */ 333#define AMB_RESET_BITS 0x40000000 334#define AMB_INTERRUPT_BITS 0x00000300 335#define AMB_DOORBELL_BITS 0x00030000 336 337/* loader commands */ 338 339#define MAX_COMMAND_DATA 13 340#define MAX_TRANSFER_DATA 11 341 342typedef struct { 343 __be32 address; 344 __be32 count; 345 __be32 data[MAX_TRANSFER_DATA]; 346} transfer_block; 347 348typedef struct { 349 __be32 result; 350 __be32 command; 351 union { 352 transfer_block transfer; 353 __be32 version; 354 __be32 start; 355 __be32 data[MAX_COMMAND_DATA]; 356 } payload; 357 __be32 valid; 358} loader_block; 359 360/* command queue */ 361 362/* Again all data are BIG ENDIAN */ 363 364typedef struct { 365 union { 366 struct { 367 __be32 vc; 368 __be32 flags; 369 __be32 rate; 370 } open; 371 struct { 372 __be32 vc; 373 __be32 rate; 374 } modify_rate; 375 struct { 376 __be32 vc; 377 __be32 flags; 378 } modify_flags; 379 struct { 380 __be32 vc; 381 } close; 382 struct { 383 __be32 lower4; 384 __be32 upper2; 385 } bia; 386 struct { 387 __be32 address; 388 } suni; 389 struct { 390 __be32 major; 391 __be32 minor; 392 } version; 393 struct { 394 __be32 read; 395 __be32 write; 396 } speed; 397 struct { 398 __be32 flags; 399 } flush; 400 struct { 401 __be32 address; 402 __be32 data; 403 } memory; 404 __be32 par[3]; 405 } args; 406 __be32 request; 407} command; 408 409/* transmit queues and associated structures */ 410 411/* The hosts transmit structure. All BIG ENDIAN; host address 412 restricted to first 1GByte, but address passed to the card must 413 have the top MS bit or'ed in. -- check this */ 414 415/* TX is described by 1+ tx_frags followed by a tx_frag_end */ 416 417typedef struct { 418 __be32 bytes; 419 __be32 address; 420} tx_frag; 421 422/* apart from handle the fields here are for the adapter to play with 423 and should be set to zero */ 424 425typedef struct { 426 u32 handle; 427 u16 vc; 428 u16 next_descriptor_length; 429 u32 next_descriptor; 430#ifdef AMB_NEW_MICROCODE 431 u8 cpcs_uu; 432 u8 cpi; 433 u16 pad; 434#endif 435} tx_frag_end; 436 437typedef struct { 438 tx_frag tx_frag; 439 tx_frag_end tx_frag_end; 440 struct sk_buff * skb; 441} tx_simple; 442 443 444/* this "points" to the sequence of fragments and trailer */ 445 446typedef struct { 447 __be16 vc; 448 __be16 tx_descr_length; 449 __be32 tx_descr_addr; 450} tx_in; 451 452/* handle is the handle from tx_in */ 453 454typedef struct { 455 u32 handle; 456} tx_out; 457 458/* receive frame structure */ 459 460/* All BIG ENDIAN; handle is as passed from host; length is zero for 461 aborted frames, and frames with errors. Header is actually VC 462 number, lec-id is NOT yet supported. */ 463 464typedef struct { 465 u32 handle; 466 __be16 vc; 467 __be16 lec_id; // unused 468 __be16 status; 469 __be16 length; 470} rx_out; 471 472/* buffer supply structure */ 473 474typedef struct { 475 u32 handle; 476 __be32 host_address; 477} rx_in; 478 479/* This first structure is the area in host memory where the adapter 480 writes its pointer values. These pointer values are BIG ENDIAN and 481 reside in the same 4MB 'page' as this structure. The host gives the 482 adapter the address of this block by sending a doorbell interrupt 483 to the adapter after downloading the code and setting it going. The 484 addresses have the top 10 bits set to 1010000010b -- really? 485 486 The host must initialise these before handing the block to the 487 adapter. */ 488 489typedef struct { 490 __be32 command_start; /* SRB commands completions */ 491 __be32 command_end; /* SRB commands completions */ 492 __be32 tx_start; 493 __be32 tx_end; 494 __be32 txcom_start; /* tx completions */ 495 __be32 txcom_end; /* tx completions */ 496 struct { 497 __be32 buffer_start; 498 __be32 buffer_end; 499 u32 buffer_q_get; 500 u32 buffer_q_end; 501 u32 buffer_aptr; 502 __be32 rx_start; /* rx completions */ 503 __be32 rx_end; 504 u32 rx_ptr; 505 __be32 buffer_size; /* size of host buffer */ 506 } rec_struct[NUM_RX_POOLS]; 507#ifdef AMB_NEW_MICROCODE 508 u16 init_flags; 509 u16 talk_block_spare; 510#endif 511} adap_talk_block; 512 513/* This structure must be kept in line with the vcr image in sarmain.h 514 515 This is the structure in the host filled in by the adapter by 516 GET_SUNI_STATS */ 517 518typedef struct { 519 u8 racp_chcs; 520 u8 racp_uhcs; 521 u16 spare; 522 u32 racp_rcell; 523 u32 tacp_tcell; 524 u32 flags; 525 u32 dropped_cells; 526 u32 dropped_frames; 527} suni_stats; 528 529typedef enum { 530 dead 531} amb_flags; 532 533#define NEXTQ(current,start,limit) \ 534 ( (current)+1 < (limit) ? (current)+1 : (start) ) 535 536typedef struct { 537 command * start; 538 command * in; 539 command * out; 540 command * limit; 541} amb_cq_ptrs; 542 543typedef struct { 544 spinlock_t lock; 545 unsigned int pending; 546 unsigned int high; 547 unsigned int filled; 548 unsigned int maximum; // size - 1 (q implementation) 549 amb_cq_ptrs ptrs; 550} amb_cq; 551 552typedef struct { 553 spinlock_t lock; 554 unsigned int pending; 555 unsigned int high; 556 unsigned int filled; 557 unsigned int maximum; // size - 1 (q implementation) 558 struct { 559 tx_in * start; 560 tx_in * ptr; 561 tx_in * limit; 562 } in; 563 struct { 564 tx_out * start; 565 tx_out * ptr; 566 tx_out * limit; 567 } out; 568} amb_txq; 569 570typedef struct { 571 spinlock_t lock; 572 unsigned int pending; 573 unsigned int low; 574 unsigned int emptied; 575 unsigned int maximum; // size - 1 (q implementation) 576 struct { 577 rx_in * start; 578 rx_in * ptr; 579 rx_in * limit; 580 } in; 581 struct { 582 rx_out * start; 583 rx_out * ptr; 584 rx_out * limit; 585 } out; 586 unsigned int buffers_wanted; 587 unsigned int buffer_size; 588} amb_rxq; 589 590typedef struct { 591 unsigned long tx_ok; 592 struct { 593 unsigned long ok; 594 unsigned long error; 595 unsigned long badcrc; 596 unsigned long toolong; 597 unsigned long aborted; 598 unsigned long unused; 599 } rx; 600} amb_stats; 601 602// a single struct pointed to by atm_vcc->dev_data 603 604typedef struct { 605 u8 tx_vc_bits:7; 606 u8 tx_present:1; 607} amb_tx_info; 608 609typedef struct { 610 unsigned char pool; 611} amb_rx_info; 612 613typedef struct { 614 amb_rx_info rx_info; 615 u16 tx_frame_bits; 616 unsigned int tx_rate; 617 unsigned int rx_rate; 618} amb_vcc; 619 620struct amb_dev { 621 u8 irq; 622 long flags; 623 u32 iobase; 624 u32 * membase; 625 626#ifdef FILL_RX_POOLS_IN_BH 627 struct work_struct bh; 628#endif 629 630 amb_cq cq; 631 amb_txq txq; 632 amb_rxq rxq[NUM_RX_POOLS]; 633 634 struct semaphore vcc_sf; 635 amb_tx_info txer[NUM_VCS]; 636 struct atm_vcc * rxer[NUM_VCS]; 637 unsigned int tx_avail; 638 unsigned int rx_avail; 639 640 amb_stats stats; 641 642 struct atm_dev * atm_dev; 643 struct pci_dev * pci_dev; 644 struct timer_list housekeeping; 645}; 646 647typedef struct amb_dev amb_dev; 648 649#define AMB_DEV(atm_dev) ((amb_dev *) (atm_dev)->dev_data) 650#define AMB_VCC(atm_vcc) ((amb_vcc *) (atm_vcc)->dev_data) 651 652/* the microcode */ 653 654typedef struct { 655 u32 start; 656 unsigned int count; 657} region; 658 659static region ucode_regions[]; 660static u32 ucode_data[]; 661static u32 ucode_start; 662 663/* rate rounding */ 664 665typedef enum { 666 round_up, 667 round_down, 668 round_nearest 669} rounding; 670 671#endif 672