1/* 2 * sata_promise.c - Promise SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2004 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * Hardware information only available under NDA. 30 * 31 */ 32 33#include <linux/kernel.h> 34#include <linux/module.h> 35#include <linux/pci.h> 36#include <linux/init.h> 37#include <linux/blkdev.h> 38#include <linux/delay.h> 39#include <linux/interrupt.h> 40#include <linux/device.h> 41#include <scsi/scsi.h> 42#include <scsi/scsi_host.h> 43#include <scsi/scsi_cmnd.h> 44#include <linux/libata.h> 45#include "sata_promise.h" 46 47#define DRV_NAME "sata_promise" 48#define DRV_VERSION "2.07" 49 50 51enum { 52 PDC_MAX_PORTS = 4, 53 PDC_MMIO_BAR = 3, 54 55 /* register offsets */ 56 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 57 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 58 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 59 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ 60 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ 61 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ 62 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 63 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 64 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 65 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 66 PDC_FLASH_CTL = 0x44, /* Flash control register */ 67 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 68 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 69 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 70 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 71 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 72 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 73 74 /* PDC_GLOBAL_CTL bit definitions */ 75 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 76 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ 77 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ 78 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ 79 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ 80 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ 81 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ 82 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ 83 PDC_DRIVE_ERR = (1 << 21), /* drive error */ 84 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ 85 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ 86 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, 87 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR, 88 PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR 89 | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR 90 | PDC1_ERR_MASK | PDC2_ERR_MASK), 91 92 board_2037x = 0, /* FastTrak S150 TX2plus */ 93 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ 94 board_20319 = 2, /* FastTrak S150 TX4 */ 95 board_20619 = 3, /* FastTrak TX4000 */ 96 board_2057x = 4, /* SATAII150 Tx2plus */ 97 board_2057x_pata = 5, /* SATAII150 Tx2plus */ 98 board_40518 = 6, /* SATAII150 Tx4 */ 99 100 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 101 102 /* Sequence counter control registers bit definitions */ 103 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ 104 105 /* Feature register values */ 106 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ 107 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ 108 109 /* Device/Head register values */ 110 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ 111 112 /* PDC_CTLSTAT bit definitions */ 113 PDC_DMA_ENABLE = (1 << 7), 114 PDC_IRQ_DISABLE = (1 << 10), 115 PDC_RESET = (1 << 11), /* HDMA reset */ 116 117 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | 118 ATA_FLAG_MMIO | 119 ATA_FLAG_PIO_POLLING, 120 121 /* ap->flags bits */ 122 PDC_FLAG_GEN_II = (1 << 24), 123 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ 124 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ 125}; 126 127 128struct pdc_port_priv { 129 u8 *pkt; 130 dma_addr_t pkt_dma; 131}; 132 133static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); 134static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 135static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 136static int pdc_common_port_start(struct ata_port *ap); 137static int pdc_sata_port_start(struct ata_port *ap); 138static void pdc_qc_prep(struct ata_queued_cmd *qc); 139static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 140static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 141static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 142static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); 143static void pdc_irq_clear(struct ata_port *ap); 144static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); 145static void pdc_freeze(struct ata_port *ap); 146static void pdc_thaw(struct ata_port *ap); 147static void pdc_pata_error_handler(struct ata_port *ap); 148static void pdc_sata_error_handler(struct ata_port *ap); 149static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 150static int pdc_pata_cable_detect(struct ata_port *ap); 151static int pdc_sata_cable_detect(struct ata_port *ap); 152 153static struct scsi_host_template pdc_ata_sht = { 154 .module = THIS_MODULE, 155 .name = DRV_NAME, 156 .ioctl = ata_scsi_ioctl, 157 .queuecommand = ata_scsi_queuecmd, 158 .can_queue = ATA_DEF_QUEUE, 159 .this_id = ATA_SHT_THIS_ID, 160 .sg_tablesize = LIBATA_MAX_PRD, 161 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 162 .emulated = ATA_SHT_EMULATED, 163 .use_clustering = ATA_SHT_USE_CLUSTERING, 164 .proc_name = DRV_NAME, 165 .dma_boundary = ATA_DMA_BOUNDARY, 166 .slave_configure = ata_scsi_slave_config, 167 .slave_destroy = ata_scsi_slave_destroy, 168 .bios_param = ata_std_bios_param, 169}; 170 171static const struct ata_port_operations pdc_sata_ops = { 172 .port_disable = ata_port_disable, 173 .tf_load = pdc_tf_load_mmio, 174 .tf_read = ata_tf_read, 175 .check_status = ata_check_status, 176 .exec_command = pdc_exec_command_mmio, 177 .dev_select = ata_std_dev_select, 178 .check_atapi_dma = pdc_check_atapi_dma, 179 180 .qc_prep = pdc_qc_prep, 181 .qc_issue = pdc_qc_issue_prot, 182 .freeze = pdc_freeze, 183 .thaw = pdc_thaw, 184 .error_handler = pdc_sata_error_handler, 185 .post_internal_cmd = pdc_post_internal_cmd, 186 .cable_detect = pdc_sata_cable_detect, 187 .data_xfer = ata_data_xfer, 188 .irq_clear = pdc_irq_clear, 189 .irq_on = ata_irq_on, 190 .irq_ack = ata_irq_ack, 191 192 .scr_read = pdc_sata_scr_read, 193 .scr_write = pdc_sata_scr_write, 194 .port_start = pdc_sata_port_start, 195}; 196 197/* First-generation chips need a more restrictive ->check_atapi_dma op */ 198static const struct ata_port_operations pdc_old_sata_ops = { 199 .port_disable = ata_port_disable, 200 .tf_load = pdc_tf_load_mmio, 201 .tf_read = ata_tf_read, 202 .check_status = ata_check_status, 203 .exec_command = pdc_exec_command_mmio, 204 .dev_select = ata_std_dev_select, 205 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 206 207 .qc_prep = pdc_qc_prep, 208 .qc_issue = pdc_qc_issue_prot, 209 .freeze = pdc_freeze, 210 .thaw = pdc_thaw, 211 .error_handler = pdc_sata_error_handler, 212 .post_internal_cmd = pdc_post_internal_cmd, 213 .cable_detect = pdc_sata_cable_detect, 214 .data_xfer = ata_data_xfer, 215 .irq_clear = pdc_irq_clear, 216 .irq_on = ata_irq_on, 217 .irq_ack = ata_irq_ack, 218 219 .scr_read = pdc_sata_scr_read, 220 .scr_write = pdc_sata_scr_write, 221 .port_start = pdc_sata_port_start, 222}; 223 224static const struct ata_port_operations pdc_pata_ops = { 225 .port_disable = ata_port_disable, 226 .tf_load = pdc_tf_load_mmio, 227 .tf_read = ata_tf_read, 228 .check_status = ata_check_status, 229 .exec_command = pdc_exec_command_mmio, 230 .dev_select = ata_std_dev_select, 231 .check_atapi_dma = pdc_check_atapi_dma, 232 233 .qc_prep = pdc_qc_prep, 234 .qc_issue = pdc_qc_issue_prot, 235 .freeze = pdc_freeze, 236 .thaw = pdc_thaw, 237 .error_handler = pdc_pata_error_handler, 238 .post_internal_cmd = pdc_post_internal_cmd, 239 .cable_detect = pdc_pata_cable_detect, 240 .data_xfer = ata_data_xfer, 241 .irq_clear = pdc_irq_clear, 242 .irq_on = ata_irq_on, 243 .irq_ack = ata_irq_ack, 244 245 .port_start = pdc_common_port_start, 246}; 247 248static const struct ata_port_info pdc_port_info[] = { 249 /* board_2037x */ 250 { 251 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 252 PDC_FLAG_SATA_PATA, 253 .pio_mask = 0x1f, /* pio0-4 */ 254 .mwdma_mask = 0x07, /* mwdma0-2 */ 255 .udma_mask = 0x7f, 256 .port_ops = &pdc_old_sata_ops, 257 }, 258 259 /* board_2037x_pata */ 260 { 261 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 262 .pio_mask = 0x1f, /* pio0-4 */ 263 .mwdma_mask = 0x07, /* mwdma0-2 */ 264 .udma_mask = 0x7f, 265 .port_ops = &pdc_pata_ops, 266 }, 267 268 /* board_20319 */ 269 { 270 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 271 PDC_FLAG_4_PORTS, 272 .pio_mask = 0x1f, /* pio0-4 */ 273 .mwdma_mask = 0x07, /* mwdma0-2 */ 274 .udma_mask = 0x7f, 275 .port_ops = &pdc_old_sata_ops, 276 }, 277 278 /* board_20619 */ 279 { 280 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 281 PDC_FLAG_4_PORTS, 282 .pio_mask = 0x1f, /* pio0-4 */ 283 .mwdma_mask = 0x07, /* mwdma0-2 */ 284 .udma_mask = 0x7f, 285 .port_ops = &pdc_pata_ops, 286 }, 287 288 /* board_2057x */ 289 { 290 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 291 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, 292 .pio_mask = 0x1f, /* pio0-4 */ 293 .mwdma_mask = 0x07, /* mwdma0-2 */ 294 .udma_mask = 0x7f, 295 .port_ops = &pdc_sata_ops, 296 }, 297 298 /* board_2057x_pata */ 299 { 300 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 301 PDC_FLAG_GEN_II, 302 .pio_mask = 0x1f, /* pio0-4 */ 303 .mwdma_mask = 0x07, /* mwdma0-2 */ 304 .udma_mask = 0x7f, 305 .port_ops = &pdc_pata_ops, 306 }, 307 308 /* board_40518 */ 309 { 310 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 311 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, 312 .pio_mask = 0x1f, /* pio0-4 */ 313 .mwdma_mask = 0x07, /* mwdma0-2 */ 314 .udma_mask = 0x7f, 315 .port_ops = &pdc_sata_ops, 316 }, 317}; 318 319static const struct pci_device_id pdc_ata_pci_tbl[] = { 320 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 321 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 322 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 323 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 324 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, 325 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, 326 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 327 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, 328 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, 329 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 330 331 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 332 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 333 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, 334 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, 335 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, 336 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 337 338 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 339 340 { } /* terminate list */ 341}; 342 343 344static struct pci_driver pdc_ata_pci_driver = { 345 .name = DRV_NAME, 346 .id_table = pdc_ata_pci_tbl, 347 .probe = pdc_ata_init_one, 348 .remove = ata_pci_remove_one, 349}; 350 351 352static int pdc_common_port_start(struct ata_port *ap) 353{ 354 struct device *dev = ap->host->dev; 355 struct pdc_port_priv *pp; 356 int rc; 357 358 rc = ata_port_start(ap); 359 if (rc) 360 return rc; 361 362 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 363 if (!pp) 364 return -ENOMEM; 365 366 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 367 if (!pp->pkt) 368 return -ENOMEM; 369 370 ap->private_data = pp; 371 372 return 0; 373} 374 375static int pdc_sata_port_start(struct ata_port *ap) 376{ 377 int rc; 378 379 rc = pdc_common_port_start(ap); 380 if (rc) 381 return rc; 382 383 /* fix up PHYMODE4 align timing */ 384 if (ap->flags & PDC_FLAG_GEN_II) { 385 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr; 386 unsigned int tmp; 387 388 tmp = readl(mmio + 0x014); 389 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 390 writel(tmp, mmio + 0x014); 391 } 392 393 return 0; 394} 395 396static void pdc_reset_port(struct ata_port *ap) 397{ 398 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 399 unsigned int i; 400 u32 tmp; 401 402 for (i = 11; i > 0; i--) { 403 tmp = readl(mmio); 404 if (tmp & PDC_RESET) 405 break; 406 407 udelay(100); 408 409 tmp |= PDC_RESET; 410 writel(tmp, mmio); 411 } 412 413 tmp &= ~PDC_RESET; 414 writel(tmp, mmio); 415 readl(mmio); /* flush */ 416} 417 418static int pdc_pata_cable_detect(struct ata_port *ap) 419{ 420 u8 tmp; 421 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; 422 423 tmp = readb(mmio); 424 if (tmp & 0x01) 425 return ATA_CBL_PATA40; 426 return ATA_CBL_PATA80; 427} 428 429static int pdc_sata_cable_detect(struct ata_port *ap) 430{ 431 return ATA_CBL_SATA; 432} 433 434static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) 435{ 436 if (sc_reg > SCR_CONTROL) 437 return 0xffffffffU; 438 return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 439} 440 441 442static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, 443 u32 val) 444{ 445 if (sc_reg > SCR_CONTROL) 446 return; 447 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 448} 449 450static void pdc_atapi_pkt(struct ata_queued_cmd *qc) 451{ 452 struct ata_port *ap = qc->ap; 453 dma_addr_t sg_table = ap->prd_dma; 454 unsigned int cdb_len = qc->dev->cdb_len; 455 u8 *cdb = qc->cdb; 456 struct pdc_port_priv *pp = ap->private_data; 457 u8 *buf = pp->pkt; 458 u32 *buf32 = (u32 *) buf; 459 unsigned int dev_sel, feature, nbytes; 460 461 /* set control bits (byte 0), zero delay seq id (byte 3), 462 * and seq id (byte 2) 463 */ 464 switch (qc->tf.protocol) { 465 case ATA_PROT_ATAPI_DMA: 466 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 467 buf32[0] = cpu_to_le32(PDC_PKT_READ); 468 else 469 buf32[0] = 0; 470 break; 471 case ATA_PROT_ATAPI_NODATA: 472 buf32[0] = cpu_to_le32(PDC_PKT_NODATA); 473 break; 474 default: 475 BUG(); 476 break; 477 } 478 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 479 buf32[2] = 0; /* no next-packet */ 480 481 /* select drive */ 482 if (sata_scr_valid(ap)) { 483 dev_sel = PDC_DEVICE_SATA; 484 } else { 485 dev_sel = ATA_DEVICE_OBS; 486 if (qc->dev->devno != 0) 487 dev_sel |= ATA_DEV1; 488 } 489 buf[12] = (1 << 5) | ATA_REG_DEVICE; 490 buf[13] = dev_sel; 491 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; 492 buf[15] = dev_sel; /* once more, waiting for BSY to clear */ 493 494 buf[16] = (1 << 5) | ATA_REG_NSECT; 495 buf[17] = 0x00; 496 buf[18] = (1 << 5) | ATA_REG_LBAL; 497 buf[19] = 0x00; 498 499 /* set feature and byte counter registers */ 500 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { 501 feature = PDC_FEATURE_ATAPI_PIO; 502 /* set byte counter register to real transfer byte count */ 503 nbytes = qc->nbytes; 504 if (nbytes > 0xffff) 505 nbytes = 0xffff; 506 } else { 507 feature = PDC_FEATURE_ATAPI_DMA; 508 /* set byte counter register to 0 */ 509 nbytes = 0; 510 } 511 buf[20] = (1 << 5) | ATA_REG_FEATURE; 512 buf[21] = feature; 513 buf[22] = (1 << 5) | ATA_REG_BYTEL; 514 buf[23] = nbytes & 0xFF; 515 buf[24] = (1 << 5) | ATA_REG_BYTEH; 516 buf[25] = (nbytes >> 8) & 0xFF; 517 518 /* send ATAPI packet command 0xA0 */ 519 buf[26] = (1 << 5) | ATA_REG_CMD; 520 buf[27] = ATA_CMD_PACKET; 521 522 /* select drive and check DRQ */ 523 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; 524 buf[29] = dev_sel; 525 526 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 527 BUG_ON(cdb_len & ~0x1E); 528 529 /* append the CDB as the final part */ 530 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 531 memcpy(buf+31, cdb, cdb_len); 532} 533 534static void pdc_qc_prep(struct ata_queued_cmd *qc) 535{ 536 struct pdc_port_priv *pp = qc->ap->private_data; 537 unsigned int i; 538 539 VPRINTK("ENTER\n"); 540 541 switch (qc->tf.protocol) { 542 case ATA_PROT_DMA: 543 ata_qc_prep(qc); 544 /* fall through */ 545 546 case ATA_PROT_NODATA: 547 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, 548 qc->dev->devno, pp->pkt); 549 550 if (qc->tf.flags & ATA_TFLAG_LBA48) 551 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 552 else 553 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 554 555 pdc_pkt_footer(&qc->tf, pp->pkt, i); 556 break; 557 558 case ATA_PROT_ATAPI: 559 ata_qc_prep(qc); 560 break; 561 562 case ATA_PROT_ATAPI_DMA: 563 ata_qc_prep(qc); 564 /*FALLTHROUGH*/ 565 case ATA_PROT_ATAPI_NODATA: 566 pdc_atapi_pkt(qc); 567 break; 568 569 default: 570 break; 571 } 572} 573 574static void pdc_freeze(struct ata_port *ap) 575{ 576 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; 577 u32 tmp; 578 579 tmp = readl(mmio + PDC_CTLSTAT); 580 tmp |= PDC_IRQ_DISABLE; 581 tmp &= ~PDC_DMA_ENABLE; 582 writel(tmp, mmio + PDC_CTLSTAT); 583 readl(mmio + PDC_CTLSTAT); /* flush */ 584} 585 586static void pdc_thaw(struct ata_port *ap) 587{ 588 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; 589 u32 tmp; 590 591 /* clear IRQ */ 592 readl(mmio + PDC_INT_SEQMASK); 593 594 /* turn IRQ back on */ 595 tmp = readl(mmio + PDC_CTLSTAT); 596 tmp &= ~PDC_IRQ_DISABLE; 597 writel(tmp, mmio + PDC_CTLSTAT); 598 readl(mmio + PDC_CTLSTAT); /* flush */ 599} 600 601static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset) 602{ 603 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 604 pdc_reset_port(ap); 605 606 /* perform recovery */ 607 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, 608 ata_std_postreset); 609} 610 611static void pdc_pata_error_handler(struct ata_port *ap) 612{ 613 pdc_common_error_handler(ap, NULL); 614} 615 616static void pdc_sata_error_handler(struct ata_port *ap) 617{ 618 pdc_common_error_handler(ap, sata_std_hardreset); 619} 620 621static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 622{ 623 struct ata_port *ap = qc->ap; 624 625 /* make DMA engine forget about the failed command */ 626 if (qc->flags & ATA_QCFLAG_FAILED) 627 pdc_reset_port(ap); 628} 629 630static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, 631 u32 port_status, u32 err_mask) 632{ 633 struct ata_eh_info *ehi = &ap->eh_info; 634 unsigned int ac_err_mask = 0; 635 636 ata_ehi_clear_desc(ehi); 637 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); 638 port_status &= err_mask; 639 640 if (port_status & PDC_DRIVE_ERR) 641 ac_err_mask |= AC_ERR_DEV; 642 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) 643 ac_err_mask |= AC_ERR_HSM; 644 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) 645 ac_err_mask |= AC_ERR_ATA_BUS; 646 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR 647 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) 648 ac_err_mask |= AC_ERR_HOST_BUS; 649 650 if (sata_scr_valid(ap)) 651 ehi->serror |= pdc_sata_scr_read(ap, SCR_ERROR); 652 653 qc->err_mask |= ac_err_mask; 654 655 pdc_reset_port(ap); 656 657 ata_port_abort(ap); 658} 659 660static inline unsigned int pdc_host_intr( struct ata_port *ap, 661 struct ata_queued_cmd *qc) 662{ 663 unsigned int handled = 0; 664 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 665 u32 port_status, err_mask; 666 667 err_mask = PDC_ERR_MASK; 668 if (ap->flags & PDC_FLAG_GEN_II) 669 err_mask &= ~PDC1_ERR_MASK; 670 else 671 err_mask &= ~PDC2_ERR_MASK; 672 port_status = readl(port_mmio + PDC_GLOBAL_CTL); 673 if (unlikely(port_status & err_mask)) { 674 pdc_error_intr(ap, qc, port_status, err_mask); 675 return 1; 676 } 677 678 switch (qc->tf.protocol) { 679 case ATA_PROT_DMA: 680 case ATA_PROT_NODATA: 681 case ATA_PROT_ATAPI_DMA: 682 case ATA_PROT_ATAPI_NODATA: 683 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 684 ata_qc_complete(qc); 685 handled = 1; 686 break; 687 688 default: 689 ap->stats.idle_irq++; 690 break; 691 } 692 693 return handled; 694} 695 696static void pdc_irq_clear(struct ata_port *ap) 697{ 698 struct ata_host *host = ap->host; 699 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 700 701 readl(mmio + PDC_INT_SEQMASK); 702} 703 704static irqreturn_t pdc_interrupt (int irq, void *dev_instance) 705{ 706 struct ata_host *host = dev_instance; 707 struct ata_port *ap; 708 u32 mask = 0; 709 unsigned int i, tmp; 710 unsigned int handled = 0; 711 void __iomem *mmio_base; 712 713 VPRINTK("ENTER\n"); 714 715 if (!host || !host->iomap[PDC_MMIO_BAR]) { 716 VPRINTK("QUICK EXIT\n"); 717 return IRQ_NONE; 718 } 719 720 mmio_base = host->iomap[PDC_MMIO_BAR]; 721 722 /* reading should also clear interrupts */ 723 mask = readl(mmio_base + PDC_INT_SEQMASK); 724 725 if (mask == 0xffffffff) { 726 VPRINTK("QUICK EXIT 2\n"); 727 return IRQ_NONE; 728 } 729 730 spin_lock(&host->lock); 731 732 mask &= 0xffff; /* only 16 tags possible */ 733 if (!mask) { 734 VPRINTK("QUICK EXIT 3\n"); 735 goto done_irq; 736 } 737 738 writel(mask, mmio_base + PDC_INT_SEQMASK); 739 740 for (i = 0; i < host->n_ports; i++) { 741 VPRINTK("port %u\n", i); 742 ap = host->ports[i]; 743 tmp = mask & (1 << (i + 1)); 744 if (tmp && ap && 745 !(ap->flags & ATA_FLAG_DISABLED)) { 746 struct ata_queued_cmd *qc; 747 748 qc = ata_qc_from_tag(ap, ap->active_tag); 749 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 750 handled += pdc_host_intr(ap, qc); 751 } 752 } 753 754 VPRINTK("EXIT\n"); 755 756done_irq: 757 spin_unlock(&host->lock); 758 return IRQ_RETVAL(handled); 759} 760 761static inline void pdc_packet_start(struct ata_queued_cmd *qc) 762{ 763 struct ata_port *ap = qc->ap; 764 struct pdc_port_priv *pp = ap->private_data; 765 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; 766 unsigned int port_no = ap->port_no; 767 u8 seq = (u8) (port_no + 1); 768 769 VPRINTK("ENTER, ap %p\n", ap); 770 771 writel(0x00000001, mmio + (seq * 4)); 772 readl(mmio + (seq * 4)); /* flush */ 773 774 pp->pkt[2] = seq; 775 wmb(); /* flush PRD, pkt writes */ 776 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 777 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ 778} 779 780static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) 781{ 782 switch (qc->tf.protocol) { 783 case ATA_PROT_ATAPI_NODATA: 784 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 785 break; 786 /*FALLTHROUGH*/ 787 case ATA_PROT_NODATA: 788 if (qc->tf.flags & ATA_TFLAG_POLLING) 789 break; 790 /*FALLTHROUGH*/ 791 case ATA_PROT_ATAPI_DMA: 792 case ATA_PROT_DMA: 793 pdc_packet_start(qc); 794 return 0; 795 796 default: 797 break; 798 } 799 800 return ata_qc_issue_prot(qc); 801} 802 803static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 804{ 805 WARN_ON (tf->protocol == ATA_PROT_DMA || 806 tf->protocol == ATA_PROT_ATAPI_DMA); 807 ata_tf_load(ap, tf); 808} 809 810 811static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 812{ 813 WARN_ON (tf->protocol == ATA_PROT_DMA || 814 tf->protocol == ATA_PROT_ATAPI_DMA); 815 ata_exec_command(ap, tf); 816} 817 818static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) 819{ 820 u8 *scsicmd = qc->scsicmd->cmnd; 821 int pio = 1; /* atapi dma off by default */ 822 823 /* Whitelist commands that may use DMA. */ 824 switch (scsicmd[0]) { 825 case WRITE_12: 826 case WRITE_10: 827 case WRITE_6: 828 case READ_12: 829 case READ_10: 830 case READ_6: 831 case 0xad: /* READ_DVD_STRUCTURE */ 832 case 0xbe: /* READ_CD */ 833 pio = 0; 834 } 835 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ 836 if (scsicmd[0] == WRITE_10) { 837 unsigned int lba; 838 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; 839 if (lba >= 0xFFFF4FA2) 840 pio = 1; 841 } 842 return pio; 843} 844 845static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) 846{ 847 /* First generation chips cannot use ATAPI DMA on SATA ports */ 848 return 1; 849} 850 851static void pdc_ata_setup_port(struct ata_port *ap, 852 void __iomem *base, void __iomem *scr_addr) 853{ 854 ap->ioaddr.cmd_addr = base; 855 ap->ioaddr.data_addr = base; 856 ap->ioaddr.feature_addr = 857 ap->ioaddr.error_addr = base + 0x4; 858 ap->ioaddr.nsect_addr = base + 0x8; 859 ap->ioaddr.lbal_addr = base + 0xc; 860 ap->ioaddr.lbam_addr = base + 0x10; 861 ap->ioaddr.lbah_addr = base + 0x14; 862 ap->ioaddr.device_addr = base + 0x18; 863 ap->ioaddr.command_addr = 864 ap->ioaddr.status_addr = base + 0x1c; 865 ap->ioaddr.altstatus_addr = 866 ap->ioaddr.ctl_addr = base + 0x38; 867 ap->ioaddr.scr_addr = scr_addr; 868} 869 870 871static void pdc_host_init(struct ata_host *host) 872{ 873 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 874 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 875 int hotplug_offset; 876 u32 tmp; 877 878 if (is_gen2) 879 hotplug_offset = PDC2_SATA_PLUG_CSR; 880 else 881 hotplug_offset = PDC_SATA_PLUG_CSR; 882 883 /* 884 * Except for the hotplug stuff, this is voodoo from the 885 * Promise driver. Label this entire section 886 * "TODO: figure out why we do this" 887 */ 888 889 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 890 tmp = readl(mmio + PDC_FLASH_CTL); 891 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 892 if (!is_gen2) 893 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 894 writel(tmp, mmio + PDC_FLASH_CTL); 895 896 /* clear plug/unplug flags for all ports */ 897 tmp = readl(mmio + hotplug_offset); 898 writel(tmp | 0xff, mmio + hotplug_offset); 899 900 /* mask plug/unplug ints */ 901 tmp = readl(mmio + hotplug_offset); 902 writel(tmp | 0xff0000, mmio + hotplug_offset); 903 904 /* don't initialise TBG or SLEW on 2nd generation chips */ 905 if (is_gen2) 906 return; 907 908 /* reduce TBG clock to 133 Mhz. */ 909 tmp = readl(mmio + PDC_TBG_MODE); 910 tmp &= ~0x30000; /* clear bit 17, 16*/ 911 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 912 writel(tmp, mmio + PDC_TBG_MODE); 913 914 readl(mmio + PDC_TBG_MODE); /* flush */ 915 msleep(10); 916 917 /* adjust slew rate control register. */ 918 tmp = readl(mmio + PDC_SLEW_CTL); 919 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 920 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 921 writel(tmp, mmio + PDC_SLEW_CTL); 922} 923 924static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 925{ 926 static int printed_version; 927 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 928 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 929 struct ata_host *host; 930 void __iomem *base; 931 int n_ports, i, rc; 932 int is_sataii_tx4; 933 934 if (!printed_version++) 935 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 936 937 /* enable and acquire resources */ 938 rc = pcim_enable_device(pdev); 939 if (rc) 940 return rc; 941 942 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 943 if (rc == -EBUSY) 944 pcim_pin_device(pdev); 945 if (rc) 946 return rc; 947 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 948 949 /* determine port configuration and setup host */ 950 n_ports = 2; 951 if (pi->flags & PDC_FLAG_4_PORTS) 952 n_ports = 4; 953 for (i = 0; i < n_ports; i++) 954 ppi[i] = pi; 955 956 if (pi->flags & PDC_FLAG_SATA_PATA) { 957 u8 tmp = readb(base + PDC_FLASH_CTL+1); 958 if (!(tmp & 0x80)) { 959 ppi[n_ports++] = pi + 1; 960 dev_printk(KERN_INFO, &pdev->dev, "PATA port found\n"); 961 } 962 } 963 964 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 965 if (!host) { 966 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); 967 return -ENOMEM; 968 } 969 host->iomap = pcim_iomap_table(pdev); 970 971 is_sataii_tx4 = 0; 972 if ((pi->flags & (PDC_FLAG_GEN_II|PDC_FLAG_4_PORTS)) == (PDC_FLAG_GEN_II|PDC_FLAG_4_PORTS)) { 973 is_sataii_tx4 = 1; 974 dev_printk(KERN_INFO, &pdev->dev, "applying SATAII TX4 port numbering workaround\n"); 975 } 976 for (i = 0; i < host->n_ports; i++) { 977 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; 978 int ata_nr; 979 980 ata_nr = i; 981 if (is_sataii_tx4) 982 ata_nr = sataii_tx4_port_remap[i]; 983 984 pdc_ata_setup_port(host->ports[i], 985 base + 0x200 + ata_nr * 0x80, 986 base + 0x400 + ata_nr * 0x100); 987 } 988 989 /* initialize adapter */ 990 pdc_host_init(host); 991 992 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 993 if (rc) 994 return rc; 995 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 996 if (rc) 997 return rc; 998 999 /* start host, request IRQ and attach */ 1000 pci_set_master(pdev); 1001 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, 1002 &pdc_ata_sht); 1003} 1004 1005 1006static int __init pdc_ata_init(void) 1007{ 1008 return pci_register_driver(&pdc_ata_pci_driver); 1009} 1010 1011 1012static void __exit pdc_ata_exit(void) 1013{ 1014 pci_unregister_driver(&pdc_ata_pci_driver); 1015} 1016 1017 1018MODULE_AUTHOR("Jeff Garzik"); 1019MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); 1020MODULE_LICENSE("GPL"); 1021MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); 1022MODULE_VERSION(DRV_VERSION); 1023 1024module_init(pdc_ata_init); 1025module_exit(pdc_ata_exit); 1026