1#include <linux/kernel.h> 2#include <linux/module.h> 3#include <linux/init.h> 4#include <linux/blkdev.h> 5#include <scsi/scsi_host.h> 6#include <linux/ata.h> 7#include <linux/libata.h> 8 9#include <asm/dma.h> 10#include <asm/ecard.h> 11 12#define DRV_NAME "pata_icside" 13 14#define ICS_IDENT_OFFSET 0x2280 15 16#define ICS_ARCIN_V5_INTRSTAT 0x0000 17#define ICS_ARCIN_V5_INTROFFSET 0x0004 18 19#define ICS_ARCIN_V6_INTROFFSET_1 0x2200 20#define ICS_ARCIN_V6_INTRSTAT_1 0x2290 21#define ICS_ARCIN_V6_INTROFFSET_2 0x3200 22#define ICS_ARCIN_V6_INTRSTAT_2 0x3290 23 24struct portinfo { 25 unsigned int dataoffset; 26 unsigned int ctrloffset; 27 unsigned int stepping; 28}; 29 30static const struct portinfo pata_icside_portinfo_v5 = { 31 .dataoffset = 0x2800, 32 .ctrloffset = 0x2b80, 33 .stepping = 6, 34}; 35 36static const struct portinfo pata_icside_portinfo_v6_1 = { 37 .dataoffset = 0x2000, 38 .ctrloffset = 0x2380, 39 .stepping = 6, 40}; 41 42static const struct portinfo pata_icside_portinfo_v6_2 = { 43 .dataoffset = 0x3000, 44 .ctrloffset = 0x3380, 45 .stepping = 6, 46}; 47 48#define PATA_ICSIDE_MAX_SG 128 49 50struct pata_icside_state { 51 void __iomem *irq_port; 52 void __iomem *ioc_base; 53 unsigned int type; 54 unsigned int dma; 55 struct { 56 u8 port_sel; 57 u8 disabled; 58 unsigned int speed[ATA_MAX_DEVICES]; 59 } port[2]; 60 struct scatterlist sg[PATA_ICSIDE_MAX_SG]; 61}; 62 63struct pata_icside_info { 64 struct pata_icside_state *state; 65 struct expansion_card *ec; 66 void __iomem *base; 67 void __iomem *irqaddr; 68 unsigned int irqmask; 69 const expansioncard_ops_t *irqops; 70 unsigned int mwdma_mask; 71 unsigned int nr_ports; 72 const struct portinfo *port[2]; 73}; 74 75#define ICS_TYPE_A3IN 0 76#define ICS_TYPE_A3USER 1 77#define ICS_TYPE_V6 3 78#define ICS_TYPE_V5 15 79#define ICS_TYPE_NOTYPE ((unsigned int)-1) 80 81/* ---------------- Version 5 PCB Support Functions --------------------- */ 82/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) 83 * Purpose : enable interrupts from card 84 */ 85static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) 86{ 87 struct pata_icside_state *state = ec->irq_data; 88 89 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); 90} 91 92/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) 93 * Purpose : disable interrupts from card 94 */ 95static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) 96{ 97 struct pata_icside_state *state = ec->irq_data; 98 99 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); 100} 101 102static const expansioncard_ops_t pata_icside_ops_arcin_v5 = { 103 .irqenable = pata_icside_irqenable_arcin_v5, 104 .irqdisable = pata_icside_irqdisable_arcin_v5, 105}; 106 107 108/* ---------------- Version 6 PCB Support Functions --------------------- */ 109/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) 110 * Purpose : enable interrupts from card 111 */ 112static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) 113{ 114 struct pata_icside_state *state = ec->irq_data; 115 void __iomem *base = state->irq_port; 116 117 if (!state->port[0].disabled) 118 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); 119 if (!state->port[1].disabled) 120 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); 121} 122 123/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) 124 * Purpose : disable interrupts from card 125 */ 126static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) 127{ 128 struct pata_icside_state *state = ec->irq_data; 129 130 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); 131 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); 132} 133 134/* Prototype: pata_icside_irqprobe(struct expansion_card *ec) 135 * Purpose : detect an active interrupt from card 136 */ 137static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec) 138{ 139 struct pata_icside_state *state = ec->irq_data; 140 141 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || 142 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; 143} 144 145static const expansioncard_ops_t pata_icside_ops_arcin_v6 = { 146 .irqenable = pata_icside_irqenable_arcin_v6, 147 .irqdisable = pata_icside_irqdisable_arcin_v6, 148 .irqpending = pata_icside_irqpending_arcin_v6, 149}; 150 151 152/* 153 * SG-DMA support. 154 * 155 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers. 156 * There is only one DMA controller per card, which means that only 157 * one drive can be accessed at one time. NOTE! We do not enforce that 158 * here, but we rely on the main IDE driver spotting that both 159 * interfaces use the same IRQ, which should guarantee this. 160 */ 161 162/* 163 * Configure the IOMD to give the appropriate timings for the transfer 164 * mode being requested. We take the advice of the ATA standards, and 165 * calculate the cycle time based on the transfer mode, and the EIDE 166 * MW DMA specs that the drive provides in the IDENTIFY command. 167 * 168 * We have the following IOMD DMA modes to choose from: 169 * 170 * Type Active Recovery Cycle 171 * A 250 (250) 312 (550) 562 (800) 172 * B 187 (200) 250 (550) 437 (750) 173 * C 125 (125) 125 (375) 250 (500) 174 * D 62 (50) 125 (375) 187 (425) 175 * 176 * (figures in brackets are actual measured timings on DIOR/DIOW) 177 * 178 * However, we also need to take care of the read/write active and 179 * recovery timings: 180 * 181 * Read Write 182 * Mode Active -- Recovery -- Cycle IOMD type 183 * MW0 215 50 215 480 A 184 * MW1 80 50 50 150 C 185 * MW2 70 25 25 120 C 186 */ 187static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev) 188{ 189 struct pata_icside_state *state = ap->host->private_data; 190 struct ata_timing t; 191 unsigned int cycle; 192 char iomd_type; 193 194 /* 195 * DMA is based on a 16MHz clock 196 */ 197 if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1)) 198 return; 199 200 /* 201 * Choose the IOMD cycle timing which ensure that the interface 202 * satisfies the measured active, recovery and cycle times. 203 */ 204 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) 205 iomd_type = 'D', cycle = 187; 206 else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) 207 iomd_type = 'C', cycle = 250; 208 else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) 209 iomd_type = 'B', cycle = 437; 210 else 211 iomd_type = 'A', cycle = 562; 212 213 ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n", 214 t.active, t.recover, t.cycle, iomd_type); 215 216 state->port[ap->port_no].speed[adev->devno] = cycle; 217} 218 219static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc) 220{ 221 struct ata_port *ap = qc->ap; 222 struct pata_icside_state *state = ap->host->private_data; 223 struct scatterlist *sg, *rsg = state->sg; 224 unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE; 225 226 /* 227 * We are simplex; BUG if we try to fiddle with DMA 228 * while it's active. 229 */ 230 BUG_ON(dma_channel_active(state->dma)); 231 232 /* 233 * Copy ATAs scattered sg list into a contiguous array of sg 234 */ 235 ata_for_each_sg(sg, qc) { 236 memcpy(rsg, sg, sizeof(*sg)); 237 rsg++; 238 } 239 240 /* 241 * Route the DMA signals to the correct interface 242 */ 243 writeb(state->port[ap->port_no].port_sel, state->ioc_base); 244 245 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); 246 set_dma_sg(state->dma, state->sg, rsg - state->sg); 247 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); 248 249 /* issue r/w command */ 250 ap->ops->exec_command(ap, &qc->tf); 251} 252 253static void pata_icside_bmdma_start(struct ata_queued_cmd *qc) 254{ 255 struct ata_port *ap = qc->ap; 256 struct pata_icside_state *state = ap->host->private_data; 257 258 BUG_ON(dma_channel_active(state->dma)); 259 enable_dma(state->dma); 260} 261 262static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc) 263{ 264 struct ata_port *ap = qc->ap; 265 struct pata_icside_state *state = ap->host->private_data; 266 267 disable_dma(state->dma); 268 269 /* see ata_bmdma_stop */ 270 ata_altstatus(ap); 271} 272 273static u8 pata_icside_bmdma_status(struct ata_port *ap) 274{ 275 struct pata_icside_state *state = ap->host->private_data; 276 void __iomem *irq_port; 277 278 irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 : 279 ICS_ARCIN_V6_INTRSTAT_1); 280 281 return readb(irq_port) & 1 ? ATA_DMA_INTR : 0; 282} 283 284static int icside_dma_init(struct pata_icside_info *info) 285{ 286 struct pata_icside_state *state = info->state; 287 struct expansion_card *ec = info->ec; 288 int i; 289 290 for (i = 0; i < ATA_MAX_DEVICES; i++) { 291 state->port[0].speed[i] = 480; 292 state->port[1].speed[i] = 480; 293 } 294 295 if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) { 296 state->dma = ec->dma; 297 info->mwdma_mask = 0x07; /* MW0..2 */ 298 } 299 300 return 0; 301} 302 303 304static int pata_icside_port_start(struct ata_port *ap) 305{ 306 /* No PRD to alloc */ 307 return ata_pad_alloc(ap, ap->dev); 308} 309 310static struct scsi_host_template pata_icside_sht = { 311 .module = THIS_MODULE, 312 .name = DRV_NAME, 313 .ioctl = ata_scsi_ioctl, 314 .queuecommand = ata_scsi_queuecmd, 315 .can_queue = ATA_DEF_QUEUE, 316 .this_id = ATA_SHT_THIS_ID, 317 .sg_tablesize = PATA_ICSIDE_MAX_SG, 318 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 319 .emulated = ATA_SHT_EMULATED, 320 .use_clustering = ATA_SHT_USE_CLUSTERING, 321 .proc_name = DRV_NAME, 322 .dma_boundary = ~0, /* no dma boundaries */ 323 .slave_configure = ata_scsi_slave_config, 324 .slave_destroy = ata_scsi_slave_destroy, 325 .bios_param = ata_std_bios_param, 326}; 327 328/* wish this was exported from libata-core */ 329static void ata_dummy_noret(struct ata_port *port) 330{ 331} 332 333static void pata_icside_port_disable(struct ata_port *ap) 334{ 335 struct pata_icside_state *state = ap->host->private_data; 336 337 ata_port_printk(ap, KERN_ERR, "disabling icside port\n"); 338 339 ata_port_disable(ap); 340 341 state->port[ap->port_no].disabled = 1; 342 343 if (state->type == ICS_TYPE_V6) { 344 /* 345 * Disable interrupts from this port, otherwise we 346 * receive spurious interrupts from the floating 347 * interrupt line. 348 */ 349 void __iomem *irq_port = state->irq_port + 350 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1); 351 readb(irq_port); 352 } 353} 354 355static u8 pata_icside_irq_ack(struct ata_port *ap, unsigned int chk_drq) 356{ 357 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY; 358 u8 status; 359 360 status = ata_busy_wait(ap, bits, 1000); 361 if (status & bits) 362 if (ata_msg_err(ap)) 363 printk(KERN_ERR "abnormal status 0x%X\n", status); 364 365 if (ata_msg_intr(ap)) 366 printk(KERN_INFO "%s: irq ack: drv_stat 0x%X\n", 367 __FUNCTION__, status); 368 369 return status; 370} 371 372static struct ata_port_operations pata_icside_port_ops = { 373 .port_disable = pata_icside_port_disable, 374 375 .set_dmamode = pata_icside_set_dmamode, 376 377 .tf_load = ata_tf_load, 378 .tf_read = ata_tf_read, 379 .exec_command = ata_exec_command, 380 .check_status = ata_check_status, 381 .dev_select = ata_std_dev_select, 382 383 .cable_detect = ata_cable_40wire, 384 385 .bmdma_setup = pata_icside_bmdma_setup, 386 .bmdma_start = pata_icside_bmdma_start, 387 388 .data_xfer = ata_data_xfer_noirq, 389 390 /* no need to build any PRD tables for DMA */ 391 .qc_prep = ata_noop_qc_prep, 392 .qc_issue = ata_qc_issue_prot, 393 394 .freeze = ata_bmdma_freeze, 395 .thaw = ata_bmdma_thaw, 396 .error_handler = ata_bmdma_error_handler, 397 .post_internal_cmd = pata_icside_bmdma_stop, 398 399 .irq_clear = ata_dummy_noret, 400 .irq_on = ata_irq_on, 401 .irq_ack = pata_icside_irq_ack, 402 403 .port_start = pata_icside_port_start, 404 405 .bmdma_stop = pata_icside_bmdma_stop, 406 .bmdma_status = pata_icside_bmdma_status, 407}; 408 409static void __devinit 410pata_icside_setup_ioaddr(struct ata_ioports *ioaddr, void __iomem *base, 411 const struct portinfo *info) 412{ 413 void __iomem *cmd = base + info->dataoffset; 414 415 ioaddr->cmd_addr = cmd; 416 ioaddr->data_addr = cmd + (ATA_REG_DATA << info->stepping); 417 ioaddr->error_addr = cmd + (ATA_REG_ERR << info->stepping); 418 ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << info->stepping); 419 ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << info->stepping); 420 ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << info->stepping); 421 ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << info->stepping); 422 ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << info->stepping); 423 ioaddr->device_addr = cmd + (ATA_REG_DEVICE << info->stepping); 424 ioaddr->status_addr = cmd + (ATA_REG_STATUS << info->stepping); 425 ioaddr->command_addr = cmd + (ATA_REG_CMD << info->stepping); 426 427 ioaddr->ctl_addr = base + info->ctrloffset; 428 ioaddr->altstatus_addr = ioaddr->ctl_addr; 429} 430 431static int __devinit pata_icside_register_v5(struct pata_icside_info *info) 432{ 433 struct pata_icside_state *state = info->state; 434 void __iomem *base; 435 436 base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0); 437 if (!base) 438 return -ENOMEM; 439 440 state->irq_port = base; 441 442 info->base = base; 443 info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; 444 info->irqmask = 1; 445 info->irqops = &pata_icside_ops_arcin_v5; 446 info->nr_ports = 1; 447 info->port[0] = &pata_icside_portinfo_v5; 448 449 return 0; 450} 451 452static int __devinit pata_icside_register_v6(struct pata_icside_info *info) 453{ 454 struct pata_icside_state *state = info->state; 455 struct expansion_card *ec = info->ec; 456 void __iomem *ioc_base, *easi_base; 457 unsigned int sel = 0; 458 459 ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 460 if (!ioc_base) 461 return -ENOMEM; 462 463 easi_base = ioc_base; 464 465 if (ecard_resource_flags(ec, ECARD_RES_EASI)) { 466 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); 467 if (!easi_base) 468 return -ENOMEM; 469 470 /* 471 * Enable access to the EASI region. 472 */ 473 sel = 1 << 5; 474 } 475 476 writeb(sel, ioc_base); 477 478 state->irq_port = easi_base; 479 state->ioc_base = ioc_base; 480 state->port[0].port_sel = sel; 481 state->port[1].port_sel = sel | 1; 482 483 state->port[0].disabled = 1; 484 485 info->base = easi_base; 486 info->irqops = &pata_icside_ops_arcin_v6; 487 info->nr_ports = 2; 488 info->port[0] = &pata_icside_portinfo_v6_1; 489 info->port[1] = &pata_icside_portinfo_v6_2; 490 491 return icside_dma_init(info); 492} 493 494static int __devinit pata_icside_add_ports(struct pata_icside_info *info) 495{ 496 struct expansion_card *ec = info->ec; 497 struct ata_host *host; 498 int i; 499 500 if (info->irqaddr) { 501 ec->irqaddr = info->irqaddr; 502 ec->irqmask = info->irqmask; 503 } 504 if (info->irqops) 505 ecard_setirq(ec, info->irqops, info->state); 506 507 /* 508 * Be on the safe side - disable interrupts 509 */ 510 ec->ops->irqdisable(ec, ec->irq); 511 512 host = ata_host_alloc(&ec->dev, info->nr_ports); 513 if (!host) 514 return -ENOMEM; 515 516 host->private_data = info->state; 517 host->flags = ATA_HOST_SIMPLEX; 518 519 for (i = 0; i < info->nr_ports; i++) { 520 struct ata_port *ap = host->ports[i]; 521 522 ap->pio_mask = 0x1f; 523 ap->mwdma_mask = info->mwdma_mask; 524 ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; 525 ap->ops = &pata_icside_port_ops; 526 527 pata_icside_setup_ioaddr(&ap->ioaddr, info->base, info->port[i]); 528 } 529 530 return ata_host_activate(host, ec->irq, ata_interrupt, 0, 531 &pata_icside_sht); 532} 533 534static int __devinit 535pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) 536{ 537 struct pata_icside_state *state; 538 struct pata_icside_info info; 539 void __iomem *idmem; 540 int ret; 541 542 ret = ecard_request_resources(ec); 543 if (ret) 544 goto out; 545 546 state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL); 547 if (!state) { 548 ret = -ENOMEM; 549 goto release; 550 } 551 552 state->type = ICS_TYPE_NOTYPE; 553 state->dma = NO_DMA; 554 555 idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 556 if (idmem) { 557 unsigned int type; 558 559 type = readb(idmem + ICS_IDENT_OFFSET) & 1; 560 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; 561 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; 562 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; 563 ecardm_iounmap(ec, idmem); 564 565 state->type = type; 566 } 567 568 memset(&info, 0, sizeof(info)); 569 info.state = state; 570 info.ec = ec; 571 572 switch (state->type) { 573 case ICS_TYPE_A3IN: 574 dev_warn(&ec->dev, "A3IN unsupported\n"); 575 ret = -ENODEV; 576 break; 577 578 case ICS_TYPE_A3USER: 579 dev_warn(&ec->dev, "A3USER unsupported\n"); 580 ret = -ENODEV; 581 break; 582 583 case ICS_TYPE_V5: 584 ret = pata_icside_register_v5(&info); 585 break; 586 587 case ICS_TYPE_V6: 588 ret = pata_icside_register_v6(&info); 589 break; 590 591 default: 592 dev_warn(&ec->dev, "unknown interface type\n"); 593 ret = -ENODEV; 594 break; 595 } 596 597 if (ret == 0) 598 ret = pata_icside_add_ports(&info); 599 600 if (ret == 0) 601 goto out; 602 603 release: 604 ecard_release_resources(ec); 605 out: 606 return ret; 607} 608 609static void pata_icside_shutdown(struct expansion_card *ec) 610{ 611 struct ata_host *host = ecard_get_drvdata(ec); 612 unsigned long flags; 613 614 /* 615 * Disable interrupts from this card. We need to do 616 * this before disabling EASI since we may be accessing 617 * this register via that region. 618 */ 619 local_irq_save(flags); 620 ec->ops->irqdisable(ec, ec->irq); 621 local_irq_restore(flags); 622 623 /* 624 * Reset the ROM pointer so that we can read the ROM 625 * after a soft reboot. This also disables access to 626 * the IDE taskfile via the EASI region. 627 */ 628 if (host) { 629 struct pata_icside_state *state = host->private_data; 630 if (state->ioc_base) 631 writeb(0, state->ioc_base); 632 } 633} 634 635static void __devexit pata_icside_remove(struct expansion_card *ec) 636{ 637 struct ata_host *host = ecard_get_drvdata(ec); 638 struct pata_icside_state *state = host->private_data; 639 640 ata_host_detach(host); 641 642 pata_icside_shutdown(ec); 643 644 /* 645 * don't NULL out the drvdata - devres/libata wants it 646 * to free the ata_host structure. 647 */ 648 if (state->dma != NO_DMA) 649 free_dma(state->dma); 650 651 ecard_release_resources(ec); 652} 653 654static const struct ecard_id pata_icside_ids[] = { 655 { MANU_ICS, PROD_ICS_IDE }, 656 { MANU_ICS2, PROD_ICS2_IDE }, 657 { 0xffff, 0xffff } 658}; 659 660static struct ecard_driver pata_icside_driver = { 661 .probe = pata_icside_probe, 662 .remove = __devexit_p(pata_icside_remove), 663 .shutdown = pata_icside_shutdown, 664 .id_table = pata_icside_ids, 665 .drv = { 666 .name = DRV_NAME, 667 }, 668}; 669 670static int __init pata_icside_init(void) 671{ 672 return ecard_register_driver(&pata_icside_driver); 673} 674 675static void __exit pata_icside_exit(void) 676{ 677 ecard_remove_driver(&pata_icside_driver); 678} 679 680MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); 681MODULE_LICENSE("GPL"); 682MODULE_DESCRIPTION("ICS PATA driver"); 683 684module_init(pata_icside_init); 685module_exit(pata_icside_exit); 686