1/* $Id: trampoline.S,v 1.1.1.1 2007-08-03 18:52:18 $
2 * trampoline.S: Jump start slave processors on sparc64.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#include <asm/head.h>
8#include <asm/asi.h>
9#include <asm/lsu.h>
10#include <asm/dcr.h>
11#include <asm/dcu.h>
12#include <asm/pstate.h>
13#include <asm/page.h>
14#include <asm/pgtable.h>
15#include <asm/spitfire.h>
16#include <asm/processor.h>
17#include <asm/thread_info.h>
18#include <asm/mmu.h>
19#include <asm/hypervisor.h>
20#include <asm/cpudata.h>
21
22	.data
23	.align	8
24call_method:
25	.asciz	"call-method"
26	.align	8
27itlb_load:
28	.asciz	"SUNW,itlb-load"
29	.align	8
30dtlb_load:
31	.asciz	"SUNW,dtlb-load"
32
33#define TRAMP_STACK_SIZE	1024
34	.align	16
35tramp_stack:
36	.skip	TRAMP_STACK_SIZE
37
38	.text
39	.align		8
40	.globl		sparc64_cpu_startup, sparc64_cpu_startup_end
41sparc64_cpu_startup:
42	BRANCH_IF_SUN4V(g1, niagara_startup)
43	BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
44	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
45
46	ba,pt	%xcc, spitfire_startup
47	 nop
48
49cheetah_plus_startup:
50	/* Preserve OBP chosen DCU and DCR register settings.  */
51	ba,pt	%xcc, cheetah_generic_startup
52	 nop
53
54cheetah_startup:
55	mov	DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
56	wr	%g1, %asr18
57
58	sethi	%uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
59	or	%g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
60	sllx	%g5, 32, %g5
61	or	%g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
62	stxa	%g5, [%g0] ASI_DCU_CONTROL_REG
63	membar	#Sync
64	/* fallthru */
65
66cheetah_generic_startup:
67	mov	TSB_EXTENSION_P, %g3
68	stxa	%g0, [%g3] ASI_DMMU
69	stxa	%g0, [%g3] ASI_IMMU
70	membar	#Sync
71
72	mov	TSB_EXTENSION_S, %g3
73	stxa	%g0, [%g3] ASI_DMMU
74	membar	#Sync
75
76	mov	TSB_EXTENSION_N, %g3
77	stxa	%g0, [%g3] ASI_DMMU
78	stxa	%g0, [%g3] ASI_IMMU
79	membar	#Sync
80	/* fallthru */
81
82niagara_startup:
83	/* Disable STICK_INT interrupts. */
84	sethi		%hi(0x80000000), %g5
85	sllx		%g5, 32, %g5
86	wr		%g5, %asr25
87
88	ba,pt		%xcc, startup_continue
89	 nop
90
91spitfire_startup:
92	mov		(LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
93	stxa		%g1, [%g0] ASI_LSU_CONTROL
94	membar		#Sync
95
96startup_continue:
97	sethi		%hi(0x80000000), %g2
98	sllx		%g2, 32, %g2
99	wr		%g2, 0, %tick_cmpr
100
101	mov		%o0, %l0
102
103	BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
104
105	/* Call OBP by hand to lock KERNBASE into i/d tlbs.
106	 * We lock 2 consequetive entries if we are 'bigkernel'.
107	 */
108	sethi		%hi(prom_entry_lock), %g2
1091:	ldstub		[%g2 + %lo(prom_entry_lock)], %g1
110	membar		#StoreLoad | #StoreStore
111	brnz,pn		%g1, 1b
112	 nop
113
114	sethi		%hi(p1275buf), %g2
115	or		%g2, %lo(p1275buf), %g2
116	ldx		[%g2 + 0x10], %l2
117	add		%l2, -(192 + 128), %sp
118	flushw
119
120	sethi		%hi(call_method), %g2
121	or		%g2, %lo(call_method), %g2
122	stx		%g2, [%sp + 2047 + 128 + 0x00]
123	mov		5, %g2
124	stx		%g2, [%sp + 2047 + 128 + 0x08]
125	mov		1, %g2
126	stx		%g2, [%sp + 2047 + 128 + 0x10]
127	sethi		%hi(itlb_load), %g2
128	or		%g2, %lo(itlb_load), %g2
129	stx		%g2, [%sp + 2047 + 128 + 0x18]
130	sethi		%hi(prom_mmu_ihandle_cache), %g2
131	lduw		[%g2 + %lo(prom_mmu_ihandle_cache)], %g2
132	stx		%g2, [%sp + 2047 + 128 + 0x20]
133	sethi		%hi(KERNBASE), %g2
134	stx		%g2, [%sp + 2047 + 128 + 0x28]
135	sethi		%hi(kern_locked_tte_data), %g2
136	ldx		[%g2 + %lo(kern_locked_tte_data)], %g2
137	stx		%g2, [%sp + 2047 + 128 + 0x30]
138
139	mov		15, %g2
140	BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
141
142	mov		63, %g2
1431:
144	stx		%g2, [%sp + 2047 + 128 + 0x38]
145	sethi		%hi(p1275buf), %g2
146	or		%g2, %lo(p1275buf), %g2
147	ldx		[%g2 + 0x08], %o1
148	call		%o1
149	 add		%sp, (2047 + 128), %o0
150
151	sethi		%hi(bigkernel), %g2
152	lduw		[%g2 + %lo(bigkernel)], %g2
153	brz,pt		%g2, do_dtlb
154	 nop
155
156	sethi		%hi(call_method), %g2
157	or		%g2, %lo(call_method), %g2
158	stx		%g2, [%sp + 2047 + 128 + 0x00]
159	mov		5, %g2
160	stx		%g2, [%sp + 2047 + 128 + 0x08]
161	mov		1, %g2
162	stx		%g2, [%sp + 2047 + 128 + 0x10]
163	sethi		%hi(itlb_load), %g2
164	or		%g2, %lo(itlb_load), %g2
165	stx		%g2, [%sp + 2047 + 128 + 0x18]
166	sethi		%hi(prom_mmu_ihandle_cache), %g2
167	lduw		[%g2 + %lo(prom_mmu_ihandle_cache)], %g2
168	stx		%g2, [%sp + 2047 + 128 + 0x20]
169	sethi		%hi(KERNBASE + 0x400000), %g2
170	stx		%g2, [%sp + 2047 + 128 + 0x28]
171	sethi		%hi(kern_locked_tte_data), %g2
172	ldx		[%g2 + %lo(kern_locked_tte_data)], %g2
173	sethi		%hi(0x400000), %g1
174	add		%g2, %g1, %g2
175	stx		%g2, [%sp + 2047 + 128 + 0x30]
176
177	mov		14, %g2
178	BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
179
180	mov		62, %g2
1811:
182	stx		%g2, [%sp + 2047 + 128 + 0x38]
183	sethi		%hi(p1275buf), %g2
184	or		%g2, %lo(p1275buf), %g2
185	ldx		[%g2 + 0x08], %o1
186	call		%o1
187	 add		%sp, (2047 + 128), %o0
188
189do_dtlb:
190	sethi		%hi(call_method), %g2
191	or		%g2, %lo(call_method), %g2
192	stx		%g2, [%sp + 2047 + 128 + 0x00]
193	mov		5, %g2
194	stx		%g2, [%sp + 2047 + 128 + 0x08]
195	mov		1, %g2
196	stx		%g2, [%sp + 2047 + 128 + 0x10]
197	sethi		%hi(dtlb_load), %g2
198	or		%g2, %lo(dtlb_load), %g2
199	stx		%g2, [%sp + 2047 + 128 + 0x18]
200	sethi		%hi(prom_mmu_ihandle_cache), %g2
201	lduw		[%g2 + %lo(prom_mmu_ihandle_cache)], %g2
202	stx		%g2, [%sp + 2047 + 128 + 0x20]
203	sethi		%hi(KERNBASE), %g2
204	stx		%g2, [%sp + 2047 + 128 + 0x28]
205	sethi		%hi(kern_locked_tte_data), %g2
206	ldx		[%g2 + %lo(kern_locked_tte_data)], %g2
207	stx		%g2, [%sp + 2047 + 128 + 0x30]
208
209	mov		15, %g2
210	BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
211
212	mov		63, %g2
2131:
214
215	stx		%g2, [%sp + 2047 + 128 + 0x38]
216	sethi		%hi(p1275buf), %g2
217	or		%g2, %lo(p1275buf), %g2
218	ldx		[%g2 + 0x08], %o1
219	call		%o1
220	 add		%sp, (2047 + 128), %o0
221
222	sethi		%hi(bigkernel), %g2
223	lduw		[%g2 + %lo(bigkernel)], %g2
224	brz,pt		%g2, do_unlock
225	 nop
226
227	sethi		%hi(call_method), %g2
228	or		%g2, %lo(call_method), %g2
229	stx		%g2, [%sp + 2047 + 128 + 0x00]
230	mov		5, %g2
231	stx		%g2, [%sp + 2047 + 128 + 0x08]
232	mov		1, %g2
233	stx		%g2, [%sp + 2047 + 128 + 0x10]
234	sethi		%hi(dtlb_load), %g2
235	or		%g2, %lo(dtlb_load), %g2
236	stx		%g2, [%sp + 2047 + 128 + 0x18]
237	sethi		%hi(prom_mmu_ihandle_cache), %g2
238	lduw		[%g2 + %lo(prom_mmu_ihandle_cache)], %g2
239	stx		%g2, [%sp + 2047 + 128 + 0x20]
240	sethi		%hi(KERNBASE + 0x400000), %g2
241	stx		%g2, [%sp + 2047 + 128 + 0x28]
242	sethi		%hi(kern_locked_tte_data), %g2
243	ldx		[%g2 + %lo(kern_locked_tte_data)], %g2
244	sethi		%hi(0x400000), %g1
245	add		%g2, %g1, %g2
246	stx		%g2, [%sp + 2047 + 128 + 0x30]
247
248	mov		14, %g2
249	BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
250
251	mov		62, %g2
2521:
253
254	stx		%g2, [%sp + 2047 + 128 + 0x38]
255	sethi		%hi(p1275buf), %g2
256	or		%g2, %lo(p1275buf), %g2
257	ldx		[%g2 + 0x08], %o1
258	call		%o1
259	 add		%sp, (2047 + 128), %o0
260
261do_unlock:
262	sethi		%hi(prom_entry_lock), %g2
263	stb		%g0, [%g2 + %lo(prom_entry_lock)]
264	membar		#StoreStore | #StoreLoad
265
266	ba,pt		%xcc, after_lock_tlb
267	 nop
268
269niagara_lock_tlb:
270	mov		HV_FAST_MMU_MAP_PERM_ADDR, %o5
271	sethi		%hi(KERNBASE), %o0
272	clr		%o1
273	sethi		%hi(kern_locked_tte_data), %o2
274	ldx		[%o2 + %lo(kern_locked_tte_data)], %o2
275	mov		HV_MMU_IMMU, %o3
276	ta		HV_FAST_TRAP
277
278	mov		HV_FAST_MMU_MAP_PERM_ADDR, %o5
279	sethi		%hi(KERNBASE), %o0
280	clr		%o1
281	sethi		%hi(kern_locked_tte_data), %o2
282	ldx		[%o2 + %lo(kern_locked_tte_data)], %o2
283	mov		HV_MMU_DMMU, %o3
284	ta		HV_FAST_TRAP
285
286	sethi		%hi(bigkernel), %g2
287	lduw		[%g2 + %lo(bigkernel)], %g2
288	brz,pt		%g2, after_lock_tlb
289	 nop
290
291	mov		HV_FAST_MMU_MAP_PERM_ADDR, %o5
292	sethi		%hi(KERNBASE + 0x400000), %o0
293	clr		%o1
294	sethi		%hi(kern_locked_tte_data), %o2
295	ldx		[%o2 + %lo(kern_locked_tte_data)], %o2
296	sethi		%hi(0x400000), %o3
297	add		%o2, %o3, %o2
298	mov		HV_MMU_IMMU, %o3
299	ta		HV_FAST_TRAP
300
301	mov		HV_FAST_MMU_MAP_PERM_ADDR, %o5
302	sethi		%hi(KERNBASE + 0x400000), %o0
303	clr		%o1
304	sethi		%hi(kern_locked_tte_data), %o2
305	ldx		[%o2 + %lo(kern_locked_tte_data)], %o2
306	sethi		%hi(0x400000), %o3
307	add		%o2, %o3, %o2
308	mov		HV_MMU_DMMU, %o3
309	ta		HV_FAST_TRAP
310
311after_lock_tlb:
312	wrpr		%g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
313	wr		%g0, 0, %fprs
314
315	wr		%g0, ASI_P, %asi
316
317	mov		PRIMARY_CONTEXT, %g7
318
319661:	stxa		%g0, [%g7] ASI_DMMU
320	.section	.sun4v_1insn_patch, "ax"
321	.word		661b
322	stxa		%g0, [%g7] ASI_MMU
323	.previous
324
325	membar		#Sync
326	mov		SECONDARY_CONTEXT, %g7
327
328661:	stxa		%g0, [%g7] ASI_DMMU
329	.section	.sun4v_1insn_patch, "ax"
330	.word		661b
331	stxa		%g0, [%g7] ASI_MMU
332	.previous
333
334	membar		#Sync
335
336	/* Everything we do here, until we properly take over the
337	 * trap table, must be done with extreme care.  We cannot
338	 * make any references to %g6 (current thread pointer),
339	 * %g4 (current task pointer), or %g5 (base of current cpu's
340	 * per-cpu area) until we properly take over the trap table
341	 * from the firmware and hypervisor.
342	 *
343	 * Get onto temporary stack which is in the locked kernel image.
344	 */
345	sethi		%hi(tramp_stack), %g1
346	or		%g1, %lo(tramp_stack), %g1
347	add		%g1, TRAMP_STACK_SIZE, %g1
348	sub		%g1, STACKFRAME_SZ + STACK_BIAS, %sp
349	mov		0, %fp
350
351	/* Put garbage in these registers to trap any access to them.  */
352	set		0xdeadbeef, %g4
353	set		0xdeadbeef, %g5
354	set		0xdeadbeef, %g6
355
356	call		init_irqwork_curcpu
357	 nop
358
359	sethi		%hi(tlb_type), %g3
360	lduw		[%g3 + %lo(tlb_type)], %g2
361	cmp		%g2, 3
362	bne,pt		%icc, 1f
363	 nop
364
365	call		hard_smp_processor_id
366	 nop
367
368	mov		%o0, %o1
369	mov		0, %o0
370	mov		0, %o2
371	call		sun4v_init_mondo_queues
372	 mov		1, %o3
373
3741:	call		init_cur_cpu_trap
375	 ldx		[%l0], %o0
376
377	/* Start using proper page size encodings in ctx register.  */
378	sethi		%hi(sparc64_kern_pri_context), %g3
379	ldx		[%g3 + %lo(sparc64_kern_pri_context)], %g2
380	mov		PRIMARY_CONTEXT, %g1
381
382661:	stxa		%g2, [%g1] ASI_DMMU
383	.section	.sun4v_1insn_patch, "ax"
384	.word		661b
385	stxa		%g2, [%g1] ASI_MMU
386	.previous
387
388	membar		#Sync
389
390	wrpr		%g0, 0, %wstate
391
392	/* As a hack, put &init_thread_union into %g6.
393	 * prom_world() loads from here to restore the %asi
394	 * register.
395	 */
396	sethi		%hi(init_thread_union), %g6
397	or		%g6, %lo(init_thread_union), %g6
398
399	sethi		%hi(is_sun4v), %o0
400	lduw		[%o0 + %lo(is_sun4v)], %o0
401	brz,pt		%o0, 1f
402	 nop
403
404	TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
405	add		%g2, TRAP_PER_CPU_FAULT_INFO, %g2
406	stxa		%g2, [%g0] ASI_SCRATCHPAD
407
408	/* Compute physical address:
409	 *
410	 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
411	 */
412	sethi		%hi(KERNBASE), %g3
413	sub		%g2, %g3, %g2
414	sethi		%hi(kern_base), %g3
415	ldx		[%g3 + %lo(kern_base)], %g3
416	add		%g2, %g3, %o1
417
418	call		prom_set_trap_table_sun4v
419	 sethi		%hi(sparc64_ttable_tl0), %o0
420
421	ba,pt		%xcc, 2f
422	 nop
423
4241:	call		prom_set_trap_table
425	 sethi		%hi(sparc64_ttable_tl0), %o0
426
4272:	ldx		[%l0], %g6
428	ldx		[%g6 + TI_TASK], %g4
429
430	mov		1, %g5
431	sllx		%g5, THREAD_SHIFT, %g5
432	sub		%g5, (STACKFRAME_SZ + STACK_BIAS), %g5
433	add		%g6, %g5, %sp
434	mov		0, %fp
435
436	rdpr		%pstate, %o1
437	or		%o1, PSTATE_IE, %o1
438	wrpr		%o1, 0, %pstate
439
440	call		smp_callin
441	 nop
442	call		cpu_idle
443	 mov		0, %o0
444	call		cpu_panic
445	 nop
4461:	b,a,pt		%xcc, 1b
447
448	.align		8
449sparc64_cpu_startup_end:
450