1/* pci_sabre.c: Sabre specific PCI controller support. 2 * 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) 6 */ 7 8#include <linux/kernel.h> 9#include <linux/types.h> 10#include <linux/pci.h> 11#include <linux/init.h> 12#include <linux/slab.h> 13#include <linux/interrupt.h> 14 15#include <asm/apb.h> 16#include <asm/iommu.h> 17#include <asm/irq.h> 18#include <asm/smp.h> 19#include <asm/oplib.h> 20#include <asm/prom.h> 21#include <asm/of_device.h> 22 23#include "pci_impl.h" 24#include "iommu_common.h" 25 26/* All SABRE registers are 64-bits. The following accessor 27 * routines are how they are accessed. The REG parameter 28 * is a physical address. 29 */ 30#define sabre_read(__reg) \ 31({ u64 __ret; \ 32 __asm__ __volatile__("ldxa [%1] %2, %0" \ 33 : "=r" (__ret) \ 34 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ 35 : "memory"); \ 36 __ret; \ 37}) 38#define sabre_write(__reg, __val) \ 39 __asm__ __volatile__("stxa %0, [%1] %2" \ 40 : /* no outputs */ \ 41 : "r" (__val), "r" (__reg), \ 42 "i" (ASI_PHYS_BYPASS_EC_E) \ 43 : "memory") 44 45/* SABRE PCI controller register offsets and definitions. */ 46#define SABRE_UE_AFSR 0x0030UL 47#define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ 48#define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ 49#define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ 50#define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ 51#define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */ 52#define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */ 53#define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ 54#define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */ 55#define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */ 56#define SABRE_UECE_AFAR 0x0038UL 57#define SABRE_CE_AFSR 0x0040UL 58#define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ 59#define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ 60#define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ 61#define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ 62#define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */ 63#define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ 64#define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */ 65#define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */ 66#define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */ 67#define SABRE_IOMMU_CONTROL 0x0200UL 68#define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */ 69#define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */ 70#define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */ 71#define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */ 72#define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 73#define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000 74#define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000 75#define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000 76#define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000 77#define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000 78#define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000 79#define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000 80#define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000 81#define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */ 82#define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 83#define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 84#define SABRE_IOMMU_TSBBASE 0x0208UL 85#define SABRE_IOMMU_FLUSH 0x0210UL 86#define SABRE_IMAP_A_SLOT0 0x0c00UL 87#define SABRE_IMAP_B_SLOT0 0x0c20UL 88#define SABRE_IMAP_SCSI 0x1000UL 89#define SABRE_IMAP_ETH 0x1008UL 90#define SABRE_IMAP_BPP 0x1010UL 91#define SABRE_IMAP_AU_REC 0x1018UL 92#define SABRE_IMAP_AU_PLAY 0x1020UL 93#define SABRE_IMAP_PFAIL 0x1028UL 94#define SABRE_IMAP_KMS 0x1030UL 95#define SABRE_IMAP_FLPY 0x1038UL 96#define SABRE_IMAP_SHW 0x1040UL 97#define SABRE_IMAP_KBD 0x1048UL 98#define SABRE_IMAP_MS 0x1050UL 99#define SABRE_IMAP_SER 0x1058UL 100#define SABRE_IMAP_UE 0x1070UL 101#define SABRE_IMAP_CE 0x1078UL 102#define SABRE_IMAP_PCIERR 0x1080UL 103#define SABRE_IMAP_GFX 0x1098UL 104#define SABRE_IMAP_EUPA 0x10a0UL 105#define SABRE_ICLR_A_SLOT0 0x1400UL 106#define SABRE_ICLR_B_SLOT0 0x1480UL 107#define SABRE_ICLR_SCSI 0x1800UL 108#define SABRE_ICLR_ETH 0x1808UL 109#define SABRE_ICLR_BPP 0x1810UL 110#define SABRE_ICLR_AU_REC 0x1818UL 111#define SABRE_ICLR_AU_PLAY 0x1820UL 112#define SABRE_ICLR_PFAIL 0x1828UL 113#define SABRE_ICLR_KMS 0x1830UL 114#define SABRE_ICLR_FLPY 0x1838UL 115#define SABRE_ICLR_SHW 0x1840UL 116#define SABRE_ICLR_KBD 0x1848UL 117#define SABRE_ICLR_MS 0x1850UL 118#define SABRE_ICLR_SER 0x1858UL 119#define SABRE_ICLR_UE 0x1870UL 120#define SABRE_ICLR_CE 0x1878UL 121#define SABRE_ICLR_PCIERR 0x1880UL 122#define SABRE_WRSYNC 0x1c20UL 123#define SABRE_PCICTRL 0x2000UL 124#define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */ 125#define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */ 126#define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */ 127#define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */ 128#define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */ 129#define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */ 130#define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */ 131#define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */ 132#define SABRE_PIOAFSR 0x2010UL 133#define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */ 134#define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */ 135#define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */ 136#define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */ 137#define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */ 138#define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */ 139#define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */ 140#define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */ 141#define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */ 142#define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */ 143#define SABRE_PIOAFAR 0x2018UL 144#define SABRE_PCIDIAG 0x2020UL 145#define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */ 146#define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */ 147#define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */ 148#define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */ 149#define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */ 150#define SABRE_PCITASR 0x2028UL 151#define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */ 152#define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */ 153#define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */ 154#define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */ 155#define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */ 156#define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */ 157#define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */ 158#define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */ 159#define SABRE_PIOBUF_DIAG 0x5000UL 160#define SABRE_DMABUF_DIAGLO 0x5100UL 161#define SABRE_DMABUF_DIAGHI 0x51c0UL 162#define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */ 163#define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */ 164#define SABRE_IOMMU_VADIAG 0xa400UL 165#define SABRE_IOMMU_TCDIAG 0xa408UL 166#define SABRE_IOMMU_TAG 0xa580UL 167#define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */ 168#define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */ 169#define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */ 170#define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */ 171#define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */ 172#define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */ 173#define SABRE_IOMMU_DATA 0xa600UL 174#define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */ 175#define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */ 176#define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */ 177#define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */ 178#define SABRE_PCI_IRQSTATE 0xa800UL 179#define SABRE_OBIO_IRQSTATE 0xa808UL 180#define SABRE_FFBCFG 0xf000UL 181#define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */ 182#define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */ 183#define SABRE_MCCTRL0 0xf010UL 184#define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */ 185#define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */ 186#define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */ 187#define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */ 188#define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */ 189#define SABRE_MCCTRL1 0xf018UL 190#define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */ 191#define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */ 192#define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */ 193#define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */ 194#define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */ 195#define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */ 196#define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */ 197#define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */ 198#define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */ 199#define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */ 200#define SABRE_RESETCTRL 0xf020UL 201 202#define SABRE_CONFIGSPACE 0x001000000UL 203#define SABRE_IOSPACE 0x002000000UL 204#define SABRE_IOSPACE_SIZE 0x000ffffffUL 205#define SABRE_MEMSPACE 0x100000000UL 206#define SABRE_MEMSPACE_SIZE 0x07fffffffUL 207 208static int hummingbird_p; 209static struct pci_bus *sabre_root_bus; 210 211/* SABRE error handling support. */ 212static void sabre_check_iommu_error(struct pci_pbm_info *pbm, 213 unsigned long afsr, 214 unsigned long afar) 215{ 216 struct iommu *iommu = pbm->iommu; 217 unsigned long iommu_tag[16]; 218 unsigned long iommu_data[16]; 219 unsigned long flags; 220 u64 control; 221 int i; 222 223 spin_lock_irqsave(&iommu->lock, flags); 224 control = sabre_read(iommu->iommu_control); 225 if (control & SABRE_IOMMUCTRL_ERR) { 226 char *type_string; 227 228 /* Clear the error encountered bit. 229 * NOTE: On Sabre this is write 1 to clear, 230 * which is different from Psycho. 231 */ 232 sabre_write(iommu->iommu_control, control); 233 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) { 234 case 1: 235 type_string = "Invalid Error"; 236 break; 237 case 3: 238 type_string = "ECC Error"; 239 break; 240 default: 241 type_string = "Unknown"; 242 break; 243 }; 244 printk("%s: IOMMU Error, type[%s]\n", 245 pbm->name, type_string); 246 247 /* Enter diagnostic mode and probe for error'd 248 * entries in the IOTLB. 249 */ 250 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR); 251 sabre_write(iommu->iommu_control, 252 (control | SABRE_IOMMUCTRL_DENAB)); 253 for (i = 0; i < 16; i++) { 254 unsigned long base = pbm->controller_regs; 255 256 iommu_tag[i] = 257 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL)); 258 iommu_data[i] = 259 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL)); 260 sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0); 261 sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0); 262 } 263 sabre_write(iommu->iommu_control, control); 264 265 for (i = 0; i < 16; i++) { 266 unsigned long tag, data; 267 268 tag = iommu_tag[i]; 269 if (!(tag & SABRE_IOMMUTAG_ERR)) 270 continue; 271 272 data = iommu_data[i]; 273 switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) { 274 case 1: 275 type_string = "Invalid Error"; 276 break; 277 case 3: 278 type_string = "ECC Error"; 279 break; 280 default: 281 type_string = "Unknown"; 282 break; 283 }; 284 printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n", 285 pbm->name, i, tag, type_string, 286 ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0), 287 ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8), 288 ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT)); 289 printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n", 290 pbm->name, i, data, 291 ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0), 292 ((data & SABRE_IOMMUDATA_USED) ? 1 : 0), 293 ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0), 294 ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT)); 295 } 296 } 297 spin_unlock_irqrestore(&iommu->lock, flags); 298} 299 300static irqreturn_t sabre_ue_intr(int irq, void *dev_id) 301{ 302 struct pci_pbm_info *pbm = dev_id; 303 unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR; 304 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; 305 unsigned long afsr, afar, error_bits; 306 int reported; 307 308 /* Latch uncorrectable error status. */ 309 afar = sabre_read(afar_reg); 310 afsr = sabre_read(afsr_reg); 311 312 /* Clear the primary/secondary error status bits. */ 313 error_bits = afsr & 314 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | 315 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | 316 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE); 317 if (!error_bits) 318 return IRQ_NONE; 319 sabre_write(afsr_reg, error_bits); 320 321 /* Log the error. */ 322 printk("%s: Uncorrectable Error, primary error type[%s%s]\n", 323 pbm->name, 324 ((error_bits & SABRE_UEAFSR_PDRD) ? 325 "DMA Read" : 326 ((error_bits & SABRE_UEAFSR_PDWR) ? 327 "DMA Write" : "???")), 328 ((error_bits & SABRE_UEAFSR_PDTE) ? 329 ":Translation Error" : "")); 330 printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n", 331 pbm->name, 332 (afsr & SABRE_UEAFSR_BMSK) >> 32UL, 333 (afsr & SABRE_UEAFSR_OFF) >> 29UL, 334 ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0)); 335 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 336 printk("%s: UE Secondary errors [", pbm->name); 337 reported = 0; 338 if (afsr & SABRE_UEAFSR_SDRD) { 339 reported++; 340 printk("(DMA Read)"); 341 } 342 if (afsr & SABRE_UEAFSR_SDWR) { 343 reported++; 344 printk("(DMA Write)"); 345 } 346 if (afsr & SABRE_UEAFSR_SDTE) { 347 reported++; 348 printk("(Translation Error)"); 349 } 350 if (!reported) 351 printk("(none)"); 352 printk("]\n"); 353 354 /* Interrogate IOMMU for error status. */ 355 sabre_check_iommu_error(pbm, afsr, afar); 356 357 return IRQ_HANDLED; 358} 359 360static irqreturn_t sabre_ce_intr(int irq, void *dev_id) 361{ 362 struct pci_pbm_info *pbm = dev_id; 363 unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR; 364 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; 365 unsigned long afsr, afar, error_bits; 366 int reported; 367 368 /* Latch error status. */ 369 afar = sabre_read(afar_reg); 370 afsr = sabre_read(afsr_reg); 371 372 /* Clear primary/secondary error status bits. */ 373 error_bits = afsr & 374 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | 375 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR); 376 if (!error_bits) 377 return IRQ_NONE; 378 sabre_write(afsr_reg, error_bits); 379 380 /* Log the error. */ 381 printk("%s: Correctable Error, primary error type[%s]\n", 382 pbm->name, 383 ((error_bits & SABRE_CEAFSR_PDRD) ? 384 "DMA Read" : 385 ((error_bits & SABRE_CEAFSR_PDWR) ? 386 "DMA Write" : "???"))); 387 388 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " 389 "was_block(%d)\n", 390 pbm->name, 391 (afsr & SABRE_CEAFSR_ESYND) >> 48UL, 392 (afsr & SABRE_CEAFSR_BMSK) >> 32UL, 393 (afsr & SABRE_CEAFSR_OFF) >> 29UL, 394 ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0)); 395 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 396 printk("%s: CE Secondary errors [", pbm->name); 397 reported = 0; 398 if (afsr & SABRE_CEAFSR_SDRD) { 399 reported++; 400 printk("(DMA Read)"); 401 } 402 if (afsr & SABRE_CEAFSR_SDWR) { 403 reported++; 404 printk("(DMA Write)"); 405 } 406 if (!reported) 407 printk("(none)"); 408 printk("]\n"); 409 410 return IRQ_HANDLED; 411} 412 413static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm) 414{ 415 unsigned long csr_reg, csr, csr_error_bits; 416 irqreturn_t ret = IRQ_NONE; 417 u16 stat; 418 419 csr_reg = pbm->controller_regs + SABRE_PCICTRL; 420 csr = sabre_read(csr_reg); 421 csr_error_bits = 422 csr & SABRE_PCICTRL_SERR; 423 if (csr_error_bits) { 424 /* Clear the errors. */ 425 sabre_write(csr_reg, csr); 426 427 /* Log 'em. */ 428 if (csr_error_bits & SABRE_PCICTRL_SERR) 429 printk("%s: PCI SERR signal asserted.\n", 430 pbm->name); 431 ret = IRQ_HANDLED; 432 } 433 pci_bus_read_config_word(sabre_root_bus, 0, 434 PCI_STATUS, &stat); 435 if (stat & (PCI_STATUS_PARITY | 436 PCI_STATUS_SIG_TARGET_ABORT | 437 PCI_STATUS_REC_TARGET_ABORT | 438 PCI_STATUS_REC_MASTER_ABORT | 439 PCI_STATUS_SIG_SYSTEM_ERROR)) { 440 printk("%s: PCI bus error, PCI_STATUS[%04x]\n", 441 pbm->name, stat); 442 pci_bus_write_config_word(sabre_root_bus, 0, 443 PCI_STATUS, 0xffff); 444 ret = IRQ_HANDLED; 445 } 446 return ret; 447} 448 449static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id) 450{ 451 struct pci_pbm_info *pbm = dev_id; 452 unsigned long afsr_reg, afar_reg; 453 unsigned long afsr, afar, error_bits; 454 int reported; 455 456 afsr_reg = pbm->controller_regs + SABRE_PIOAFSR; 457 afar_reg = pbm->controller_regs + SABRE_PIOAFAR; 458 459 /* Latch error status. */ 460 afar = sabre_read(afar_reg); 461 afsr = sabre_read(afsr_reg); 462 463 /* Clear primary/secondary error status bits. */ 464 error_bits = afsr & 465 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA | 466 SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR | 467 SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA | 468 SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR); 469 if (!error_bits) 470 return sabre_pcierr_intr_other(pbm); 471 sabre_write(afsr_reg, error_bits); 472 473 /* Log the error. */ 474 printk("%s: PCI Error, primary error type[%s]\n", 475 pbm->name, 476 (((error_bits & SABRE_PIOAFSR_PMA) ? 477 "Master Abort" : 478 ((error_bits & SABRE_PIOAFSR_PTA) ? 479 "Target Abort" : 480 ((error_bits & SABRE_PIOAFSR_PRTRY) ? 481 "Excessive Retries" : 482 ((error_bits & SABRE_PIOAFSR_PPERR) ? 483 "Parity Error" : "???")))))); 484 printk("%s: bytemask[%04lx] was_block(%d)\n", 485 pbm->name, 486 (afsr & SABRE_PIOAFSR_BMSK) >> 32UL, 487 (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0); 488 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar); 489 printk("%s: PCI Secondary errors [", pbm->name); 490 reported = 0; 491 if (afsr & SABRE_PIOAFSR_SMA) { 492 reported++; 493 printk("(Master Abort)"); 494 } 495 if (afsr & SABRE_PIOAFSR_STA) { 496 reported++; 497 printk("(Target Abort)"); 498 } 499 if (afsr & SABRE_PIOAFSR_SRTRY) { 500 reported++; 501 printk("(Excessive Retries)"); 502 } 503 if (afsr & SABRE_PIOAFSR_SPERR) { 504 reported++; 505 printk("(Parity Error)"); 506 } 507 if (!reported) 508 printk("(none)"); 509 printk("]\n"); 510 511 /* For the error types shown, scan both PCI buses for devices 512 * which have logged that error type. 513 */ 514 515 /* If we see a Target Abort, this could be the result of an 516 * IOMMU translation error of some sort. It is extremely 517 * useful to log this information as usually it indicates 518 * a bug in the IOMMU support code or a PCI device driver. 519 */ 520 if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) { 521 sabre_check_iommu_error(pbm, afsr, afar); 522 pci_scan_for_target_abort(pbm, pbm->pci_bus); 523 } 524 if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) 525 pci_scan_for_master_abort(pbm, pbm->pci_bus); 526 527 /* For excessive retries, SABRE/PBM will abort the device 528 * and there is no way to specifically check for excessive 529 * retries in the config space status registers. So what 530 * we hope is that we'll catch it via the master/target 531 * abort events. 532 */ 533 534 if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) 535 pci_scan_for_parity_error(pbm, pbm->pci_bus); 536 537 return IRQ_HANDLED; 538} 539 540static void sabre_register_error_handlers(struct pci_pbm_info *pbm) 541{ 542 struct device_node *dp = pbm->prom_node; 543 struct of_device *op; 544 unsigned long base = pbm->controller_regs; 545 u64 tmp; 546 int err; 547 548 if (pbm->chip_type == PBM_CHIP_TYPE_SABRE) 549 dp = dp->parent; 550 551 op = of_find_device_by_node(dp); 552 if (!op) 553 return; 554 555 /* Sabre/Hummingbird IRQ property layout is: 556 * 0: PCI ERR 557 * 1: UE ERR 558 * 2: CE ERR 559 * 3: POWER FAIL 560 */ 561 if (op->num_irqs < 4) 562 return; 563 564 /* We clear the error bits in the appropriate AFSR before 565 * registering the handler so that we don't get spurious 566 * interrupts. 567 */ 568 sabre_write(base + SABRE_UE_AFSR, 569 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | 570 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | 571 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE)); 572 573 err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm); 574 if (err) 575 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n", 576 pbm->name, err); 577 578 sabre_write(base + SABRE_CE_AFSR, 579 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | 580 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR)); 581 582 err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm); 583 if (err) 584 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n", 585 pbm->name, err); 586 err = request_irq(op->irqs[0], sabre_pcierr_intr, 0, 587 "SABRE_PCIERR", pbm); 588 if (err) 589 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n", 590 pbm->name, err); 591 592 tmp = sabre_read(base + SABRE_PCICTRL); 593 tmp |= SABRE_PCICTRL_ERREN; 594 sabre_write(base + SABRE_PCICTRL, tmp); 595} 596 597static void apb_init(struct pci_bus *sabre_bus) 598{ 599 struct pci_dev *pdev; 600 601 list_for_each_entry(pdev, &sabre_bus->devices, bus_list) { 602 if (pdev->vendor == PCI_VENDOR_ID_SUN && 603 pdev->device == PCI_DEVICE_ID_SUN_SIMBA) { 604 u16 word16; 605 606 pci_read_config_word(pdev, PCI_COMMAND, &word16); 607 word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | 608 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | 609 PCI_COMMAND_IO; 610 pci_write_config_word(pdev, PCI_COMMAND, word16); 611 612 /* Status register bits are "write 1 to clear". */ 613 pci_write_config_word(pdev, PCI_STATUS, 0xffff); 614 pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff); 615 616 /* Use a primary/seconday latency timer value 617 * of 64. 618 */ 619 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 620 pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64); 621 622 /* Enable reporting/forwarding of master aborts, 623 * parity, and SERR. 624 */ 625 pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL, 626 (PCI_BRIDGE_CTL_PARITY | 627 PCI_BRIDGE_CTL_SERR | 628 PCI_BRIDGE_CTL_MASTER_ABORT)); 629 } 630 } 631} 632 633static void sabre_scan_bus(struct pci_pbm_info *pbm) 634{ 635 static int once; 636 637 /* The APB bridge speaks to the Sabre host PCI bridge 638 * at 66Mhz, but the front side of APB runs at 33Mhz 639 * for both segments. 640 * 641 * Hummingbird systems do not use APB, so they run 642 * at 66MHZ. 643 */ 644 if (hummingbird_p) 645 pbm->is_66mhz_capable = 1; 646 else 647 pbm->is_66mhz_capable = 0; 648 649 /* This driver has not been verified to handle 650 * multiple SABREs yet, so trap this. 651 * 652 * Also note that the SABRE host bridge is hardwired 653 * to live at bus 0. 654 */ 655 if (once != 0) { 656 prom_printf("SABRE: Multiple controllers unsupported.\n"); 657 prom_halt(); 658 } 659 once++; 660 661 pbm->pci_bus = pci_scan_one_pbm(pbm); 662 if (!pbm->pci_bus) 663 return; 664 665 sabre_root_bus = pbm->pci_bus; 666 667 apb_init(pbm->pci_bus); 668 669 sabre_register_error_handlers(pbm); 670} 671 672static void sabre_iommu_init(struct pci_pbm_info *pbm, 673 int tsbsize, unsigned long dvma_offset, 674 u32 dma_mask) 675{ 676 struct iommu *iommu = pbm->iommu; 677 unsigned long i; 678 u64 control; 679 680 /* Register addresses. */ 681 iommu->iommu_control = pbm->controller_regs + SABRE_IOMMU_CONTROL; 682 iommu->iommu_tsbbase = pbm->controller_regs + SABRE_IOMMU_TSBBASE; 683 iommu->iommu_flush = pbm->controller_regs + SABRE_IOMMU_FLUSH; 684 iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC; 685 /* Sabre's IOMMU lacks ctx flushing. */ 686 iommu->iommu_ctxflush = 0; 687 688 /* Invalidate TLB Entries. */ 689 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL); 690 control |= SABRE_IOMMUCTRL_DENAB; 691 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control); 692 693 for(i = 0; i < 16; i++) { 694 sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0); 695 sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0); 696 } 697 698 /* Leave diag mode enabled for full-flushing done 699 * in pci_iommu.c 700 */ 701 pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask); 702 703 sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE, 704 __pa(iommu->page_table)); 705 706 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL); 707 control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ); 708 control |= SABRE_IOMMUCTRL_ENAB; 709 switch(tsbsize) { 710 case 64: 711 control |= SABRE_IOMMU_TSBSZ_64K; 712 break; 713 case 128: 714 control |= SABRE_IOMMU_TSBSZ_128K; 715 break; 716 default: 717 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize); 718 prom_halt(); 719 break; 720 } 721 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control); 722} 723 724static void sabre_pbm_init(struct pci_controller_info *p, struct pci_pbm_info *pbm, struct device_node *dp) 725{ 726 pbm->name = dp->full_name; 727 printk("%s: SABRE PCI Bus Module\n", pbm->name); 728 729 pbm->scan_bus = sabre_scan_bus; 730 pbm->pci_ops = &sun4u_pci_ops; 731 pbm->config_space_reg_bits = 8; 732 733 pbm->index = pci_num_pbms++; 734 735 pbm->chip_type = PBM_CHIP_TYPE_SABRE; 736 pbm->parent = p; 737 pbm->prom_node = dp; 738 pci_get_pbm_props(pbm); 739 740 pci_determine_mem_io_space(pbm); 741} 742 743void sabre_init(struct device_node *dp, char *model_name) 744{ 745 const struct linux_prom64_registers *pr_regs; 746 struct pci_controller_info *p; 747 struct pci_pbm_info *pbm; 748 struct iommu *iommu; 749 int tsbsize; 750 const u32 *vdma; 751 u32 upa_portid, dma_mask; 752 u64 clear_irq; 753 754 hummingbird_p = 0; 755 if (!strcmp(model_name, "pci108e,a001")) 756 hummingbird_p = 1; 757 else if (!strcmp(model_name, "SUNW,sabre")) { 758 const char *compat = of_get_property(dp, "compatible", NULL); 759 if (compat && !strcmp(compat, "pci108e,a001")) 760 hummingbird_p = 1; 761 if (!hummingbird_p) { 762 struct device_node *dp; 763 764 /* Of course, Sun has to encode things a thousand 765 * different ways, inconsistently. 766 */ 767 for_each_node_by_type(dp, "cpu") { 768 if (!strcmp(dp->name, "SUNW,UltraSPARC-IIe")) 769 hummingbird_p = 1; 770 } 771 } 772 } 773 774 p = kzalloc(sizeof(*p), GFP_ATOMIC); 775 if (!p) { 776 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n"); 777 prom_halt(); 778 } 779 780 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC); 781 if (!iommu) { 782 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n"); 783 prom_halt(); 784 } 785 pbm = &p->pbm_A; 786 pbm->iommu = iommu; 787 788 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); 789 790 pbm->next = pci_pbm_root; 791 pci_pbm_root = pbm; 792 793 pbm->portid = upa_portid; 794 795 /* 796 * Map in SABRE register set and report the presence of this SABRE. 797 */ 798 799 pr_regs = of_get_property(dp, "reg", NULL); 800 801 /* 802 * First REG in property is base of entire SABRE register space. 803 */ 804 pbm->controller_regs = pr_regs[0].phys_addr; 805 806 /* Clear interrupts */ 807 808 /* PCI first */ 809 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) 810 sabre_write(pbm->controller_regs + clear_irq, 0x0UL); 811 812 /* Then OBIO */ 813 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) 814 sabre_write(pbm->controller_regs + clear_irq, 0x0UL); 815 816 /* Error interrupts are enabled later after the bus scan. */ 817 sabre_write(pbm->controller_regs + SABRE_PCICTRL, 818 (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | 819 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN)); 820 821 /* Now map in PCI config space for entire SABRE. */ 822 pbm->config_space = 823 (pbm->controller_regs + SABRE_CONFIGSPACE); 824 825 vdma = of_get_property(dp, "virtual-dma", NULL); 826 827 dma_mask = vdma[0]; 828 switch(vdma[1]) { 829 case 0x20000000: 830 dma_mask |= 0x1fffffff; 831 tsbsize = 64; 832 break; 833 case 0x40000000: 834 dma_mask |= 0x3fffffff; 835 tsbsize = 128; 836 break; 837 838 case 0x80000000: 839 dma_mask |= 0x7fffffff; 840 tsbsize = 128; 841 break; 842 default: 843 prom_printf("SABRE: strange virtual-dma size.\n"); 844 prom_halt(); 845 } 846 847 sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask); 848 849 /* 850 * Look for APB underneath. 851 */ 852 sabre_pbm_init(p, pbm, dp); 853} 854