1/* $Id: etrap.S,v 1.1.1.1 2007-08-03 18:52:18 $ 2 * etrap.S: Preparing for entry into the kernel on Sparc V9. 3 * 4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz) 6 */ 7 8 9#include <asm/asi.h> 10#include <asm/pstate.h> 11#include <asm/ptrace.h> 12#include <asm/page.h> 13#include <asm/spitfire.h> 14#include <asm/head.h> 15#include <asm/processor.h> 16#include <asm/mmu.h> 17 18#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ) 19#define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV) 20#define ETRAP_PSTATE2 \ 21 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE) 22 23/* 24 * On entry, %g7 is return address - 0x4. 25 * %g4 and %g5 will be preserved %l4 and %l5 respectively. 26 */ 27 28 .text 29 .align 64 30 .globl etrap, etrap_irq, etraptl1 31etrap: rdpr %pil, %g2 32etrap_irq: 33 TRAP_LOAD_THREAD_REG(%g6, %g1) 34 rdpr %tstate, %g1 35 sllx %g2, 20, %g3 36 andcc %g1, TSTATE_PRIV, %g0 37 or %g1, %g3, %g1 38 bne,pn %xcc, 1f 39 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2 40 wrpr %g0, 7, %cleanwin 41 42 sethi %hi(TASK_REGOFF), %g2 43 sethi %hi(TSTATE_PEF), %g3 44 or %g2, %lo(TASK_REGOFF), %g2 45 and %g1, %g3, %g3 46 brnz,pn %g3, 1f 47 add %g6, %g2, %g2 48 wr %g0, 0, %fprs 491: rdpr %tpc, %g3 50 51 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE] 52 rdpr %tnpc, %g1 53 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC] 54 rd %y, %g3 55 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC] 56 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y] 57 58 rdpr %cansave, %g1 59 brnz,pt %g1, etrap_save 60 nop 61 62 rdpr %cwp, %g1 63 add %g1, 2, %g1 64 wrpr %g1, %cwp 65 be,pt %xcc, etrap_user_spill 66 mov ASI_AIUP, %g3 67 68 rdpr %otherwin, %g3 69 brz %g3, etrap_kernel_spill 70 mov ASI_AIUS, %g3 71 72etrap_user_spill: 73 74 wr %g3, 0x0, %asi 75 ldx [%g6 + TI_FLAGS], %g3 76 and %g3, _TIF_32BIT, %g3 77 brnz,pt %g3, etrap_user_spill_32bit 78 nop 79 ba,a,pt %xcc, etrap_user_spill_64bit 80 81etrap_save: save %g2, -STACK_BIAS, %sp 82 mov %g6, %l6 83 84 bne,pn %xcc, 3f 85 mov PRIMARY_CONTEXT, %l4 86 rdpr %canrestore, %g3 87 rdpr %wstate, %g2 88 wrpr %g0, 0, %canrestore 89 sll %g2, 3, %g2 90 mov 1, %l5 91 stb %l5, [%l6 + TI_FPDEPTH] 92 93 wrpr %g3, 0, %otherwin 94 wrpr %g2, 0, %wstate 95 sethi %hi(sparc64_kern_pri_context), %g2 96 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3 97 98661: stxa %g3, [%l4] ASI_DMMU 99 .section .sun4v_1insn_patch, "ax" 100 .word 661b 101 stxa %g3, [%l4] ASI_MMU 102 .previous 103 104 sethi %hi(KERNBASE), %l4 105 flush %l4 106 mov ASI_AIUS, %l7 1072: mov %g4, %l4 108 mov %g5, %l5 109 add %g7, 4, %l2 110 111 /* Go to trap time globals so we can save them. */ 112661: wrpr %g0, ETRAP_PSTATE1, %pstate 113 .section .sun4v_1insn_patch, "ax" 114 .word 661b 115 SET_GL(0) 116 .previous 117 118 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1] 119 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2] 120 sllx %l7, 24, %l7 121 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3] 122 rdpr %cwp, %l0 123 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4] 124 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5] 125 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6] 126 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7] 127 or %l7, %l0, %l7 128 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0 129 or %l7, %l0, %l7 130 wrpr %l2, %tnpc 131 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate 132 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0] 133 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1] 134 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2] 135 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3] 136 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4] 137 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5] 138 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6] 139 mov %l6, %g6 140 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] 141 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1) 142 ldx [%g6 + TI_TASK], %g4 143 done 144 1453: mov ASI_P, %l7 146 ldub [%l6 + TI_FPDEPTH], %l5 147 add %l6, TI_FPSAVED + 1, %l4 148 srl %l5, 1, %l3 149 add %l5, 2, %l5 150 stb %l5, [%l6 + TI_FPDEPTH] 151 ba,pt %xcc, 2b 152 stb %g0, [%l4 + %l3] 153 nop 154 155etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself. 156 * We place this right after pt_regs on the trap stack. 157 * The layout is: 158 * 0x00 TL1's TSTATE 159 * 0x08 TL1's TPC 160 * 0x10 TL1's TNPC 161 * 0x18 TL1's TT 162 * ... 163 * 0x58 TL4's TT 164 * 0x60 TL 165 */ 166 TRAP_LOAD_THREAD_REG(%g6, %g1) 167 sub %sp, ((4 * 8) * 4) + 8, %g2 168 rdpr %tl, %g1 169 170 wrpr %g0, 1, %tl 171 rdpr %tstate, %g3 172 stx %g3, [%g2 + STACK_BIAS + 0x00] 173 rdpr %tpc, %g3 174 stx %g3, [%g2 + STACK_BIAS + 0x08] 175 rdpr %tnpc, %g3 176 stx %g3, [%g2 + STACK_BIAS + 0x10] 177 rdpr %tt, %g3 178 stx %g3, [%g2 + STACK_BIAS + 0x18] 179 180 wrpr %g0, 2, %tl 181 rdpr %tstate, %g3 182 stx %g3, [%g2 + STACK_BIAS + 0x20] 183 rdpr %tpc, %g3 184 stx %g3, [%g2 + STACK_BIAS + 0x28] 185 rdpr %tnpc, %g3 186 stx %g3, [%g2 + STACK_BIAS + 0x30] 187 rdpr %tt, %g3 188 stx %g3, [%g2 + STACK_BIAS + 0x38] 189 190 sethi %hi(is_sun4v), %g3 191 lduw [%g3 + %lo(is_sun4v)], %g3 192 brnz,pn %g3, finish_tl1_capture 193 nop 194 195 wrpr %g0, 3, %tl 196 rdpr %tstate, %g3 197 stx %g3, [%g2 + STACK_BIAS + 0x40] 198 rdpr %tpc, %g3 199 stx %g3, [%g2 + STACK_BIAS + 0x48] 200 rdpr %tnpc, %g3 201 stx %g3, [%g2 + STACK_BIAS + 0x50] 202 rdpr %tt, %g3 203 stx %g3, [%g2 + STACK_BIAS + 0x58] 204 205 wrpr %g0, 4, %tl 206 rdpr %tstate, %g3 207 stx %g3, [%g2 + STACK_BIAS + 0x60] 208 rdpr %tpc, %g3 209 stx %g3, [%g2 + STACK_BIAS + 0x68] 210 rdpr %tnpc, %g3 211 stx %g3, [%g2 + STACK_BIAS + 0x70] 212 rdpr %tt, %g3 213 stx %g3, [%g2 + STACK_BIAS + 0x78] 214 215 stx %g1, [%g2 + STACK_BIAS + 0x80] 216 217finish_tl1_capture: 218 wrpr %g0, 1, %tl 219661: nop 220 .section .sun4v_1insn_patch, "ax" 221 .word 661b 222 SET_GL(1) 223 .previous 224 225 rdpr %tstate, %g1 226 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2 227 ba,pt %xcc, 1b 228 andcc %g1, TSTATE_PRIV, %g0 229 230#undef TASK_REGOFF 231#undef ETRAP_PSTATE1 232