1/* Created by Tony Li <tony.li@freescale.com>
2 * Copyright (c) 2005 freescale semiconductor
3 *
4 * This program is free software; you can redistribute  it and/or modify it
5 * under  the terms of  the GNU General  Public License as published by the
6 * Free Software Foundation;  either version 2 of the  License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the  GNU General Public License along
15 * with this program; if not, write  to the Free Software Foundation, Inc.,
16 * 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __PPC_SYSLIB_PPC83XX_PCI_H
20#define __PPC_SYSLIB_PPC83XX_PCI_H
21
22typedef struct immr_clk {
23	u32 spmr; /* system PLL mode Register  */
24	u32 occr; /* output clock control Register  */
25	u32 sccr; /* system clock control Register  */
26	u8 res0[0xF4];
27} immr_clk_t;
28
29/*
30 * Sequencer
31 */
32typedef struct immr_ios {
33	u32	potar0;
34	u8	res0[4];
35	u32	pobar0;
36	u8	res1[4];
37	u32	pocmr0;
38	u8	res2[4];
39	u32	potar1;
40	u8	res3[4];
41	u32	pobar1;
42	u8	res4[4];
43	u32	pocmr1;
44	u8	res5[4];
45	u32	potar2;
46	u8	res6[4];
47	u32	pobar2;
48	u8	res7[4];
49	u32	pocmr2;
50	u8	res8[4];
51	u32	potar3;
52	u8	res9[4];
53	u32	pobar3;
54	u8	res10[4];
55	u32	pocmr3;
56	u8	res11[4];
57	u32	potar4;
58	u8	res12[4];
59	u32	pobar4;
60	u8	res13[4];
61	u32	pocmr4;
62	u8	res14[4];
63	u32	potar5;
64	u8	res15[4];
65	u32	pobar5;
66	u8	res16[4];
67	u32	pocmr5;
68	u8	res17[4];
69	u8	res18[0x60];
70	u32	pmcr;
71	u8	res19[4];
72	u32	dtcr;
73	u8	res20[4];
74} immr_ios_t;
75#define POTAR_TA_MASK	0x000fffff
76#define POBAR_BA_MASK	0x000fffff
77#define POCMR_EN	0x80000000
78#define POCMR_IO	0x40000000 /* 0--memory space 1--I/O space */
79#define POCMR_SE	0x20000000 /* streaming enable */
80#define POCMR_DST	0x10000000 /* 0--PCI1 1--PCI2 */
81#define POCMR_CM_MASK	0x000fffff
82
83/*
84 * PCI Controller Control and Status Registers
85 */
86typedef struct immr_pcictrl {
87	u32	esr;
88	u32	ecdr;
89	u32	eer;
90	u32	eatcr;
91	u32	eacr;
92	u32	eeacr;
93	u32	edlcr;
94	u32	edhcr;
95	u32	gcr;
96	u32	ecr;
97	u32	gsr;
98	u8	res0[12];
99	u32	pitar2;
100	u8	res1[4];
101	u32	pibar2;
102	u32	piebar2;
103	u32	piwar2;
104	u8	res2[4];
105	u32	pitar1;
106	u8	res3[4];
107	u32	pibar1;
108	u32	piebar1;
109	u32	piwar1;
110	u8	res4[4];
111	u32	pitar0;
112	u8	res5[4];
113	u32	pibar0;
114	u8	res6[4];
115	u32	piwar0;
116	u8	res7[132];
117} immr_pcictrl_t;
118#define PITAR_TA_MASK	0x000fffff
119#define PIBAR_MASK	0xffffffff
120#define PIEBAR_EBA_MASK	0x000fffff
121#define PIWAR_EN	0x80000000
122#define PIWAR_PF	0x20000000
123#define PIWAR_RTT_MASK	0x000f0000
124#define PIWAR_RTT_NO_SNOOP	0x00040000
125#define PIWAR_RTT_SNOOP	0x00050000
126#define PIWAR_WTT_MASK	0x0000f000
127#define PIWAR_WTT_NO_SNOOP	0x00004000
128#define PIWAR_WTT_SNOOP	0x00005000
129#define PIWAR_IWS_MASK	0x0000003F
130#define PIWAR_IWS_4K	0x0000000B
131#define PIWAR_IWS_8K	0x0000000C
132#define PIWAR_IWS_16K	0x0000000D
133#define PIWAR_IWS_32K	0x0000000E
134#define PIWAR_IWS_64K	0x0000000F
135#define PIWAR_IWS_128K	0x00000010
136#define PIWAR_IWS_256K	0x00000011
137#define PIWAR_IWS_512K	0x00000012
138#define PIWAR_IWS_1M	0x00000013
139#define PIWAR_IWS_2M	0x00000014
140#define PIWAR_IWS_4M	0x00000015
141#define PIWAR_IWS_8M	0x00000016
142#define PIWAR_IWS_16M	0x00000017
143#define PIWAR_IWS_32M	0x00000018
144#define PIWAR_IWS_64M	0x00000019
145#define PIWAR_IWS_128M	0x0000001A
146#define PIWAR_IWS_256M	0x0000001B
147#define PIWAR_IWS_512M	0x0000001C
148#define PIWAR_IWS_1G	0x0000001D
149#define PIWAR_IWS_2G	0x0000001E
150
151#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */
152