1/*
2 * Motorola MCG Harrier northbridge/memory controller support
3 *
4 * Author: Dale Farnsworth
5 *         dale.farnsworth@mvista.com
6 *
7 * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
8 * the terms of the GNU General Public License version 2.  This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/harrier_defs.h>
16
17#include <asm/byteorder.h>
18#include <asm/io.h>
19#include <asm/irq.h>
20#include <asm/pci.h>
21#include <asm/pci-bridge.h>
22#include <asm/open_pic.h>
23#include <asm/harrier.h>
24
25/* define defaults for inbound windows */
26#define HARRIER_ITAT_DEFAULT		(HARRIER_ITAT_ENA | \
27					 HARRIER_ITAT_MEM | \
28					 HARRIER_ITAT_WPE | \
29					 HARRIER_ITAT_GBL)
30
31#define HARRIER_MPAT_DEFAULT		(HARRIER_ITAT_ENA | \
32					 HARRIER_ITAT_MEM | \
33					 HARRIER_ITAT_WPE | \
34					 HARRIER_ITAT_GBL)
35
36/*
37 * Initialize the inbound window size on a non-monarch harrier.
38 */
39void __init harrier_setup_nonmonarch(uint ppc_reg_base, uint in0_size)
40{
41	u16 temps;
42	u32 temp;
43
44	if (in0_size > HARRIER_ITSZ_2GB) {
45		printk
46		    ("harrier_setup_nonmonarch: Invalid window size code %d\n",
47		     in0_size);
48		return;
49	}
50
51	/* Clear the PCI memory enable bit. If we don't, then when the
52	 * inbound windows are enabled below, the corresponding BARs will be
53	 * "live" and start answering to PCI memory reads from their default
54	 * addresses (0x0), which overlap with system RAM.
55	 */
56	temps = in_le16((u16 *) (ppc_reg_base +
57				 HARRIER_XCSR_CONFIG(PCI_COMMAND)));
58	temps &= ~(PCI_COMMAND_MEMORY);
59	out_le16((u16 *) (ppc_reg_base + HARRIER_XCSR_CONFIG(PCI_COMMAND)),
60		 temps);
61
62	/* Setup a non-prefetchable inbound window */
63	out_le32((u32 *) (ppc_reg_base +
64			  HARRIER_XCSR_CONFIG(HARRIER_ITSZ0_OFF)), in0_size);
65
66	temp = in_le32((u32 *) (ppc_reg_base +
67				HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)));
68	temp &= ~HARRIER_ITAT_PRE;
69	temp |= HARRIER_ITAT_DEFAULT;
70	out_le32((u32 *) (ppc_reg_base +
71			  HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)), temp);
72
73	/* Enable the message passing block */
74	temp = in_le32((u32 *) (ppc_reg_base +
75				HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)));
76	temp |= HARRIER_MPAT_DEFAULT;
77	out_le32((u32 *) (ppc_reg_base +
78			  HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)), temp);
79}
80
81void __init harrier_release_eready(uint ppc_reg_base)
82{
83	ulong temp;
84
85	/*
86	 * Set EREADY to allow the line to be pulled up after everyone is
87	 * ready.
88	 */
89	temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
90	temp |= HARRIER_EREADY;
91	out_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF), temp);
92}
93
94void __init harrier_wait_eready(uint ppc_reg_base)
95{
96	ulong temp;
97
98	/*
99	 * Poll the ERDYS line until it goes high to indicate that all
100	 * non-monarch PrPMCs are ready for bus enumeration (or that there are
101	 * no PrPMCs present).
102	 */
103
104	do {
105
106		temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
107
108	} while (!(temp & HARRIER_ERDYS));
109}
110
111/*
112 * Initialize the Motorola MCG Harrier host bridge.
113 *
114 * This means setting up the PPC bus to PCI memory and I/O space mappings,
115 * setting the PCI memory space address of the MPIC (mapped straight
116 * through), and ioremap'ing the mpic registers.
117 * 'OpenPIC_Addr' will be set correctly by this routine.
118 * This routine will not change the PCI_CONFIG_ADDR or PCI_CONFIG_DATA
119 * addresses and assumes that the mapping of PCI memory space back to system
120 * memory is set up correctly by PPCBug.
121 */
122int __init
123harrier_init(struct pci_controller *hose,
124	     uint ppc_reg_base,
125	     ulong processor_pci_mem_start,
126	     ulong processor_pci_mem_end,
127	     ulong processor_pci_io_start,
128	     ulong processor_pci_io_end, ulong processor_mpic_base)
129{
130	uint addr, offset;
131
132	/*
133	 * Some sanity checks...
134	 */
135	if (((processor_pci_mem_start & 0xffff0000) != processor_pci_mem_start)
136	    || ((processor_pci_io_start & 0xffff0000) !=
137		processor_pci_io_start)) {
138		printk("harrier_init: %s\n",
139		       "PPC to PCI mappings must start on 64 KB boundaries");
140		return -1;
141	}
142
143	if (((processor_pci_mem_end & 0x0000ffff) != 0x0000ffff) ||
144	    ((processor_pci_io_end & 0x0000ffff) != 0x0000ffff)) {
145		printk("harrier_init: PPC to PCI mappings %s\n",
146		       "must end just before a 64 KB boundaries");
147		return -1;
148	}
149
150	if (((processor_pci_mem_end - processor_pci_mem_start) !=
151	     (hose->mem_space.end - hose->mem_space.start)) ||
152	    ((processor_pci_io_end - processor_pci_io_start) !=
153	     (hose->io_space.end - hose->io_space.start))) {
154		printk("harrier_init: %s\n",
155		       "PPC and PCI memory or I/O space sizes don't match");
156		return -1;
157	}
158
159	if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
160		printk("harrier_init: %s\n",
161		       "MPIC address must start on 256 KB boundary");
162		return -1;
163	}
164
165	if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
166		printk("harrier_init: %s\n",
167		       "pci_dram_offset must be multiple of 64 KB");
168		return -1;
169	}
170
171	/*
172	 * Program the OTAD/OTOF registers to set up the PCI Mem & I/O
173	 * space mappings.  These are the mappings going from the processor to
174	 * the PCI bus.
175	 *
176	 * Note: Don't need to 'AND' start/end addresses with 0xffff0000
177	 *       because sanity check above ensures that they are properly
178	 *       aligned.
179	 */
180
181	/* Set up PPC->PCI Mem mapping */
182	addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
183#ifdef CONFIG_HARRIER_STORE_GATHERING
184	offset = (hose->mem_space.start - processor_pci_mem_start) | 0x9a;
185#else
186	offset = (hose->mem_space.start - processor_pci_mem_start) | 0x92;
187#endif
188	out_be32((uint *) (ppc_reg_base + HARRIER_OTAD0_OFF), addr);
189	out_be32((uint *) (ppc_reg_base + HARRIER_OTOF0_OFF), offset);
190
191	/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
192	addr = processor_pci_io_start | (processor_pci_io_end >> 16);
193	offset = (hose->io_space.start - processor_pci_io_start) | 0x80;
194	out_be32((uint *) (ppc_reg_base + HARRIER_OTAD1_OFF), addr);
195	out_be32((uint *) (ppc_reg_base + HARRIER_OTOF1_OFF), offset);
196
197	/* Enable MPIC */
198	OpenPIC_Addr = (void *)processor_mpic_base;
199	addr = (processor_mpic_base >> 16) | 1;
200	out_be16((ushort *) (ppc_reg_base + HARRIER_MBAR_OFF), addr);
201	out_8((u_char *) (ppc_reg_base + HARRIER_MPIC_CSR_OFF),
202	      HARRIER_MPIC_OPI_ENABLE);
203
204	return 0;
205}
206
207/*
208 * Find the amount of RAM present.
209 * This assumes that PPCBug has initialized the memory controller (SMC)
210 * on the Harrier correctly (i.e., it does no sanity checking).
211 * It also assumes that the memory base registers are set to configure the
212 * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc.
213 * however, RAM base registers can be skipped (e.g. A, B, C are set,
214 * D is skipped but E is set is okay).
215 */
216#define	MB	(1024*1024UL)
217
218static uint harrier_size_table[] __initdata = {
219	0 * MB,			/* 0 ==>    0 MB */
220	32 * MB,		/* 1 ==>   32 MB */
221	64 * MB,		/* 2 ==>   64 MB */
222	64 * MB,		/* 3 ==>   64 MB */
223	128 * MB,		/* 4 ==>  128 MB */
224	128 * MB,		/* 5 ==>  128 MB */
225	128 * MB,		/* 6 ==>  128 MB */
226	256 * MB,		/* 7 ==>  256 MB */
227	256 * MB,		/* 8 ==>  256 MB */
228	256 * MB,		/* 9 ==>  256 MB */
229	512 * MB,		/* a ==>  512 MB */
230	512 * MB,		/* b ==>  512 MB */
231	512 * MB,		/* c ==>  512 MB */
232	1024 * MB,		/* d ==> 1024 MB */
233	1024 * MB,		/* e ==> 1024 MB */
234	2048 * MB,		/* f ==> 2048 MB */
235};
236
237/*
238 * *** WARNING: You MUST have a BAT set up to map in the XCSR regs ***
239 *
240 * Read the memory controller's registers to determine the amount of system
241 * memory.  Assumes that the memory controller registers are already mapped
242 * into virtual memory--too early to use ioremap().
243 */
244unsigned long __init harrier_get_mem_size(uint xcsr_base)
245{
246	ulong last_addr;
247	int i;
248	uint vend_dev_id;
249	uint *size_table;
250	uint val;
251	uint *csrp;
252	uint size;
253	int size_table_entries;
254
255	vend_dev_id = in_be32((uint *) xcsr_base + PCI_VENDOR_ID);
256
257	if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
258		printk("harrier_get_mem_size: %s (0x%x)\n",
259		       "Not a Motorola Memory Controller", vend_dev_id);
260		return 0;
261	}
262
263	vend_dev_id &= 0x0000ffff;
264
265	if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HARRIER) {
266		size_table = harrier_size_table;
267		size_table_entries = sizeof(harrier_size_table) /
268		    sizeof(harrier_size_table[0]);
269	} else {
270		printk("harrier_get_mem_size: %s (0x%x)\n",
271		       "Not a Harrier", vend_dev_id);
272		return 0;
273	}
274
275	last_addr = 0;
276
277	csrp = (uint *) (xcsr_base + HARRIER_SDBA_OFF);
278	for (i = 0; i < 8; i++) {
279		val = in_be32(csrp++);
280
281		if (val & 0x100) {	/* If enabled */
282			size = val >> HARRIER_SDB_SIZE_SHIFT;
283			size &= HARRIER_SDB_SIZE_MASK;
284			if (size >= size_table_entries) {
285				break;	/* Register not set correctly */
286			}
287			size = size_table[size];
288
289			val &= ~(size - 1);
290			val += size;
291
292			if (val > last_addr) {
293				last_addr = val;
294			}
295		}
296	}
297
298	return last_addr;
299}
300