1/* 2 * Board setup routines for the Motorola SPS Sandpoint Test Platform. 3 * 4 * Author: Mark A. Greer 5 * mgreer@mvista.com 6 * 7 * 2000-2003 (c) MontaVista Software, Inc. This file is licensed under 8 * the terms of the GNU General Public License version 2. This program 9 * is licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 */ 12 13/* 14 * This file adds support for the Motorola SPS Sandpoint Test Platform. 15 * These boards have a PPMC slot for the processor so any combination 16 * of cpu and host bridge can be attached. This port is for an 8240 PPMC 17 * module from Motorola SPS and other closely related cpu/host bridge 18 * combinations (e.g., 750/755/7400 with MPC107 host bridge). 19 * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2 20 * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a 21 * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr), 22 * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V 23 * but are really 5V). 24 * 25 * The firmware on the sandpoint is called DINK (not my acronym :). This port 26 * depends on DINK to do some basic initialization (e.g., initialize the memory 27 * ctlr) and to ensure that the processor is using MAP B (CHRP map). 28 * 29 * The switch settings for the Sandpoint board MUST be as follows: 30 * S3: down 31 * S4: up 32 * S5: up 33 * S6: down 34 * 35 * 'down' is in the direction from the PCI slots towards the PPMC slot; 36 * 'up' is in the direction from the PPMC slot towards the PCI slots. 37 * Be careful, the way the sandpoint board is installed in XT chasses will 38 * make the directions reversed. 39 * 40 * Since Motorola listened to our suggestions for improvement, we now have 41 * the Sandpoint X3 board. All of the PCI slots are available, it uses 42 * the serial interrupt interface (just a hardware thing we need to 43 * configure properly). 44 * 45 * Use the default X3 switch settings. The interrupts are then: 46 * EPIC Source 47 * 0 SIOINT (8259, active low) 48 * 1 PCI #1 49 * 2 PCI #2 50 * 3 PCI #3 51 * 4 PCI #4 52 * 7 Winbond INTC (IDE interrupt) 53 * 8 Winbond INTD (IDE interrupt) 54 * 55 * 56 * Motorola has finally released a version of DINK32 that correctly 57 * (seemingly) initializes the memory controller correctly, regardless 58 * of the amount of memory in the system. Once a method of determining 59 * what version of DINK initializes the system for us, if applicable, is 60 * found, we can hopefully stop hardcoding 32MB of RAM. 61 */ 62 63#include <linux/stddef.h> 64#include <linux/kernel.h> 65#include <linux/init.h> 66#include <linux/errno.h> 67#include <linux/reboot.h> 68#include <linux/pci.h> 69#include <linux/kdev_t.h> 70#include <linux/major.h> 71#include <linux/initrd.h> 72#include <linux/console.h> 73#include <linux/delay.h> 74#include <linux/ide.h> 75#include <linux/seq_file.h> 76#include <linux/root_dev.h> 77#include <linux/serial.h> 78#include <linux/tty.h> /* for linux/serial_core.h */ 79#include <linux/serial_core.h> 80#include <linux/serial_8250.h> 81 82#include <asm/system.h> 83#include <asm/pgtable.h> 84#include <asm/page.h> 85#include <asm/time.h> 86#include <asm/dma.h> 87#include <asm/io.h> 88#include <asm/machdep.h> 89#include <asm/prom.h> 90#include <asm/smp.h> 91#include <asm/vga.h> 92#include <asm/open_pic.h> 93#include <asm/i8259.h> 94#include <asm/todc.h> 95#include <asm/bootinfo.h> 96#include <asm/mpc10x.h> 97#include <asm/pci-bridge.h> 98#include <asm/kgdb.h> 99#include <asm/ppc_sys.h> 100 101#include "sandpoint.h" 102 103/* Set non-zero if an X2 Sandpoint detected. */ 104static int sandpoint_is_x2; 105 106unsigned char __res[sizeof(bd_t)]; 107 108static void sandpoint_halt(void); 109static void sandpoint_probe_type(void); 110 111/* 112 * Define all of the IRQ senses and polarities. Taken from the 113 * Sandpoint X3 User's manual. 114 */ 115static u_char sandpoint_openpic_initsenses[] __initdata = { 116 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */ 117 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */ 118 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */ 119 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */ 120 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */ 121 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */ 122 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */ 123}; 124 125/* 126 * Motorola SPS Sandpoint interrupt routing. 127 */ 128static inline int 129x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) 130{ 131 static char pci_irq_table[][4] = 132 /* 133 * PCI IDSEL/INTPIN->INTLINE 134 * A B C D 135 */ 136 { 137 { 16, 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */ 138 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */ 139 { 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */ 140 { 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */ 141 { 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */ 142 { 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */ 143 }; 144 145 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4; 146 return PCI_IRQ_TABLE_LOOKUP; 147} 148 149static inline int 150x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) 151{ 152 static char pci_irq_table[][4] = 153 /* 154 * PCI IDSEL/INTPIN->INTLINE 155 * A B C D 156 */ 157 { 158 { 18, 0, 0, 0 }, /* IDSEL 11 - i8259 on Windbond */ 159 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */ 160 { 16, 17, 18, 19 }, /* IDSEL 13 - PCI slot 1 */ 161 { 17, 18, 19, 16 }, /* IDSEL 14 - PCI slot 2 */ 162 { 18, 19, 16, 17 }, /* IDSEL 15 - PCI slot 3 */ 163 { 19, 16, 17, 18 }, /* IDSEL 16 - PCI slot 4 */ 164 }; 165 166 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4; 167 return PCI_IRQ_TABLE_LOOKUP; 168} 169 170static void __init 171sandpoint_setup_winbond_83553(struct pci_controller *hose) 172{ 173 int devfn; 174 175 /* 176 * Route IDE interrupts directly to the 8259's IRQ 14 & 15. 177 * We can't route the IDE interrupt to PCI INTC# or INTD# because those 178 * woule interfere with the PMC's INTC# and INTD# lines. 179 */ 180 /* 181 * Winbond Fcn 0 182 */ 183 devfn = PCI_DEVFN(11,0); 184 185 early_write_config_byte(hose, 186 0, 187 devfn, 188 0x43, /* IDE Interrupt Routing Control */ 189 0xef); 190 early_write_config_word(hose, 191 0, 192 devfn, 193 0x44, /* PCI Interrupt Routing Control */ 194 0x0000); 195 196 /* Want ISA memory cycles to be forwarded to PCI bus */ 197 early_write_config_byte(hose, 198 0, 199 devfn, 200 0x48, /* ISA-to-PCI Addr Decoder Control */ 201 0xf0); 202 203 /* Enable Port 92. */ 204 early_write_config_byte(hose, 205 0, 206 devfn, 207 0x4e, /* AT System Control Register */ 208 0x06); 209 /* 210 * Winbond Fcn 1 211 */ 212 devfn = PCI_DEVFN(11,1); 213 214 /* Put IDE controller into native mode. */ 215 early_write_config_byte(hose, 216 0, 217 devfn, 218 0x09, /* Programming interface Register */ 219 0x8f); 220 221 /* Init IRQ routing, enable both ports, disable fast 16 */ 222 early_write_config_dword(hose, 223 0, 224 devfn, 225 0x40, /* IDE Control/Status Register */ 226 0x00ff0011); 227 return; 228} 229 230/* On the sandpoint X2, we must avoid sending configuration cycles to 231 * device #12 (IDSEL addr = AD12). 232 */ 233static int 234x2_exclude_device(u_char bus, u_char devfn) 235{ 236 if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL)) 237 return PCIBIOS_DEVICE_NOT_FOUND; 238 else 239 return PCIBIOS_SUCCESSFUL; 240} 241 242static void __init 243sandpoint_find_bridges(void) 244{ 245 struct pci_controller *hose; 246 247 hose = pcibios_alloc_controller(); 248 249 if (!hose) 250 return; 251 252 hose->first_busno = 0; 253 hose->last_busno = 0xff; 254 255 if (mpc10x_bridge_init(hose, 256 MPC10X_MEM_MAP_B, 257 MPC10X_MEM_MAP_B, 258 MPC10X_MAPB_EUMB_BASE) == 0) { 259 260 /* Do early winbond init, then scan PCI bus */ 261 sandpoint_setup_winbond_83553(hose); 262 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); 263 264 ppc_md.pcibios_fixup = NULL; 265 ppc_md.pcibios_fixup_bus = NULL; 266 ppc_md.pci_swizzle = common_swizzle; 267 if (sandpoint_is_x2) { 268 ppc_md.pci_map_irq = x2_map_irq; 269 ppc_md.pci_exclude_device = x2_exclude_device; 270 } else 271 ppc_md.pci_map_irq = x3_map_irq; 272 } 273 else { 274 if (ppc_md.progress) 275 ppc_md.progress("Bridge init failed", 0x100); 276 printk("Host bridge init failed\n"); 277 } 278 279 return; 280} 281 282static void __init 283sandpoint_setup_arch(void) 284{ 285 /* Probe for Sandpoint model */ 286 sandpoint_probe_type(); 287 if (sandpoint_is_x2) 288 epic_serial_mode = 0; 289 290 loops_per_jiffy = 100000000 / HZ; 291 292#ifdef CONFIG_BLK_DEV_INITRD 293 if (initrd_start) 294 ROOT_DEV = Root_RAM0; 295 else 296#endif 297#ifdef CONFIG_ROOT_NFS 298 ROOT_DEV = Root_NFS; 299#else 300 ROOT_DEV = Root_HDA1; 301#endif 302 303 /* Lookup PCI host bridges */ 304 sandpoint_find_bridges(); 305 306 if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0) 307 { 308 bd_t *bp = (bd_t *)__res; 309 struct plat_serial8250_port *pdata; 310 311 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0); 312 if (pdata) 313 { 314 pdata[0].uartclk = bp->bi_busfreq; 315 } 316 317#ifdef CONFIG_SANDPOINT_ENABLE_UART1 318 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1); 319 if (pdata) 320 { 321 pdata[0].uartclk = bp->bi_busfreq; 322 } 323#else 324 ppc_sys_device_remove(MPC10X_UART1); 325#endif 326 } 327 328 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n"); 329 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n"); 330 331 /* DINK32 12.3 and below do not correctly enable any caches. 332 * We will do this now with good known values. Future versions 333 * of DINK32 are supposed to get this correct. 334 */ 335 if (cpu_has_feature(CPU_FTR_SPEC7450)) 336 /* 745x is different. We only want to pass along enable. */ 337 _set_L2CR(L2CR_L2E); 338 else if (cpu_has_feature(CPU_FTR_L2CR)) 339 /* All modules have 1MB of L2. We also assume that an 340 * L2 divisor of 3 will work. 341 */ 342 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 343 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); 344} 345 346#define SANDPOINT_87308_CFG_ADDR 0x15c 347#define SANDPOINT_87308_CFG_DATA 0x15d 348 349#define SANDPOINT_87308_CFG_INB(addr, byte) { \ 350 outb((addr), SANDPOINT_87308_CFG_ADDR); \ 351 (byte) = inb(SANDPOINT_87308_CFG_DATA); \ 352} 353 354#define SANDPOINT_87308_CFG_OUTB(addr, byte) { \ 355 outb((addr), SANDPOINT_87308_CFG_ADDR); \ 356 outb((byte), SANDPOINT_87308_CFG_DATA); \ 357} 358 359#define SANDPOINT_87308_SELECT_DEV(dev_num) { \ 360 SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \ 361} 362 363#define SANDPOINT_87308_DEV_ENABLE(dev_num) { \ 364 SANDPOINT_87308_SELECT_DEV(dev_num); \ 365 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \ 366} 367 368/* 369 * To probe the Sandpoint type, we need to check for a connection between GPIO 370 * pins 6 and 7 on the NS87308 SuperIO. 371 */ 372static void __init sandpoint_probe_type(void) 373{ 374 u8 x; 375 /* First, ensure that the GPIO pins are enabled. */ 376 SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */ 377 SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */ 378 SANDPOINT_87308_CFG_OUTB(0x61, 0x00); 379 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */ 380 381 /* Now, set pin 7 to output and pin 6 to input. */ 382 outb((inb(0x701) | 0x80) & 0xbf, 0x701); 383 /* Set push-pull output */ 384 outb(inb(0x702) | 0x80, 0x702); 385 /* Set pull-up on input */ 386 outb(inb(0x703) | 0x40, 0x703); 387 /* Set output high and check */ 388 x = inb(0x700); 389 outb(x | 0x80, 0x700); 390 x = inb(0x700); 391 sandpoint_is_x2 = ! (x & 0x40); 392 if (ppc_md.progress && sandpoint_is_x2) 393 ppc_md.progress("High output says X2", 0); 394 /* Set output low and check */ 395 outb(x & 0x7f, 0x700); 396 sandpoint_is_x2 |= inb(0x700) & 0x40; 397 if (ppc_md.progress && sandpoint_is_x2) 398 ppc_md.progress("Low output says X2", 0); 399 if (ppc_md.progress && ! sandpoint_is_x2) 400 ppc_md.progress("Sandpoint is X3", 0); 401} 402 403/* 404 * Fix IDE interrupts. 405 */ 406static int __init 407sandpoint_fix_winbond_83553(void) 408{ 409 /* Make some 8259 interrupt level sensitive */ 410 outb(0xe0, 0x4d0); 411 outb(0xde, 0x4d1); 412 413 return 0; 414} 415 416arch_initcall(sandpoint_fix_winbond_83553); 417 418/* 419 * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip. 420 */ 421static int __init 422sandpoint_setup_natl_87308(void) 423{ 424 u_char reg; 425 426 /* 427 * Enable all the devices on the Super I/O chip. 428 */ 429 SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */ 430 SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */ 431 SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */ 432 SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */ 433 SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */ 434 SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */ 435 SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */ 436 SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */ 437 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */ 438 SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */ 439 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */ 440 441 /* Set up floppy in PS/2 mode */ 442 outb(0x09, SIO_CONFIG_RA); 443 reg = inb(SIO_CONFIG_RD); 444 reg = (reg & 0x3F) | 0x40; 445 outb(reg, SIO_CONFIG_RD); 446 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */ 447 448 return 0; 449} 450 451arch_initcall(sandpoint_setup_natl_87308); 452 453static int __init 454sandpoint_request_io(void) 455{ 456 request_region(0x00,0x20,"dma1"); 457 request_region(0x20,0x20,"pic1"); 458 request_region(0x40,0x20,"timer"); 459 request_region(0x80,0x10,"dma page reg"); 460 request_region(0xa0,0x20,"pic2"); 461 request_region(0xc0,0x20,"dma2"); 462 463 return 0; 464} 465 466arch_initcall(sandpoint_request_io); 467 468/* 469 * Interrupt setup and service. Interrupts on the Sandpoint come 470 * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO). 471 * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4, 472 * IDE is on EPIC 7 and 8. 473 */ 474static void __init 475sandpoint_init_IRQ(void) 476{ 477 int i; 478 479 OpenPIC_InitSenses = sandpoint_openpic_initsenses; 480 OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses); 481 482 mpc10x_set_openpic(); 483 openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade", 484 i8259_irq); 485 486 /* 487 * The EPIC allows for a read in the range of 0xFEF00000 -> 488 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction. 489 */ 490 i8259_init(0xfef00000, 0); 491} 492 493static unsigned long __init 494sandpoint_find_end_of_memory(void) 495{ 496 bd_t *bp = (bd_t *)__res; 497 498 if (bp->bi_memsize) 499 return bp->bi_memsize; 500 501 /* DINK32 13.0 correctly initializes things, so iff you use 502 * this you _should_ be able to change this instead of a 503 * hardcoded value. */ 504 return 32*1024*1024; 505} 506 507static void __init 508sandpoint_map_io(void) 509{ 510 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); 511} 512 513static void 514sandpoint_restart(char *cmd) 515{ 516 local_irq_disable(); 517 518 /* Set exception prefix high - to the firmware */ 519 _nmask_and_or_msr(0, MSR_IP); 520 521 /* Reset system via Port 92 */ 522 outb(0x00, 0x92); 523 outb(0x01, 0x92); 524 for(;;); /* Spin until reset happens */ 525} 526 527static void 528sandpoint_power_off(void) 529{ 530 local_irq_disable(); 531 for(;;); /* No way to shut power off with software */ 532 /* NOTREACHED */ 533} 534 535static void 536sandpoint_halt(void) 537{ 538 sandpoint_power_off(); 539 /* NOTREACHED */ 540} 541 542static int 543sandpoint_show_cpuinfo(struct seq_file *m) 544{ 545 seq_printf(m, "vendor\t\t: Motorola SPS\n"); 546 seq_printf(m, "machine\t\t: Sandpoint\n"); 547 548 return 0; 549} 550 551#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) 552/* 553 * IDE support. 554 */ 555static int sandpoint_ide_ports_known = 0; 556static unsigned long sandpoint_ide_regbase[MAX_HWIFS]; 557static unsigned long sandpoint_ide_ctl_regbase[MAX_HWIFS]; 558static unsigned long sandpoint_idedma_regbase; 559 560static void 561sandpoint_ide_probe(void) 562{ 563 struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_WINBOND, 564 PCI_DEVICE_ID_WINBOND_82C105, NULL); 565 566 if (pdev) { 567 sandpoint_ide_regbase[0]=pdev->resource[0].start; 568 sandpoint_ide_regbase[1]=pdev->resource[2].start; 569 sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start; 570 sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start; 571 sandpoint_idedma_regbase=pdev->resource[4].start; 572 pci_dev_put(pdev); 573 } 574 575 sandpoint_ide_ports_known = 1; 576} 577 578static int 579sandpoint_ide_default_irq(unsigned long base) 580{ 581 if (sandpoint_ide_ports_known == 0) 582 sandpoint_ide_probe(); 583 584 if (base == sandpoint_ide_regbase[0]) 585 return SANDPOINT_IDE_INT0; 586 else if (base == sandpoint_ide_regbase[1]) 587 return SANDPOINT_IDE_INT1; 588 else 589 return 0; 590} 591 592static unsigned long 593sandpoint_ide_default_io_base(int index) 594{ 595 if (sandpoint_ide_ports_known == 0) 596 sandpoint_ide_probe(); 597 598 return sandpoint_ide_regbase[index]; 599} 600 601static void __init 602sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, 603 unsigned long ctrl_port, int *irq) 604{ 605 unsigned long reg = data_port; 606 uint alt_status_base; 607 int i; 608 609 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 610 hw->io_ports[i] = reg++; 611 } 612 613 if (data_port == sandpoint_ide_regbase[0]) { 614 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2; 615 hw->irq = 14; 616 } 617 else if (data_port == sandpoint_ide_regbase[1]) { 618 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2; 619 hw->irq = 15; 620 } 621 else { 622 alt_status_base = 0; 623 hw->irq = 0; 624 } 625 626 if (ctrl_port) { 627 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; 628 } else { 629 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base; 630 } 631 632 if (irq != NULL) { 633 *irq = hw->irq; 634 } 635} 636#endif 637 638/* 639 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1. 640 */ 641static __inline__ void 642sandpoint_set_bat(void) 643{ 644 unsigned long bat3u, bat3l; 645 646 __asm__ __volatile__( 647 " lis %0,0xf800\n \ 648 ori %1,%0,0x002a\n \ 649 ori %0,%0,0x0ffe\n \ 650 mtspr 0x21e,%0\n \ 651 mtspr 0x21f,%1\n \ 652 isync\n \ 653 sync " 654 : "=r" (bat3u), "=r" (bat3l)); 655} 656 657TODC_ALLOC(); 658 659void __init 660platform_init(unsigned long r3, unsigned long r4, unsigned long r5, 661 unsigned long r6, unsigned long r7) 662{ 663 parse_bootinfo(find_bootinfo()); 664 665 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) 666 * are non-zero, then we should use the board info from the bd_t 667 * structure and the cmdline pointed to by r6 instead of the 668 * information from birecs, if any. Otherwise, use the information 669 * from birecs as discovered by the preceding call to 670 * parse_bootinfo(). This rule should work with both PPCBoot, which 671 * uses a bd_t board info structure, and the kernel boot wrapper, 672 * which uses birecs. 673 */ 674 if (r3 && r6) { 675 /* copy board info structure */ 676 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); 677 /* copy command line */ 678 *(char *)(r7+KERNELBASE) = 0; 679 strcpy(cmd_line, (char *)(r6+KERNELBASE)); 680 } 681 682#ifdef CONFIG_BLK_DEV_INITRD 683 /* take care of initrd if we have one */ 684 if (r4) { 685 initrd_start = r4 + KERNELBASE; 686 initrd_end = r5 + KERNELBASE; 687 } 688#endif /* CONFIG_BLK_DEV_INITRD */ 689 690 /* Map in board regs, etc. */ 691 sandpoint_set_bat(); 692 693 isa_io_base = MPC10X_MAPB_ISA_IO_BASE; 694 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE; 695 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET; 696 ISA_DMA_THRESHOLD = 0x00ffffff; 697 DMA_MODE_READ = 0x44; 698 DMA_MODE_WRITE = 0x48; 699 ppc_do_canonicalize_irqs = 1; 700 701 ppc_md.setup_arch = sandpoint_setup_arch; 702 ppc_md.show_cpuinfo = sandpoint_show_cpuinfo; 703 ppc_md.init_IRQ = sandpoint_init_IRQ; 704 ppc_md.get_irq = openpic_get_irq; 705 706 ppc_md.restart = sandpoint_restart; 707 ppc_md.power_off = sandpoint_power_off; 708 ppc_md.halt = sandpoint_halt; 709 710 ppc_md.find_end_of_memory = sandpoint_find_end_of_memory; 711 ppc_md.setup_io_mappings = sandpoint_map_io; 712 713 TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8); 714 ppc_md.time_init = todc_time_init; 715 ppc_md.set_rtc_time = todc_set_rtc_time; 716 ppc_md.get_rtc_time = todc_get_rtc_time; 717 ppc_md.calibrate_decr = todc_calibrate_decr; 718 719 ppc_md.nvram_read_val = todc_mc146818_read_val; 720 ppc_md.nvram_write_val = todc_mc146818_write_val; 721 722#ifdef CONFIG_KGDB 723 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; 724#endif 725#ifdef CONFIG_SERIAL_TEXT_DEBUG 726 ppc_md.progress = gen550_progress; 727#endif 728 729#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) 730 ppc_ide_md.default_irq = sandpoint_ide_default_irq; 731 ppc_ide_md.default_io_base = sandpoint_ide_default_io_base; 732 ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports; 733#endif 734} 735