1/* 2 * Definitions for Artesyn Katana750i/3750 board. 3 * 4 * Author: Tim Montgomery <timm@artesyncp.com> 5 * Maintained by: Mark A. Greer <mgreer@mvista.com> 6 * 7 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il 8 * Based on code done by Mark A. Greer <mgreer@mvista.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16/* 17 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to 18 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. 19 * We'll only use one PCI MEM window on each PCI bus. 20 * 21 * This is the CPU physical memory map (windows must be at least 64 KB and start 22 * on a boundary that is a multiple of the window size): 23 * 24 * 0xff800000-0xffffffff - Boot window 25 * 0xf8400000-0xf843ffff - Internal SRAM 26 * 0xf8200000-0xf83fffff - CPLD 27 * 0xf8100000-0xf810ffff - MV64360 Registers (CONFIG_MV64X60_NEW_BASE) 28 * 0xf8000000-0xf80fffff - Socketed FLASH 29 * 0xe0000000-0xefffffff - Soldered FLASH 30 * 0xc0000000-0xc3ffffff - PCI I/O (second hose) 31 * 0x80000000-0xbfffffff - PCI MEM (second hose) 32 */ 33 34#ifndef __PPC_PLATFORMS_KATANA_H 35#define __PPC_PLATFORMS_KATANA_H 36 37/* CPU Physical Memory Map setup. */ 38#define KATANA_BOOT_WINDOW_BASE 0xff800000 39#define KATANA_BOOT_WINDOW_SIZE 0x00800000 /* 8 MB */ 40#define KATANA_INTERNAL_SRAM_BASE 0xf8400000 41#define KATANA_CPLD_BASE 0xf8200000 42#define KATANA_CPLD_SIZE 0x00200000 /* 2 MB */ 43#define KATANA_SOCKET_BASE 0xf8000000 44#define KATANA_SOCKETED_FLASH_SIZE 0x00100000 /* 1 MB */ 45#define KATANA_SOLDERED_FLASH_BASE 0xe0000000 46#define KATANA_SOLDERED_FLASH_SIZE 0x10000000 /* 256 MB */ 47 48#define KATANA_PCI1_MEM_START_PROC_ADDR 0x80000000 49#define KATANA_PCI1_MEM_START_PCI_HI_ADDR 0x00000000 50#define KATANA_PCI1_MEM_START_PCI_LO_ADDR 0x80000000 51#define KATANA_PCI1_MEM_SIZE 0x40000000 /* 1 GB */ 52#define KATANA_PCI1_IO_START_PROC_ADDR 0xc0000000 53#define KATANA_PCI1_IO_START_PCI_ADDR 0x00000000 54#define KATANA_PCI1_IO_SIZE 0x04000000 /* 64 MB */ 55 56/* Board-specific IRQ info */ 57#define KATANA_PCI_INTA_IRQ_3750 (64+8) 58#define KATANA_PCI_INTB_IRQ_3750 (64+9) 59#define KATANA_PCI_INTC_IRQ_3750 (64+10) 60 61#define KATANA_PCI_INTA_IRQ_750i (64+8) 62#define KATANA_PCI_INTB_IRQ_750i (64+9) 63#define KATANA_PCI_INTC_IRQ_750i (64+10) 64#define KATANA_PCI_INTD_IRQ_750i (64+14) 65 66#define KATANA_CPLD_RST_EVENT 0x00000000 67#define KATANA_CPLD_RST_CMD 0x00001000 68#define KATANA_CPLD_PCI_ERR_INT_EN 0x00002000 69#define KATANA_CPLD_PCI_ERR_INT_PEND 0x00003000 70#define KATANA_CPLD_PRODUCT_ID 0x00004000 71#define KATANA_CPLD_EREADY 0x00005000 72 73#define KATANA_CPLD_HARDWARE_VER 0x00007000 74#define KATANA_CPLD_PLD_VER 0x00008000 75#define KATANA_CPLD_BD_CFG_0 0x00009000 76#define KATANA_CPLD_BD_CFG_1 0x0000a000 77#define KATANA_CPLD_BD_CFG_3 0x0000c000 78#define KATANA_CPLD_LED 0x0000d000 79#define KATANA_CPLD_RESET_OUT 0x0000e000 80 81#define KATANA_CPLD_RST_EVENT_INITACT 0x80 82#define KATANA_CPLD_RST_EVENT_SW 0x40 83#define KATANA_CPLD_RST_EVENT_WD 0x20 84#define KATANA_CPLD_RST_EVENT_COPS 0x10 85#define KATANA_CPLD_RST_EVENT_COPH 0x08 86#define KATANA_CPLD_RST_EVENT_CPCI 0x02 87#define KATANA_CPLD_RST_EVENT_FP 0x01 88 89#define KATANA_CPLD_RST_CMD_SCL 0x80 90#define KATANA_CPLD_RST_CMD_SDA 0x40 91#define KATANA_CPLD_RST_CMD_I2C 0x10 92#define KATANA_CPLD_RST_CMD_FR 0x08 93#define KATANA_CPLD_RST_CMD_SR 0x04 94#define KATANA_CPLD_RST_CMD_HR 0x01 95 96#define KATANA_CPLD_BD_CFG_0_SYSCLK_MASK 0xc0 97#define KATANA_CPLD_BD_CFG_0_SYSCLK_200 0x00 98#define KATANA_CPLD_BD_CFG_0_SYSCLK_166 0x80 99#define KATANA_CPLD_BD_CFG_0_SYSCLK_133 0xc0 100#define KATANA_CPLD_BD_CFG_0_SYSCLK_100 0x40 101 102#define KATANA_CPLD_BD_CFG_1_FL_BANK_MASK 0x03 103#define KATANA_CPLD_BD_CFG_1_FL_BANK_16MB 0x00 104#define KATANA_CPLD_BD_CFG_1_FL_BANK_32MB 0x01 105#define KATANA_CPLD_BD_CFG_1_FL_BANK_64MB 0x02 106#define KATANA_CPLD_BD_CFG_1_FL_BANK_128MB 0x03 107 108#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_MASK 0x04 109#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_ONE 0x00 110#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_TWO 0x04 111 112#define KATANA_CPLD_BD_CFG_3_MONARCH 0x04 113 114#define KATANA_CPLD_RESET_OUT_PORTSEL 0x80 115#define KATANA_CPLD_RESET_OUT_WD 0x20 116#define KATANA_CPLD_RESET_OUT_COPH 0x08 117#define KATANA_CPLD_RESET_OUT_PCI_RST_PCI 0x02 118#define KATANA_CPLD_RESET_OUT_PCI_RST_FP 0x01 119 120#define KATANA_MBOX_RESET_REQUEST 0xC83A 121#define KATANA_MBOX_RESET_ACK 0xE430 122#define KATANA_MBOX_RESET_DONE 0x32E5 123 124#define HSL_PLD_BASE 0x00010000 125#define HSL_PLD_J4SGA_REG_OFF 0 126#define HSL_PLD_J4GA_REG_OFF 1 127#define HSL_PLD_J2GA_REG_OFF 2 128#define HSL_PLD_HOT_SWAP_OFF 6 129#define HSL_PLD_HOT_SWAP_LED_BIT 0x1 130#define GA_MASK 0x1f 131#define HSL_PLD_SIZE 0x1000 132#define K3750_GPP_GEO_ADDR_PINS 0xf8000000 133#define K3750_GPP_GEO_ADDR_SHIFT 27 134 135#define K3750_GPP_EVENT_PROC_0 (1 << 21) 136#define K3750_GPP_EVENT_PROC_1_2 (1 << 2) 137 138#define PCI_VENDOR_ID_ARTESYN 0x1223 139#define PCI_DEVICE_ID_KATANA_3750_PROC0 0x0041 140#define PCI_DEVICE_ID_KATANA_3750_PROC1 0x0042 141#define PCI_DEVICE_ID_KATANA_3750_PROC2 0x0043 142 143#define COPROC_MEM_FUNCTION 0 144#define COPROC_MEM_BAR 0 145#define COPROC_REGS_FUNCTION 0 146#define COPROC_REGS_BAR 4 147#define COPROC_FLASH_FUNCTION 2 148#define COPROC_FLASH_BAR 4 149 150#define KATANA_IPMB_LOCAL_I2C_ADDR 0x08 151 152#define KATANA_DEFAULT_BAUD 9600 153#define KATANA_MPSC_CLK_SRC 8 /* TCLK */ 154 155#define KATANA_MTD_MONITOR_SIZE (1 << 20) /* 1 MB */ 156 157#define KATANA_ETH0_PHY_ADDR 12 158#define KATANA_ETH1_PHY_ADDR 11 159#define KATANA_ETH2_PHY_ADDR 4 160 161#define KATANA_PRODUCT_ID_3750 0x01 162#define KATANA_PRODUCT_ID_750i 0x02 163#define KATANA_PRODUCT_ID_752i 0x04 164 165#define KATANA_ETH_TX_QUEUE_SIZE 800 166#define KATANA_ETH_RX_QUEUE_SIZE 400 167 168#define KATANA_ETH_PORT_CONFIG_VALUE \ 169 ETH_UNICAST_NORMAL_MODE | \ 170 ETH_DEFAULT_RX_QUEUE_0 | \ 171 ETH_DEFAULT_RX_ARP_QUEUE_0 | \ 172 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ 173 ETH_RECEIVE_BC_IF_IP | \ 174 ETH_RECEIVE_BC_IF_ARP | \ 175 ETH_CAPTURE_TCP_FRAMES_DIS | \ 176 ETH_CAPTURE_UDP_FRAMES_DIS | \ 177 ETH_DEFAULT_RX_TCP_QUEUE_0 | \ 178 ETH_DEFAULT_RX_UDP_QUEUE_0 | \ 179 ETH_DEFAULT_RX_BPDU_QUEUE_0 180 181#define KATANA_ETH_PORT_CONFIG_EXTEND_VALUE \ 182 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ 183 ETH_PARTITION_DISABLE 184 185#define GT_ETH_IPG_INT_RX(value) \ 186 ((value & 0x3fff) << 8) 187 188#define KATANA_ETH_PORT_SDMA_CONFIG_VALUE \ 189 ETH_RX_BURST_SIZE_4_64BIT | \ 190 GT_ETH_IPG_INT_RX(0) | \ 191 ETH_TX_BURST_SIZE_4_64BIT 192 193#define KATANA_ETH_PORT_SERIAL_CONTROL_VALUE \ 194 ETH_FORCE_LINK_PASS | \ 195 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ 196 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ 197 ETH_ADV_SYMMETRIC_FLOW_CTRL | \ 198 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 199 ETH_FORCE_BP_MODE_NO_JAM | \ 200 BIT9 | \ 201 ETH_DO_NOT_FORCE_LINK_FAIL | \ 202 ETH_RETRANSMIT_16_ATTEMPTS | \ 203 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ 204 ETH_DTE_ADV_0 | \ 205 ETH_DISABLE_AUTO_NEG_BYPASS | \ 206 ETH_AUTO_NEG_NO_CHANGE | \ 207 ETH_MAX_RX_PACKET_9700BYTE | \ 208 ETH_CLR_EXT_LOOPBACK | \ 209 ETH_SET_FULL_DUPLEX_MODE | \ 210 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 211 212#ifndef __ASSEMBLY__ 213 214typedef enum { 215 KATANA_ID_3750, 216 KATANA_ID_750I, 217 KATANA_ID_752I, 218 KATANA_ID_MAX 219} katana_id_t; 220 221#endif 222 223static inline u32 224katana_bus_freq(void __iomem *cpld_base) 225{ 226 u8 bd_cfg_0; 227 228 bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0); 229 230 switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) { 231 case KATANA_CPLD_BD_CFG_0_SYSCLK_200: 232 return 200000000; 233 break; 234 235 case KATANA_CPLD_BD_CFG_0_SYSCLK_166: 236 return 166666666; 237 break; 238 239 case KATANA_CPLD_BD_CFG_0_SYSCLK_133: 240 return 133333333; 241 break; 242 243 case KATANA_CPLD_BD_CFG_0_SYSCLK_100: 244 return 100000000; 245 break; 246 247 default: 248 return 133333333; 249 break; 250 } 251} 252 253#endif /* __PPC_PLATFORMS_KATANA_H */ 254