1/* 2 * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board. 3 * 4 * Author: Mark A. Greer <mgreer@mvista.com> 5 * 6 * 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 */ 11 12/* 13 * The EV-64260-BP port is the result of hard work from many people from 14 * many companies. In particular, employees of Marvell/Galileo, Mission 15 * Critical Linux, Xyterra, and MontaVista Software were heavily involved. 16 * 17 * Note: I have not been able to get *all* PCI slots to work reliably 18 * at 66 MHz. I recommend setting jumpers J15 & J16 to short pins 1&2 19 * so that 33 MHz is used. --MAG 20 * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK. 21 * At 100MHz, they are solid. 22 */ 23 24#include <linux/delay.h> 25#include <linux/pci.h> 26#include <linux/ide.h> 27#include <linux/irq.h> 28#include <linux/fs.h> 29#include <linux/seq_file.h> 30#include <linux/console.h> 31#include <linux/initrd.h> 32#include <linux/root_dev.h> 33#include <linux/platform_device.h> 34#if !defined(CONFIG_SERIAL_MPSC_CONSOLE) 35#include <linux/serial.h> 36#include <linux/tty.h> 37#include <linux/serial_core.h> 38#else 39#include <linux/mv643xx.h> 40#endif 41#include <asm/bootinfo.h> 42#include <asm/machdep.h> 43#include <asm/mv64x60.h> 44#include <asm/todc.h> 45#include <asm/time.h> 46 47#include <platforms/ev64260.h> 48 49#define BOARD_VENDOR "Marvell/Galileo" 50#define BOARD_MACHINE "EV-64260-BP" 51 52static struct mv64x60_handle bh; 53 54#if !defined(CONFIG_SERIAL_MPSC_CONSOLE) 55extern void gen550_progress(char *, unsigned short); 56extern void gen550_init(int, struct uart_port *); 57#endif 58 59static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */ 60 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 61}; 62static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */ 63 { 1, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 }, 64 { 0, 30, 0, 2, 0, 26, 0, 18, 0, 22, 20, 24, 28, 32, 0, 0 } 65}; 66 67 68TODC_ALLOC(); 69 70static int 71ev64260_get_bus_speed(void) 72{ 73 return 100000000; 74} 75 76static int 77ev64260_get_cpu_speed(void) 78{ 79 unsigned long pvr, hid1, pll_ext; 80 81 pvr = PVR_VER(mfspr(SPRN_PVR)); 82 83 if (pvr != PVR_VER(PVR_7450)) { 84 hid1 = mfspr(SPRN_HID1) >> 28; 85 return ev64260_get_bus_speed() * cpu_7xx[hid1]/2; 86 } 87 else { 88 hid1 = (mfspr(SPRN_HID1) & 0x0001e000) >> 13; 89 pll_ext = 0; /* No way to read; must get from schematic */ 90 return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2; 91 } 92} 93 94unsigned long __init 95ev64260_find_end_of_memory(void) 96{ 97 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, 98 MV64x60_TYPE_GT64260A); 99} 100 101/* 102 * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing. 103 * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first 104 * PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ). 105 * This is the most IRQs you can get from one bus with this board, though. 106 */ 107static int __init 108ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) 109{ 110 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); 111 112 if (hose->index == 0) { 113 static char pci_irq_table[][4] = 114 /* 115 * PCI IDSEL/INTPIN->INTLINE 116 * A B C D 117 */ 118 { 119 {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */ 120 {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */ 121 }; 122 123 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4; 124 return PCI_IRQ_TABLE_LOOKUP; 125 } 126 else { 127 static char pci_irq_table[][4] = 128 /* 129 * PCI IDSEL/INTPIN->INTLINE 130 * A B C D 131 */ 132 { 133 { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */ 134 { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */ 135 }; 136 137 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4; 138 return PCI_IRQ_TABLE_LOOKUP; 139 } 140} 141 142static void __init 143ev64260_setup_peripherals(void) 144{ 145 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 146 EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0); 147 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); 148 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 149 EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0); 150 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); 151 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 152 EV64260_TODC_BASE, EV64260_TODC_SIZE, 0); 153 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); 154 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 155 EV64260_UART_BASE, EV64260_UART_SIZE, 0); 156 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); 157 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 158 EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0); 159 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); 160 161 TODC_INIT(TODC_TYPE_DS1501, 0, 0, 162 ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8); 163 164 mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29))); 165 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27)); 166 167 if (ev64260_get_bus_speed() > 100000000) 168 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23)); 169 170 mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3))); 171 mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3))); 172 173 /* 174 * Enabling of PCI internal-vs-external arbitration 175 * is a platform- and errata-dependent decision. 176 */ 177 if (bh.type == MV64x60_TYPE_GT64260A ) { 178 mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31)); 179 mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31)); 180 } 181 182 mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */ 183 184 /* 185 * Turn off timer/counters. Not turning off watchdog timer because 186 * can't read its reg on the 64260A so don't know if we'll be enabling 187 * or disabling. 188 */ 189 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, 190 ((1<<0) | (1<<8) | (1<<16) | (1<<24))); 191 mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL, 192 ((1<<0) | (1<<8) | (1<<16) | (1<<24))); 193 194 /* 195 * Set MPSC Multiplex RMII 196 * NOTE: ethernet driver modifies bit 0 and 1 197 */ 198 mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102); 199 200 /* 201 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260 202 * bridge as interrupt inputs (via the General Purpose Ports (GPP) 203 * register). Need to route the MPP inputs to the GPP and set the 204 * polarity correctly. 205 * 206 * In MPP Control 2 Register 207 * MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0 208 * MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0 209 */ 210 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) ); 211 212 /* 213 * In MPP Control 3 Register 214 * MPP 26 -> GPP 26 (RTC INT) bits 8-11 -> 0 215 * MPP 27 -> GPP 27 (PCI 0 INTA) bits 12-15 -> 0 216 * MPP 29 -> GPP 29 (PCI 1 INTA) bits 20-23 -> 0 217 */ 218 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20)); 219 220#define GPP_EXTERNAL_INTERRUPTS \ 221 ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29)) 222 /* DUART & PCI interrupts are inputs */ 223 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS); 224 /* DUART & PCI interrupts are active low */ 225 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS); 226 227 /* Clear any pending interrupts for these inputs and enable them. */ 228 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS); 229 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS); 230 231 return; 232} 233 234static void __init 235ev64260_setup_bridge(void) 236{ 237 struct mv64x60_setup_info si; 238 int i; 239 240 memset(&si, 0, sizeof(si)); 241 242 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; 243 244 si.pci_0.enable_bus = 1; 245 si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE; 246 si.pci_0.pci_io.pci_base_hi = 0; 247 si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE; 248 si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE; 249 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; 250 si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE; 251 si.pci_0.pci_mem[0].pci_base_hi = 0; 252 si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE; 253 si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE; 254 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; 255 si.pci_0.pci_cmd_bits = 0; 256 si.pci_0.latency_timer = 0x8; 257 258 si.pci_1.enable_bus = 1; 259 si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE; 260 si.pci_1.pci_io.pci_base_hi = 0; 261 si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE; 262 si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE; 263 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; 264 si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE; 265 si.pci_1.pci_mem[0].pci_base_hi = 0; 266 si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE; 267 si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE; 268 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; 269 si.pci_1.pci_cmd_bits = 0; 270 si.pci_1.latency_timer = 0x8; 271 272 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) { 273 si.cpu_prot_options[i] = 0; 274 si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB; 275 si.pci_0.acc_cntl_options[i] = 276 GT64260_PCI_ACC_CNTL_DREADEN | 277 GT64260_PCI_ACC_CNTL_RDPREFETCH | 278 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH | 279 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | 280 GT64260_PCI_ACC_CNTL_SWAP_NONE | 281 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES; 282 si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB; 283 si.pci_1.acc_cntl_options[i] = 284 GT64260_PCI_ACC_CNTL_DREADEN | 285 GT64260_PCI_ACC_CNTL_RDPREFETCH | 286 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH | 287 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | 288 GT64260_PCI_ACC_CNTL_SWAP_NONE | 289 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES; 290 si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB; 291 } 292 293 /* Lookup PCI host bridges */ 294 if (mv64x60_init(&bh, &si)) 295 printk(KERN_ERR "Bridge initialization failed.\n"); 296 297 pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */ 298 ppc_md.pci_swizzle = common_swizzle; 299 ppc_md.pci_map_irq = ev64260_map_irq; 300 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; 301 302 mv64x60_set_bus(&bh, 0, 0); 303 bh.hose_a->first_busno = 0; 304 bh.hose_a->last_busno = 0xff; 305 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); 306 307 bh.hose_b->first_busno = bh.hose_a->last_busno + 1; 308 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); 309 bh.hose_b->last_busno = 0xff; 310 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 311 bh.hose_b->first_busno); 312 313 return; 314} 315 316#if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE) 317static void __init 318ev64260_early_serial_map(void) 319{ 320 struct uart_port port; 321 static char first_time = 1; 322 323 if (first_time) { 324 memset(&port, 0, sizeof(port)); 325 326 port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE); 327 port.irq = EV64260_UART_0_IRQ; 328 port.uartclk = BASE_BAUD * 16; 329 port.regshift = 2; 330 port.iotype = UPIO_MEM; 331 port.flags = STD_COM_FLAGS; 332 333#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 334 gen550_init(0, &port); 335#endif 336 337 if (early_serial_setup(&port) != 0) 338 printk(KERN_WARNING "Early serial init of port 0" 339 "failed\n"); 340 341 first_time = 0; 342 } 343 344 return; 345} 346#elif defined(CONFIG_SERIAL_MPSC_CONSOLE) 347static void __init 348ev64260_early_serial_map(void) 349{ 350} 351#endif 352 353static void __init 354ev64260_setup_arch(void) 355{ 356 if (ppc_md.progress) 357 ppc_md.progress("ev64260_setup_arch: enter", 0); 358 359#ifdef CONFIG_BLK_DEV_INITRD 360 if (initrd_start) 361 ROOT_DEV = Root_RAM0; 362 else 363#endif 364#ifdef CONFIG_ROOT_NFS 365 ROOT_DEV = Root_NFS; 366#else 367 ROOT_DEV = Root_SDA2; 368#endif 369 370 if (ppc_md.progress) 371 ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0); 372 373 /* Enable L2 and L3 caches (if 745x) */ 374 _set_L2CR(_get_L2CR() | L2CR_L2E); 375 _set_L3CR(_get_L3CR() | L3CR_L3E); 376 377 if (ppc_md.progress) 378 ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0); 379 380 ev64260_setup_bridge(); /* set up PCI bridge(s) */ 381 ev64260_setup_peripherals(); /* set up chip selects/GPP/MPP etc */ 382 383 if (ppc_md.progress) 384 ppc_md.progress("ev64260_setup_arch: bridge init complete", 0); 385 386#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE) 387 ev64260_early_serial_map(); 388#endif 389 390 printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc." 391 "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE); 392 393 if (ppc_md.progress) 394 ppc_md.progress("ev64260_setup_arch: exit", 0); 395 396 return; 397} 398 399/* Platform device data fixup routines. */ 400#if defined(CONFIG_SERIAL_MPSC) 401static void __init 402ev64260_fixup_mpsc_pdata(struct platform_device *pdev) 403{ 404 struct mpsc_pdata *pdata; 405 406 pdata = (struct mpsc_pdata *)pdev->dev.platform_data; 407 408 pdata->max_idle = 40; 409 pdata->default_baud = EV64260_DEFAULT_BAUD; 410 pdata->brg_clk_src = EV64260_MPSC_CLK_SRC; 411 pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ; 412 413 return; 414} 415 416static int 417ev64260_platform_notify(struct device *dev) 418{ 419 static struct { 420 char *bus_id; 421 void ((*rtn)(struct platform_device *pdev)); 422 } dev_map[] = { 423 { MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata }, 424 { MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata }, 425 }; 426 struct platform_device *pdev; 427 int i; 428 429 if (dev && dev->bus_id) 430 for (i=0; i<ARRAY_SIZE(dev_map); i++) 431 if (!strncmp(dev->bus_id, dev_map[i].bus_id, 432 BUS_ID_SIZE)) { 433 434 pdev = container_of(dev, 435 struct platform_device, dev); 436 dev_map[i].rtn(pdev); 437 } 438 439 return 0; 440} 441#endif 442 443static void 444ev64260_reset_board(void *addr) 445{ 446 local_irq_disable(); 447 448 /* disable and invalidate the L2 cache */ 449 _set_L2CR(0); 450 _set_L2CR(0x200000); 451 452 /* flush and disable L1 I/D cache */ 453 __asm__ __volatile__ 454 ("mfspr 3,1008\n\t" 455 "ori 5,5,0xcc00\n\t" 456 "ori 4,3,0xc00\n\t" 457 "andc 5,3,5\n\t" 458 "sync\n\t" 459 "mtspr 1008,4\n\t" 460 "isync\n\t" 461 "sync\n\t" 462 "mtspr 1008,5\n\t" 463 "isync\n\t" 464 "sync\n\t"); 465 466 /* unmap any other random cs's that might overlap with bootcs */ 467 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0); 468 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); 469 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0); 470 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); 471 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0); 472 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); 473 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0); 474 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); 475 476 /* map bootrom back in to gt @ reset defaults */ 477 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 478 0xff800000, 8*1024*1024, 0); 479 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); 480 481 /* move reg base back to default, setup default pci0 */ 482 mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE, 483 (1<<24) | CONFIG_MV64X60_BASE >> 20); 484 485 /* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped 486 * via BAT or MMU, and MSR IR/DR is ON */ 487 /* SRR0 has system reset vector, SRR1 has default MSR value */ 488 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ 489 /* NOTE: assumes reset vector is at 0xfff00100 */ 490 __asm__ __volatile__ 491 ("mtspr 26, %0\n\t" 492 "li 4,(1<<6)\n\t" 493 "mtspr 27,4\n\t" 494 "rfi\n\t" 495 :: "r" (addr):"r4"); 496 497 return; 498} 499 500static void 501ev64260_restart(char *cmd) 502{ 503 volatile ulong i = 10000000; 504 505 ev64260_reset_board((void *)0xfff00100); 506 507 while (i-- > 0); 508 panic("restart failed\n"); 509} 510 511static void 512ev64260_halt(void) 513{ 514 local_irq_disable(); 515 while (1); 516 /* NOTREACHED */ 517} 518 519static void 520ev64260_power_off(void) 521{ 522 ev64260_halt(); 523 /* NOTREACHED */ 524} 525 526static int 527ev64260_show_cpuinfo(struct seq_file *m) 528{ 529 uint pvid; 530 531 pvid = mfspr(SPRN_PVR); 532 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); 533 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); 534 seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000); 535 seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000); 536 537 return 0; 538} 539 540/* DS1501 RTC has too much variation to use RTC for calibration */ 541static void __init 542ev64260_calibrate_decr(void) 543{ 544 ulong freq; 545 546 freq = ev64260_get_bus_speed()/4; 547 548 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", 549 freq/1000000, freq%1000000); 550 551 tb_ticks_per_jiffy = freq / HZ; 552 tb_to_us = mulhwu_scale_factor(freq, 1000000); 553 554 return; 555} 556 557/* 558 * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space. 559 */ 560static __inline__ void 561ev64260_set_bat(void) 562{ 563 mb(); 564 mtspr(SPRN_DBAT1U, 0xfb0001fe); 565 mtspr(SPRN_DBAT1L, 0xfb00002a); 566 mb(); 567 568 return; 569} 570 571#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 572static void __init 573ev64260_map_io(void) 574{ 575 io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO); 576} 577#endif 578 579void __init 580platform_init(unsigned long r3, unsigned long r4, unsigned long r5, 581 unsigned long r6, unsigned long r7) 582{ 583#ifdef CONFIG_BLK_DEV_INITRD 584 extern int initrd_below_start_ok; 585 586 initrd_start=initrd_end=0; 587 initrd_below_start_ok=0; 588#endif /* CONFIG_BLK_DEV_INITRD */ 589 590 parse_bootinfo(find_bootinfo()); 591 592 isa_mem_base = 0; 593 isa_io_base = EV64260_PCI0_IO_CPU_BASE; 594 pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE; 595 596 loops_per_jiffy = ev64260_get_cpu_speed() / HZ; 597 598 ppc_md.setup_arch = ev64260_setup_arch; 599 ppc_md.show_cpuinfo = ev64260_show_cpuinfo; 600 ppc_md.init_IRQ = gt64260_init_irq; 601 ppc_md.get_irq = gt64260_get_irq; 602 603 ppc_md.restart = ev64260_restart; 604 ppc_md.power_off = ev64260_power_off; 605 ppc_md.halt = ev64260_halt; 606 607 ppc_md.find_end_of_memory = ev64260_find_end_of_memory; 608 609 ppc_md.init = NULL; 610 611 ppc_md.time_init = todc_time_init; 612 ppc_md.set_rtc_time = todc_set_rtc_time; 613 ppc_md.get_rtc_time = todc_get_rtc_time; 614 ppc_md.nvram_read_val = todc_direct_read_val; 615 ppc_md.nvram_write_val = todc_direct_write_val; 616 ppc_md.calibrate_decr = ev64260_calibrate_decr; 617 618 bh.p_base = CONFIG_MV64X60_NEW_BASE; 619 620 ev64260_set_bat(); 621 622#ifdef CONFIG_SERIAL_8250 623#if defined(CONFIG_SERIAL_TEXT_DEBUG) 624 ppc_md.setup_io_mappings = ev64260_map_io; 625 ppc_md.progress = gen550_progress; 626#endif 627#if defined(CONFIG_KGDB) 628 ppc_md.setup_io_mappings = ev64260_map_io; 629 ppc_md.early_serial_map = ev64260_early_serial_map; 630#endif 631#elif defined(CONFIG_SERIAL_MPSC_CONSOLE) 632#ifdef CONFIG_SERIAL_TEXT_DEBUG 633 ppc_md.setup_io_mappings = ev64260_map_io; 634 ppc_md.progress = mv64x60_mpsc_progress; 635 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); 636#endif /* CONFIG_SERIAL_TEXT_DEBUG */ 637#ifdef CONFIG_KGDB 638 ppc_md.setup_io_mappings = ev64260_map_io; 639 ppc_md.early_serial_map = ev64260_early_serial_map; 640#endif /* CONFIG_KGDB */ 641 642#endif 643 644#if defined(CONFIG_SERIAL_MPSC) 645 platform_notify = ev64260_platform_notify; 646#endif 647 648 return; 649} 650