1/* 2 * Yucca board definitions 3 * 4 * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter) 5 * 6 * Copyright 2004-2005 MontaVista Software Inc. 7 * Copyright (c) 2005 Cisco Systems. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 */ 15 16#ifdef __KERNEL__ 17#ifndef __ASM_YUCCA_H__ 18#define __ASM_YUCCA_H__ 19 20#include <platforms/4xx/ppc440spe.h> 21 22/* F/W TLB mapping used in bootloader glue to reset EMAC */ 23#define PPC44x_EMAC0_MR0 0xa0000800 24 25/* Location of MAC addresses in PIBS image */ 26#define PIBS_FLASH_BASE 0xffe00000 27#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400) 28 29/* External timer clock frequency */ 30#define YUCCA_TMR_CLK 25000000 31 32/* 33 * FPGA registers 34 */ 35#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL 36#define YUCCA_FPGA_REG_SIZE 0x24 37 38#define FPGA_REG1A 0x1a 39 40#define FPGA_REG1A_PE0_GLED 0x8000 41#define FPGA_REG1A_PE1_GLED 0x4000 42#define FPGA_REG1A_PE2_GLED 0x2000 43#define FPGA_REG1A_PE0_YLED 0x1000 44#define FPGA_REG1A_PE1_YLED 0x0800 45#define FPGA_REG1A_PE2_YLED 0x0400 46#define FPGA_REG1A_PE0_PWRON 0x0200 47#define FPGA_REG1A_PE1_PWRON 0x0100 48#define FPGA_REG1A_PE2_PWRON 0x0080 49#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040 50#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020 51#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010 52#define FPGA_REG1A_PE_SPREAD0 0x0008 53#define FPGA_REG1A_PE_SPREAD1 0x0004 54#define FPGA_REG1A_PE_SELSOURCE_0 0x0002 55#define FPGA_REG1A_PE_SELSOURCE_1 0x0001 56 57#define FPGA_REG1C 0x1c 58 59#define FPGA_REG1C_PE0_ROOTPOINT 0x8000 60#define FPGA_REG1C_PE1_ENDPOINT 0x4000 61#define FPGA_REG1C_PE2_ENDPOINT 0x2000 62#define FPGA_REG1C_PE0_PRSNT 0x1000 63#define FPGA_REG1C_PE1_PRSNT 0x0800 64#define FPGA_REG1C_PE2_PRSNT 0x0400 65#define FPGA_REG1C_PE0_WAKE 0x0080 66#define FPGA_REG1C_PE1_WAKE 0x0040 67#define FPGA_REG1C_PE2_WAKE 0x0020 68#define FPGA_REG1C_PE0_PERST 0x0010 69#define FPGA_REG1C_PE1_PERST 0x0008 70#define FPGA_REG1C_PE2_PERST 0x0004 71 72/* 73 * Serial port defines 74 */ 75#define RS_TABLE_SIZE 3 76 77/* PIBS defined UART mappings, used before early_serial_setup */ 78#define UART0_IO_BASE 0xa0000200 79#define UART1_IO_BASE 0xa0000300 80#define UART2_IO_BASE 0xa0000600 81 82#define BASE_BAUD 11059200 83#define STD_UART_OP(num) \ 84 { 0, BASE_BAUD, 0, UART##num##_INT, \ 85 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 86 iomem_base: (void*)UART##num##_IO_BASE, \ 87 io_type: SERIAL_IO_MEM}, 88 89#define SERIAL_PORT_DFNS \ 90 STD_UART_OP(0) \ 91 STD_UART_OP(1) \ 92 STD_UART_OP(2) 93 94/* PCI support */ 95#define YUCCA_PCIX_LOWER_IO 0x00000000 96#define YUCCA_PCIX_UPPER_IO 0x0000ffff 97#define YUCCA_PCIX_LOWER_MEM 0x80000000 98#define YUCCA_PCIX_UPPER_MEM 0x8fffffff 99#define YUCCA_PCIE_LOWER_MEM 0x90000000 100#define YUCCA_PCIE_MEM_SIZE 0x10000000 101 102#define YUCCA_PCIX_MEM_SIZE 0x10000000 103#define YUCCA_PCIX_MEM_OFFSET 0x00000000 104#define YUCCA_PCIE_MEM_SIZE 0x10000000 105#define YUCCA_PCIE_MEM_OFFSET 0x00000000 106 107#endif /* __ASM_YUCCA_H__ */ 108#endif /* __KERNEL__ */ 109