1/* 2 * Ocotea board specific routines 3 * 4 * Matt Porter <mporter@kernel.crashing.org> 5 * 6 * Copyright 2003-2005 MontaVista Software Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14#include <linux/stddef.h> 15#include <linux/kernel.h> 16#include <linux/init.h> 17#include <linux/errno.h> 18#include <linux/reboot.h> 19#include <linux/pci.h> 20#include <linux/kdev_t.h> 21#include <linux/types.h> 22#include <linux/major.h> 23#include <linux/blkdev.h> 24#include <linux/console.h> 25#include <linux/delay.h> 26#include <linux/ide.h> 27#include <linux/initrd.h> 28#include <linux/seq_file.h> 29#include <linux/root_dev.h> 30#include <linux/tty.h> 31#include <linux/serial.h> 32#include <linux/serial_core.h> 33 34#include <asm/system.h> 35#include <asm/pgtable.h> 36#include <asm/page.h> 37#include <asm/dma.h> 38#include <asm/io.h> 39#include <asm/machdep.h> 40#include <asm/ocp.h> 41#include <asm/pci-bridge.h> 42#include <asm/time.h> 43#include <asm/todc.h> 44#include <asm/bootinfo.h> 45#include <asm/ppc4xx_pic.h> 46#include <asm/ppcboot.h> 47#include <asm/tlbflush.h> 48 49#include <syslib/gen550.h> 50#include <syslib/ibm440gx_common.h> 51 52extern bd_t __res; 53 54static struct ibm44x_clocks clocks __initdata; 55 56static void __init 57ocotea_calibrate_decr(void) 58{ 59 unsigned int freq; 60 61 if (mfspr(SPRN_CCR1) & CCR1_TCS) 62 freq = OCOTEA_TMR_CLK; 63 else 64 freq = clocks.cpu; 65 66 ibm44x_calibrate_decr(freq); 67} 68 69static int 70ocotea_show_cpuinfo(struct seq_file *m) 71{ 72 seq_printf(m, "vendor\t\t: IBM\n"); 73 seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n"); 74 ibm440gx_show_cpuinfo(m); 75 return 0; 76} 77 78static inline int 79ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) 80{ 81 static char pci_irq_table[][4] = 82 /* 83 * PCI IDSEL/INTPIN->INTLINE 84 * A B C D 85 */ 86 { 87 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */ 88 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */ 89 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */ 90 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */ 91 }; 92 93 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; 94 return PCI_IRQ_TABLE_LOOKUP; 95} 96 97static void __init ocotea_set_emacdata(void) 98{ 99 struct ocp_def *def; 100 struct ocp_func_emac_data *emacdata; 101 int i; 102 103 /* 104 * Note: Current rev. board only operates in Group 4a 105 * mode, so we always set EMAC0-1 for SMII and EMAC2-3 106 * for RGMII (though these could run in RTBI just the same). 107 * 108 * The FPGA reg 3 information isn't even suitable for 109 * determining the phy_mode, so if the board becomes 110 * usable in !4a, it will be necessary to parse an environment 111 * variable from the firmware or similar to properly configure 112 * the phy_map/phy_mode. 113 */ 114 /* Set phy_map, phy_mode, and mac_addr for each EMAC */ 115 for (i=0; i<4; i++) { 116 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); 117 emacdata = def->additions; 118 if (i < 2) { 119 emacdata->phy_map = 0x00000001; /* Skip 0x00 */ 120 emacdata->phy_mode = PHY_MODE_SMII; 121 } 122 else { 123 emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */ 124 emacdata->phy_mode = PHY_MODE_RGMII; 125 } 126 if (i == 0) 127 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); 128 else if (i == 1) 129 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); 130 else if (i == 2) 131 memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6); 132 else if (i == 3) 133 memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6); 134 } 135} 136 137#define PCIX_READW(offset) \ 138 (readw(pcix_reg_base+offset)) 139 140#define PCIX_WRITEW(value, offset) \ 141 (writew(value, pcix_reg_base+offset)) 142 143#define PCIX_WRITEL(value, offset) \ 144 (writel(value, pcix_reg_base+offset)) 145 146static void __init 147ocotea_setup_pcix(void) 148{ 149 void *pcix_reg_base; 150 151 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); 152 153 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ 154 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); 155 156 /* Disable all windows */ 157 PCIX_WRITEL(0, PCIX0_POM0SA); 158 PCIX_WRITEL(0, PCIX0_POM1SA); 159 PCIX_WRITEL(0, PCIX0_POM2SA); 160 PCIX_WRITEL(0, PCIX0_PIM0SA); 161 PCIX_WRITEL(0, PCIX0_PIM0SAH); 162 PCIX_WRITEL(0, PCIX0_PIM1SA); 163 PCIX_WRITEL(0, PCIX0_PIM2SA); 164 PCIX_WRITEL(0, PCIX0_PIM2SAH); 165 166 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ 167 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); 168 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); 169 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); 170 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); 171 PCIX_WRITEL(0x80000001, PCIX0_POM0SA); 172 173 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ 174 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); 175 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); 176 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); 177 178 eieio(); 179} 180 181static void __init 182ocotea_setup_hose(void) 183{ 184 struct pci_controller *hose; 185 186 /* Configure windows on the PCI-X host bridge */ 187 ocotea_setup_pcix(); 188 189 hose = pcibios_alloc_controller(); 190 191 if (!hose) 192 return; 193 194 hose->first_busno = 0; 195 hose->last_busno = 0xff; 196 197 hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET; 198 199 pci_init_resource(&hose->io_resource, 200 OCOTEA_PCI_LOWER_IO, 201 OCOTEA_PCI_UPPER_IO, 202 IORESOURCE_IO, 203 "PCI host bridge"); 204 205 pci_init_resource(&hose->mem_resources[0], 206 OCOTEA_PCI_LOWER_MEM, 207 OCOTEA_PCI_UPPER_MEM, 208 IORESOURCE_MEM, 209 "PCI host bridge"); 210 211 hose->io_space.start = OCOTEA_PCI_LOWER_IO; 212 hose->io_space.end = OCOTEA_PCI_UPPER_IO; 213 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM; 214 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM; 215 hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE); 216 isa_io_base = (unsigned long) hose->io_base_virt; 217 218 setup_indirect_pci(hose, 219 OCOTEA_PCI_CFGA_PLB32, 220 OCOTEA_PCI_CFGD_PLB32); 221 hose->set_cfg_type = 1; 222 223 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); 224 225 ppc_md.pci_swizzle = common_swizzle; 226 ppc_md.pci_map_irq = ocotea_map_irq; 227} 228 229 230TODC_ALLOC(); 231 232static void __init 233ocotea_early_serial_map(void) 234{ 235 struct uart_port port; 236 237 /* Setup ioremapped serial port access */ 238 memset(&port, 0, sizeof(port)); 239 port.membase = ioremap64(PPC440GX_UART0_ADDR, 8); 240 port.irq = UART0_INT; 241 port.uartclk = clocks.uart0; 242 port.regshift = 0; 243 port.iotype = UPIO_MEM; 244 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; 245 port.line = 0; 246 247 if (early_serial_setup(&port) != 0) { 248 printk("Early serial init of port 0 failed\n"); 249 } 250 251#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 252 /* Configure debug serial access */ 253 gen550_init(0, &port); 254 255 /* Purge TLB entry added in head_44x.S for early serial access */ 256 _tlbie(UART0_IO_BASE); 257#endif 258 259 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); 260 port.irq = UART1_INT; 261 port.uartclk = clocks.uart1; 262 port.line = 1; 263 264 if (early_serial_setup(&port) != 0) { 265 printk("Early serial init of port 1 failed\n"); 266 } 267 268#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 269 /* Configure debug serial access */ 270 gen550_init(1, &port); 271#endif 272} 273 274static void __init 275ocotea_setup_arch(void) 276{ 277 ocotea_set_emacdata(); 278 279 ibm440gx_tah_enable(); 280 281 /* 282 * Determine various clocks. 283 * To be completely correct we should get SysClk 284 * from FPGA, because it can be changed by on-board switches 285 * --ebs 286 */ 287 ibm440gx_get_clocks(&clocks, 33300000, 6 * 1843200); 288 ocp_sys_info.opb_bus_freq = clocks.opb; 289 290 /* Setup TODC access */ 291 TODC_INIT(TODC_TYPE_DS1743, 292 0, 293 0, 294 ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE), 295 8); 296 297 /* init to some ~sane value until calibrate_delay() runs */ 298 loops_per_jiffy = 50000000/HZ; 299 300 /* Setup PCI host bridge */ 301 ocotea_setup_hose(); 302 303#ifdef CONFIG_BLK_DEV_INITRD 304 if (initrd_start) 305 ROOT_DEV = Root_RAM0; 306 else 307#endif 308#ifdef CONFIG_ROOT_NFS 309 ROOT_DEV = Root_NFS; 310#else 311 ROOT_DEV = Root_HDA1; 312#endif 313 314 ocotea_early_serial_map(); 315 316 /* Identify the system */ 317 printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n"); 318} 319 320static void __init ocotea_init(void) 321{ 322 ibm440gx_l2c_setup(&clocks); 323} 324 325void __init platform_init(unsigned long r3, unsigned long r4, 326 unsigned long r5, unsigned long r6, unsigned long r7) 327{ 328 ibm440gx_platform_init(r3, r4, r5, r6, r7); 329 330 ppc_md.setup_arch = ocotea_setup_arch; 331 ppc_md.show_cpuinfo = ocotea_show_cpuinfo; 332 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ 333 334 ppc_md.calibrate_decr = ocotea_calibrate_decr; 335 ppc_md.time_init = todc_time_init; 336 ppc_md.set_rtc_time = todc_set_rtc_time; 337 ppc_md.get_rtc_time = todc_get_rtc_time; 338 339 ppc_md.nvram_read_val = todc_direct_read_val; 340 ppc_md.nvram_write_val = todc_direct_write_val; 341#ifdef CONFIG_KGDB 342 ppc_md.early_serial_map = ocotea_early_serial_map; 343#endif 344 ppc_md.init = ocotea_init; 345} 346