1/* 2 * Common defines for the Motorola SPS MPC106/8240/107 Host bridge/Mem 3 * ctrl/EPIC/etc. 4 * 5 * Author: Tom Rini <trini@mvista.com> 6 * 7 * This is a heavily stripped down version of: 8 * include/asm-ppc/mpc10x.h 9 * 10 * Author: Mark A. Greer 11 * mgreer@mvista.com 12 * 13 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under 14 * the terms of the GNU General Public License version 2. This program 15 * is licensed "as is" without any warranty of any kind, whether express 16 * or implied. 17 */ 18#ifndef __BOOT_MPC10X_H__ 19#define __BOOT_MPC10X_H__ 20 21/* 22 * The values here don't completely map everything but should work in most 23 * cases. 24 * 25 * MAP A (PReP Map) 26 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff 27 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff 28 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 29 * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) 30 * 31 * MAP B (CHRP Map) 32 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff 33 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff 34 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 35 * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) 36 */ 37 38/* Define the type of map to use */ 39#define MPC10X_MEM_MAP_A 1 40#define MPC10X_MEM_MAP_B 2 41 42/* Map A (PReP Map) Defines */ 43#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 44#define MPC10X_MAPA_CNFG_DATA 0x80000cfc 45 46/* Map B (CHRP Map) Defines */ 47#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 48#define MPC10X_MAPB_CNFG_DATA 0xfee00000 49 50/* Define offsets for the memory controller registers in the config space */ 51#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ 52#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ 53#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ 54#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ 55 56#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ 57#define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ 58#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ 59#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ 60 61#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 62 63#endif /* __BOOT_MPC10X_H__ */ 64